scu-pd.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4 * Copyright 2017-2018 NXP
  5 *	Dong Aisheng <aisheng.dong@nxp.com>
  6 *
  7 * Implementation of the SCU based Power Domains
  8 *
  9 * NOTE: a better implementation suggested by Ulf Hansson is using a
 10 * single global power domain and implement the ->attach|detach_dev()
 11 * callback for the genpd and use the regular of_genpd_add_provider_simple().
 12 * From within the ->attach_dev(), we could get the OF node for
 13 * the device that is being attached and then parse the power-domain
 14 * cell containing the "resource id" and store that in the per device
 15 * struct generic_pm_domain_data (we have void pointer there for
 16 * storing these kind of things).
 17 *
 18 * Additionally, we need to implement the ->stop() and ->start()
 19 * callbacks of genpd, which is where you "power on/off" devices,
 20 * rather than using the above ->power_on|off() callbacks.
 21 *
 22 * However, there're two known issues:
 23 * 1. The ->attach_dev() of power domain infrastructure still does
 24 *    not support multi domains case as the struct device *dev passed
 25 *    in is a virtual PD device, it does not help for parsing the real
 26 *    device resource id from device tree, so it's unware of which
 27 *    real sub power domain of device should be attached.
 28 *
 29 *    The framework needs some proper extension to support multi power
 30 *    domain cases.
 31 *
 32 *    Update: Genpd assigns the ->of_node for the virtual device before it
 33 *    invokes ->attach_dev() callback, hence parsing for device resources via
 34 *    DT should work fine.
 35 *
 36 * 2. It also breaks most of current drivers as the driver probe sequence
 37 *    behavior changed if removing ->power_on|off() callback and use
 38 *    ->start() and ->stop() instead. genpd_dev_pm_attach will only power
 39 *    up the domain and attach device, but will not call .start() which
 40 *    relies on device runtime pm. That means the device power is still
 41 *    not up before running driver probe function. For SCU enabled
 42 *    platforms, all device drivers accessing registers/clock without power
 43 *    domain enabled will trigger a HW access error. That means we need fix
 44 *    most drivers probe sequence with proper runtime pm.
 45 *
 46 *    Update: Runtime PM support isn't necessary. Instead, this can easily be
 47 *    fixed in drivers by adding a call to dev_pm_domain_start() during probe.
 48 *
 49 * In summary, the second part needs to be addressed via minor updates to the
 50 * relevant drivers, before the "single global power domain" model can be used.
 51 *
 52 */
 53
 54#include <dt-bindings/firmware/imx/rsrc.h>
 55#include <linux/console.h>
 56#include <linux/firmware/imx/sci.h>
 57#include <linux/firmware/imx/svc/rm.h>
 58#include <linux/io.h>
 59#include <linux/module.h>
 60#include <linux/of.h>
 61#include <linux/of_address.h>
 62#include <linux/of_platform.h>
 63#include <linux/platform_device.h>
 64#include <linux/pm.h>
 65#include <linux/pm_domain.h>
 66#include <linux/slab.h>
 67
 68/* SCU Power Mode Protocol definition */
 69struct imx_sc_msg_req_set_resource_power_mode {
 70	struct imx_sc_rpc_msg hdr;
 71	u16 resource;
 72	u8 mode;
 73} __packed __aligned(4);
 74
 75struct req_get_resource_mode {
 76	u16 resource;
 77};
 78
 79struct resp_get_resource_mode {
 80	u8 mode;
 81};
 82
 83struct imx_sc_msg_req_get_resource_power_mode {
 84	struct imx_sc_rpc_msg hdr;
 85	union {
 86		struct req_get_resource_mode req;
 87		struct resp_get_resource_mode resp;
 88	} data;
 89} __packed __aligned(4);
 90
 91#define IMX_SCU_PD_NAME_SIZE 20
 92struct imx_sc_pm_domain {
 93	struct generic_pm_domain pd;
 94	char name[IMX_SCU_PD_NAME_SIZE];
 95	u32 rsrc;
 96};
 97
 98struct imx_sc_pd_range {
 99	char *name;
100	u32 rsrc;
101	u8 num;
102
103	/* add domain index */
104	bool postfix;
105	u8 start_from;
106};
107
108struct imx_sc_pd_soc {
109	const struct imx_sc_pd_range *pd_ranges;
110	u8 num_ranges;
111};
112
113static int imx_con_rsrc;
114
115/* Align with the IMX_SC_PM_PW_MODE_[OFF,STBY,LP,ON] macros */
116static const char * const imx_sc_pm_mode[] = {
117	"IMX_SC_PM_PW_MODE_OFF",
118	"IMX_SC_PM_PW_MODE_STBY",
119	"IMX_SC_PM_PW_MODE_LP",
120	"IMX_SC_PM_PW_MODE_ON"
121};
122
123static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
124	/* LSIO SS */
125	{ "pwm", IMX_SC_R_PWM_0, 8, true, 0 },
126	{ "gpio", IMX_SC_R_GPIO_0, 8, true, 0 },
127	{ "gpt", IMX_SC_R_GPT_0, 5, true, 0 },
128	{ "kpp", IMX_SC_R_KPP, 1, false, 0 },
129	{ "fspi", IMX_SC_R_FSPI_0, 2, true, 0 },
130	{ "mu_a", IMX_SC_R_MU_0A, 14, true, 0 },
131	{ "mu_b", IMX_SC_R_MU_5B, 9, true, 5 },
132
133	/* CONN SS */
134	{ "usb", IMX_SC_R_USB_0, 2, true, 0 },
135	{ "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 },
136	{ "usb1phy", IMX_SC_R_USB_1_PHY, 1, false, 0},
137	{ "usb2", IMX_SC_R_USB_2, 1, false, 0 },
138	{ "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 },
139	{ "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 },
140	{ "enet", IMX_SC_R_ENET_0, 2, true, 0 },
141	{ "nand", IMX_SC_R_NAND, 1, false, 0 },
142	{ "mlb", IMX_SC_R_MLB_0, 1, true, 0 },
143
144	/* AUDIO SS */
145	{ "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 },
146	{ "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
147	{ "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
148	{ "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
149	{ "mclk-out-0", IMX_SC_R_MCLK_OUT_0, 1, false, 0 },
150	{ "mclk-out-1", IMX_SC_R_MCLK_OUT_1, 1, false, 0 },
151	{ "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 },
152	{ "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
153	{ "dma2-ch-0", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
154	{ "dma2-ch-1", IMX_SC_R_DMA_2_CH5, 27, true, 0 },
155	{ "dma3-ch", IMX_SC_R_DMA_3_CH0, 32, true, 0 },
156	{ "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 },
157	{ "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
158	{ "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
159	{ "esai1", IMX_SC_R_ESAI_1, 1, false, 0 },
160	{ "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 },
161	{ "spdif1", IMX_SC_R_SPDIF_1, 1, false, 0 },
162	{ "sai", IMX_SC_R_SAI_0, 3, true, 0 },
163	{ "sai3", IMX_SC_R_SAI_3, 1, false, 0 },
164	{ "sai4", IMX_SC_R_SAI_4, 1, false, 0 },
165	{ "sai5", IMX_SC_R_SAI_5, 1, false, 0 },
166	{ "sai6", IMX_SC_R_SAI_6, 1, false, 0 },
167	{ "sai7", IMX_SC_R_SAI_7, 1, false, 0 },
168	{ "amix", IMX_SC_R_AMIX, 1, false, 0 },
169	{ "mqs0", IMX_SC_R_MQS_0, 1, false, 0 },
170	{ "dsp", IMX_SC_R_DSP, 1, false, 0 },
171	{ "dsp-ram", IMX_SC_R_DSP_RAM, 1, false, 0 },
172
173	/* DMA SS */
174	{ "can", IMX_SC_R_CAN_0, 3, true, 0 },
175	{ "ftm", IMX_SC_R_FTM_0, 2, true, 0 },
176	{ "lpi2c", IMX_SC_R_I2C_0, 5, true, 0 },
177	{ "adc", IMX_SC_R_ADC_0, 2, true, 0 },
178	{ "lcd", IMX_SC_R_LCD_0, 1, true, 0 },
179	{ "lcd-pll", IMX_SC_R_ELCDIF_PLL, 1, true, 0 },
180	{ "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 },
181	{ "lpuart", IMX_SC_R_UART_0, 5, true, 0 },
182	{ "sim", IMX_SC_R_EMVSIM_0, 2, true, 0 },
183	{ "lpspi", IMX_SC_R_SPI_0, 4, true, 0 },
184	{ "irqstr_dsp", IMX_SC_R_IRQSTR_DSP, 1, false, 0 },
185
186	/* VPU SS */
187	{ "vpu", IMX_SC_R_VPU, 1, false, 0 },
188	{ "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 },
189	{ "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 },
190	{ "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 },
191	{ "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 },
192	{ "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 },
193	{ "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 },
194	{ "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 },
195
196	/* GPU SS */
197	{ "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
198	{ "gpu1-pid", IMX_SC_R_GPU_1_PID0, 4, true, 0 },
199
200
201	/* HSIO SS */
202	{ "pcie-a", IMX_SC_R_PCIE_A, 1, false, 0 },
203	{ "serdes-0", IMX_SC_R_SERDES_0, 1, false, 0 },
204	{ "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 },
205	{ "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 },
206	{ "sata-0", IMX_SC_R_SATA_0, 1, false, 0 },
207	{ "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 },
208
209	/* MIPI SS */
210	{ "mipi0", IMX_SC_R_MIPI_0, 1, false, 0 },
211	{ "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 },
212	{ "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 },
213
214	{ "mipi1", IMX_SC_R_MIPI_1, 1, false, 0 },
215	{ "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, false, 0 },
216	{ "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, true, 0 },
217
218	/* LVDS SS */
219	{ "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 },
220	{ "lvds0-pwm", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 },
221	{ "lvds0-lpi2c", IMX_SC_R_LVDS_0_I2C_0, 2, true, 0 },
222	{ "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 },
223	{ "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 },
224	{ "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 },
225
226	/* DC SS */
227	{ "dc0", IMX_SC_R_DC_0, 1, false, 0 },
228	{ "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 },
229	{ "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 },
230
231	{ "dc1", IMX_SC_R_DC_1, 1, false, 0 },
232	{ "dc1-pll", IMX_SC_R_DC_1_PLL_0, 2, true, 0 },
233	{ "dc1-video", IMX_SC_R_DC_1_VIDEO0, 2, true, 0 },
234
235	/* CM40 SS */
236	{ "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 },
237	{ "cm40-intmux", IMX_SC_R_M4_0_INTMUX, 1, false, 0 },
238	{ "cm40-pid", IMX_SC_R_M4_0_PID0, 5, true, 0},
239	{ "cm40-mu-a1", IMX_SC_R_M4_0_MU_1A, 1, false, 0},
240	{ "cm40-lpuart", IMX_SC_R_M4_0_UART, 1, false, 0},
241
242	/* CM41 SS */
243	{ "cm41-i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 },
244	{ "cm41-intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 },
245	{ "cm41-pid", IMX_SC_R_M4_1_PID0, 5, true, 0},
246	{ "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0},
247	{ "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0},
248
249	/* CM41 SS */
250	{ "cm41_i2c", IMX_SC_R_M4_1_I2C, 1, false, 0 },
251	{ "cm41_intmux", IMX_SC_R_M4_1_INTMUX, 1, false, 0 },
252
253	/* DB SS */
254	{ "perf", IMX_SC_R_PERF, 1, false, 0},
255
256	/* IMAGE SS */
257	{ "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 },
258	{ "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 },
259	{ "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 },
260	{ "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 },
261
262	/* SECO SS */
263	{ "seco_mu", IMX_SC_R_SECO_MU_2, 3, true, 2},
264
265	/* V2X SS */
266	{ "v2x_mu", IMX_SC_R_V2X_MU_0, 2, true, 0},
267	{ "v2x_mu", IMX_SC_R_V2X_MU_2, 1, true, 2},
268	{ "v2x_mu", IMX_SC_R_V2X_MU_3, 2, true, 3},
269	{ "img-pdma", IMX_SC_R_ISI_CH0, 8, true, 0 },
270	{ "img-csi0", IMX_SC_R_CSI_0, 1, false, 0 },
271	{ "img-csi0-i2c0", IMX_SC_R_CSI_0_I2C_0, 1, false, 0 },
272	{ "img-csi0-pwm0", IMX_SC_R_CSI_0_PWM_0, 1, false, 0 },
273	{ "img-csi1", IMX_SC_R_CSI_1, 1, false, 0 },
274	{ "img-csi1-i2c0", IMX_SC_R_CSI_1_I2C_0, 1, false, 0 },
275	{ "img-csi1-pwm0", IMX_SC_R_CSI_1_PWM_0, 1, false, 0 },
276	{ "img-parallel", IMX_SC_R_PI_0, 1, false, 0 },
277	{ "img-parallel-i2c0", IMX_SC_R_PI_0_I2C_0, 1, false, 0 },
278	{ "img-parallel-pwm0", IMX_SC_R_PI_0_PWM_0, 2, true, 0 },
279	{ "img-parallel-pll", IMX_SC_R_PI_0_PLL, 1, false, 0 },
280
281	/* HDMI TX SS */
282	{ "hdmi-tx", IMX_SC_R_HDMI, 1, false, 0},
283	{ "hdmi-tx-i2s", IMX_SC_R_HDMI_I2S, 1, false, 0},
284	{ "hdmi-tx-i2c0", IMX_SC_R_HDMI_I2C_0, 1, false, 0},
285	{ "hdmi-tx-pll0", IMX_SC_R_HDMI_PLL_0, 1, false, 0},
286	{ "hdmi-tx-pll1", IMX_SC_R_HDMI_PLL_1, 1, false, 0},
287
288	/* HDMI RX SS */
289	{ "hdmi-rx", IMX_SC_R_HDMI_RX, 1, false, 0},
290	{ "hdmi-rx-pwm", IMX_SC_R_HDMI_RX_PWM_0, 1, false, 0},
291	{ "hdmi-rx-i2c0", IMX_SC_R_HDMI_RX_I2C_0, 1, false, 0},
292	{ "hdmi-rx-bypass", IMX_SC_R_HDMI_RX_BYPASS, 1, false, 0},
293
294	/* SECURITY SS */
295	{ "sec-jr", IMX_SC_R_CAAM_JR2, 2, true, 2},
296
297	/* BOARD SS */
298	{ "board", IMX_SC_R_BOARD_R0, 8, true, 0},
299};
300
301static const struct imx_sc_pd_soc imx8qxp_scu_pd = {
302	.pd_ranges = imx8qxp_scu_pd_ranges,
303	.num_ranges = ARRAY_SIZE(imx8qxp_scu_pd_ranges),
304};
305
306static struct imx_sc_ipc *pm_ipc_handle;
307
308static inline struct imx_sc_pm_domain *
309to_imx_sc_pd(struct generic_pm_domain *genpd)
310{
311	return container_of(genpd, struct imx_sc_pm_domain, pd);
312}
313
314static void imx_sc_pd_get_console_rsrc(void)
315{
316	struct of_phandle_args specs;
317	int ret;
318
319	if (!of_stdout)
320		return;
321
322	ret = of_parse_phandle_with_args(of_stdout, "power-domains",
323					 "#power-domain-cells",
324					 0, &specs);
325	if (ret)
326		return;
327
328	imx_con_rsrc = specs.args[0];
329}
330
331static int imx_sc_get_pd_power(struct device *dev, u32 rsrc)
332{
333	struct imx_sc_msg_req_get_resource_power_mode msg;
334	struct imx_sc_rpc_msg *hdr = &msg.hdr;
335	int ret;
336
337	hdr->ver = IMX_SC_RPC_VERSION;
338	hdr->svc = IMX_SC_RPC_SVC_PM;
339	hdr->func = IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE;
340	hdr->size = 2;
341
342	msg.data.req.resource = rsrc;
343
344	ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true);
345	if (ret)
346		dev_err(dev, "failed to get power resource %d mode, ret %d\n",
347			rsrc, ret);
348
349	return msg.data.resp.mode;
350}
351
352static int imx_sc_pd_power(struct generic_pm_domain *domain, bool power_on)
353{
354	struct imx_sc_msg_req_set_resource_power_mode msg;
355	struct imx_sc_rpc_msg *hdr = &msg.hdr;
356	struct imx_sc_pm_domain *pd;
357	int ret;
358
359	pd = to_imx_sc_pd(domain);
360
361	hdr->ver = IMX_SC_RPC_VERSION;
362	hdr->svc = IMX_SC_RPC_SVC_PM;
363	hdr->func = IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE;
364	hdr->size = 2;
365
366	msg.resource = pd->rsrc;
367	msg.mode = power_on ? IMX_SC_PM_PW_MODE_ON : IMX_SC_PM_PW_MODE_LP;
368
369	/* keep uart console power on for no_console_suspend */
370	if (imx_con_rsrc == pd->rsrc && !console_suspend_enabled && !power_on)
371		return -EBUSY;
372
373	ret = imx_scu_call_rpc(pm_ipc_handle, &msg, true);
374	if (ret)
375		dev_err(&domain->dev, "failed to power %s resource %d ret %d\n",
376			power_on ? "up" : "off", pd->rsrc, ret);
377
378	return ret;
379}
380
381static int imx_sc_pd_power_on(struct generic_pm_domain *domain)
382{
383	return imx_sc_pd_power(domain, true);
384}
385
386static int imx_sc_pd_power_off(struct generic_pm_domain *domain)
387{
388	return imx_sc_pd_power(domain, false);
389}
390
391static struct generic_pm_domain *imx_scu_pd_xlate(const struct of_phandle_args *spec,
392						  void *data)
393{
394	struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
395	struct genpd_onecell_data *pd_data = data;
396	unsigned int i;
397
398	for (i = 0; i < pd_data->num_domains; i++) {
399		struct imx_sc_pm_domain *sc_pd;
400
401		sc_pd = to_imx_sc_pd(pd_data->domains[i]);
402		if (sc_pd->rsrc == spec->args[0]) {
403			domain = &sc_pd->pd;
404			break;
405		}
406	}
407
408	return domain;
409}
410
411static struct imx_sc_pm_domain *
412imx_scu_add_pm_domain(struct device *dev, int idx,
413		      const struct imx_sc_pd_range *pd_ranges)
414{
415	struct imx_sc_pm_domain *sc_pd;
416	bool is_off;
417	int mode, ret;
418
419	if (!imx_sc_rm_is_resource_owned(pm_ipc_handle, pd_ranges->rsrc + idx))
420		return NULL;
421
422	sc_pd = devm_kzalloc(dev, sizeof(*sc_pd), GFP_KERNEL);
423	if (!sc_pd)
424		return ERR_PTR(-ENOMEM);
425
426	sc_pd->rsrc = pd_ranges->rsrc + idx;
427	sc_pd->pd.power_off = imx_sc_pd_power_off;
428	sc_pd->pd.power_on = imx_sc_pd_power_on;
429
430	if (pd_ranges->postfix)
431		snprintf(sc_pd->name, sizeof(sc_pd->name),
432			 "%s%i", pd_ranges->name, pd_ranges->start_from + idx);
433	else
434		snprintf(sc_pd->name, sizeof(sc_pd->name),
435			 "%s", pd_ranges->name);
436
437	sc_pd->pd.name = sc_pd->name;
438	if (imx_con_rsrc == sc_pd->rsrc)
439		sc_pd->pd.flags = GENPD_FLAG_RPM_ALWAYS_ON;
440
441	mode = imx_sc_get_pd_power(dev, pd_ranges->rsrc + idx);
442	if (mode == IMX_SC_PM_PW_MODE_ON)
443		is_off = false;
444	else
445		is_off = true;
446
447	dev_dbg(dev, "%s : %s\n", sc_pd->name, imx_sc_pm_mode[mode]);
448
449	if (sc_pd->rsrc >= IMX_SC_R_LAST) {
450		dev_warn(dev, "invalid pd %s rsrc id %d found",
451			 sc_pd->name, sc_pd->rsrc);
452
453		devm_kfree(dev, sc_pd);
454		return NULL;
455	}
456
457	ret = pm_genpd_init(&sc_pd->pd, NULL, is_off);
458	if (ret) {
459		dev_warn(dev, "failed to init pd %s rsrc id %d",
460			 sc_pd->name, sc_pd->rsrc);
461		devm_kfree(dev, sc_pd);
462		return NULL;
463	}
464
465	return sc_pd;
466}
467
468static int imx_scu_init_pm_domains(struct device *dev,
469				    const struct imx_sc_pd_soc *pd_soc)
470{
471	const struct imx_sc_pd_range *pd_ranges = pd_soc->pd_ranges;
472	struct generic_pm_domain **domains;
473	struct genpd_onecell_data *pd_data;
474	struct imx_sc_pm_domain *sc_pd;
475	u32 count = 0;
476	int i, j;
477
478	for (i = 0; i < pd_soc->num_ranges; i++)
479		count += pd_ranges[i].num;
480
481	domains = devm_kcalloc(dev, count, sizeof(*domains), GFP_KERNEL);
482	if (!domains)
483		return -ENOMEM;
484
485	pd_data = devm_kzalloc(dev, sizeof(*pd_data), GFP_KERNEL);
486	if (!pd_data)
487		return -ENOMEM;
488
489	count = 0;
490	for (i = 0; i < pd_soc->num_ranges; i++) {
491		for (j = 0; j < pd_ranges[i].num; j++) {
492			sc_pd = imx_scu_add_pm_domain(dev, j, &pd_ranges[i]);
493			if (IS_ERR_OR_NULL(sc_pd))
494				continue;
495
496			domains[count++] = &sc_pd->pd;
497			dev_dbg(dev, "added power domain %s\n", sc_pd->pd.name);
498		}
499	}
500
501	pd_data->domains = domains;
502	pd_data->num_domains = count;
503	pd_data->xlate = imx_scu_pd_xlate;
504
505	of_genpd_add_provider_onecell(dev->of_node, pd_data);
506
507	return 0;
508}
509
510static int imx_sc_pd_probe(struct platform_device *pdev)
511{
512	const struct imx_sc_pd_soc *pd_soc;
513	int ret;
514
515	ret = imx_scu_get_handle(&pm_ipc_handle);
516	if (ret)
517		return ret;
518
519	pd_soc = of_device_get_match_data(&pdev->dev);
520	if (!pd_soc)
521		return -ENODEV;
522
523	imx_sc_pd_get_console_rsrc();
524
525	return imx_scu_init_pm_domains(&pdev->dev, pd_soc);
526}
527
528static const struct of_device_id imx_sc_pd_match[] = {
529	{ .compatible = "fsl,imx8qxp-scu-pd", &imx8qxp_scu_pd},
530	{ .compatible = "fsl,scu-pd", &imx8qxp_scu_pd},
531	{ /* sentinel */ }
532};
533
534static struct platform_driver imx_sc_pd_driver = {
535	.driver = {
536		.name = "imx-scu-pd",
537		.of_match_table = imx_sc_pd_match,
538		.suppress_bind_attrs = true,
539	},
540	.probe = imx_sc_pd_probe,
541};
542builtin_platform_driver(imx_sc_pd_driver);
543
544MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
545MODULE_DESCRIPTION("IMX SCU Power Domain driver");
546MODULE_LICENSE("GPL v2");