meson-secure-pwrc.c

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2019 Amlogic, Inc.
  4 * Author: Jianxin Pan <jianxin.pan@amlogic.com>
  5 */
  6
  7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8
  9#include <linux/io.h>
 10#include <linux/of.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm_domain.h>
 13#include <dt-bindings/power/meson-a1-power.h>
 14#include <dt-bindings/power/amlogic,c3-pwrc.h>
 15#include <dt-bindings/power/meson-s4-power.h>
 16#include <dt-bindings/power/amlogic,t7-pwrc.h>
 17#include <dt-bindings/power/amlogic,a4-pwrc.h>
 18#include <dt-bindings/power/amlogic,a5-pwrc.h>
 19#include <dt-bindings/power/amlogic,s6-pwrc.h>
 20#include <dt-bindings/power/amlogic,s7-pwrc.h>
 21#include <dt-bindings/power/amlogic,s7d-pwrc.h>
 22#include <linux/arm-smccc.h>
 23#include <linux/firmware/meson/meson_sm.h>
 24#include <linux/module.h>
 25
 26#define PWRC_ON		1
 27#define PWRC_OFF	0
 28#define PWRC_NO_PARENT	UINT_MAX
 29
 30struct meson_secure_pwrc_domain {
 31	struct generic_pm_domain base;
 32	unsigned int index;
 33	unsigned int parent;
 34	struct meson_secure_pwrc *pwrc;
 35};
 36
 37struct meson_secure_pwrc {
 38	struct meson_secure_pwrc_domain *domains;
 39	struct genpd_onecell_data xlate;
 40	struct meson_sm_firmware *fw;
 41};
 42
 43struct meson_secure_pwrc_domain_desc {
 44	unsigned int index;
 45	unsigned int parent;
 46	unsigned int flags;
 47	char *name;
 48	bool (*is_off)(struct meson_secure_pwrc_domain *pwrc_domain);
 49};
 50
 51struct meson_secure_pwrc_domain_data {
 52	unsigned int count;
 53	const struct meson_secure_pwrc_domain_desc *domains;
 54};
 55
 56static bool pwrc_secure_is_off(struct meson_secure_pwrc_domain *pwrc_domain)
 57{
 58	int is_off = 1;
 59
 60	if (meson_sm_call(pwrc_domain->pwrc->fw, SM_A1_PWRC_GET, &is_off,
 61			  pwrc_domain->index, 0, 0, 0, 0) < 0)
 62		pr_err("failed to get power domain status\n");
 63
 64	return is_off;
 65}
 66
 67static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
 68{
 69	int ret = 0;
 70	struct meson_secure_pwrc_domain *pwrc_domain =
 71		container_of(domain, struct meson_secure_pwrc_domain, base);
 72
 73	if (meson_sm_call(pwrc_domain->pwrc->fw, SM_A1_PWRC_SET, NULL,
 74			  pwrc_domain->index, PWRC_OFF, 0, 0, 0) < 0) {
 75		pr_err("failed to set power domain off\n");
 76		ret = -EINVAL;
 77	}
 78
 79	return ret;
 80}
 81
 82static int meson_secure_pwrc_on(struct generic_pm_domain *domain)
 83{
 84	int ret = 0;
 85	struct meson_secure_pwrc_domain *pwrc_domain =
 86		container_of(domain, struct meson_secure_pwrc_domain, base);
 87
 88	if (meson_sm_call(pwrc_domain->pwrc->fw, SM_A1_PWRC_SET, NULL,
 89			  pwrc_domain->index, PWRC_ON, 0, 0, 0) < 0) {
 90		pr_err("failed to set power domain on\n");
 91		ret = -EINVAL;
 92	}
 93
 94	return ret;
 95}
 96
 97#define SEC_PD(__name, __flag)			\
 98[PWRC_##__name##_ID] =				\
 99{						\
100	.name = #__name,			\
101	.index = PWRC_##__name##_ID,		\
102	.is_off = pwrc_secure_is_off,		\
103	.flags = __flag,			\
104	.parent = PWRC_NO_PARENT,		\
105}
106
107#define TOP_PD(__name, __flag, __parent)	\
108[PWRC_##__name##_ID] =				\
109{						\
110	.name = #__name,			\
111	.index = PWRC_##__name##_ID,		\
112	.is_off = pwrc_secure_is_off,		\
113	.flags = __flag,			\
114	.parent = __parent,			\
115}
116
117static const struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
118	SEC_PD(DSPA,	0),
119	SEC_PD(DSPB,	0),
120	/* UART should keep working in ATF after suspend and before resume */
121	SEC_PD(UART,	GENPD_FLAG_ALWAYS_ON),
122	/* DMC is for DDR PHY ana/dig and DMC, and should be always on */
123	SEC_PD(DMC,	GENPD_FLAG_ALWAYS_ON),
124	SEC_PD(I2C,	0),
125	SEC_PD(PSRAM,	0),
126	SEC_PD(ACODEC,	0),
127	SEC_PD(AUDIO,	0),
128	SEC_PD(OTP,	0),
129	SEC_PD(DMA,	GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_IRQ_SAFE),
130	SEC_PD(SD_EMMC,	0),
131	SEC_PD(RAMA,	0),
132	/* SRAMB is used as ATF runtime memory, and should be always on */
133	SEC_PD(RAMB,	GENPD_FLAG_ALWAYS_ON),
134	SEC_PD(IR,	0),
135	SEC_PD(SPICC,	0),
136	SEC_PD(SPIFC,	0),
137	SEC_PD(USB,	0),
138	/* NIC is for the Arm NIC-400 interconnect, and should be always on */
139	SEC_PD(NIC,	GENPD_FLAG_ALWAYS_ON),
140	SEC_PD(PDMIN,	0),
141	SEC_PD(RSA,	0),
142};
143
144static const struct meson_secure_pwrc_domain_desc a4_pwrc_domains[] = {
145	SEC_PD(A4_AUDIO,	0),
146	SEC_PD(A4_SDIOA,	0),
147	SEC_PD(A4_EMMC,	0),
148	SEC_PD(A4_USB_COMB,	0),
149	SEC_PD(A4_ETH,		0),
150	SEC_PD(A4_VOUT,		0),
151	SEC_PD(A4_AUDIO_PDM,	0),
152	/* DMC is for DDR PHY ana/dig and DMC, and should be always on */
153	SEC_PD(A4_DMC,	GENPD_FLAG_ALWAYS_ON),
154	/* WRAP is secure_top, a lot of modules are included, and should be always on */
155	SEC_PD(A4_SYS_WRAP,	GENPD_FLAG_ALWAYS_ON),
156	SEC_PD(A4_AO_I2C_S,	0),
157	SEC_PD(A4_AO_UART,	0),
158	/* IR is wake up trigger source, and should be always on */
159	SEC_PD(A4_AO_IR,	GENPD_FLAG_ALWAYS_ON),
160};
161
162static const struct meson_secure_pwrc_domain_desc a5_pwrc_domains[] = {
163	SEC_PD(A5_NNA,		0),
164	SEC_PD(A5_AUDIO,	0),
165	SEC_PD(A5_SDIOA,	0),
166	SEC_PD(A5_EMMC,		0),
167	SEC_PD(A5_USB_COMB,	0),
168	SEC_PD(A5_ETH,		0),
169	SEC_PD(A5_RSA,		0),
170	SEC_PD(A5_AUDIO_PDM,	0),
171	/* DMC is for DDR PHY ana/dig and DMC, and should be always on */
172	SEC_PD(A5_DMC,		GENPD_FLAG_ALWAYS_ON),
173	/* WRAP is secure_top, a lot of modules are included, and should be always on */
174	SEC_PD(A5_SYS_WRAP,	GENPD_FLAG_ALWAYS_ON),
175	SEC_PD(A5_DSPA,		0),
176};
177
178static const struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
179	SEC_PD(C3_NNA,		0),
180	SEC_PD(C3_AUDIO,	0),
181	SEC_PD(C3_SDIOA,	0),
182	SEC_PD(C3_EMMC,		0),
183	SEC_PD(C3_USB_COMB,	0),
184	SEC_PD(C3_SDCARD,	0),
185	/* ETH is for ethernet online wakeup, and should be always on */
186	SEC_PD(C3_ETH,		GENPD_FLAG_ALWAYS_ON),
187	SEC_PD(C3_GE2D,		0),
188	SEC_PD(C3_CVE,		0),
189	SEC_PD(C3_GDC_WRAP,	0),
190	SEC_PD(C3_ISP_TOP,	0),
191	SEC_PD(C3_MIPI_ISP_WRAP, 0),
192	SEC_PD(C3_VCODEC,	0),
193};
194
195static const struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = {
196	SEC_PD(S4_DOS_HEVC,	0),
197	SEC_PD(S4_DOS_VDEC,	0),
198	SEC_PD(S4_VPU_HDMI,	0),
199	SEC_PD(S4_USB_COMB,	0),
200	SEC_PD(S4_GE2D,		0),
201	/* ETH is for ethernet online wakeup, and should be always on */
202	SEC_PD(S4_ETH,		GENPD_FLAG_ALWAYS_ON),
203	SEC_PD(S4_DEMOD,	0),
204	SEC_PD(S4_AUDIO,	0),
205};
206
207static const struct meson_secure_pwrc_domain_desc s6_pwrc_domains[] = {
208	SEC_PD(S6_DSPA,		0),
209	SEC_PD(S6_DOS_HEVC,	0),
210	SEC_PD(S6_DOS_VDEC,	0),
211	SEC_PD(S6_VPU_HDMI,	0),
212	SEC_PD(S6_U2DRD,	0),
213	SEC_PD(S6_U3DRD,	0),
214	SEC_PD(S6_SD_EMMC_C,	0),
215	SEC_PD(S6_GE2D,		0),
216	SEC_PD(S6_AMFC,		0),
217	SEC_PD(S6_VC9000E,	0),
218	SEC_PD(S6_DEWARP,	0),
219	SEC_PD(S6_VICP,		0),
220	SEC_PD(S6_SD_EMMC_A,	0),
221	SEC_PD(S6_SD_EMMC_B,	0),
222	/* ETH is for ethernet online wakeup, and should be always on */
223	SEC_PD(S6_ETH,		GENPD_FLAG_ALWAYS_ON),
224	SEC_PD(S6_PCIE,		0),
225	SEC_PD(S6_NNA_4T,	0),
226	SEC_PD(S6_AUDIO,	0),
227	SEC_PD(S6_AUCPU,	0),
228	SEC_PD(S6_ADAPT,	0),
229};
230
231static const struct meson_secure_pwrc_domain_desc s7_pwrc_domains[] = {
232	SEC_PD(S7_DOS_HEVC,	0),
233	SEC_PD(S7_DOS_VDEC,	0),
234	SEC_PD(S7_VPU_HDMI,	0),
235	SEC_PD(S7_USB_COMB,	0),
236	SEC_PD(S7_SD_EMMC_C,	0),
237	SEC_PD(S7_GE2D,		0),
238	SEC_PD(S7_SD_EMMC_A,	0),
239	SEC_PD(S7_SD_EMMC_B,	0),
240	/* ETH is for ethernet online wakeup, and should be always on */
241	SEC_PD(S7_ETH,		GENPD_FLAG_ALWAYS_ON),
242	SEC_PD(S7_AUCPU,	0),
243	SEC_PD(S7_AUDIO,	0),
244};
245
246static const struct meson_secure_pwrc_domain_desc s7d_pwrc_domains[] = {
247	SEC_PD(S7D_DOS_HCODEC,	0),
248	SEC_PD(S7D_DOS_HEVC,	0),
249	SEC_PD(S7D_DOS_VDEC,	0),
250	SEC_PD(S7D_VPU_HDMI,	0),
251	SEC_PD(S7D_USB_U2DRD,	0),
252	SEC_PD(S7D_USB_U2H,	0),
253	SEC_PD(S7D_SSD_EMMC_C,	0),
254	SEC_PD(S7D_GE2D,	0),
255	SEC_PD(S7D_AMFC,	0),
256	SEC_PD(S7D_EMMC_A,	0),
257	SEC_PD(S7D_EMMC_B,	0),
258	/* ETH is for ethernet online wakeup, and should be always on */
259	SEC_PD(S7D_ETH,		GENPD_FLAG_ALWAYS_ON),
260	SEC_PD(S7D_AUCPU,	0),
261	SEC_PD(S7D_AUDIO,	0),
262	/* SRAMA is used as ATF runtime memory, and should be always on */
263	SEC_PD(S7D_SRAMA,	GENPD_FLAG_ALWAYS_ON),
264	/* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */
265	SEC_PD(S7D_DMC0,	GENPD_FLAG_ALWAYS_ON),
266	/* DMC1 is for DDR PHY ana/dig and DMC, and should be always on */
267	SEC_PD(S7D_DMC1,	GENPD_FLAG_ALWAYS_ON),
268	/* DDR should be always on */
269	SEC_PD(S7D_DDR,		GENPD_FLAG_ALWAYS_ON),
270};
271
272static const struct meson_secure_pwrc_domain_desc t7_pwrc_domains[] = {
273	SEC_PD(T7_DSPA,		0),
274	SEC_PD(T7_DSPB,		0),
275	TOP_PD(T7_DOS_HCODEC,	0, PWRC_T7_NIC3_ID),
276	TOP_PD(T7_DOS_HEVC,	0, PWRC_T7_NIC3_ID),
277	TOP_PD(T7_DOS_VDEC,	0, PWRC_T7_NIC3_ID),
278	TOP_PD(T7_DOS_WAVE,	0, PWRC_T7_NIC3_ID),
279	SEC_PD(T7_VPU_HDMI,	0),
280	SEC_PD(T7_USB_COMB,	0),
281	SEC_PD(T7_PCIE,		0),
282	TOP_PD(T7_GE2D,		0, PWRC_T7_NIC3_ID),
283	/* SRAMA is used as ATF runtime memory, and should be always on */
284	SEC_PD(T7_SRAMA,	GENPD_FLAG_ALWAYS_ON),
285	/* SRAMB is used as ATF runtime memory, and should be always on */
286	SEC_PD(T7_SRAMB,	GENPD_FLAG_ALWAYS_ON),
287	SEC_PD(T7_HDMIRX,	0),
288	SEC_PD(T7_VI_CLK1,	0),
289	SEC_PD(T7_VI_CLK2,	0),
290	/* ETH is for ethernet online wakeup, and should be always on */
291	SEC_PD(T7_ETH,		GENPD_FLAG_ALWAYS_ON),
292	TOP_PD(T7_ISP,		0, PWRC_T7_MIPI_ISP_ID),
293	SEC_PD(T7_MIPI_ISP,	0),
294	TOP_PD(T7_GDC,		0, PWRC_T7_NIC3_ID),
295	TOP_PD(T7_DEWARP,	0, PWRC_T7_NIC3_ID),
296	SEC_PD(T7_SDIO_A,	0),
297	SEC_PD(T7_SDIO_B,	0),
298	SEC_PD(T7_EMMC,		0),
299	TOP_PD(T7_MALI_SC0,	0, PWRC_T7_NNA_TOP_ID),
300	TOP_PD(T7_MALI_SC1,	0, PWRC_T7_NNA_TOP_ID),
301	TOP_PD(T7_MALI_SC2,	0, PWRC_T7_NNA_TOP_ID),
302	TOP_PD(T7_MALI_SC3,	0, PWRC_T7_NNA_TOP_ID),
303	SEC_PD(T7_MALI_TOP,	0),
304	TOP_PD(T7_NNA_CORE0,	0, PWRC_T7_NNA_TOP_ID),
305	TOP_PD(T7_NNA_CORE1,	0, PWRC_T7_NNA_TOP_ID),
306	TOP_PD(T7_NNA_CORE2,	0, PWRC_T7_NNA_TOP_ID),
307	TOP_PD(T7_NNA_CORE3,	0, PWRC_T7_NNA_TOP_ID),
308	SEC_PD(T7_NNA_TOP,	0),
309	SEC_PD(T7_DDR0,		GENPD_FLAG_ALWAYS_ON),
310	SEC_PD(T7_DDR1,		GENPD_FLAG_ALWAYS_ON),
311	/* DMC0 is for DDR PHY ana/dig and DMC, and should be always on */
312	SEC_PD(T7_DMC0,		GENPD_FLAG_ALWAYS_ON),
313	/* DMC1 is for DDR PHY ana/dig and DMC, and should be always on */
314	SEC_PD(T7_DMC1,		GENPD_FLAG_ALWAYS_ON),
315	/* NOC is related to clk bus, and should be always on */
316	SEC_PD(T7_NOC,		GENPD_FLAG_ALWAYS_ON),
317	/* NIC is for the Arm NIC-400 interconnect, and should be always on */
318	SEC_PD(T7_NIC2,		GENPD_FLAG_ALWAYS_ON),
319	SEC_PD(T7_NIC3,		0),
320	/* CPU accesses the interleave data to the ddr need cci, and should be always on */
321	SEC_PD(T7_CCI,		GENPD_FLAG_ALWAYS_ON),
322	SEC_PD(T7_MIPI_DSI0,	0),
323	SEC_PD(T7_SPICC0,	0),
324	SEC_PD(T7_SPICC1,	0),
325	SEC_PD(T7_SPICC2,	0),
326	SEC_PD(T7_SPICC3,	0),
327	SEC_PD(T7_SPICC4,	0),
328	SEC_PD(T7_SPICC5,	0),
329	SEC_PD(T7_EDP0,		0),
330	SEC_PD(T7_EDP1,		0),
331	SEC_PD(T7_MIPI_DSI1,	0),
332	SEC_PD(T7_AUDIO,	0),
333};
334
335static int meson_secure_pwrc_probe(struct platform_device *pdev)
336{
337	int i;
338	struct device_node *sm_np;
339	struct meson_secure_pwrc *pwrc;
340	const struct meson_secure_pwrc_domain_data *match;
341
342	match = of_device_get_match_data(&pdev->dev);
343	if (!match) {
344		dev_err(&pdev->dev, "failed to get match data\n");
345		return -ENODEV;
346	}
347
348	sm_np = of_find_compatible_node(NULL, NULL, "amlogic,meson-gxbb-sm");
349	if (!sm_np) {
350		dev_err(&pdev->dev, "no secure-monitor node\n");
351		return -ENODEV;
352	}
353
354	pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
355	if (!pwrc) {
356		of_node_put(sm_np);
357		return -ENOMEM;
358	}
359
360	pwrc->fw = meson_sm_get(sm_np);
361	of_node_put(sm_np);
362	if (!pwrc->fw)
363		return -EPROBE_DEFER;
364
365	pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
366					   sizeof(*pwrc->xlate.domains),
367					   GFP_KERNEL);
368	if (!pwrc->xlate.domains)
369		return -ENOMEM;
370
371	pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
372				     sizeof(*pwrc->domains), GFP_KERNEL);
373	if (!pwrc->domains)
374		return -ENOMEM;
375
376	pwrc->xlate.num_domains = match->count;
377	platform_set_drvdata(pdev, pwrc);
378
379	for (i = 0 ; i < match->count ; ++i) {
380		struct meson_secure_pwrc_domain *dom = &pwrc->domains[i];
381
382		if (!match->domains[i].name)
383			continue;
384
385		dom->pwrc = pwrc;
386		dom->index = match->domains[i].index;
387		dom->parent = match->domains[i].parent;
388		dom->base.name = match->domains[i].name;
389		dom->base.flags = match->domains[i].flags;
390		dom->base.power_on = meson_secure_pwrc_on;
391		dom->base.power_off = meson_secure_pwrc_off;
392
393		if (match->domains[i].is_off(dom) && (dom->base.flags & GENPD_FLAG_ALWAYS_ON))
394			meson_secure_pwrc_on(&dom->base);
395
396		pm_genpd_init(&dom->base, NULL, match->domains[i].is_off(dom));
397
398		pwrc->xlate.domains[i] = &dom->base;
399	}
400
401	for (i = 0; i < match->count; i++) {
402		struct meson_secure_pwrc_domain *dom = pwrc->domains;
403
404		if (!match->domains[i].name || match->domains[i].parent == PWRC_NO_PARENT)
405			continue;
406
407		pm_genpd_add_subdomain(&dom[dom[i].parent].base, &dom[i].base);
408	}
409
410	return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
411}
412
413static const struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = {
414	.domains = a1_pwrc_domains,
415	.count = ARRAY_SIZE(a1_pwrc_domains),
416};
417
418static const struct meson_secure_pwrc_domain_data amlogic_secure_a4_pwrc_data = {
419	.domains = a4_pwrc_domains,
420	.count = ARRAY_SIZE(a4_pwrc_domains),
421};
422
423static const struct meson_secure_pwrc_domain_data amlogic_secure_a5_pwrc_data = {
424	.domains = a5_pwrc_domains,
425	.count = ARRAY_SIZE(a5_pwrc_domains),
426};
427
428static const struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = {
429	.domains = c3_pwrc_domains,
430	.count = ARRAY_SIZE(c3_pwrc_domains),
431};
432
433static const struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = {
434	.domains = s4_pwrc_domains,
435	.count = ARRAY_SIZE(s4_pwrc_domains),
436};
437
438static const struct meson_secure_pwrc_domain_data amlogic_secure_s6_pwrc_data = {
439	.domains = s6_pwrc_domains,
440	.count = ARRAY_SIZE(s6_pwrc_domains),
441};
442
443static const struct meson_secure_pwrc_domain_data amlogic_secure_s7_pwrc_data = {
444	.domains = s7_pwrc_domains,
445	.count = ARRAY_SIZE(s7_pwrc_domains),
446};
447
448static const struct meson_secure_pwrc_domain_data amlogic_secure_s7d_pwrc_data = {
449	.domains = s7d_pwrc_domains,
450	.count = ARRAY_SIZE(s7d_pwrc_domains),
451};
452
453static const struct meson_secure_pwrc_domain_data amlogic_secure_t7_pwrc_data = {
454	.domains = t7_pwrc_domains,
455	.count = ARRAY_SIZE(t7_pwrc_domains),
456};
457
458static const struct of_device_id meson_secure_pwrc_match_table[] = {
459	{
460		.compatible = "amlogic,meson-a1-pwrc",
461		.data = &meson_secure_a1_pwrc_data,
462	},
463	{
464		.compatible = "amlogic,a4-pwrc",
465		.data = &amlogic_secure_a4_pwrc_data,
466	},
467	{
468		.compatible = "amlogic,a5-pwrc",
469		.data = &amlogic_secure_a5_pwrc_data,
470	},
471	{
472		.compatible = "amlogic,c3-pwrc",
473		.data = &amlogic_secure_c3_pwrc_data,
474	},
475	{
476		.compatible = "amlogic,meson-s4-pwrc",
477		.data = &meson_secure_s4_pwrc_data,
478	},
479	{
480		.compatible = "amlogic,s6-pwrc",
481		.data = &amlogic_secure_s6_pwrc_data,
482	},
483	{
484		.compatible = "amlogic,s7-pwrc",
485		.data = &amlogic_secure_s7_pwrc_data,
486	},
487	{
488		.compatible = "amlogic,s7d-pwrc",
489		.data = &amlogic_secure_s7d_pwrc_data,
490	},
491	{
492		.compatible = "amlogic,t7-pwrc",
493		.data = &amlogic_secure_t7_pwrc_data,
494	},
495	{ /* sentinel */ }
496};
497MODULE_DEVICE_TABLE(of, meson_secure_pwrc_match_table);
498
499static struct platform_driver meson_secure_pwrc_driver = {
500	.probe = meson_secure_pwrc_probe,
501	.driver = {
502		.name		= "meson_secure_pwrc",
503		.of_match_table	= meson_secure_pwrc_match_table,
504	},
505};
506module_platform_driver(meson_secure_pwrc_driver);
507MODULE_DESCRIPTION("Amlogic Meson Secure Power Domains driver");
508MODULE_LICENSE("Dual MIT/GPL");