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wcl.c
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linux-6.19.14/drivers/platform/x86/intel/pmc/wcl.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains platform specific structure definitions 4 * and init function used by Wildcat Lake PCH. 5 * 6 * Copyright (c) 2025, Intel Corporation. 7 */ 8 9#include <linux/bits.h> 10#include <linux/pci.h> 11 12#include "core.h" 13 14/* PMC SSRAM PMT Telemetry GUIDS */ 15#define PCDN_LPM_REQ_GUID 0x33747648 16 17static const struct pmc_bit_map wcl_pcdn_pfear_map[] = { 18 {"PMC_0", BIT(0)}, 19 {"FUSE_OSSE", BIT(1)}, 20 {"ESPISPI", BIT(2)}, 21 {"XHCI", BIT(3)}, 22 {"SPA", BIT(4)}, 23 {"RSVD", BIT(5)}, 24 {"MPFPW2", BIT(6)}, 25 {"GBE", BIT(7)}, 26 27 {"SBR16B21", BIT(0)}, 28 {"SBR16B5", BIT(1)}, 29 {"SBR8B1", BIT(2)}, 30 {"SBR8B0", BIT(3)}, 31 {"P2SB0", BIT(4)}, 32 {"D2D_DISP_1", BIT(5)}, 33 {"LPSS", BIT(6)}, 34 {"LPC", BIT(7)}, 35 36 {"SMB", BIT(0)}, 37 {"ISH", BIT(1)}, 38 {"DBG_SBR16B", BIT(2)}, 39 {"NPK_0", BIT(3)}, 40 {"D2D_NOC_1", BIT(4)}, 41 {"FIA_P", BIT(5)}, 42 {"FUSE", BIT(6)}, 43 {"DBG_PSF", BIT(7)}, 44 45 {"DISP_PGA1", BIT(0)}, 46 {"XDCI", BIT(1)}, 47 {"EXI", BIT(2)}, 48 {"CSE", BIT(3)}, 49 {"KVMCC", BIT(4)}, 50 {"PMT", BIT(5)}, 51 {"CLINK", BIT(6)}, 52 {"PTIO", BIT(7)}, 53 54 {"USBR0", BIT(0)}, 55 {"SBR16B22", BIT(1)}, 56 {"SMT1", BIT(2)}, 57 {"MPFPW1", BIT(3)}, 58 {"SMS2", BIT(4)}, 59 {"SMS1", BIT(5)}, 60 {"CSMERTC", BIT(6)}, 61 {"CSMEPSF", BIT(7)}, 62 63 {"D2D_NOC_0", BIT(0)}, 64 {"ESE", BIT(1)}, 65 {"FIACPCB_P", BIT(2)}, 66 {"RSVD", BIT(3)}, 67 {"SBR8B2", BIT(4)}, 68 {"OSSE_SMT1", BIT(5)}, 69 {"D2D_DISP", BIT(6)}, 70 {"P2SB1", BIT(7)}, 71 72 {"U3FPW1", BIT(0)}, 73 {"SBR16B3", BIT(1)}, 74 {"PSF4", BIT(2)}, 75 {"CNVI", BIT(3)}, 76 {"UFSX2", BIT(4)}, 77 {"ENDBG", BIT(5)}, 78 {"DBC", BIT(6)}, 79 {"SBRG", BIT(7)}, 80 81 {"RSVD", BIT(0)}, 82 {"NPK1", BIT(1)}, 83 {"SBR16B7", BIT(2)}, 84 {"SBR16B4", BIT(3)}, 85 {"FIA_XG", BIT(4)}, 86 {"PSF6", BIT(5)}, 87 {"UFSPW1", BIT(6)}, 88 {"FIA_U", BIT(7)}, 89 90 {"PSF8", BIT(0)}, 91 {"PSF0", BIT(1)}, 92 {"RSVD", BIT(2)}, 93 {"FIACPCB_U", BIT(3)}, 94 {"TAM", BIT(4)}, 95 {"SBR16B0", BIT(5)}, 96 {"TBTLSX", BIT(6)}, 97 {"THC0", BIT(7)}, 98 99 {"THC1", BIT(0)}, 100 {"PMC_1", BIT(1)}, 101 {"FIACPCB_XG", BIT(2)}, 102 {"TCSS", BIT(3)}, 103 {"DISP_PGA", BIT(4)}, 104 {"SBR16B20", BIT(5)}, 105 {"SBR8B20", BIT(6)}, 106 {"DBG_SBR", BIT(7)}, 107 108 {"SPC", BIT(0)}, 109 {"ACE_0", BIT(1)}, 110 {"ACE_1", BIT(2)}, 111 {"ACE_2", BIT(3)}, 112 {"ACE_3", BIT(4)}, 113 {"ACE_4", BIT(5)}, 114 {"ACE_5", BIT(6)}, 115 {"ACE_6", BIT(7)}, 116 117 {"ACE_7", BIT(0)}, 118 {"ACE_8", BIT(1)}, 119 {"ACE_9", BIT(2)}, 120 {"ACE_10", BIT(3)}, 121 {"SBR16B2", BIT(4)}, 122 {"SBR8B4", BIT(5)}, 123 {"OSSE", BIT(6)}, 124 {"SBR16B1", BIT(7)}, 125 {} 126}; 127 128static const struct pmc_bit_map *ext_wcl_pcdn_pfear_map[] = { 129 wcl_pcdn_pfear_map, 130 NULL 131}; 132 133static const struct pmc_bit_map wcl_pcdn_ltr_show_map[] = { 134 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 135 {"RSVD", WCL_PMC_LTR_RESERVED}, 136 {"SATA", CNP_PMC_LTR_SATA}, 137 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 138 {"XHCI", CNP_PMC_LTR_XHCI}, 139 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 140 {"ME", CNP_PMC_LTR_ME}, 141 {"SATA1", CNP_PMC_LTR_EVA}, 142 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 143 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 144 {"CNV", CNP_PMC_LTR_CNV}, 145 {"LPSS", CNP_PMC_LTR_LPSS}, 146 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 147 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 148 {"SATA2", PTL_PMC_LTR_SATA2}, 149 {"ESPI", CNP_PMC_LTR_ESPI}, 150 {"SCC", CNP_PMC_LTR_SCC}, 151 {"ISH", CNP_PMC_LTR_ISH}, 152 {"UFSX2", CNP_PMC_LTR_UFSX2}, 153 {"EMMC", CNP_PMC_LTR_EMMC}, 154 {"WIGIG", ICL_PMC_LTR_WIGIG}, 155 {"THC0", TGL_PMC_LTR_THC0}, 156 {"THC1", TGL_PMC_LTR_THC1}, 157 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 158 {"ESE", MTL_PMC_LTR_ESE}, 159 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 160 {"DMI3", ARL_PMC_LTR_DMI3}, 161 {"OSSE", LNL_PMC_LTR_OSSE}, 162 163 /* Below two cannot be used for LTR_IGNORE */ 164 {"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT}, 165 {"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT}, 166 {} 167}; 168 169static const struct pmc_bit_map wcl_pcdn_power_gating_status_0_map[] = { 170 {"PMC_PGD0_PG_STS", BIT(0), 0}, 171 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, 172 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 173 {"XHCI_PGD0_PG_STS", BIT(3), 1}, 174 {"SPA_PGD0_PG_STS", BIT(4), 1}, 175 {"RSVD_5", BIT(5), 0}, 176 {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, 177 {"GBE_PGD0_PG_STS", BIT(7), 1}, 178 {"SBR16B21_PGD0_PG_STS", BIT(8), 0}, 179 {"SBR16B5_PGD0_PG_STS", BIT(9), 0}, 180 {"SBR8B1_PGD0_PG_STS", BIT(10), 0}, 181 {"SBR8B0_PGD0_PG_STS", BIT(11), 0}, 182 {"P2SB0_PG_STS", BIT(12), 1}, 183 {"D2D_DISP_PGD1_PG_STS", BIT(13), 0}, 184 {"LPSS_PGD0_PG_STS", BIT(14), 1}, 185 {"LPC_PGD0_PG_STS", BIT(15), 0}, 186 {"SMB_PGD0_PG_STS", BIT(16), 0}, 187 {"ISH_PGD0_PG_STS", BIT(17), 0}, 188 {"DBG_SBR16B_PGD0_PG_STS", BIT(18), 0}, 189 {"NPK_PGD0_PG_STS", BIT(19), 0}, 190 {"D2D_NOC_PGD1_PG_STS", BIT(20), 0}, 191 {"FIA_P_PGD0_PG_STS", BIT(21), 0}, 192 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 193 {"DBG_PSF_PGD0_PG_STS", BIT(23), 0}, 194 {"DISP_PGA1_PGD0_PG_STS", BIT(24), 0}, 195 {"XDCI_PGD0_PG_STS", BIT(25), 1}, 196 {"EXI_PGD0_PG_STS", BIT(26), 0}, 197 {"CSE_PGD0_PG_STS", BIT(27), 1}, 198 {"KVMCC_PGD0_PG_STS", BIT(28), 1}, 199 {"PMT_PGD0_PG_STS", BIT(29), 1}, 200 {"CLINK_PGD0_PG_STS", BIT(30), 1}, 201 {"PTIO_PGD0_PG_STS", BIT(31), 1}, 202 {} 203}; 204 205static const struct pmc_bit_map wcl_pcdn_power_gating_status_1_map[] = { 206 {"USBR0_PGD0_PG_STS", BIT(0), 1}, 207 {"SBR16B22_PGD0_PG_STS", BIT(1), 0}, 208 {"SMT1_PGD0_PG_STS", BIT(2), 1}, 209 {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, 210 {"SMS2_PGD0_PG_STS", BIT(4), 1}, 211 {"SMS1_PGD0_PG_STS", BIT(5), 1}, 212 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 213 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 214 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 215 {"ESE_PGD0_PG_STS", BIT(9), 1}, 216 {"FIACPCB_P_PGD0_PG_STS", BIT(10), 0}, 217 {"SBR8B2_PGD0_PG_STS", BIT(12), 0}, 218 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, 219 {"D2D_DISP_PGD0_PG_STS", BIT(14), 0}, 220 {"P2SB1_PGD0_PG_STS", BIT(15), 1}, 221 {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, 222 {"SBR16B3_PGD0_PG_STS", BIT(17), 0}, 223 {"PSF4_PGD0_PG_STS", BIT(18), 0}, 224 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 225 {"UFSX2_PGD0_PG_STS", BIT(20), 1}, 226 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 227 {"DBC_PGD0_PG_STS", BIT(22), 0}, 228 {"SBRG_PGD0_PG_STS", BIT(23), 0}, 229 {"NPK_PGD1_PG_STS", BIT(25), 0}, 230 {"SBR16B7_PGD0_PG_STS", BIT(26), 0}, 231 {"SBR16B4_PGD0_PG_STS", BIT(27), 0}, 232 {"FIA_XG_PSF_PGD0_PG_STS", BIT(28), 0}, 233 {"PSF6_PGD0_PG_STS", BIT(29), 0}, 234 {"UFSPW1_PGD0_PG_STS", BIT(30), 0}, 235 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 236 {} 237}; 238 239static const struct pmc_bit_map wcl_pcdn_power_gating_status_2_map[] = { 240 {"PSF8_PGD0_PG_STS", BIT(0), 0}, 241 {"PSF0_PGD0_PG_STS", BIT(1), 0}, 242 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 243 {"TAM_PGD0_PG_STS", BIT(4), 1}, 244 {"SBR16B0_PGD0_PG_STS", BIT(5), 0}, 245 {"TBTLSX_PGD0_PG_STS", BIT(6), 1}, 246 {"THC0_PGD0_PG_STS", BIT(7), 1}, 247 {"THC1_PGD0_PG_STS", BIT(8), 1}, 248 {"PMC_PGD1_PG_STS", BIT(9), 0}, 249 {"FIACPCB_XG_PGD0_PG_STS", BIT(10), 0}, 250 {"TCSS_PGD0_PG_STS", BIT(11), 0}, 251 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, 252 {"SBR8B4_PGD0_PG_STS", BIT(13), 0}, 253 {"SBR8B20_PGD0_PG_STS", BIT(14), 0}, 254 {"DBG_PGD0_PG_STS", BIT(15), 0}, 255 {"SPC_PGD0_PG_STS", BIT(16), 1}, 256 {"ACE_PGD0_PG_STS", BIT(17), 0}, 257 {"ACE_PGD1_PG_STS", BIT(18), 0}, 258 {"ACE_PGD2_PG_STS", BIT(19), 0}, 259 {"ACE_PGD3_PG_STS", BIT(20), 0}, 260 {"ACE_PGD4_PG_STS", BIT(21), 0}, 261 {"ACE_PGD5_PG_STS", BIT(22), 0}, 262 {"ACE_PGD6_PG_STS", BIT(23), 0}, 263 {"ACE_PGD7_PG_STS", BIT(24), 0}, 264 {"ACE_PGD8_PG_STS", BIT(25), 0}, 265 {"ACE_PGD9_PG_STS", BIT(26), 0}, 266 {"ACE_PGD10_PG_STS", BIT(27), 0}, 267 {"SBR16B2_PG_PGD0_PG_STS", BIT(28), 0}, 268 {"SBR16B20_PGD0_PG_STS", BIT(29), 0}, 269 {"OSSE_PGD0_PG_STS", BIT(30), 1}, 270 {"SBR16B1_PGD0_PG_STS", BIT(31), 0}, 271 {} 272}; 273 274static const struct pmc_bit_map wcl_pcdn_d3_status_0_map[] = { 275 {"LPSS_D3_STS", BIT(3), 1}, 276 {"XDCI_D3_STS", BIT(4), 1}, 277 {"XHCI_D3_STS", BIT(5), 1}, 278 {"SPA_D3_STS", BIT(12), 0}, 279 {"SPC_D3_STS", BIT(14), 0}, 280 {"OSSE_D3_STS", BIT(15), 0}, 281 {"ESPISPI_D3_STS", BIT(18), 0}, 282 {"PSTH_D3_STS", BIT(21), 0}, 283 {} 284}; 285 286static const struct pmc_bit_map wcl_pcdn_d3_status_1_map[] = { 287 {"OSSE_SMT1_D3_STS", BIT(16), 0}, 288 {"GBE_D3_STS", BIT(19), 0}, 289 {"ITSS_D3_STS", BIT(23), 0}, 290 {"CNVI_D3_STS", BIT(27), 0}, 291 {"UFSX2_D3_STS", BIT(28), 0}, 292 {} 293}; 294 295static const struct pmc_bit_map wcl_pcdn_d3_status_2_map[] = { 296 {"CSMERTC_D3_STS", BIT(1), 0}, 297 {"ESE_D3_STS", BIT(2), 0}, 298 {"CSE_D3_STS", BIT(4), 0}, 299 {"KVMCC_D3_STS", BIT(5), 0}, 300 {"USBR0_D3_STS", BIT(6), 0}, 301 {"ISH_D3_STS", BIT(7), 0}, 302 {"SMT1_D3_STS", BIT(8), 0}, 303 {"SMT2_D3_STS", BIT(9), 0}, 304 {"SMT3_D3_STS", BIT(10), 0}, 305 {"CLINK_D3_STS", BIT(14), 0}, 306 {"PTIO_D3_STS", BIT(16), 0}, 307 {"PMT_D3_STS", BIT(17), 0}, 308 {"SMS1_D3_STS", BIT(18), 0}, 309 {"SMS2_D3_STS", BIT(19), 0}, 310 {"OSSE_SMT2_D3_STS", BIT(22), 0}, 311 {} 312}; 313 314static const struct pmc_bit_map wcl_pcdn_d3_status_3_map[] = { 315 {"THC0_D3_STS", BIT(14), 1}, 316 {"THC1_D3_STS", BIT(15), 1}, 317 {"OSSE_SMT3_D3_STS", BIT(16), 0}, 318 {"ACE_D3_STS", BIT(23), 0}, 319 {} 320}; 321 322static const struct pmc_bit_map wcl_pcdn_vnn_req_status_0_map[] = { 323 {"LPSS_VNN_REQ_STS", BIT(3), 1}, 324 {"OSSE_VNN_REQ_STS", BIT(15), 1}, 325 {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, 326 {} 327}; 328 329static const struct pmc_bit_map wcl_pcdn_vnn_req_status_1_map[] = { 330 {"NPK_VNN_REQ_STS", BIT(4), 1}, 331 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 332 {"EXI_VNN_REQ_STS", BIT(9), 1}, 333 {"OSSE_SMT1_VNN_REQ_STS", BIT(16), 1}, 334 {"P2D_VNN_REQ_STS", BIT(18), 1}, 335 {"GBE_VNN_REQ_STS", BIT(19), 1}, 336 {"SMB_VNN_REQ_STS", BIT(25), 1}, 337 {"LPC_VNN_REQ_STS", BIT(26), 0}, 338 {} 339}; 340 341static const struct pmc_bit_map wcl_pcdn_vnn_req_status_2_map[] = { 342 {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, 343 {"ESE_VNN_REQ_STS", BIT(2), 1}, 344 {"CSE_VNN_REQ_STS", BIT(4), 1}, 345 {"ISH_VNN_REQ_STS", BIT(7), 1}, 346 {"SMT1_VNN_REQ_STS", BIT(8), 1}, 347 {"CLINK_VNN_REQ_STS", BIT(14), 1}, 348 {"SMS1_VNN_REQ_STS", BIT(18), 1}, 349 {"SMS2_VNN_REQ_STS", BIT(19), 1}, 350 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1}, 351 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, 352 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, 353 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, 354 {"DISP_SHIM_VNN_REQ_STS", BIT(31), 1}, 355 {} 356}; 357 358static const struct pmc_bit_map wcl_pcdn_vnn_misc_status_map[] = { 359 {"CPU_C10_REQ_STS", BIT(0), 0}, 360 {"TS_OFF_REQ_STS", BIT(1), 0}, 361 {"PNDE_MET_REQ_STS", BIT(2), 1}, 362 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 363 {"VNN_SOC_REQ_STS", BIT(6), 1}, 364 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 365 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, 366 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, 367 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 368 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 369 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 370 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 371 {"EA_REQ_STS", BIT(15), 0}, 372 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, 373 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 374 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 375 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 376 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 377 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, 378 {"XDCI_ATTACHED_REQ_STS", BIT(24), 1}, 379 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 380 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, 381 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 382 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 383 {"PRE_WAKE2_REQ_STS", BIT(29), 1}, 384 {} 385}; 386 387static const struct pmc_bit_map wcl_pcdn_rsc_status_map[] = { 388 {"Memory", 0, 1}, 389 {"PSF0", 0, 1}, 390 {"PSF6", 0, 1}, 391 {"PSF8", 0, 1}, 392 {"SAF_CFI_LINK", 0, 1}, 393 {"SB", 0, 1}, 394 {} 395}; 396 397static const struct pmc_bit_map *wcl_pcdn_lpm_maps[] = { 398 ptl_pcdp_clocksource_status_map, 399 wcl_pcdn_power_gating_status_0_map, 400 wcl_pcdn_power_gating_status_1_map, 401 wcl_pcdn_power_gating_status_2_map, 402 wcl_pcdn_d3_status_0_map, 403 wcl_pcdn_d3_status_1_map, 404 wcl_pcdn_d3_status_2_map, 405 wcl_pcdn_d3_status_3_map, 406 wcl_pcdn_vnn_req_status_0_map, 407 wcl_pcdn_vnn_req_status_1_map, 408 wcl_pcdn_vnn_req_status_2_map, 409 ptl_pcdp_vnn_req_status_3_map, 410 wcl_pcdn_vnn_misc_status_map, 411 ptl_pcdp_signal_status_map, 412 NULL 413}; 414 415static const struct pmc_bit_map *wcl_pcdn_blk_maps[] = { 416 wcl_pcdn_power_gating_status_0_map, 417 wcl_pcdn_power_gating_status_1_map, 418 wcl_pcdn_power_gating_status_2_map, 419 wcl_pcdn_rsc_status_map, 420 wcl_pcdn_vnn_req_status_0_map, 421 wcl_pcdn_vnn_req_status_1_map, 422 wcl_pcdn_vnn_req_status_2_map, 423 ptl_pcdp_vnn_req_status_3_map, 424 wcl_pcdn_d3_status_0_map, 425 wcl_pcdn_d3_status_1_map, 426 wcl_pcdn_d3_status_2_map, 427 wcl_pcdn_d3_status_3_map, 428 ptl_pcdp_clocksource_status_map, 429 wcl_pcdn_vnn_misc_status_map, 430 ptl_pcdp_signal_status_map, 431 NULL 432}; 433 434static const struct pmc_reg_map wcl_pcdn_reg_map = { 435 .pfear_sts = ext_wcl_pcdn_pfear_map, 436 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 437 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 438 .ltr_show_sts = wcl_pcdn_ltr_show_map, 439 .msr_sts = msr_map, 440 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 441 .regmap_length = WCL_PCD_PMC_MMIO_REG_LEN, 442 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 443 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 444 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 445 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 446 .lpm_num_maps = PTL_LPM_NUM_MAPS, 447 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 448 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 449 .etr3_offset = ETR3_OFFSET, 450 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 451 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 452 .lpm_en_offset = MTL_LPM_EN_OFFSET, 453 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 454 .lpm_sts = wcl_pcdn_lpm_maps, 455 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 456 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 457 .s0ix_blocker_maps = wcl_pcdn_blk_maps, 458 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 459 .num_s0ix_blocker = WCL_NUM_S0IX_BLOCKER, 460 .blocker_req_offset = WCL_BLK_REQ_OFFSET, 461 .lpm_req_guid = PCDN_LPM_REQ_GUID, 462}; 463 464static struct pmc_info wcl_pmc_info_list[] = { 465 { 466 .devid = PMC_DEVID_WCL_PCDN, 467 .map = &wcl_pcdn_reg_map, 468 }, 469 {} 470}; 471 472#define WCL_NPU_PCI_DEV 0xfd3e 473 474/* 475 * Set power state of select devices that do not have drivers to D3 476 * so that they do not block Package C entry. 477 */ 478static void wcl_d3_fixup(void) 479{ 480 pmc_core_set_device_d3(WCL_NPU_PCI_DEV); 481} 482 483static int wcl_resume(struct pmc_dev *pmcdev) 484{ 485 wcl_d3_fixup(); 486 return cnl_resume(pmcdev); 487} 488 489static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 490{ 491 wcl_d3_fixup(); 492 return generic_core_init(pmcdev, pmc_dev_info); 493} 494 495struct pmc_dev_info wcl_pmc_dev = { 496 .pci_func = 2, 497 .regmap_list = wcl_pmc_info_list, 498 .map = &wcl_pcdn_reg_map, 499 .sub_req_show = &pmc_core_substate_blk_req_fops, 500 .suspend = cnl_suspend, 501 .resume = wcl_resume, 502 .init = wcl_core_init, 503 .sub_req = pmc_core_pmt_get_blk_sub_req, 504};
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