spt.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * This file contains platform specific structure definitions
  4 * and init function used by Sunrise Point PCH.
  5 *
  6 * Copyright (c) 2022, Intel Corporation.
  7 * All Rights Reserved.
  8 *
  9 */
 10
 11#include <linux/pci.h>
 12
 13#include "core.h"
 14
 15static const struct pmc_bit_map spt_pll_map[] = {
 16	{"MIPI PLL",			SPT_PMC_BIT_MPHY_CMN_LANE0},
 17	{"GEN2 USB2PCIE2 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE1},
 18	{"DMIPCIE3 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE2},
 19	{"SATA PLL",			SPT_PMC_BIT_MPHY_CMN_LANE3},
 20	{}
 21};
 22
 23static const struct pmc_bit_map spt_mphy_map[] = {
 24	{"MPHY CORE LANE 0",           SPT_PMC_BIT_MPHY_LANE0},
 25	{"MPHY CORE LANE 1",           SPT_PMC_BIT_MPHY_LANE1},
 26	{"MPHY CORE LANE 2",           SPT_PMC_BIT_MPHY_LANE2},
 27	{"MPHY CORE LANE 3",           SPT_PMC_BIT_MPHY_LANE3},
 28	{"MPHY CORE LANE 4",           SPT_PMC_BIT_MPHY_LANE4},
 29	{"MPHY CORE LANE 5",           SPT_PMC_BIT_MPHY_LANE5},
 30	{"MPHY CORE LANE 6",           SPT_PMC_BIT_MPHY_LANE6},
 31	{"MPHY CORE LANE 7",           SPT_PMC_BIT_MPHY_LANE7},
 32	{"MPHY CORE LANE 8",           SPT_PMC_BIT_MPHY_LANE8},
 33	{"MPHY CORE LANE 9",           SPT_PMC_BIT_MPHY_LANE9},
 34	{"MPHY CORE LANE 10",          SPT_PMC_BIT_MPHY_LANE10},
 35	{"MPHY CORE LANE 11",          SPT_PMC_BIT_MPHY_LANE11},
 36	{"MPHY CORE LANE 12",          SPT_PMC_BIT_MPHY_LANE12},
 37	{"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
 38	{"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
 39	{"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
 40	{}
 41};
 42
 43static const struct pmc_bit_map spt_pfear_map[] = {
 44	{"PMC",				SPT_PMC_BIT_PMC},
 45	{"OPI-DMI",			SPT_PMC_BIT_OPI},
 46	{"SPI / eSPI",			SPT_PMC_BIT_SPI},
 47	{"XHCI",			SPT_PMC_BIT_XHCI},
 48	{"SPA",				SPT_PMC_BIT_SPA},
 49	{"SPB",				SPT_PMC_BIT_SPB},
 50	{"SPC",				SPT_PMC_BIT_SPC},
 51	{"GBE",				SPT_PMC_BIT_GBE},
 52	{"SATA",			SPT_PMC_BIT_SATA},
 53	{"HDA-PGD0",			SPT_PMC_BIT_HDA_PGD0},
 54	{"HDA-PGD1",			SPT_PMC_BIT_HDA_PGD1},
 55	{"HDA-PGD2",			SPT_PMC_BIT_HDA_PGD2},
 56	{"HDA-PGD3",			SPT_PMC_BIT_HDA_PGD3},
 57	{"RSVD",			SPT_PMC_BIT_RSVD_0B},
 58	{"LPSS",			SPT_PMC_BIT_LPSS},
 59	{"LPC",				SPT_PMC_BIT_LPC},
 60	{"SMB",				SPT_PMC_BIT_SMB},
 61	{"ISH",				SPT_PMC_BIT_ISH},
 62	{"P2SB",			SPT_PMC_BIT_P2SB},
 63	{"DFX",				SPT_PMC_BIT_DFX},
 64	{"SCC",				SPT_PMC_BIT_SCC},
 65	{"RSVD",			SPT_PMC_BIT_RSVD_0C},
 66	{"FUSE",			SPT_PMC_BIT_FUSE},
 67	{"CAMERA",			SPT_PMC_BIT_CAMREA},
 68	{"RSVD",			SPT_PMC_BIT_RSVD_0D},
 69	{"USB3-OTG",			SPT_PMC_BIT_USB3_OTG},
 70	{"EXI",				SPT_PMC_BIT_EXI},
 71	{"CSE",				SPT_PMC_BIT_CSE},
 72	{"CSME_KVM",			SPT_PMC_BIT_CSME_KVM},
 73	{"CSME_PMT",			SPT_PMC_BIT_CSME_PMT},
 74	{"CSME_CLINK",			SPT_PMC_BIT_CSME_CLINK},
 75	{"CSME_PTIO",			SPT_PMC_BIT_CSME_PTIO},
 76	{"CSME_USBR",			SPT_PMC_BIT_CSME_USBR},
 77	{"CSME_SUSRAM",			SPT_PMC_BIT_CSME_SUSRAM},
 78	{"CSME_SMT",			SPT_PMC_BIT_CSME_SMT},
 79	{"RSVD",			SPT_PMC_BIT_RSVD_1A},
 80	{"CSME_SMS2",			SPT_PMC_BIT_CSME_SMS2},
 81	{"CSME_SMS1",			SPT_PMC_BIT_CSME_SMS1},
 82	{"CSME_RTC",			SPT_PMC_BIT_CSME_RTC},
 83	{"CSME_PSF",			SPT_PMC_BIT_CSME_PSF},
 84	{}
 85};
 86
 87static const struct pmc_bit_map *ext_spt_pfear_map[] = {
 88	/*
 89	 * Check intel_pmc_core_ids[] users of spt_reg_map for
 90	 * a list of core SoCs using this.
 91	 */
 92	spt_pfear_map,
 93	NULL
 94};
 95
 96static const struct pmc_bit_map spt_ltr_show_map[] = {
 97	{"SOUTHPORT_A",		SPT_PMC_LTR_SPA},
 98	{"SOUTHPORT_B",		SPT_PMC_LTR_SPB},
 99	{"SATA",		SPT_PMC_LTR_SATA},
100	{"GIGABIT_ETHERNET",	SPT_PMC_LTR_GBE},
101	{"XHCI",		SPT_PMC_LTR_XHCI},
102	{"Reserved",		SPT_PMC_LTR_RESERVED},
103	{"ME",			SPT_PMC_LTR_ME},
104	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
105	{"EVA",			SPT_PMC_LTR_EVA},
106	{"SOUTHPORT_C",		SPT_PMC_LTR_SPC},
107	{"HD_AUDIO",		SPT_PMC_LTR_AZ},
108	{"LPSS",		SPT_PMC_LTR_LPSS},
109	{"SOUTHPORT_D",		SPT_PMC_LTR_SPD},
110	{"SOUTHPORT_E",		SPT_PMC_LTR_SPE},
111	{"CAMERA",		SPT_PMC_LTR_CAM},
112	{"ESPI",		SPT_PMC_LTR_ESPI},
113	{"SCC",			SPT_PMC_LTR_SCC},
114	{"ISH",			SPT_PMC_LTR_ISH},
115	/* Below two cannot be used for LTR_IGNORE */
116	{"CURRENT_PLATFORM",	SPT_PMC_LTR_CUR_PLT},
117	{"AGGREGATED_SYSTEM",	SPT_PMC_LTR_CUR_ASLT},
118	{}
119};
120
121static const struct pmc_reg_map spt_reg_map = {
122	.pfear_sts = ext_spt_pfear_map,
123	.mphy_sts = spt_mphy_map,
124	.pll_sts = spt_pll_map,
125	.ltr_show_sts = spt_ltr_show_map,
126	.msr_sts = msr_map,
127	.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
128	.slp_s0_res_counter_step = SPT_PMC_SLP_S0_RES_COUNTER_STEP,
129	.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
130	.regmap_length = SPT_PMC_MMIO_REG_LEN,
131	.ppfear0_offset = SPT_PMC_XRAM_PPFEAR0A,
132	.ppfear_buckets = SPT_PPFEAR_NUM_ENTRIES,
133	.pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
134	.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
135	.ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
136	.pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
137};
138
139static const struct pci_device_id spt_pmc_pci_id[] = {
140	{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
141	{ }
142};
143
144static int spt_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
145{
146	/*
147	 * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
148	 * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
149	 * in this case.
150	 */
151	if (!pci_dev_present(spt_pmc_pci_id))
152		return generic_core_init(pmcdev, &cnp_pmc_dev);
153
154	return generic_core_init(pmcdev, pmc_dev_info);
155}
156
157struct pmc_dev_info spt_pmc_dev = {
158	.map = &spt_reg_map,
159	.init = spt_core_init,
160};