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ptl.c
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linux-6.19.14/drivers/platform/x86/intel/pmc/ptl.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains platform specific structure definitions 4 * and init function used by Panther Lake PCH. 5 * 6 * Copyright (c) 2025, Intel Corporation. 7 */ 8 9#include <linux/pci.h> 10 11#include "core.h" 12 13/* PMC SSRAM PMT Telemetry GUIDS */ 14#define PCDP_LPM_REQ_GUID 0x47179370 15 16/* 17 * Die Mapping to Product. 18 * Product PCDDie 19 * PTL-H PCD-H 20 * PTL-P PCD-P 21 * PTL-U PCD-P 22 */ 23 24static const struct pmc_bit_map ptl_pcdp_pfear_map[] = { 25 {"PMC_0", BIT(0)}, 26 {"FUSE_OSSE", BIT(1)}, 27 {"ESPISPI", BIT(2)}, 28 {"XHCI", BIT(3)}, 29 {"SPA", BIT(4)}, 30 {"SPB", BIT(5)}, 31 {"MPFPW2", BIT(6)}, 32 {"GBE", BIT(7)}, 33 34 {"SBR16B20", BIT(0)}, 35 {"SBR8B20", BIT(1)}, 36 {"SBR16B21", BIT(2)}, 37 {"DBG_SBR16B", BIT(3)}, 38 {"OSSE_HOTHAM", BIT(4)}, 39 {"D2D_DISP_1", BIT(5)}, 40 {"LPSS", BIT(6)}, 41 {"LPC", BIT(7)}, 42 43 {"SMB", BIT(0)}, 44 {"ISH", BIT(1)}, 45 {"SBR16B2", BIT(2)}, 46 {"NPK_0", BIT(3)}, 47 {"D2D_NOC_1", BIT(4)}, 48 {"SBR8B2", BIT(5)}, 49 {"FUSE", BIT(6)}, 50 {"SBR16B0", BIT(7)}, 51 52 {"PSF0", BIT(0)}, 53 {"XDCI", BIT(1)}, 54 {"EXI", BIT(2)}, 55 {"CSE", BIT(3)}, 56 {"KVMCC", BIT(4)}, 57 {"PMT", BIT(5)}, 58 {"CLINK", BIT(6)}, 59 {"PTIO", BIT(7)}, 60 61 {"USBR0", BIT(0)}, 62 {"SUSRAM", BIT(1)}, 63 {"SMT1", BIT(2)}, 64 {"MPFPW1", BIT(3)}, 65 {"SMS2", BIT(4)}, 66 {"SMS1", BIT(5)}, 67 {"CSMERTC", BIT(6)}, 68 {"CSMEPSF", BIT(7)}, 69 70 {"D2D_NOC_0", BIT(0)}, 71 {"ESE", BIT(1)}, 72 {"P2SB8B", BIT(2)}, 73 {"SBR16B7", BIT(3)}, 74 {"SBR16B3", BIT(4)}, 75 {"OSSE_SMT1", BIT(5)}, 76 {"D2D_DISP", BIT(6)}, 77 {"DBG_SBR", BIT(7)}, 78 79 {"U3FPW1", BIT(0)}, 80 {"FIA_X", BIT(1)}, 81 {"PSF4", BIT(2)}, 82 {"CNVI", BIT(3)}, 83 {"UFSX2", BIT(4)}, 84 {"ENDBG", BIT(5)}, 85 {"DBC", BIT(6)}, 86 {"FIA_PG", BIT(7)}, 87 88 {"D2D_IPU", BIT(0)}, 89 {"NPK1", BIT(1)}, 90 {"FIACPCB_X", BIT(2)}, 91 {"SBR8B4", BIT(3)}, 92 {"DBG_PSF", BIT(4)}, 93 {"PSF6", BIT(5)}, 94 {"UFSPW1", BIT(6)}, 95 {"FIA_U", BIT(7)}, 96 97 {"PSF8", BIT(0)}, 98 {"SBR16B4", BIT(1)}, 99 {"SBR16B5", BIT(2)}, 100 {"FIACPCB_U", BIT(3)}, 101 {"TAM", BIT(4)}, 102 {"D2D_NOC_2", BIT(5)}, 103 {"TBTLSX", BIT(6)}, 104 {"THC0", BIT(7)}, 105 106 {"THC1", BIT(0)}, 107 {"PMC_1", BIT(1)}, 108 {"SBR8B1", BIT(2)}, 109 {"TCSS", BIT(3)}, 110 {"DISP_PGA", BIT(4)}, 111 {"SBR16B1", BIT(5)}, 112 {"SBRG", BIT(6)}, 113 {"PSF5", BIT(7)}, 114 115 {"P2SB16B", BIT(0)}, 116 {"ACE_0", BIT(1)}, 117 {"ACE_1", BIT(2)}, 118 {"ACE_2", BIT(3)}, 119 {"ACE_3", BIT(4)}, 120 {"ACE_4", BIT(5)}, 121 {"ACE_5", BIT(6)}, 122 {"ACE_6", BIT(7)}, 123 124 {"ACE_7", BIT(0)}, 125 {"ACE_8", BIT(1)}, 126 {"ACE_9", BIT(2)}, 127 {"ACE_10", BIT(3)}, 128 {"FIACPCB_PG", BIT(4)}, 129 {"SBR16B6", BIT(5)}, 130 {"OSSE", BIT(6)}, 131 {"SBR8B0", BIT(7)}, 132 {} 133}; 134 135static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = { 136 ptl_pcdp_pfear_map, 137 NULL 138}; 139 140static const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = { 141 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 142 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 143 {"SATA", CNP_PMC_LTR_SATA}, 144 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 145 {"XHCI", CNP_PMC_LTR_XHCI}, 146 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 147 {"ME", CNP_PMC_LTR_ME}, 148 {"SATA1", CNP_PMC_LTR_EVA}, 149 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 150 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 151 {"CNV", CNP_PMC_LTR_CNV}, 152 {"LPSS", CNP_PMC_LTR_LPSS}, 153 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 154 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 155 {"SATA2", PTL_PMC_LTR_SATA2}, 156 {"ESPI", CNP_PMC_LTR_ESPI}, 157 {"SCC", CNP_PMC_LTR_SCC}, 158 {"ISH", CNP_PMC_LTR_ISH}, 159 {"UFSX2", CNP_PMC_LTR_UFSX2}, 160 {"EMMC", CNP_PMC_LTR_EMMC}, 161 {"WIGIG", ICL_PMC_LTR_WIGIG}, 162 {"THC0", TGL_PMC_LTR_THC0}, 163 {"THC1", TGL_PMC_LTR_THC1}, 164 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 165 {"ESE", MTL_PMC_LTR_ESE}, 166 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 167 {"DMI3", ARL_PMC_LTR_DMI3}, 168 {"OSSE", LNL_PMC_LTR_OSSE}, 169 170 /* Below two cannot be used for LTR_IGNORE */ 171 {"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT}, 172 {"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT}, 173 {} 174}; 175 176const struct pmc_bit_map ptl_pcdp_clocksource_status_map[] = { 177 {"AON2_OFF_STS", BIT(0), 1}, 178 {"AON3_OFF_STS", BIT(1), 0}, 179 {"AON4_OFF_STS", BIT(2), 1}, 180 {"AON5_OFF_STS", BIT(3), 1}, 181 {"AON1_OFF_STS", BIT(4), 0}, 182 {"XTAL_LVM_OFF_STS", BIT(5), 0}, 183 {"MPFPW1_0_PLL_OFF_STS", BIT(6), 1}, 184 {"USB3_PLL_OFF_STS", BIT(8), 1}, 185 {"AON3_SPL_OFF_STS", BIT(9), 1}, 186 {"MPFPW2_0_PLL_OFF_STS", BIT(12), 1}, 187 {"XTAL_AGGR_OFF_STS", BIT(17), 1}, 188 {"USB2_PLL_OFF_STS", BIT(18), 0}, 189 {"SAF_PLL_OFF_STS", BIT(19), 1}, 190 {"SE_TCSS_PLL_OFF_STS", BIT(20), 1}, 191 {"DDI_PLL_OFF_STS", BIT(21), 1}, 192 {"FILTER_PLL_OFF_STS", BIT(22), 1}, 193 {"ACE_PLL_OFF_STS", BIT(24), 0}, 194 {"FABRIC_PLL_OFF_STS", BIT(25), 1}, 195 {"SOC_PLL_OFF_STS", BIT(26), 1}, 196 {"REF_PLL_OFF_STS", BIT(28), 1}, 197 {"IMG_PLL_OFF_STS", BIT(29), 1}, 198 {"RTC_PLL_OFF_STS", BIT(31), 0}, 199 {} 200}; 201 202static const struct pmc_bit_map ptl_pcdp_power_gating_status_0_map[] = { 203 {"PMC_PGD0_PG_STS", BIT(0), 0}, 204 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, 205 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 206 {"XHCI_PGD0_PG_STS", BIT(3), 1}, 207 {"SPA_PGD0_PG_STS", BIT(4), 1}, 208 {"SPB_PGD0_PG_STS", BIT(5), 1}, 209 {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, 210 {"GBE_PGD0_PG_STS", BIT(7), 1}, 211 {"SBR16B20_PGD0_PG_STS", BIT(8), 0}, 212 {"SBR8B20_PGD0_PG_STS", BIT(9), 0}, 213 {"SBR16B21_PGD0_PG_STS", BIT(10), 0}, 214 {"DBG_PGD0_PG_STS", BIT(11), 0}, 215 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(12), 1}, 216 {"D2D_DISP_PGD1_PG_STS", BIT(13), 1}, 217 {"LPSS_PGD0_PG_STS", BIT(14), 1}, 218 {"LPC_PGD0_PG_STS", BIT(15), 0}, 219 {"SMB_PGD0_PG_STS", BIT(16), 0}, 220 {"ISH_PGD0_PG_STS", BIT(17), 0}, 221 {"SBR16B2_PGD0_PG_STS", BIT(18), 0}, 222 {"NPK_PGD0_PG_STS", BIT(19), 0}, 223 {"D2D_NOC_PGD1_PG_STS", BIT(20), 1}, 224 {"SBR8B2_PGD0_PG_STS", BIT(21), 0}, 225 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 226 {"SBR16B0_PGD0_PG_STS", BIT(23), 0}, 227 {"PSF0_PGD0_PG_STS", BIT(24), 0}, 228 {"XDCI_PGD0_PG_STS", BIT(25), 1}, 229 {"EXI_PGD0_PG_STS", BIT(26), 0}, 230 {"CSE_PGD0_PG_STS", BIT(27), 1}, 231 {"KVMCC_PGD0_PG_STS", BIT(28), 1}, 232 {"PMT_PGD0_PG_STS", BIT(29), 1}, 233 {"CLINK_PGD0_PG_STS", BIT(30), 1}, 234 {"PTIO_PGD0_PG_STS", BIT(31), 1}, 235 {} 236}; 237 238static const struct pmc_bit_map ptl_pcdp_power_gating_status_1_map[] = { 239 {"USBR0_PGD0_PG_STS", BIT(0), 1}, 240 {"SUSRAM_PGD0_PG_STS", BIT(1), 1}, 241 {"SMT1_PGD0_PG_STS", BIT(2), 1}, 242 {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, 243 {"SMS2_PGD0_PG_STS", BIT(4), 1}, 244 {"SMS1_PGD0_PG_STS", BIT(5), 1}, 245 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 246 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 247 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 248 {"ESE_PGD0_PG_STS", BIT(9), 1}, 249 {"P2SB8B_PGD0_PG_STS", BIT(10), 1}, 250 {"SBR16B7_PGD0_PG_STS", BIT(11), 0}, 251 {"SBR16B3_PGD0_PG_STS", BIT(12), 0}, 252 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, 253 {"D2D_DISP_PGD0_PG_STS", BIT(14), 1}, 254 {"DBG_SBR_PGD0_PG_STS", BIT(15), 0}, 255 {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, 256 {"FIA_X_PGD0_PG_STS", BIT(17), 0}, 257 {"PSF4_PGD0_PG_STS", BIT(18), 0}, 258 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 259 {"UFSX2_PGD0_PG_STS", BIT(20), 1}, 260 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 261 {"DBC_PGD0_PG_STS", BIT(22), 0}, 262 {"FIA_PG_PGD0_PG_STS", BIT(23), 0}, 263 {"D2D_IPU_PGD0_PG_STS", BIT(24), 1}, 264 {"NPK_PGD1_PG_STS", BIT(25), 0}, 265 {"FIACPCB_X_PGD0_PG_STS", BIT(26), 0}, 266 {"SBR8B4_PGD0_PG_STS", BIT(27), 0}, 267 {"DBG_PSF_PGD0_PG_STS", BIT(28), 0}, 268 {"PSF6_PGD0_PG_STS", BIT(29), 0}, 269 {"UFSPW1_PGD0_PG_STS", BIT(30), 0}, 270 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 271 {} 272}; 273 274static const struct pmc_bit_map ptl_pcdp_power_gating_status_2_map[] = { 275 {"PSF8_PGD0_PG_STS", BIT(0), 0}, 276 {"SBR16B4_PGD0_PG_STS", BIT(1), 0}, 277 {"SBR16B5_PGD0_PG_STS", BIT(2), 0}, 278 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 279 {"TAM_PGD0_PG_STS", BIT(4), 1}, 280 {"D2D_NOC_PGD0_PG_STS", BIT(5), 1}, 281 {"TBTLSX_PGD0_PG_STS", BIT(6), 1}, 282 {"THC0_PGD0_PG_STS", BIT(7), 1}, 283 {"THC1_PGD0_PG_STS", BIT(8), 1}, 284 {"PMC_PGD1_PG_STS", BIT(9), 0}, 285 {"SBR8B1_PGD0_PG_STS", BIT(10), 0}, 286 {"TCSS_PGD0_PG_STS", BIT(11), 0}, 287 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, 288 {"SBR16B1_PGD0_PG_STS", BIT(13), 0}, 289 {"SBRG_PGD0_PG_STS", BIT(14), 0}, 290 {"PSF5_PGD0_PG_STS", BIT(15), 0}, 291 {"P2SB16B_PGD0_PG_STS", BIT(16), 1}, 292 {"ACE_PGD0_PG_STS", BIT(17), 0}, 293 {"ACE_PGD1_PG_STS", BIT(18), 0}, 294 {"ACE_PGD2_PG_STS", BIT(19), 0}, 295 {"ACE_PGD3_PG_STS", BIT(20), 0}, 296 {"ACE_PGD4_PG_STS", BIT(21), 0}, 297 {"ACE_PGD5_PG_STS", BIT(22), 0}, 298 {"ACE_PGD6_PG_STS", BIT(23), 0}, 299 {"ACE_PGD7_PG_STS", BIT(24), 0}, 300 {"ACE_PGD8_PG_STS", BIT(25), 0}, 301 {"ACE_PGD9_PG_STS", BIT(26), 0}, 302 {"ACE_PGD10_PG_STS", BIT(27), 0}, 303 {"FIACPCB_PG_PGD0_PG_STS", BIT(28), 0}, 304 {"SBR16B6_PGD0_PG_STS", BIT(29), 0}, 305 {"OSSE_PGD0_PG_STS", BIT(30), 1}, 306 {"SBR8B0_PGD0_PG_STS", BIT(31), 0}, 307 {} 308}; 309 310static const struct pmc_bit_map ptl_pcdp_d3_status_0_map[] = { 311 {"LPSS_D3_STS", BIT(3), 1}, 312 {"XDCI_D3_STS", BIT(4), 1}, 313 {"XHCI_D3_STS", BIT(5), 1}, 314 {"OSSE_D3_STS", BIT(6), 0}, 315 {"SPA_D3_STS", BIT(12), 0}, 316 {"SPB_D3_STS", BIT(13), 0}, 317 {"ESPISPI_D3_STS", BIT(18), 0}, 318 {"PSTH_D3_STS", BIT(21), 0}, 319 {"OSSE_SMT1_D3_STS", BIT(30), 0}, 320 {} 321}; 322 323static const struct pmc_bit_map ptl_pcdp_d3_status_1_map[] = { 324 {"GBE_D3_STS", BIT(19), 0}, 325 {"ITSS_D3_STS", BIT(23), 0}, 326 {"CNVI_D3_STS", BIT(27), 0}, 327 {"UFSX2_D3_STS", BIT(28), 1}, 328 {"OSSE_HOTHAM_D3_STS", BIT(29), 0}, 329 {"ESE_D3_STS", BIT(30), 0}, 330 {} 331}; 332 333static const struct pmc_bit_map ptl_pcdp_d3_status_2_map[] = { 334 {"CSMERTC_D3_STS", BIT(1), 0}, 335 {"SUSRAM_D3_STS", BIT(2), 0}, 336 {"CSE_D3_STS", BIT(4), 0}, 337 {"KVMCC_D3_STS", BIT(5), 0}, 338 {"USBR0_D3_STS", BIT(6), 0}, 339 {"ISH_D3_STS", BIT(7), 0}, 340 {"SMT1_D3_STS", BIT(8), 0}, 341 {"SMT2_D3_STS", BIT(9), 0}, 342 {"SMT3_D3_STS", BIT(10), 0}, 343 {"OSSE_SMT2_D3_STS", BIT(12), 0}, 344 {"CLINK_D3_STS", BIT(14), 0}, 345 {"PTIO_D3_STS", BIT(16), 0}, 346 {"PMT_D3_STS", BIT(17), 0}, 347 {"SMS1_D3_STS", BIT(18), 0}, 348 {"SMS2_D3_STS", BIT(19), 0}, 349 {} 350}; 351 352static const struct pmc_bit_map ptl_pcdp_d3_status_3_map[] = { 353 {"THC0_D3_STS", BIT(14), 1}, 354 {"THC1_D3_STS", BIT(15), 1}, 355 {"OSSE_SMT3_D3_STS", BIT(18), 0}, 356 {"ACE_D3_STS", BIT(23), 0}, 357 {} 358}; 359 360static const struct pmc_bit_map ptl_pcdp_vnn_req_status_0_map[] = { 361 {"LPSS_VNN_REQ_STS", BIT(3), 1}, 362 {"OSSE_VNN_REQ_STS", BIT(6), 1}, 363 {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, 364 {"OSSE_SMT1_VNN_REQ_STS", BIT(30), 1}, 365 {} 366}; 367 368static const struct pmc_bit_map ptl_pcdp_vnn_req_status_1_map[] = { 369 {"NPK_VNN_REQ_STS", BIT(4), 1}, 370 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 371 {"EXI_VNN_REQ_STS", BIT(9), 1}, 372 {"P2D_VNN_REQ_STS", BIT(18), 1}, 373 {"GBE_VNN_REQ_STS", BIT(19), 1}, 374 {"SMB_VNN_REQ_STS", BIT(25), 1}, 375 {"LPC_VNN_REQ_STS", BIT(26), 0}, 376 {"ESE_VNN_REQ_STS", BIT(30), 1}, 377 {} 378}; 379 380static const struct pmc_bit_map ptl_pcdp_vnn_req_status_2_map[] = { 381 {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, 382 {"CSE_VNN_REQ_STS", BIT(4), 1}, 383 {"ISH_VNN_REQ_STS", BIT(7), 1}, 384 {"SMT1_VNN_REQ_STS", BIT(8), 1}, 385 {"CLINK_VNN_REQ_STS", BIT(14), 1}, 386 {"SMS1_VNN_REQ_STS", BIT(18), 1}, 387 {"SMS2_VNN_REQ_STS", BIT(19), 1}, 388 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1}, 389 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, 390 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, 391 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, 392 {"DISP_SHIM_VNN_REQ_STS", BIT(26), 1}, 393 {} 394}; 395 396const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[] = { 397 {"DTS0_VNN_REQ_STS", BIT(7), 0}, 398 {"GPIOCOM5_VNN_REQ_STS", BIT(11), 1}, 399 {} 400}; 401 402static const struct pmc_bit_map ptl_pcdp_vnn_misc_status_map[] = { 403 {"CPU_C10_REQ_STS", BIT(0), 0}, 404 {"TS_OFF_REQ_STS", BIT(1), 0}, 405 {"PNDE_MET_REQ_STS", BIT(2), 1}, 406 {"PG5_PMA0_REQ_STS", BIT(3), 0}, 407 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 408 {"VNN_SOC_REQ_STS", BIT(6), 1}, 409 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 410 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, 411 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, 412 {"D2D_IPU_QACTIVE_REQ_STS", BIT(10), 1}, 413 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 414 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 415 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 416 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 417 {"EA_REQ_STS", BIT(15), 0}, 418 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, 419 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 420 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 421 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 422 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 423 {"PG5_PMA1_REQ_STS", BIT(22), 0}, 424 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, 425 {"XDCI_ATTACHED_REQ_STS", BIT(24), 1}, 426 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 427 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, 428 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 429 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 430 {"PRE_WAKE2_REQ_STS", BIT(29), 1}, 431 {"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31), 1}, 432 {} 433}; 434 435const struct pmc_bit_map ptl_pcdp_signal_status_map[] = { 436 {"LSX_Wake0_STS", BIT(0), 0}, 437 {"LSX_Wake1_STS", BIT(1), 0}, 438 {"LSX_Wake2_STS", BIT(2), 0}, 439 {"LSX_Wake3_STS", BIT(3), 0}, 440 {"LSX_Wake4_STS", BIT(4), 0}, 441 {"LSX_Wake5_STS", BIT(5), 0}, 442 {"LSX_Wake6_STS", BIT(6), 0}, 443 {"LSX_Wake7_STS", BIT(7), 0}, 444 {"LPSS_Wake0_STS", BIT(8), 1}, 445 {"LPSS_Wake1_STS", BIT(9), 1}, 446 {"Int_Timer_SS_Wake0_STS", BIT(10), 1}, 447 {"Int_Timer_SS_Wake1_STS", BIT(11), 1}, 448 {"Int_Timer_SS_Wake2_STS", BIT(12), 1}, 449 {"Int_Timer_SS_Wake3_STS", BIT(13), 1}, 450 {"Int_Timer_SS_Wake4_STS", BIT(14), 1}, 451 {"Int_Timer_SS_Wake5_STS", BIT(15), 1}, 452 {} 453}; 454 455static const struct pmc_bit_map ptl_pcdp_rsc_status_map[] = { 456 {"Memory", 0, 1}, 457 {"PSF0", 0, 1}, 458 {"PSF4", 0, 1}, 459 {"PSF5", 0, 1}, 460 {"PSF6", 0, 1}, 461 {"PSF8", 0, 1}, 462 {"SAF_CFI_LINK", 0, 1}, 463 {"SB", 0, 1}, 464 {} 465}; 466 467static const struct pmc_bit_map *ptl_pcdp_lpm_maps[] = { 468 ptl_pcdp_clocksource_status_map, 469 ptl_pcdp_power_gating_status_0_map, 470 ptl_pcdp_power_gating_status_1_map, 471 ptl_pcdp_power_gating_status_2_map, 472 ptl_pcdp_d3_status_0_map, 473 ptl_pcdp_d3_status_1_map, 474 ptl_pcdp_d3_status_2_map, 475 ptl_pcdp_d3_status_3_map, 476 ptl_pcdp_vnn_req_status_0_map, 477 ptl_pcdp_vnn_req_status_1_map, 478 ptl_pcdp_vnn_req_status_2_map, 479 ptl_pcdp_vnn_req_status_3_map, 480 ptl_pcdp_vnn_misc_status_map, 481 ptl_pcdp_signal_status_map, 482 NULL 483}; 484 485static const struct pmc_bit_map *ptl_pcdp_blk_maps[] = { 486 ptl_pcdp_power_gating_status_0_map, 487 ptl_pcdp_power_gating_status_1_map, 488 ptl_pcdp_power_gating_status_2_map, 489 ptl_pcdp_rsc_status_map, 490 ptl_pcdp_vnn_req_status_0_map, 491 ptl_pcdp_vnn_req_status_1_map, 492 ptl_pcdp_vnn_req_status_2_map, 493 ptl_pcdp_vnn_req_status_3_map, 494 ptl_pcdp_d3_status_0_map, 495 ptl_pcdp_d3_status_1_map, 496 ptl_pcdp_d3_status_2_map, 497 ptl_pcdp_d3_status_3_map, 498 ptl_pcdp_clocksource_status_map, 499 ptl_pcdp_vnn_misc_status_map, 500 ptl_pcdp_signal_status_map, 501 NULL 502}; 503 504static const struct pmc_reg_map ptl_pcdp_reg_map = { 505 .pfear_sts = ext_ptl_pcdp_pfear_map, 506 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 507 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 508 .ltr_show_sts = ptl_pcdp_ltr_show_map, 509 .msr_sts = msr_map, 510 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 511 .regmap_length = PTL_PCD_PMC_MMIO_REG_LEN, 512 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 513 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 514 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 515 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 516 .lpm_num_maps = PTL_LPM_NUM_MAPS, 517 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 518 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 519 .etr3_offset = ETR3_OFFSET, 520 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 521 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 522 .lpm_en_offset = MTL_LPM_EN_OFFSET, 523 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 524 .lpm_sts = ptl_pcdp_lpm_maps, 525 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 526 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 527 .s0ix_blocker_maps = ptl_pcdp_blk_maps, 528 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 529 .num_s0ix_blocker = PTL_NUM_S0IX_BLOCKER, 530 .blocker_req_offset = PTL_BLK_REQ_OFFSET, 531 .lpm_req_guid = PCDP_LPM_REQ_GUID, 532}; 533 534static struct pmc_info ptl_pmc_info_list[] = { 535 { 536 .devid = PMC_DEVID_PTL_PCDH, 537 .map = &ptl_pcdp_reg_map, 538 }, 539 { 540 .devid = PMC_DEVID_PTL_PCDP, 541 .map = &ptl_pcdp_reg_map, 542 }, 543 {} 544}; 545 546#define PTL_NPU_PCI_DEV 0xb03e 547#define PTL_IPU_PCI_DEV 0xb05d 548 549/* 550 * Set power state of select devices that do not have drivers to D3 551 * so that they do not block Package C entry. 552 */ 553static void ptl_d3_fixup(void) 554{ 555 pmc_core_set_device_d3(PTL_IPU_PCI_DEV); 556 pmc_core_set_device_d3(PTL_NPU_PCI_DEV); 557} 558 559static int ptl_resume(struct pmc_dev *pmcdev) 560{ 561 ptl_d3_fixup(); 562 return cnl_resume(pmcdev); 563} 564 565static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 566{ 567 ptl_d3_fixup(); 568 return generic_core_init(pmcdev, pmc_dev_info); 569} 570 571struct pmc_dev_info ptl_pmc_dev = { 572 .pci_func = 2, 573 .regmap_list = ptl_pmc_info_list, 574 .map = &ptl_pcdp_reg_map, 575 .sub_req_show = &pmc_core_substate_blk_req_fops, 576 .suspend = cnl_suspend, 577 .resume = ptl_resume, 578 .init = ptl_core_init, 579 .sub_req = pmc_core_pmt_get_blk_sub_req, 580};
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