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mtl.c
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linux-6.19.14/drivers/platform/x86/intel/pmc/mtl.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains platform specific structure definitions 4 * and init function used by Meteor Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11#include <linux/pci.h> 12#include "core.h" 13 14/* PMC SSRAM PMT Telemetry GUIDS */ 15#define SOCP_LPM_REQ_GUID 0x2625030 16#define IOEM_LPM_REQ_GUID 0x4357464 17#define IOEP_LPM_REQ_GUID 0x5077612 18 19static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; 20 21/* 22 * Die Mapping to Product. 23 * Product SOCDie IOEDie PCHDie 24 * MTL-M SOC-M IOE-M None 25 * MTL-P SOC-M IOE-P None 26 * MTL-S SOC-S IOE-P PCH-S 27 */ 28 29const struct pmc_bit_map mtl_socm_pfear_map[] = { 30 {"PMC", BIT(0)}, 31 {"OPI", BIT(1)}, 32 {"SPI", BIT(2)}, 33 {"XHCI", BIT(3)}, 34 {"SPA", BIT(4)}, 35 {"SPB", BIT(5)}, 36 {"SPC", BIT(6)}, 37 {"GBE", BIT(7)}, 38 39 {"SATA", BIT(0)}, 40 {"DSP0", BIT(1)}, 41 {"DSP1", BIT(2)}, 42 {"DSP2", BIT(3)}, 43 {"DSP3", BIT(4)}, 44 {"SPD", BIT(5)}, 45 {"LPSS", BIT(6)}, 46 {"LPC", BIT(7)}, 47 48 {"SMB", BIT(0)}, 49 {"ISH", BIT(1)}, 50 {"P2SB", BIT(2)}, 51 {"NPK_VNN", BIT(3)}, 52 {"SDX", BIT(4)}, 53 {"SPE", BIT(5)}, 54 {"FUSE", BIT(6)}, 55 {"SBR8", BIT(7)}, 56 57 {"RSVD24", BIT(0)}, 58 {"OTG", BIT(1)}, 59 {"EXI", BIT(2)}, 60 {"CSE", BIT(3)}, 61 {"CSME_KVM", BIT(4)}, 62 {"CSME_PMT", BIT(5)}, 63 {"CSME_CLINK", BIT(6)}, 64 {"CSME_PTIO", BIT(7)}, 65 66 {"CSME_USBR", BIT(0)}, 67 {"CSME_SUSRAM", BIT(1)}, 68 {"CSME_SMT1", BIT(2)}, 69 {"RSVD35", BIT(3)}, 70 {"CSME_SMS2", BIT(4)}, 71 {"CSME_SMS", BIT(5)}, 72 {"CSME_RTC", BIT(6)}, 73 {"CSME_PSF", BIT(7)}, 74 75 {"SBR0", BIT(0)}, 76 {"SBR1", BIT(1)}, 77 {"SBR2", BIT(2)}, 78 {"SBR3", BIT(3)}, 79 {"SBR4", BIT(4)}, 80 {"SBR5", BIT(5)}, 81 {"RSVD46", BIT(6)}, 82 {"PSF1", BIT(7)}, 83 84 {"PSF2", BIT(0)}, 85 {"PSF3", BIT(1)}, 86 {"PSF4", BIT(2)}, 87 {"CNVI", BIT(3)}, 88 {"UFSX2", BIT(4)}, 89 {"EMMC", BIT(5)}, 90 {"SPF", BIT(6)}, 91 {"SBR6", BIT(7)}, 92 93 {"SBR7", BIT(0)}, 94 {"NPK_AON", BIT(1)}, 95 {"HDA4", BIT(2)}, 96 {"HDA5", BIT(3)}, 97 {"HDA6", BIT(4)}, 98 {"PSF6", BIT(5)}, 99 {"RSVD62", BIT(6)}, 100 {"RSVD63", BIT(7)}, 101 {} 102}; 103 104static const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = { 105 mtl_socm_pfear_map, 106 NULL 107}; 108 109static const struct pmc_bit_map mtl_socm_ltr_show_map[] = { 110 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 111 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 112 {"SATA", CNP_PMC_LTR_SATA}, 113 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 114 {"XHCI", CNP_PMC_LTR_XHCI}, 115 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 116 {"ME", CNP_PMC_LTR_ME}, 117 {"SATA1", CNP_PMC_LTR_EVA}, 118 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 119 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 120 {"CNV", CNP_PMC_LTR_CNV}, 121 {"LPSS", CNP_PMC_LTR_LPSS}, 122 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 123 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 124 {"SATA2", CNP_PMC_LTR_CAM}, 125 {"ESPI", CNP_PMC_LTR_ESPI}, 126 {"SCC", CNP_PMC_LTR_SCC}, 127 {"ISH", CNP_PMC_LTR_ISH}, 128 {"UFSX2", CNP_PMC_LTR_UFSX2}, 129 {"EMMC", CNP_PMC_LTR_EMMC}, 130 {"WIGIG", ICL_PMC_LTR_WIGIG}, 131 {"THC0", TGL_PMC_LTR_THC0}, 132 {"THC1", TGL_PMC_LTR_THC1}, 133 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 134 {"ESE", MTL_PMC_LTR_ESE}, 135 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 136 137 /* Below two cannot be used for LTR_IGNORE */ 138 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 139 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 140 {} 141}; 142 143static const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { 144 {"AON2_OFF_STS", BIT(0)}, 145 {"AON3_OFF_STS", BIT(1)}, 146 {"AON4_OFF_STS", BIT(2)}, 147 {"AON5_OFF_STS", BIT(3)}, 148 {"AON1_OFF_STS", BIT(4)}, 149 {"XTAL_LVM_OFF_STS", BIT(5)}, 150 {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, 151 {"MPFPW1_1_PLL_OFF_STS", BIT(7)}, 152 {"USB3_PLL_OFF_STS", BIT(8)}, 153 {"AON3_SPL_OFF_STS", BIT(9)}, 154 {"MPFPW2_0_PLL_OFF_STS", BIT(12)}, 155 {"MPFPW3_0_PLL_OFF_STS", BIT(13)}, 156 {"XTAL_AGGR_OFF_STS", BIT(17)}, 157 {"USB2_PLL_OFF_STS", BIT(18)}, 158 {"FILTER_PLL_OFF_STS", BIT(22)}, 159 {"ACE_PLL_OFF_STS", BIT(24)}, 160 {"FABRIC_PLL_OFF_STS", BIT(25)}, 161 {"SOC_PLL_OFF_STS", BIT(26)}, 162 {"PCIFAB_PLL_OFF_STS", BIT(27)}, 163 {"REF_PLL_OFF_STS", BIT(28)}, 164 {"IMG_PLL_OFF_STS", BIT(29)}, 165 {"RTC_PLL_OFF_STS", BIT(31)}, 166 {} 167}; 168 169static const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { 170 {"PMC_PGD0_PG_STS", BIT(0)}, 171 {"DMI_PGD0_PG_STS", BIT(1)}, 172 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 173 {"XHCI_PGD0_PG_STS", BIT(3)}, 174 {"SPA_PGD0_PG_STS", BIT(4)}, 175 {"SPB_PGD0_PG_STS", BIT(5)}, 176 {"SPC_PGD0_PG_STS", BIT(6)}, 177 {"GBE_PGD0_PG_STS", BIT(7)}, 178 {"SATA_PGD0_PG_STS", BIT(8)}, 179 {"PSF13_PGD0_PG_STS", BIT(9)}, 180 {"SOC_D2D_PGD3_PG_STS", BIT(10)}, 181 {"MPFPW3_PGD0_PG_STS", BIT(11)}, 182 {"ESE_PGD0_PG_STS", BIT(12)}, 183 {"SPD_PGD0_PG_STS", BIT(13)}, 184 {"LPSS_PGD0_PG_STS", BIT(14)}, 185 {"LPC_PGD0_PG_STS", BIT(15)}, 186 {"SMB_PGD0_PG_STS", BIT(16)}, 187 {"ISH_PGD0_PG_STS", BIT(17)}, 188 {"P2S_PGD0_PG_STS", BIT(18)}, 189 {"NPK_PGD0_PG_STS", BIT(19)}, 190 {"DBG_SBR_PGD0_PG_STS", BIT(20)}, 191 {"SBRG_PGD0_PG_STS", BIT(21)}, 192 {"FUSE_PGD0_PG_STS", BIT(22)}, 193 {"SBR8_PGD0_PG_STS", BIT(23)}, 194 {"SOC_D2D_PGD2_PG_STS", BIT(24)}, 195 {"XDCI_PGD0_PG_STS", BIT(25)}, 196 {"EXI_PGD0_PG_STS", BIT(26)}, 197 {"CSE_PGD0_PG_STS", BIT(27)}, 198 {"KVMCC_PGD0_PG_STS", BIT(28)}, 199 {"PMT_PGD0_PG_STS", BIT(29)}, 200 {"CLINK_PGD0_PG_STS", BIT(30)}, 201 {"PTIO_PGD0_PG_STS", BIT(31)}, 202 {} 203}; 204 205static const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { 206 {"USBR0_PGD0_PG_STS", BIT(0)}, 207 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 208 {"SMT1_PGD0_PG_STS", BIT(2)}, 209 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 210 {"SMS2_PGD0_PG_STS", BIT(4)}, 211 {"SMS1_PGD0_PG_STS", BIT(5)}, 212 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 213 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 214 {"SBR0_PGD0_PG_STS", BIT(8)}, 215 {"SBR1_PGD0_PG_STS", BIT(9)}, 216 {"SBR2_PGD0_PG_STS", BIT(10)}, 217 {"SBR3_PGD0_PG_STS", BIT(11)}, 218 {"U3FPW1_PGD0_PG_STS", BIT(12)}, 219 {"SBR5_PGD0_PG_STS", BIT(13)}, 220 {"MPFPW1_PGD0_PG_STS", BIT(14)}, 221 {"UFSPW1_PGD0_PG_STS", BIT(15)}, 222 {"FIA_X_PGD0_PG_STS", BIT(16)}, 223 {"SOC_D2D_PGD0_PG_STS", BIT(17)}, 224 {"MPFPW2_PGD0_PG_STS", BIT(18)}, 225 {"CNVI_PGD0_PG_STS", BIT(19)}, 226 {"UFSX2_PGD0_PG_STS", BIT(20)}, 227 {"ENDBG_PGD0_PG_STS", BIT(21)}, 228 {"DBG_PSF_PGD0_PG_STS", BIT(22)}, 229 {"SBR6_PGD0_PG_STS", BIT(23)}, 230 {"SBR7_PGD0_PG_STS", BIT(24)}, 231 {"NPK_PGD1_PG_STS", BIT(25)}, 232 {"FIACPCB_X_PGD0_PG_STS", BIT(26)}, 233 {"DBC_PGD0_PG_STS", BIT(27)}, 234 {"FUSEGPSB_PGD0_PG_STS", BIT(28)}, 235 {"PSF6_PGD0_PG_STS", BIT(29)}, 236 {"PSF7_PGD0_PG_STS", BIT(30)}, 237 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 238 {} 239}; 240 241static const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = { 242 {"PSF8_PGD0_PG_STS", BIT(0)}, 243 {"FIA_PGD0_PG_STS", BIT(1)}, 244 {"SOC_D2D_PGD1_PG_STS", BIT(2)}, 245 {"FIA_U_PGD0_PG_STS", BIT(3)}, 246 {"TAM_PGD0_PG_STS", BIT(4)}, 247 {"GBETSN_PGD0_PG_STS", BIT(5)}, 248 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 249 {"THC0_PGD0_PG_STS", BIT(7)}, 250 {"THC1_PGD0_PG_STS", BIT(8)}, 251 {"PMC_PGD1_PG_STS", BIT(9)}, 252 {"GNA_PGD0_PG_STS", BIT(10)}, 253 {"ACE_PGD0_PG_STS", BIT(11)}, 254 {"ACE_PGD1_PG_STS", BIT(12)}, 255 {"ACE_PGD2_PG_STS", BIT(13)}, 256 {"ACE_PGD3_PG_STS", BIT(14)}, 257 {"ACE_PGD4_PG_STS", BIT(15)}, 258 {"ACE_PGD5_PG_STS", BIT(16)}, 259 {"ACE_PGD6_PG_STS", BIT(17)}, 260 {"ACE_PGD7_PG_STS", BIT(18)}, 261 {"ACE_PGD8_PG_STS", BIT(19)}, 262 {"FIA_PGS_PGD0_PG_STS", BIT(20)}, 263 {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)}, 264 {"FUSEPMSB_PGD0_PG_STS", BIT(22)}, 265 {} 266}; 267 268const struct pmc_bit_map mtl_socm_d3_status_0_map[] = { 269 {"LPSS_D3_STS", BIT(3)}, 270 {"XDCI_D3_STS", BIT(4)}, 271 {"XHCI_D3_STS", BIT(5)}, 272 {"SPA_D3_STS", BIT(12)}, 273 {"SPB_D3_STS", BIT(13)}, 274 {"SPC_D3_STS", BIT(14)}, 275 {"SPD_D3_STS", BIT(15)}, 276 {"ESPISPI_D3_STS", BIT(18)}, 277 {"SATA_D3_STS", BIT(20)}, 278 {"PSTH_D3_STS", BIT(21)}, 279 {"DMI_D3_STS", BIT(22)}, 280 {} 281}; 282 283const struct pmc_bit_map mtl_socm_d3_status_1_map[] = { 284 {"GBETSN1_D3_STS", BIT(14)}, 285 {"GBE_D3_STS", BIT(19)}, 286 {"ITSS_D3_STS", BIT(23)}, 287 {"P2S_D3_STS", BIT(24)}, 288 {"CNVI_D3_STS", BIT(27)}, 289 {"UFSX2_D3_STS", BIT(28)}, 290 {} 291}; 292 293static const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { 294 {"GNA_D3_STS", BIT(0)}, 295 {"CSMERTC_D3_STS", BIT(1)}, 296 {"SUSRAM_D3_STS", BIT(2)}, 297 {"CSE_D3_STS", BIT(4)}, 298 {"KVMCC_D3_STS", BIT(5)}, 299 {"USBR0_D3_STS", BIT(6)}, 300 {"ISH_D3_STS", BIT(7)}, 301 {"SMT1_D3_STS", BIT(8)}, 302 {"SMT2_D3_STS", BIT(9)}, 303 {"SMT3_D3_STS", BIT(10)}, 304 {"CLINK_D3_STS", BIT(14)}, 305 {"PTIO_D3_STS", BIT(16)}, 306 {"PMT_D3_STS", BIT(17)}, 307 {"SMS1_D3_STS", BIT(18)}, 308 {"SMS2_D3_STS", BIT(19)}, 309 {} 310}; 311 312static const struct pmc_bit_map mtl_socm_d3_status_3_map[] = { 313 {"ESE_D3_STS", BIT(2)}, 314 {"GBETSN_D3_STS", BIT(13)}, 315 {"THC0_D3_STS", BIT(14)}, 316 {"THC1_D3_STS", BIT(15)}, 317 {"ACE_D3_STS", BIT(23)}, 318 {} 319}; 320 321const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] = { 322 {"LPSS_VNN_REQ_STS", BIT(3)}, 323 {"FIA_VNN_REQ_STS", BIT(17)}, 324 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 325 {} 326}; 327 328const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] = { 329 {"NPK_VNN_REQ_STS", BIT(4)}, 330 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 331 {"EXI_VNN_REQ_STS", BIT(9)}, 332 {"P2D_VNN_REQ_STS", BIT(18)}, 333 {"GBE_VNN_REQ_STS", BIT(19)}, 334 {"SMB_VNN_REQ_STS", BIT(25)}, 335 {"LPC_VNN_REQ_STS", BIT(26)}, 336 {} 337}; 338 339const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = { 340 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 341 {"CSE_VNN_REQ_STS", BIT(4)}, 342 {"ISH_VNN_REQ_STS", BIT(7)}, 343 {"SMT1_VNN_REQ_STS", BIT(8)}, 344 {"CLINK_VNN_REQ_STS", BIT(14)}, 345 {"SMS1_VNN_REQ_STS", BIT(18)}, 346 {"SMS2_VNN_REQ_STS", BIT(19)}, 347 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 348 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 349 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 350 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 351 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 352 {} 353}; 354 355static const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = { 356 {"ESE_VNN_REQ_STS", BIT(2)}, 357 {"DTS0_VNN_REQ_STS", BIT(7)}, 358 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 359 {} 360}; 361 362const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] = { 363 {"CPU_C10_REQ_STS", BIT(0)}, 364 {"TS_OFF_REQ_STS", BIT(1)}, 365 {"PNDE_MET_REQ_STS", BIT(2)}, 366 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 367 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 368 {"NPK_VNNAON_REQ_STS", BIT(5)}, 369 {"VNN_SOC_REQ_STS", BIT(6)}, 370 {"ISH_VNNAON_REQ_STS", BIT(7)}, 371 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)}, 372 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)}, 373 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)}, 374 {"PLT_GREATER_REQ_STS", BIT(11)}, 375 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 376 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 377 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 378 {"EA_REQ_STS", BIT(15)}, 379 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 380 {"BRK_EV_EN_REQ_STS", BIT(17)}, 381 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 382 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 383 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 384 {"ARC_IDLE_REQ_STS", BIT(21)}, 385 {"MPHY_SUS_REQ_STS", BIT(22)}, 386 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 387 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 388 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 389 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 390 {"PRE_WAKE0_REQ_STS", BIT(27)}, 391 {"PRE_WAKE1_REQ_STS", BIT(28)}, 392 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 393 {"WOV_REQ_STS", BIT(30)}, 394 {"CNVI_V1P05_REQ_STS", BIT(31)}, 395 {} 396}; 397 398const struct pmc_bit_map mtl_socm_signal_status_map[] = { 399 {"LSX_Wake0_En_STS", BIT(0)}, 400 {"LSX_Wake0_Pol_STS", BIT(1)}, 401 {"LSX_Wake1_En_STS", BIT(2)}, 402 {"LSX_Wake1_Pol_STS", BIT(3)}, 403 {"LSX_Wake2_En_STS", BIT(4)}, 404 {"LSX_Wake2_Pol_STS", BIT(5)}, 405 {"LSX_Wake3_En_STS", BIT(6)}, 406 {"LSX_Wake3_Pol_STS", BIT(7)}, 407 {"LSX_Wake4_En_STS", BIT(8)}, 408 {"LSX_Wake4_Pol_STS", BIT(9)}, 409 {"LSX_Wake5_En_STS", BIT(10)}, 410 {"LSX_Wake5_Pol_STS", BIT(11)}, 411 {"LSX_Wake6_En_STS", BIT(12)}, 412 {"LSX_Wake6_Pol_STS", BIT(13)}, 413 {"LSX_Wake7_En_STS", BIT(14)}, 414 {"LSX_Wake7_Pol_STS", BIT(15)}, 415 {"LPSS_Wake0_En_STS", BIT(16)}, 416 {"LPSS_Wake0_Pol_STS", BIT(17)}, 417 {"LPSS_Wake1_En_STS", BIT(18)}, 418 {"LPSS_Wake1_Pol_STS", BIT(19)}, 419 {"Int_Timer_SS_Wake0_En_STS", BIT(20)}, 420 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)}, 421 {"Int_Timer_SS_Wake1_En_STS", BIT(22)}, 422 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)}, 423 {"Int_Timer_SS_Wake2_En_STS", BIT(24)}, 424 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)}, 425 {"Int_Timer_SS_Wake3_En_STS", BIT(26)}, 426 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)}, 427 {"Int_Timer_SS_Wake4_En_STS", BIT(28)}, 428 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)}, 429 {"Int_Timer_SS_Wake5_En_STS", BIT(30)}, 430 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)}, 431 {} 432}; 433 434static const struct pmc_bit_map *mtl_socm_lpm_maps[] = { 435 mtl_socm_clocksource_status_map, 436 mtl_socm_power_gating_status_0_map, 437 mtl_socm_power_gating_status_1_map, 438 mtl_socm_power_gating_status_2_map, 439 mtl_socm_d3_status_0_map, 440 mtl_socm_d3_status_1_map, 441 mtl_socm_d3_status_2_map, 442 mtl_socm_d3_status_3_map, 443 mtl_socm_vnn_req_status_0_map, 444 mtl_socm_vnn_req_status_1_map, 445 mtl_socm_vnn_req_status_2_map, 446 mtl_socm_vnn_req_status_3_map, 447 mtl_socm_vnn_misc_status_map, 448 mtl_socm_signal_status_map, 449 NULL 450}; 451 452const struct pmc_reg_map mtl_socm_reg_map = { 453 .pfear_sts = ext_mtl_socm_pfear_map, 454 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 455 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 456 .ltr_show_sts = mtl_socm_ltr_show_map, 457 .msr_sts = msr_map, 458 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 459 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN, 460 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 461 .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES, 462 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 463 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 464 .lpm_num_maps = ADL_LPM_NUM_MAPS, 465 .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED, 466 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 467 .etr3_offset = ETR3_OFFSET, 468 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 469 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 470 .lpm_en_offset = MTL_LPM_EN_OFFSET, 471 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 472 .lpm_sts = mtl_socm_lpm_maps, 473 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 474 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 475 .lpm_reg_index = MTL_LPM_REG_INDEX, 476 .lpm_req_guid = SOCP_LPM_REQ_GUID, 477}; 478 479static const struct pmc_bit_map mtl_ioep_pfear_map[] = { 480 {"PMC_0", BIT(0)}, 481 {"OPI", BIT(1)}, 482 {"TCSS", BIT(2)}, 483 {"RSVD3", BIT(3)}, 484 {"SPA", BIT(4)}, 485 {"SPB", BIT(5)}, 486 {"SPC", BIT(6)}, 487 {"IOE_D2D_3", BIT(7)}, 488 489 {"RSVD8", BIT(0)}, 490 {"RSVD9", BIT(1)}, 491 {"SPE", BIT(2)}, 492 {"RSVD11", BIT(3)}, 493 {"RSVD12", BIT(4)}, 494 {"SPD", BIT(5)}, 495 {"ACE_7", BIT(6)}, 496 {"RSVD15", BIT(7)}, 497 498 {"ACE_0", BIT(0)}, 499 {"FIACPCB_P", BIT(1)}, 500 {"P2S", BIT(2)}, 501 {"RSVD19", BIT(3)}, 502 {"ACE_8", BIT(4)}, 503 {"IOE_D2D_0", BIT(5)}, 504 {"FUSE", BIT(6)}, 505 {"RSVD23", BIT(7)}, 506 507 {"FIACPCB_P5", BIT(0)}, 508 {"ACE_3", BIT(1)}, 509 {"RSF5", BIT(2)}, 510 {"ACE_2", BIT(3)}, 511 {"ACE_4", BIT(4)}, 512 {"RSVD29", BIT(5)}, 513 {"RSF10", BIT(6)}, 514 {"MPFPW5", BIT(7)}, 515 516 {"PSF9", BIT(0)}, 517 {"MPFPW4", BIT(1)}, 518 {"RSVD34", BIT(2)}, 519 {"RSVD35", BIT(3)}, 520 {"RSVD36", BIT(4)}, 521 {"RSVD37", BIT(5)}, 522 {"RSVD38", BIT(6)}, 523 {"RSVD39", BIT(7)}, 524 525 {"SBR0", BIT(0)}, 526 {"SBR1", BIT(1)}, 527 {"SBR2", BIT(2)}, 528 {"SBR3", BIT(3)}, 529 {"SBR4", BIT(4)}, 530 {"SBR5", BIT(5)}, 531 {"RSVD46", BIT(6)}, 532 {"RSVD47", BIT(7)}, 533 534 {"RSVD48", BIT(0)}, 535 {"FIA_P5", BIT(1)}, 536 {"RSVD50", BIT(2)}, 537 {"RSVD51", BIT(3)}, 538 {"RSVD52", BIT(4)}, 539 {"RSVD53", BIT(5)}, 540 {"RSVD54", BIT(6)}, 541 {"ACE_1", BIT(7)}, 542 543 {"RSVD56", BIT(0)}, 544 {"ACE_5", BIT(1)}, 545 {"RSVD58", BIT(2)}, 546 {"G5FPW1", BIT(3)}, 547 {"RSVD60", BIT(4)}, 548 {"ACE_6", BIT(5)}, 549 {"RSVD62", BIT(6)}, 550 {"GBETSN1", BIT(7)}, 551 552 {"RSVD64", BIT(0)}, 553 {"FIA", BIT(1)}, 554 {"RSVD66", BIT(2)}, 555 {"FIA_P", BIT(3)}, 556 {"TAM", BIT(4)}, 557 {"GBETSN", BIT(5)}, 558 {"IOE_D2D_2", BIT(6)}, 559 {"IOE_D2D_1", BIT(7)}, 560 561 {"SPF", BIT(0)}, 562 {"PMC_1", BIT(1)}, 563 {} 564}; 565 566static const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = { 567 mtl_ioep_pfear_map, 568 NULL 569}; 570 571static const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { 572 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 573 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 574 {"SATA", CNP_PMC_LTR_SATA}, 575 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 576 {"XHCI", CNP_PMC_LTR_XHCI}, 577 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 578 {"ME", CNP_PMC_LTR_ME}, 579 {"SATA1", CNP_PMC_LTR_EVA}, 580 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 581 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 582 {"CNV", CNP_PMC_LTR_CNV}, 583 {"LPSS", CNP_PMC_LTR_LPSS}, 584 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 585 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 586 {"SATA2", CNP_PMC_LTR_CAM}, 587 {"ESPI", CNP_PMC_LTR_ESPI}, 588 {"SCC", CNP_PMC_LTR_SCC}, 589 {"Reserved", MTL_PMC_LTR_RESERVED}, 590 {"UFSX2", CNP_PMC_LTR_UFSX2}, 591 {"EMMC", CNP_PMC_LTR_EMMC}, 592 {"WIGIG", ICL_PMC_LTR_WIGIG}, 593 {"THC0", TGL_PMC_LTR_THC0}, 594 {"THC1", TGL_PMC_LTR_THC1}, 595 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 596 597 /* Below two cannot be used for LTR_IGNORE */ 598 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 599 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 600 {} 601}; 602 603static const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { 604 {"AON2_OFF_STS", BIT(0)}, 605 {"AON3_OFF_STS", BIT(1)}, 606 {"AON4_OFF_STS", BIT(2)}, 607 {"AON5_OFF_STS", BIT(3)}, 608 {"AON1_OFF_STS", BIT(4)}, 609 {"TBT_PLL_OFF_STS", BIT(5)}, 610 {"TMU_PLL_OFF_STS", BIT(6)}, 611 {"BCLK_PLL_OFF_STS", BIT(7)}, 612 {"D2D_PLL_OFF_STS", BIT(8)}, 613 {"AON3_SPL_OFF_STS", BIT(9)}, 614 {"MPFPW4_0_PLL_OFF_STS", BIT(12)}, 615 {"MPFPW5_0_PLL_OFF_STS", BIT(13)}, 616 {"G5FPW_0_PLL_OFF_STS", BIT(14)}, 617 {"G5FPW_1_PLL_OFF_STS", BIT(15)}, 618 {"XTAL_AGGR_OFF_STS", BIT(17)}, 619 {"FABRIC_PLL_OFF_STS", BIT(25)}, 620 {"SOC_PLL_OFF_STS", BIT(26)}, 621 {"REF_PLL_OFF_STS", BIT(28)}, 622 {"RTC_PLL_OFF_STS", BIT(31)}, 623 {} 624}; 625 626static const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { 627 {"PMC_PGD0_PG_STS", BIT(0)}, 628 {"DMI_PGD0_PG_STS", BIT(1)}, 629 {"TCSS_PGD0_PG_STS", BIT(2)}, 630 {"SPA_PGD0_PG_STS", BIT(4)}, 631 {"SPB_PGD0_PG_STS", BIT(5)}, 632 {"SPC_PGD0_PG_STS", BIT(6)}, 633 {"IOE_D2D_PGD3_PG_STS", BIT(7)}, 634 {"SPE_PGD0_PG_STS", BIT(10)}, 635 {"SPD_PGD0_PG_STS", BIT(13)}, 636 {"ACE_PGD7_PG_STS", BIT(14)}, 637 {"ACE_PGD0_PG_STS", BIT(16)}, 638 {"FIACPCB_P_PGD0_PG_STS", BIT(17)}, 639 {"P2S_PGD0_PG_STS", BIT(18)}, 640 {"ACE_PGD8_PG_STS", BIT(20)}, 641 {"IOE_D2D_PGD0_PG_STS", BIT(21)}, 642 {"FUSE_PGD0_PG_STS", BIT(22)}, 643 {"FIACPCB_P5_PGD0_PG_STS", BIT(24)}, 644 {"ACE_PGD3_PG_STS", BIT(25)}, 645 {"PSF5_PGD0_PG_STS", BIT(26)}, 646 {"ACE_PGD2_PG_STS", BIT(27)}, 647 {"ACE_PGD4_PG_STS", BIT(28)}, 648 {"PSF10_PGD0_PG_STS", BIT(30)}, 649 {"MPFPW5_PGD0_PG_STS", BIT(31)}, 650 {} 651}; 652 653static const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { 654 {"PSF9_PGD0_PG_STS", BIT(0)}, 655 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 656 {"SBR0_PGD0_PG_STS", BIT(8)}, 657 {"SBR1_PGD0_PG_STS", BIT(9)}, 658 {"SBR2_PGD0_PG_STS", BIT(10)}, 659 {"SBR3_PGD0_PG_STS", BIT(11)}, 660 {"SBR4_PGD0_PG_STS", BIT(12)}, 661 {"SBR5_PGD0_PG_STS", BIT(13)}, 662 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 663 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 664 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 665 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 666 {"ACE_PGD6_PG_STS", BIT(29)}, 667 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 668 {} 669}; 670 671static const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { 672 {"FIA_PGD0_PG_STS", BIT(1)}, 673 {"FIA_P_PGD0_PG_STS", BIT(3)}, 674 {"TAM_PGD0_PG_STS", BIT(4)}, 675 {"GBETSN_PGD0_PG_STS", BIT(5)}, 676 {"IOE_D2D_PGD2_PG_STS", BIT(6)}, 677 {"IOE_D2D_PGD1_PG_STS", BIT(7)}, 678 {"SPF_PGD0_PG_STS", BIT(8)}, 679 {"PMC_PGD1_PG_STS", BIT(9)}, 680 {} 681}; 682 683static const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { 684 {"SPF_D3_STS", BIT(0)}, 685 {"SPA_D3_STS", BIT(12)}, 686 {"SPB_D3_STS", BIT(13)}, 687 {"SPC_D3_STS", BIT(14)}, 688 {"SPD_D3_STS", BIT(15)}, 689 {"SPE_D3_STS", BIT(16)}, 690 {"DMI_D3_STS", BIT(22)}, 691 {} 692}; 693 694static const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = { 695 {"GBETSN1_D3_STS", BIT(14)}, 696 {"P2S_D3_STS", BIT(24)}, 697 {} 698}; 699 700static const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = { 701 {} 702}; 703 704static const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = { 705 {"GBETSN_D3_STS", BIT(13)}, 706 {"ACE_D3_STS", BIT(23)}, 707 {} 708}; 709 710static const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = { 711 {"FIA_VNN_REQ_STS", BIT(17)}, 712 {} 713}; 714 715static const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = { 716 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 717 {} 718}; 719 720static const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = { 721 {} 722}; 723 724static const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = { 725 {"DTS0_VNN_REQ_STS", BIT(7)}, 726 {"DISP_VNN_REQ_STS", BIT(19)}, 727 {} 728}; 729 730static const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { 731 {"CPU_C10_REQ_STS", BIT(0)}, 732 {"TS_OFF_REQ_STS", BIT(1)}, 733 {"PNDE_MET_REQ_STS", BIT(2)}, 734 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 735 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 736 {"NPK_VNNAON_REQ_STS", BIT(5)}, 737 {"VNN_SOC_REQ_STS", BIT(6)}, 738 {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)}, 739 {"FIA_EXIT_REQ_STS", BIT(9)}, 740 {"USB2_SUS_PG_REQ_STS", BIT(10)}, 741 {"PLT_GREATER_REQ_STS", BIT(11)}, 742 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 743 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 744 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 745 {"EA_REQ_STS", BIT(15)}, 746 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 747 {"BRK_EV_EN_REQ_STS", BIT(17)}, 748 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 749 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 750 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 751 {"ARC_IDLE_REQ_STS", BIT(21)}, 752 {"MPHY_SUS_REQ_STS", BIT(22)}, 753 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 754 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 755 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 756 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 757 {"PRE_WAKE0_REQ_STS", BIT(27)}, 758 {"PRE_WAKE1_REQ_STS", BIT(28)}, 759 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 760 {"WOV_REQ_STS", BIT(30)}, 761 {"CNVI_V1P05_REQ_STS", BIT(31)}, 762 {} 763}; 764 765static const struct pmc_bit_map *mtl_ioep_lpm_maps[] = { 766 mtl_ioep_clocksource_status_map, 767 mtl_ioep_power_gating_status_0_map, 768 mtl_ioep_power_gating_status_1_map, 769 mtl_ioep_power_gating_status_2_map, 770 mtl_ioep_d3_status_0_map, 771 mtl_ioep_d3_status_1_map, 772 mtl_ioep_d3_status_2_map, 773 mtl_ioep_d3_status_3_map, 774 mtl_ioep_vnn_req_status_0_map, 775 mtl_ioep_vnn_req_status_1_map, 776 mtl_ioep_vnn_req_status_2_map, 777 mtl_ioep_vnn_req_status_3_map, 778 mtl_ioep_vnn_misc_status_map, 779 mtl_socm_signal_status_map, 780 NULL 781}; 782 783const struct pmc_reg_map mtl_ioep_reg_map = { 784 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 785 .pfear_sts = ext_mtl_ioep_pfear_map, 786 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 787 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 788 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 789 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 790 .lpm_sts = mtl_ioep_lpm_maps, 791 .ltr_show_sts = mtl_ioep_ltr_show_map, 792 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 793 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 794 .lpm_num_maps = ADL_LPM_NUM_MAPS, 795 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 796 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 797 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 798 .lpm_en_offset = MTL_LPM_EN_OFFSET, 799 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 800 .lpm_reg_index = MTL_LPM_REG_INDEX, 801 .lpm_req_guid = IOEP_LPM_REQ_GUID, 802}; 803 804static const struct pmc_bit_map mtl_ioem_pfear_map[] = { 805 {"PMC_0", BIT(0)}, 806 {"OPI", BIT(1)}, 807 {"TCSS", BIT(2)}, 808 {"RSVD3", BIT(3)}, 809 {"SPA", BIT(4)}, 810 {"SPB", BIT(5)}, 811 {"SPC", BIT(6)}, 812 {"IOE_D2D_3", BIT(7)}, 813 814 {"RSVD8", BIT(0)}, 815 {"RSVD9", BIT(1)}, 816 {"SPE", BIT(2)}, 817 {"RSVD11", BIT(3)}, 818 {"RSVD12", BIT(4)}, 819 {"SPD", BIT(5)}, 820 {"ACE_7", BIT(6)}, 821 {"RSVD15", BIT(7)}, 822 823 {"ACE_0", BIT(0)}, 824 {"FIACPCB_P", BIT(1)}, 825 {"P2S", BIT(2)}, 826 {"RSVD19", BIT(3)}, 827 {"ACE_8", BIT(4)}, 828 {"IOE_D2D_0", BIT(5)}, 829 {"FUSE", BIT(6)}, 830 {"RSVD23", BIT(7)}, 831 832 {"FIACPCB_P5", BIT(0)}, 833 {"ACE_3", BIT(1)}, 834 {"RSF5", BIT(2)}, 835 {"ACE_2", BIT(3)}, 836 {"ACE_4", BIT(4)}, 837 {"RSVD29", BIT(5)}, 838 {"RSF10", BIT(6)}, 839 {"MPFPW5", BIT(7)}, 840 841 {"PSF9", BIT(0)}, 842 {"MPFPW4", BIT(1)}, 843 {"RSVD34", BIT(2)}, 844 {"RSVD35", BIT(3)}, 845 {"RSVD36", BIT(4)}, 846 {"RSVD37", BIT(5)}, 847 {"RSVD38", BIT(6)}, 848 {"RSVD39", BIT(7)}, 849 850 {"SBR0", BIT(0)}, 851 {"SBR1", BIT(1)}, 852 {"SBR2", BIT(2)}, 853 {"SBR3", BIT(3)}, 854 {"SBR4", BIT(4)}, 855 {"RSVD45", BIT(5)}, 856 {"RSVD46", BIT(6)}, 857 {"RSVD47", BIT(7)}, 858 859 {"RSVD48", BIT(0)}, 860 {"FIA_P5", BIT(1)}, 861 {"RSVD50", BIT(2)}, 862 {"RSVD51", BIT(3)}, 863 {"RSVD52", BIT(4)}, 864 {"RSVD53", BIT(5)}, 865 {"RSVD54", BIT(6)}, 866 {"ACE_1", BIT(7)}, 867 868 {"RSVD56", BIT(0)}, 869 {"ACE_5", BIT(1)}, 870 {"RSVD58", BIT(2)}, 871 {"G5FPW1", BIT(3)}, 872 {"RSVD60", BIT(4)}, 873 {"ACE_6", BIT(5)}, 874 {"RSVD62", BIT(6)}, 875 {"GBETSN1", BIT(7)}, 876 877 {"RSVD64", BIT(0)}, 878 {"FIA", BIT(1)}, 879 {"RSVD66", BIT(2)}, 880 {"FIA_P", BIT(3)}, 881 {"TAM", BIT(4)}, 882 {"GBETSN", BIT(5)}, 883 {"IOE_D2D_2", BIT(6)}, 884 {"IOE_D2D_1", BIT(7)}, 885 886 {"SPF", BIT(0)}, 887 {"PMC_1", BIT(1)}, 888 {} 889}; 890 891static const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = { 892 mtl_ioem_pfear_map, 893 NULL 894}; 895 896static const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { 897 {"PSF9_PGD0_PG_STS", BIT(0)}, 898 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 899 {"SBR0_PGD0_PG_STS", BIT(8)}, 900 {"SBR1_PGD0_PG_STS", BIT(9)}, 901 {"SBR2_PGD0_PG_STS", BIT(10)}, 902 {"SBR3_PGD0_PG_STS", BIT(11)}, 903 {"SBR4_PGD0_PG_STS", BIT(12)}, 904 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 905 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 906 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 907 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 908 {"ACE_PGD6_PG_STS", BIT(29)}, 909 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 910 {} 911}; 912 913static const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { 914 mtl_ioep_clocksource_status_map, 915 mtl_ioep_power_gating_status_0_map, 916 mtl_ioem_power_gating_status_1_map, 917 mtl_ioep_power_gating_status_2_map, 918 mtl_ioep_d3_status_0_map, 919 mtl_ioep_d3_status_1_map, 920 mtl_ioep_d3_status_2_map, 921 mtl_ioep_d3_status_3_map, 922 mtl_ioep_vnn_req_status_0_map, 923 mtl_ioep_vnn_req_status_1_map, 924 mtl_ioep_vnn_req_status_2_map, 925 mtl_ioep_vnn_req_status_3_map, 926 mtl_ioep_vnn_misc_status_map, 927 mtl_socm_signal_status_map, 928 NULL 929}; 930 931static const struct pmc_reg_map mtl_ioem_reg_map = { 932 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 933 .pfear_sts = ext_mtl_ioem_pfear_map, 934 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 935 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 936 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 937 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 938 .lpm_sts = mtl_ioem_lpm_maps, 939 .ltr_show_sts = mtl_ioep_ltr_show_map, 940 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 941 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 942 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 943 .lpm_num_maps = ADL_LPM_NUM_MAPS, 944 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 945 .lpm_en_offset = MTL_LPM_EN_OFFSET, 946 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 947 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 948 .lpm_reg_index = MTL_LPM_REG_INDEX, 949 .lpm_req_guid = IOEM_LPM_REQ_GUID, 950}; 951 952static struct pmc_info mtl_pmc_info_list[] = { 953 { 954 .devid = PMC_DEVID_MTL_SOCM, 955 .map = &mtl_socm_reg_map, 956 }, 957 { 958 .devid = PMC_DEVID_MTL_IOEP, 959 .map = &mtl_ioep_reg_map, 960 }, 961 { 962 .devid = PMC_DEVID_MTL_IOEM, 963 .map = &mtl_ioem_reg_map 964 }, 965 {} 966}; 967 968#define MTL_GNA_PCI_DEV 0x7e4c 969#define MTL_IPU_PCI_DEV 0x7d19 970#define MTL_VPU_PCI_DEV 0x7d1d 971/* 972 * Set power state of select devices that do not have drivers to D3 973 * so that they do not block Package C entry. 974 */ 975static void mtl_d3_fixup(void) 976{ 977 pmc_core_set_device_d3(MTL_GNA_PCI_DEV); 978 pmc_core_set_device_d3(MTL_IPU_PCI_DEV); 979 pmc_core_set_device_d3(MTL_VPU_PCI_DEV); 980} 981 982static int mtl_resume(struct pmc_dev *pmcdev) 983{ 984 mtl_d3_fixup(); 985 986 return cnl_resume(pmcdev); 987} 988 989static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 990{ 991 mtl_d3_fixup(); 992 return generic_core_init(pmcdev, pmc_dev_info); 993} 994 995static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0}; 996struct pmc_dev_info mtl_pmc_dev = { 997 .pci_func = 2, 998 .dmu_guids = MTL_PMT_DMU_GUIDS, 999 .regmap_list = mtl_pmc_info_list, 1000 .map = &mtl_socm_reg_map, 1001 .sub_req_show = &pmc_core_substate_req_regs_fops, 1002 .suspend = cnl_suspend, 1003 .resume = mtl_resume, 1004 .init = mtl_core_init, 1005 .sub_req = pmc_core_pmt_get_lpm_req, 1006};
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