lnl.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * This file contains platform specific structure definitions
  4 * and init function used by Lunar Lake PCH.
  5 *
  6 * Copyright (c) 2022, Intel Corporation.
  7 * All Rights Reserved.
  8 *
  9 */
 10
 11#include <linux/cpu.h>
 12#include <linux/pci.h>
 13
 14#include "core.h"
 15
 16#define SOCM_LPM_REQ_GUID	0x15099748
 17
 18static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
 19
 20static const struct pmc_bit_map lnl_ltr_show_map[] = {
 21	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
 22	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
 23	{"SATA",		CNP_PMC_LTR_SATA},
 24	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
 25	{"XHCI",		CNP_PMC_LTR_XHCI},
 26	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
 27	{"ME",			CNP_PMC_LTR_ME},
 28	/* EVA is Enterprise Value Add, doesn't really exist on PCH */
 29	{"SATA1",		CNP_PMC_LTR_EVA},
 30	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
 31	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
 32	{"CNV",			CNP_PMC_LTR_CNV},
 33	{"LPSS",		CNP_PMC_LTR_LPSS},
 34	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
 35	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
 36	{"SATA2",		CNP_PMC_LTR_CAM},
 37	{"ESPI",		CNP_PMC_LTR_ESPI},
 38	{"SCC",			CNP_PMC_LTR_SCC},
 39	{"ISH",			CNP_PMC_LTR_ISH},
 40	{"UFSX2",		CNP_PMC_LTR_UFSX2},
 41	{"EMMC",		CNP_PMC_LTR_EMMC},
 42	/*
 43	 * Check intel_pmc_core_ids[] users of cnp_reg_map for
 44	 * a list of core SoCs using this.
 45	 */
 46	{"WIGIG",		ICL_PMC_LTR_WIGIG},
 47	{"THC0",		TGL_PMC_LTR_THC0},
 48	{"THC1",		TGL_PMC_LTR_THC1},
 49	{"SOUTHPORT_G",		CNP_PMC_LTR_RESERVED},
 50
 51	{"ESE",			MTL_PMC_LTR_ESE},
 52	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
 53	{"DMI3",		ARL_PMC_LTR_DMI3},
 54	{"OSSE",		LNL_PMC_LTR_OSSE},
 55
 56	/* Below two cannot be used for LTR_IGNORE */
 57	{"CURRENT_PLATFORM",	CNP_PMC_LTR_CUR_PLT},
 58	{"AGGREGATED_SYSTEM",	CNP_PMC_LTR_CUR_ASLT},
 59	{}
 60};
 61
 62static const struct pmc_bit_map lnl_power_gating_status_0_map[] = {
 63	{"PMC_PGD0_PG_STS",			BIT(0),		0},
 64	{"FUSE_OSSE_PGD0_PG_STS",		BIT(1),		0},
 65	{"ESPISPI_PGD0_PG_STS",			BIT(2),		0},
 66	{"XHCI_PGD0_PG_STS",			BIT(3),		1},
 67	{"SPA_PGD0_PG_STS",			BIT(4),		1},
 68	{"SPB_PGD0_PG_STS",			BIT(5),		1},
 69	{"SPR16B0_PGD0_PG_STS",			BIT(6),		0},
 70	{"GBE_PGD0_PG_STS",			BIT(7),		1},
 71	{"SBR8B7_PGD0_PG_STS",			BIT(8),		0},
 72	{"SBR8B6_PGD0_PG_STS",			BIT(9),		0},
 73	{"SBR16B1_PGD0_PG_STS",			BIT(10),	0},
 74	{"SBR8B8_PGD0_PG_STS",			BIT(11),	0},
 75	{"ESE_PGD3_PG_STS",			BIT(12),	1},
 76	{"D2D_DISP_PGD0_PG_STS",		BIT(13),	1},
 77	{"LPSS_PGD0_PG_STS",			BIT(14),	1},
 78	{"LPC_PGD0_PG_STS",			BIT(15),	0},
 79	{"SMB_PGD0_PG_STS",			BIT(16),	0},
 80	{"ISH_PGD0_PG_STS",			BIT(17),	0},
 81	{"SBR8B2_PGD0_PG_STS",			BIT(18),	0},
 82	{"NPK_PGD0_PG_STS",			BIT(19),	0},
 83	{"D2D_NOC_PGD0_PG_STS",			BIT(20),	0},
 84	{"SAFSS_PGD0_PG_STS",			BIT(21),	0},
 85	{"FUSE_PGD0_PG_STS",			BIT(22),	0},
 86	{"D2D_DISP_PGD1_PG_STS",		BIT(23),	1},
 87	{"MPFPW1_PGD0_PG_STS",			BIT(24),	0},
 88	{"XDCI_PGD0_PG_STS",			BIT(25),	1},
 89	{"EXI_PGD0_PG_STS",			BIT(26),	0},
 90	{"CSE_PGD0_PG_STS",			BIT(27),	1},
 91	{"KVMCC_PGD0_PG_STS",			BIT(28),	1},
 92	{"PMT_PGD0_PG_STS",			BIT(29),	1},
 93	{"CLINK_PGD0_PG_STS",			BIT(30),	1},
 94	{"PTIO_PGD0_PG_STS",			BIT(31),	1},
 95	{}
 96};
 97
 98static const struct pmc_bit_map lnl_power_gating_status_1_map[] = {
 99	{"USBR0_PGD0_PG_STS",			BIT(0),		1},
100	{"SUSRAM_PGD0_PG_STS",			BIT(1),		1},
101	{"SMT1_PGD0_PG_STS",			BIT(2),		1},
102	{"U3FPW1_PGD0_PG_STS",			BIT(3),		0},
103	{"SMS2_PGD0_PG_STS",			BIT(4),		1},
104	{"SMS1_PGD0_PG_STS",			BIT(5),		1},
105	{"CSMERTC_PGD0_PG_STS",			BIT(6),		0},
106	{"CSMEPSF_PGD0_PG_STS",			BIT(7),		0},
107	{"FIA_PG_PGD0_PG_STS",			BIT(8),		0},
108	{"SBR16B4_PGD0_PG_STS",			BIT(9),		0},
109	{"P2SB8B_PGD0_PG_STS",			BIT(10),	1},
110	{"DBG_SBR_PGD0_PG_STS",			BIT(11),	0},
111	{"SBR8B9_PGD0_PG_STS",			BIT(12),	0},
112	{"OSSE_SMT1_PGD0_PG_STS",		BIT(13),	1},
113	{"SBR8B10_PGD0_PG_STS",			BIT(14),	0},
114	{"SBR16B3_PGD0_PG_STS",			BIT(15),	0},
115	{"G5FPW1_PGD0_PG_STS",			BIT(16),	0},
116	{"SBRG_PGD0_PG_STS",			BIT(17),	0},
117	{"PSF4_PGD0_PG_STS",			BIT(18),	0},
118	{"CNVI_PGD0_PG_STS",			BIT(19),	0},
119	{"USFX2_PGD0_PG_STS",			BIT(20),	1},
120	{"ENDBG_PGD0_PG_STS",			BIT(21),	0},
121	{"FIACPCB_P5X4_PGD0_PG_STS",		BIT(22),	0},
122	{"SBR8B3_PGD0_PG_STS",			BIT(23),	0},
123	{"SBR8B0_PGD0_PG_STS",			BIT(24),	0},
124	{"NPK_PGD1_PG_STS",			BIT(25),	0},
125	{"OSSE_HOTHAM_PGD0_PG_STS",		BIT(26),	1},
126	{"D2D_NOC_PGD2_PG_STS",			BIT(27),	1},
127	{"SBR8B1_PGD0_PG_STS",			BIT(28),	0},
128	{"PSF6_PGD0_PG_STS",			BIT(29),	0},
129	{"PSF7_PGD0_PG_STS",			BIT(30),	0},
130	{"FIA_U_PGD0_PG_STS",			BIT(31),	0},
131	{}
132};
133
134static const struct pmc_bit_map lnl_power_gating_status_2_map[] = {
135	{"PSF8_PGD0_PG_STS",			BIT(0),		0},
136	{"SBR16B2_PGD0_PG_STS",			BIT(1),		0},
137	{"D2D_IPU_PGD0_PG_STS",			BIT(2),		1},
138	{"FIACPCB_U_PGD0_PG_STS",		BIT(3),		0},
139	{"TAM_PGD0_PG_STS",			BIT(4),		1},
140	{"D2D_NOC_PGD1_PG_STS",			BIT(5),		1},
141	{"TBTLSX_PGD0_PG_STS",			BIT(6),		1},
142	{"THC0_PGD0_PG_STS",			BIT(7),		1},
143	{"THC1_PGD0_PG_STS",			BIT(8),		1},
144	{"PMC_PGD0_PG_STS",			BIT(9),		0},
145	{"SBR8B5_PGD0_PG_STS",			BIT(10),	0},
146	{"UFSPW1_PGD0_PG_STS",			BIT(11),	0},
147	{"DBC_PGD0_PG_STS",			BIT(12),	0},
148	{"TCSS_PGD0_PG_STS",			BIT(13),	0},
149	{"FIA_P5X4_PGD0_PG_STS",		BIT(14),	0},
150	{"DISP_PGA_PGD0_PG_STS",		BIT(15),	0},
151	{"DISP_PSF_PGD0_PG_STS",		BIT(16),	0},
152	{"PSF0_PGD0_PG_STS",			BIT(17),	0},
153	{"P2SB16B_PGD0_PG_STS",			BIT(18),	1},
154	{"ACE_PGD0_PG_STS",			BIT(19),	0},
155	{"ACE_PGD1_PG_STS",			BIT(20),	0},
156	{"ACE_PGD2_PG_STS",			BIT(21),	0},
157	{"ACE_PGD3_PG_STS",			BIT(22),	0},
158	{"ACE_PGD4_PG_STS",			BIT(23),	0},
159	{"ACE_PGD5_PG_STS",			BIT(24),	0},
160	{"ACE_PGD6_PG_STS",			BIT(25),	0},
161	{"ACE_PGD7_PG_STS",			BIT(26),	0},
162	{"ACE_PGD8_PG_STS",			BIT(27),	0},
163	{"ACE_PGD9_PG_STS",			BIT(28),	0},
164	{"ACE_PGD10_PG_STS",			BIT(29),	0},
165	{"FIACPCB_PG_PGD0_PG_STS",		BIT(30),	0},
166	{"OSSE_PGD0_PG_STS",			BIT(31),	1},
167	{}
168};
169
170static const struct pmc_bit_map lnl_d3_status_0_map[] = {
171	{"LPSS_D3_STS",				BIT(3),		1},
172	{"XDCI_D3_STS",				BIT(4),		1},
173	{"XHCI_D3_STS",				BIT(5),		1},
174	{"SPA_D3_STS",				BIT(12),	0},
175	{"SPB_D3_STS",				BIT(13),	0},
176	{"OSSE_D3_STS",				BIT(15),	0},
177	{"ESPISPI_D3_STS",			BIT(18),	0},
178	{"PSTH_D3_STS",				BIT(21),	0},
179	{}
180};
181
182static const struct pmc_bit_map lnl_d3_status_1_map[] = {
183	{"OSSE_SMT1_D3_STS",			BIT(7),		0},
184	{"GBE_D3_STS",				BIT(19),	0},
185	{"ITSS_D3_STS",				BIT(23),	0},
186	{"CNVI_D3_STS",				BIT(27),	0},
187	{"UFSX2_D3_STS",			BIT(28),	1},
188	{"OSSE_HOTHAM_D3_STS",			BIT(31),	0},
189	{}
190};
191
192static const struct pmc_bit_map lnl_d3_status_2_map[] = {
193	{"ESE_D3_STS",				BIT(0),		0},
194	{"CSMERTC_D3_STS",			BIT(1),		0},
195	{"SUSRAM_D3_STS",			BIT(2),		0},
196	{"CSE_D3_STS",				BIT(4),		0},
197	{"KVMCC_D3_STS",			BIT(5),		0},
198	{"USBR0_D3_STS",			BIT(6),		0},
199	{"ISH_D3_STS",				BIT(7),		0},
200	{"SMT1_D3_STS",				BIT(8),		0},
201	{"SMT2_D3_STS",				BIT(9),		0},
202	{"SMT3_D3_STS",				BIT(10),	0},
203	{"OSSE_SMT2_D3_STS",			BIT(13),	0},
204	{"CLINK_D3_STS",			BIT(14),	0},
205	{"PTIO_D3_STS",				BIT(16),	0},
206	{"PMT_D3_STS",				BIT(17),	0},
207	{"SMS1_D3_STS",				BIT(18),	0},
208	{"SMS2_D3_STS",				BIT(19),	0},
209	{}
210};
211
212static const struct pmc_bit_map lnl_d3_status_3_map[] = {
213	{"THC0_D3_STS",				BIT(14),	1},
214	{"THC1_D3_STS",				BIT(15),	1},
215	{"OSSE_SMT3_D3_STS",			BIT(21),	0},
216	{"ACE_D3_STS",				BIT(23),	0},
217	{}
218};
219
220static const struct pmc_bit_map lnl_vnn_req_status_0_map[] = {
221	{"LPSS_VNN_REQ_STS",			BIT(3),		1},
222	{"OSSE_VNN_REQ_STS",			BIT(15),	1},
223	{"ESPISPI_VNN_REQ_STS",			BIT(18),	1},
224	{}
225};
226
227static const struct pmc_bit_map lnl_vnn_req_status_1_map[] = {
228	{"NPK_VNN_REQ_STS",			BIT(4),		1},
229	{"OSSE_SMT1_VNN_REQ_STS",		BIT(7),		1},
230	{"DFXAGG_VNN_REQ_STS",			BIT(8),		0},
231	{"EXI_VNN_REQ_STS",			BIT(9),		1},
232	{"P2D_VNN_REQ_STS",			BIT(18),	1},
233	{"GBE_VNN_REQ_STS",			BIT(19),	1},
234	{"SMB_VNN_REQ_STS",			BIT(25),	1},
235	{"LPC_VNN_REQ_STS",			BIT(26),	0},
236	{}
237};
238
239static const struct pmc_bit_map lnl_vnn_req_status_2_map[] = {
240	{"eSE_VNN_REQ_STS",			BIT(0),		1},
241	{"CSMERTC_VNN_REQ_STS",			BIT(1),		1},
242	{"CSE_VNN_REQ_STS",			BIT(4),		1},
243	{"ISH_VNN_REQ_STS",			BIT(7),		1},
244	{"SMT1_VNN_REQ_STS",			BIT(8),		1},
245	{"CLINK_VNN_REQ_STS",			BIT(14),	1},
246	{"SMS1_VNN_REQ_STS",			BIT(18),	1},
247	{"SMS2_VNN_REQ_STS",			BIT(19),	1},
248	{"GPIOCOM4_VNN_REQ_STS",		BIT(20),	1},
249	{"GPIOCOM3_VNN_REQ_STS",		BIT(21),	1},
250	{"GPIOCOM2_VNN_REQ_STS",		BIT(22),	0},
251	{"GPIOCOM1_VNN_REQ_STS",		BIT(23),	1},
252	{"GPIOCOM0_VNN_REQ_STS",		BIT(24),	1},
253	{}
254};
255
256static const struct pmc_bit_map lnl_vnn_req_status_3_map[] = {
257	{"DISP_SHIM_VNN_REQ_STS",		BIT(2),		0},
258	{"DTS0_VNN_REQ_STS",			BIT(7),		0},
259	{"GPIOCOM5_VNN_REQ_STS",		BIT(11),	2},
260	{}
261};
262
263static const struct pmc_bit_map lnl_vnn_misc_status_map[] = {
264	{"CPU_C10_REQ_STS",			BIT(0),		0},
265	{"TS_OFF_REQ_STS",			BIT(1),		0},
266	{"PNDE_MET_REQ_STS",			BIT(2),		1},
267	{"PCIE_DEEP_PM_REQ_STS",		BIT(3),		0},
268	{"PMC_CLK_THROTTLE_EN_REQ_STS",		BIT(4),		0},
269	{"NPK_VNNAON_REQ_STS",			BIT(5),		0},
270	{"VNN_SOC_REQ_STS",			BIT(6),		1},
271	{"ISH_VNNAON_REQ_STS",			BIT(7),		0},
272	{"D2D_NOC_CFI_QACTIVE_REQ_STS",		BIT(8),		1},
273	{"D2D_NOC_GPSB_QACTIVE_REQ_STS",	BIT(9),		1},
274	{"D2D_NOC_IPU_QACTIVE_REQ_STS",		BIT(10),	1},
275	{"PLT_GREATER_REQ_STS",			BIT(11),	1},
276	{"PCIE_CLKREQ_REQ_STS",			BIT(12),	0},
277	{"PMC_IDLE_FB_OCP_REQ_STS",		BIT(13),	0},
278	{"PM_SYNC_STATES_REQ_STS",		BIT(14),	0},
279	{"EA_REQ_STS",				BIT(15),	0},
280	{"MPHY_CORE_OFF_REQ_STS",		BIT(16),	0},
281	{"BRK_EV_EN_REQ_STS",			BIT(17),	0},
282	{"AUTO_DEMO_EN_REQ_STS",		BIT(18),	0},
283	{"ITSS_CLK_SRC_REQ_STS",		BIT(19),	1},
284	{"LPC_CLK_SRC_REQ_STS",			BIT(20),	0},
285	{"ARC_IDLE_REQ_STS",			BIT(21),	0},
286	{"MPHY_SUS_REQ_STS",			BIT(22),	0},
287	{"FIA_DEEP_PM_REQ_STS",			BIT(23),	0},
288	{"UXD_CONNECTED_REQ_STS",		BIT(24),	1},
289	{"ARC_INTERRUPT_WAKE_REQ_STS",		BIT(25),	0},
290	{"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS",	BIT(26),	1},
291	{"PRE_WAKE0_REQ_STS",			BIT(27),	1},
292	{"PRE_WAKE1_REQ_STS",			BIT(28),	1},
293	{"PRE_WAKE2_EN_REQ_STS",		BIT(29),	1},
294	{"WOV_REQ_STS",				BIT(30),	0},
295	{"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31",	BIT(31),	1},
296	{}
297};
298
299static const struct pmc_bit_map lnl_clocksource_status_map[] = {
300	{"AON2_OFF_STS",			BIT(0),		0},
301	{"AON3_OFF_STS",			BIT(1),		1},
302	{"AON4_OFF_STS",			BIT(2),		1},
303	{"AON5_OFF_STS",			BIT(3),		1},
304	{"AON1_OFF_STS",			BIT(4),		0},
305	{"MPFPW1_0_PLL_OFF_STS",		BIT(6),		1},
306	{"USB3_PLL_OFF_STS",			BIT(8),		1},
307	{"AON3_SPL_OFF_STS",			BIT(9),		1},
308	{"G5FPW1_PLL_OFF_STS",			BIT(15),	1},
309	{"XTAL_AGGR_OFF_STS",			BIT(17),	1},
310	{"USB2_PLL_OFF_STS",			BIT(18),	0},
311	{"SAF_PLL_OFF_STS",			BIT(19),	1},
312	{"SE_TCSS_PLL_OFF_STS",			BIT(20),	1},
313	{"DDI_PLL_OFF_STS",			BIT(21),	1},
314	{"FILTER_PLL_OFF_STS",			BIT(22),	1},
315	{"ACE_PLL_OFF_STS",			BIT(24),	0},
316	{"FABRIC_PLL_OFF_STS",			BIT(25),	1},
317	{"SOC_PLL_OFF_STS",			BIT(26),	1},
318	{"REF_OFF_STS",				BIT(28),	1},
319	{"IMG_OFF_STS",				BIT(29),	1},
320	{"RTC_PLL_OFF_STS",			BIT(31),	0},
321	{}
322};
323
324static const struct pmc_bit_map lnl_signal_status_map[] = {
325	{"LSX_Wake0_STS",			BIT(0),		0},
326	{"LSX_Wake1_STS",			BIT(1),		0},
327	{"LSX_Wake2_STS",			BIT(2),		0},
328	{"LSX_Wake3_STS",			BIT(3),		0},
329	{"LSX_Wake4_STS",			BIT(4),		0},
330	{"LSX_Wake5_STS",			BIT(5),		0},
331	{"LSX_Wake6_STS",			BIT(6),		0},
332	{"LSX_Wake7_STS",			BIT(7),		0},
333	{"LPSS_Wake0_STS",			BIT(8),		1},
334	{"LPSS_Wake1_STS",			BIT(9),		1},
335	{"Int_Timer_SS_Wake0_STS",		BIT(10),	1},
336	{"Int_Timer_SS_Wake1_STS",		BIT(11),	1},
337	{"Int_Timer_SS_Wake2_STS",		BIT(12),	1},
338	{"Int_Timer_SS_Wake3_STS",		BIT(13),	1},
339	{"Int_Timer_SS_Wake4_STS",		BIT(14),	1},
340	{"Int_Timer_SS_Wake5_STS",		BIT(15),	1},
341	{}
342};
343
344static const struct pmc_bit_map lnl_rsc_status_map[] = {
345	{"Memory",				0,		1},
346	{"PSF0",				0,		1},
347	{"PSF4",				0,		1},
348	{"PSF6",				0,		1},
349	{"PSF7",				0,		1},
350	{"PSF8",				0,		1},
351	{"SAF_CFI_LINK",			0,		1},
352	{"SBR",					0,		1},
353	{}
354};
355
356static const struct pmc_bit_map *lnl_lpm_maps[] = {
357	lnl_clocksource_status_map,
358	lnl_power_gating_status_0_map,
359	lnl_power_gating_status_1_map,
360	lnl_power_gating_status_2_map,
361	lnl_d3_status_0_map,
362	lnl_d3_status_1_map,
363	lnl_d3_status_2_map,
364	lnl_d3_status_3_map,
365	lnl_vnn_req_status_0_map,
366	lnl_vnn_req_status_1_map,
367	lnl_vnn_req_status_2_map,
368	lnl_vnn_req_status_3_map,
369	lnl_vnn_misc_status_map,
370	lnl_signal_status_map,
371	NULL
372};
373
374static const struct pmc_bit_map *lnl_blk_maps[] = {
375	lnl_power_gating_status_0_map,
376	lnl_power_gating_status_1_map,
377	lnl_power_gating_status_2_map,
378	lnl_rsc_status_map,
379	lnl_vnn_req_status_0_map,
380	lnl_vnn_req_status_1_map,
381	lnl_vnn_req_status_2_map,
382	lnl_vnn_req_status_3_map,
383	lnl_d3_status_0_map,
384	lnl_d3_status_1_map,
385	lnl_d3_status_2_map,
386	lnl_d3_status_3_map,
387	lnl_clocksource_status_map,
388	lnl_vnn_misc_status_map,
389	lnl_signal_status_map,
390	NULL
391};
392
393static const struct pmc_bit_map lnl_pfear_map[] = {
394	{"PMC_0",			BIT(0)},
395	{"FUSE_OSSE",			BIT(1)},
396	{"ESPISPI",			BIT(2)},
397	{"XHCI",			BIT(3)},
398	{"SPA",				BIT(4)},
399	{"SPB",				BIT(5)},
400	{"SBR16B0",			BIT(6)},
401	{"GBE",				BIT(7)},
402
403	{"SBR8B7",			BIT(0)},
404	{"SBR8B6",			BIT(1)},
405	{"SBR16B1",			BIT(1)},
406	{"SBR8B8",			BIT(2)},
407	{"ESE",				BIT(3)},
408	{"SBR8B10",			BIT(4)},
409	{"D2D_DISP_0",			BIT(5)},
410	{"LPSS",			BIT(6)},
411	{"LPC",				BIT(7)},
412
413	{"SMB",				BIT(0)},
414	{"ISH",				BIT(1)},
415	{"SBR8B2",			BIT(2)},
416	{"NPK_0",			BIT(3)},
417	{"D2D_NOC_0",			BIT(4)},
418	{"SAFSS",			BIT(5)},
419	{"FUSE",			BIT(6)},
420	{"D2D_DISP_1",			BIT(7)},
421
422	{"MPFPW1",			BIT(0)},
423	{"XDCI",			BIT(1)},
424	{"EXI",				BIT(2)},
425	{"CSE",				BIT(3)},
426	{"KVMCC",			BIT(4)},
427	{"PMT",				BIT(5)},
428	{"CLINK",			BIT(6)},
429	{"PTIO",			BIT(7)},
430
431	{"USBR",			BIT(0)},
432	{"SUSRAM",			BIT(1)},
433	{"SMT1",			BIT(2)},
434	{"U3FPW1",			BIT(3)},
435	{"SMS2",			BIT(4)},
436	{"SMS1",			BIT(5)},
437	{"CSMERTC",			BIT(6)},
438	{"CSMEPSF",			BIT(7)},
439
440	{"FIA_PG",			BIT(0)},
441	{"SBR16B4",			BIT(1)},
442	{"P2SB8B",			BIT(2)},
443	{"DBG_SBR",			BIT(3)},
444	{"SBR8B9",			BIT(4)},
445	{"OSSE_SMT1",			BIT(5)},
446	{"SBR8B10",			BIT(6)},
447	{"SBR16B3",			BIT(7)},
448
449	{"G5FPW1",			BIT(0)},
450	{"SBRG",			BIT(1)},
451	{"PSF4",			BIT(2)},
452	{"CNVI",			BIT(3)},
453	{"UFSX2",			BIT(4)},
454	{"ENDBG",			BIT(5)},
455	{"FIACPCB_P5X4",		BIT(6)},
456	{"SBR8B3",			BIT(7)},
457
458	{"SBR8B0",			BIT(0)},
459	{"NPK_1",			BIT(1)},
460	{"OSSE_HOTHAM",			BIT(2)},
461	{"D2D_NOC_2",			BIT(3)},
462	{"SBR8B1",			BIT(4)},
463	{"PSF6",			BIT(5)},
464	{"PSF7",			BIT(6)},
465	{"FIA_U",			BIT(7)},
466
467	{"PSF8",			BIT(0)},
468	{"SBR16B2",			BIT(1)},
469	{"D2D_IPU",			BIT(2)},
470	{"FIACPCB_U",			BIT(3)},
471	{"TAM",				BIT(4)},
472	{"D2D_NOC_1",			BIT(5)},
473	{"TBTLSX",			BIT(6)},
474	{"THC0",			BIT(7)},
475
476	{"THC1",			BIT(0)},
477	{"PMC_1",			BIT(1)},
478	{"SBR8B5",			BIT(2)},
479	{"UFSPW1",			BIT(3)},
480	{"DBC",				BIT(4)},
481	{"TCSS",			BIT(5)},
482	{"FIA_P5X4",			BIT(6)},
483	{"DISP_PGA",			BIT(7)},
484
485	{"DBG_PSF",			BIT(0)},
486	{"PSF0",			BIT(1)},
487	{"P2SB16B",			BIT(2)},
488	{"ACE0",			BIT(3)},
489	{"ACE1",			BIT(4)},
490	{"ACE2",			BIT(5)},
491	{"ACE3",			BIT(6)},
492	{"ACE4",			BIT(7)},
493
494	{"ACE5",			BIT(0)},
495	{"ACE6",			BIT(1)},
496	{"ACE7",			BIT(2)},
497	{"ACE8",			BIT(3)},
498	{"ACE9",			BIT(4)},
499	{"ACE10",			BIT(5)},
500	{"FIACPCB",			BIT(6)},
501	{"OSSE",			BIT(7)},
502	{}
503};
504
505static const struct pmc_bit_map *ext_lnl_pfear_map[] = {
506	lnl_pfear_map,
507	NULL
508};
509
510static const struct pmc_reg_map lnl_socm_reg_map = {
511	.pfear_sts = ext_lnl_pfear_map,
512	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
513	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
514	.ltr_show_sts = lnl_ltr_show_map,
515	.msr_sts = msr_map,
516	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
517	.regmap_length = LNL_PMC_MMIO_REG_LEN,
518	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
519	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
520	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
521	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
522	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
523	.lpm_num_maps = ADL_LPM_NUM_MAPS,
524	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
525	.etr3_offset = ETR3_OFFSET,
526	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
527	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
528	.lpm_en_offset = MTL_LPM_EN_OFFSET,
529	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
530	.lpm_sts = lnl_lpm_maps,
531	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
532	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
533	.s0ix_blocker_maps = lnl_blk_maps,
534	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
535	.lpm_reg_index = LNL_LPM_REG_INDEX,
536	.lpm_req_guid = SOCM_LPM_REQ_GUID,
537};
538
539static struct pmc_info lnl_pmc_info_list[] = {
540	{
541		.devid	= PMC_DEVID_LNL_SOCM,
542		.map	= &lnl_socm_reg_map,
543	},
544	{}
545};
546
547#define LNL_NPU_PCI_DEV		0x643e
548#define LNL_IPU_PCI_DEV		0x645d
549
550/*
551 * Set power state of select devices that do not have drivers to D3
552 * so that they do not block Package C entry.
553 */
554static void lnl_d3_fixup(void)
555{
556	pmc_core_set_device_d3(LNL_IPU_PCI_DEV);
557	pmc_core_set_device_d3(LNL_NPU_PCI_DEV);
558}
559
560static int lnl_resume(struct pmc_dev *pmcdev)
561{
562	lnl_d3_fixup();
563
564	return cnl_resume(pmcdev);
565}
566
567static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
568{
569	lnl_d3_fixup();
570	return generic_core_init(pmcdev, pmc_dev_info);
571}
572
573struct pmc_dev_info lnl_pmc_dev = {
574	.pci_func = 2,
575	.regmap_list = lnl_pmc_info_list,
576	.map = &lnl_socm_reg_map,
577	.sub_req_show = &pmc_core_substate_req_regs_fops,
578	.suspend = cnl_suspend,
579	.resume = lnl_resume,
580	.init = lnl_core_init,
581	.sub_req = pmc_core_pmt_get_lpm_req,
582};