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asus-armoury.h
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linux-6.19.14/drivers/platform/x86/asus-armoury.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Definitions for kernel modules using asus-armoury driver 4 * 5 * Copyright (c) 2024 Luke Jones <luke@ljones.dev> 6 */ 7 8#ifndef _ASUS_ARMOURY_H_ 9#define _ASUS_ARMOURY_H_ 10 11#include <linux/dmi.h> 12#include <linux/platform_device.h> 13#include <linux/sysfs.h> 14#include <linux/types.h> 15 16#define DRIVER_NAME "asus-armoury" 17 18/** 19 * armoury_attr_uint_store() - Send an uint to WMI method if within min/max. 20 * @kobj: Pointer to the driver object. 21 * @attr: Pointer to the attribute calling this function. 22 * @buf: The buffer to read from, this is parsed to `uint` type. 23 * @count: Required by sysfs attribute macros, pass in from the callee attr. 24 * @min: Minimum accepted value. Below this returns -EINVAL. 25 * @max: Maximum accepted value. Above this returns -EINVAL. 26 * @store_value: Pointer to where the parsed value should be stored. 27 * @wmi_dev: The WMI function ID to use. 28 * 29 * This function is intended to be generic so it can be called from any "_store" 30 * attribute which works only with integers. 31 * 32 * Integers to be sent to the WMI method is inclusive range checked and 33 * an error returned if out of range. 34 * 35 * If the value is valid and WMI is success then the sysfs attribute is notified 36 * and if asus_bios_requires_reboot() is true then reboot attribute 37 * is also notified. 38 * 39 * Returns: Either count, or an error. 40 */ 41ssize_t armoury_attr_uint_store(struct kobject *kobj, struct kobj_attribute *attr, 42 const char *buf, size_t count, u32 min, u32 max, 43 u32 *store_value, u32 wmi_dev); 44 45/** 46 * armoury_attr_uint_show() - Receive an uint from a WMI method. 47 * @kobj: Pointer to the driver object. 48 * @attr: Pointer to the attribute calling this function. 49 * @buf: The buffer to write to, as an `uint` type. 50 * @wmi_dev: The WMI function ID to use. 51 * 52 * This function is intended to be generic so it can be called from any "_show" 53 * attribute which works only with integers. 54 * 55 * Returns: Either count, or an error. 56 */ 57ssize_t armoury_attr_uint_show(struct kobject *kobj, struct kobj_attribute *attr, 58 char *buf, u32 wmi_dev); 59 60#define __ASUS_ATTR_RO(_func, _name) \ 61 { \ 62 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 63 .show = _func##_##_name##_show, \ 64 } 65 66#define __ASUS_ATTR_RO_AS(_name, _show) \ 67 { \ 68 .attr = { .name = __stringify(_name), .mode = 0444 }, \ 69 .show = _show, \ 70 } 71 72#define __ASUS_ATTR_RW(_func, _name) \ 73 __ATTR(_name, 0644, _func##_##_name##_show, _func##_##_name##_store) 74 75#define __WMI_STORE_INT(_attr, _min, _max, _wmi) \ 76 static ssize_t _attr##_store(struct kobject *kobj, \ 77 struct kobj_attribute *attr, \ 78 const char *buf, size_t count) \ 79 { \ 80 return armoury_attr_uint_store(kobj, attr, buf, count, _min, \ 81 _max, NULL, _wmi); \ 82 } 83 84#define ASUS_WMI_SHOW_INT(_attr, _wmi) \ 85 static ssize_t _attr##_show(struct kobject *kobj, \ 86 struct kobj_attribute *attr, char *buf) \ 87 { \ 88 return armoury_attr_uint_show(kobj, attr, buf, _wmi); \ 89 } 90 91/* Create functions and attributes for use in other macros or on their own */ 92 93/* Shows a formatted static variable */ 94#define __ATTR_SHOW_FMT(_prop, _attrname, _fmt, _val) \ 95 static ssize_t _attrname##_##_prop##_show( \ 96 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 97 { \ 98 return sysfs_emit(buf, _fmt, _val); \ 99 } \ 100 static struct kobj_attribute attr_##_attrname##_##_prop = \ 101 __ASUS_ATTR_RO(_attrname, _prop) 102 103#define __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname)\ 104 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 105 static struct kobj_attribute attr_##_attrname##_current_value = \ 106 __ASUS_ATTR_RO(_attrname, current_value); \ 107 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 108 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 109 static struct kobj_attribute attr_##_attrname##_type = \ 110 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 111 static struct attribute *_attrname##_attrs[] = { \ 112 &attr_##_attrname##_current_value.attr, \ 113 &attr_##_attrname##_display_name.attr, \ 114 &attr_##_attrname##_possible_values.attr, \ 115 &attr_##_attrname##_type.attr, \ 116 NULL \ 117 }; \ 118 static const struct attribute_group _attrname##_attr_group = { \ 119 .name = _fsname, .attrs = _attrname##_attrs \ 120 } 121 122#define __ATTR_RW_INT_GROUP_ENUM(_attrname, _minv, _maxv, _wmi, _fsname,\ 123 _possible, _dispname) \ 124 __WMI_STORE_INT(_attrname##_current_value, _minv, _maxv, _wmi); \ 125 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 126 static struct kobj_attribute attr_##_attrname##_current_value = \ 127 __ASUS_ATTR_RW(_attrname, current_value); \ 128 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 129 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 130 static struct kobj_attribute attr_##_attrname##_type = \ 131 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 132 static struct attribute *_attrname##_attrs[] = { \ 133 &attr_##_attrname##_current_value.attr, \ 134 &attr_##_attrname##_display_name.attr, \ 135 &attr_##_attrname##_possible_values.attr, \ 136 &attr_##_attrname##_type.attr, \ 137 NULL \ 138 }; \ 139 static const struct attribute_group _attrname##_attr_group = { \ 140 .name = _fsname, .attrs = _attrname##_attrs \ 141 } 142 143/* Boolean style enumeration, base macro. Requires adding show/store */ 144#define __ATTR_GROUP_ENUM(_attrname, _fsname, _possible, _dispname) \ 145 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 146 __ATTR_SHOW_FMT(possible_values, _attrname, "%s\n", _possible); \ 147 static struct kobj_attribute attr_##_attrname##_type = \ 148 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 149 static struct attribute *_attrname##_attrs[] = { \ 150 &attr_##_attrname##_current_value.attr, \ 151 &attr_##_attrname##_display_name.attr, \ 152 &attr_##_attrname##_possible_values.attr, \ 153 &attr_##_attrname##_type.attr, \ 154 NULL \ 155 }; \ 156 static const struct attribute_group _attrname##_attr_group = { \ 157 .name = _fsname, .attrs = _attrname##_attrs \ 158 } 159 160#define ASUS_ATTR_GROUP_BOOL_RO(_attrname, _fsname, _wmi, _dispname) \ 161 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, "0;1", _dispname) 162 163 164#define ASUS_ATTR_GROUP_BOOL_RW(_attrname, _fsname, _wmi, _dispname) \ 165 __ATTR_RW_INT_GROUP_ENUM(_attrname, 0, 1, _wmi, _fsname, "0;1", _dispname) 166 167#define ASUS_ATTR_GROUP_ENUM_INT_RO(_attrname, _fsname, _wmi, _possible, _dispname) \ 168 __ATTR_RO_INT_GROUP_ENUM(_attrname, _wmi, _fsname, _possible, _dispname) 169 170/* 171 * Requires <name>_current_value_show(), <name>_current_value_show() 172 */ 173#define ASUS_ATTR_GROUP_BOOL(_attrname, _fsname, _dispname) \ 174 static struct kobj_attribute attr_##_attrname##_current_value = \ 175 __ASUS_ATTR_RW(_attrname, current_value); \ 176 __ATTR_GROUP_ENUM(_attrname, _fsname, "0;1", _dispname) 177 178/* 179 * Requires <name>_current_value_show(), <name>_current_value_show() 180 * and <name>_possible_values_show() 181 */ 182#define ASUS_ATTR_GROUP_ENUM(_attrname, _fsname, _dispname) \ 183 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 184 static struct kobj_attribute attr_##_attrname##_current_value = \ 185 __ASUS_ATTR_RW(_attrname, current_value); \ 186 static struct kobj_attribute attr_##_attrname##_possible_values = \ 187 __ASUS_ATTR_RO(_attrname, possible_values); \ 188 static struct kobj_attribute attr_##_attrname##_type = \ 189 __ASUS_ATTR_RO_AS(type, enum_type_show); \ 190 static struct attribute *_attrname##_attrs[] = { \ 191 &attr_##_attrname##_current_value.attr, \ 192 &attr_##_attrname##_display_name.attr, \ 193 &attr_##_attrname##_possible_values.attr, \ 194 &attr_##_attrname##_type.attr, \ 195 NULL \ 196 }; \ 197 static const struct attribute_group _attrname##_attr_group = { \ 198 .name = _fsname, .attrs = _attrname##_attrs \ 199 } 200 201#define ASUS_ATTR_GROUP_INT_VALUE_ONLY_RO(_attrname, _fsname, _wmi, _dispname) \ 202 ASUS_WMI_SHOW_INT(_attrname##_current_value, _wmi); \ 203 static struct kobj_attribute attr_##_attrname##_current_value = \ 204 __ASUS_ATTR_RO(_attrname, current_value); \ 205 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 206 static struct kobj_attribute attr_##_attrname##_type = \ 207 __ASUS_ATTR_RO_AS(type, int_type_show); \ 208 static struct attribute *_attrname##_attrs[] = { \ 209 &attr_##_attrname##_current_value.attr, \ 210 &attr_##_attrname##_display_name.attr, \ 211 &attr_##_attrname##_type.attr, NULL \ 212 }; \ 213 static const struct attribute_group _attrname##_attr_group = { \ 214 .name = _fsname, .attrs = _attrname##_attrs \ 215 } 216 217/* 218 * ROG PPT attributes need a little different in setup as they 219 * require rog_tunables members. 220 */ 221 222#define __ROG_TUNABLE_SHOW(_prop, _attrname, _val) \ 223 static ssize_t _attrname##_##_prop##_show( \ 224 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 225 { \ 226 struct rog_tunables *tunables = get_current_tunables(); \ 227 \ 228 if (!tunables || !tunables->power_limits) \ 229 return -ENODEV; \ 230 \ 231 return sysfs_emit(buf, "%d\n", tunables->power_limits->_val); \ 232 } \ 233 static struct kobj_attribute attr_##_attrname##_##_prop = \ 234 __ASUS_ATTR_RO(_attrname, _prop) 235 236#define __ROG_TUNABLE_SHOW_DEFAULT(_attrname) \ 237 static ssize_t _attrname##_default_value_show( \ 238 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 239 { \ 240 struct rog_tunables *tunables = get_current_tunables(); \ 241 \ 242 if (!tunables || !tunables->power_limits) \ 243 return -ENODEV; \ 244 \ 245 return sysfs_emit( \ 246 buf, "%d\n", \ 247 tunables->power_limits->_attrname##_def ? \ 248 tunables->power_limits->_attrname##_def : \ 249 tunables->power_limits->_attrname##_max); \ 250 } \ 251 static struct kobj_attribute attr_##_attrname##_default_value = \ 252 __ASUS_ATTR_RO(_attrname, default_value) 253 254#define __ROG_TUNABLE_RW(_attr, _wmi) \ 255 static ssize_t _attr##_current_value_store( \ 256 struct kobject *kobj, struct kobj_attribute *attr, \ 257 const char *buf, size_t count) \ 258 { \ 259 struct rog_tunables *tunables = get_current_tunables(); \ 260 \ 261 if (!tunables || !tunables->power_limits) \ 262 return -ENODEV; \ 263 \ 264 if (tunables->power_limits->_attr##_min == \ 265 tunables->power_limits->_attr##_max) \ 266 return -EINVAL; \ 267 \ 268 return armoury_attr_uint_store(kobj, attr, buf, count, \ 269 tunables->power_limits->_attr##_min, \ 270 tunables->power_limits->_attr##_max, \ 271 &tunables->_attr, _wmi); \ 272 } \ 273 static ssize_t _attr##_current_value_show( \ 274 struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 275 { \ 276 struct rog_tunables *tunables = get_current_tunables(); \ 277 \ 278 if (!tunables) \ 279 return -ENODEV; \ 280 \ 281 return sysfs_emit(buf, "%u\n", tunables->_attr); \ 282 } \ 283 static struct kobj_attribute attr_##_attr##_current_value = \ 284 __ASUS_ATTR_RW(_attr, current_value) 285 286#define ASUS_ATTR_GROUP_ROG_TUNABLE(_attrname, _fsname, _wmi, _dispname) \ 287 __ROG_TUNABLE_RW(_attrname, _wmi); \ 288 __ROG_TUNABLE_SHOW_DEFAULT(_attrname); \ 289 __ROG_TUNABLE_SHOW(min_value, _attrname, _attrname##_min); \ 290 __ROG_TUNABLE_SHOW(max_value, _attrname, _attrname##_max); \ 291 __ATTR_SHOW_FMT(scalar_increment, _attrname, "%d\n", 1); \ 292 __ATTR_SHOW_FMT(display_name, _attrname, "%s\n", _dispname); \ 293 static struct kobj_attribute attr_##_attrname##_type = \ 294 __ASUS_ATTR_RO_AS(type, int_type_show); \ 295 static struct attribute *_attrname##_attrs[] = { \ 296 &attr_##_attrname##_current_value.attr, \ 297 &attr_##_attrname##_default_value.attr, \ 298 &attr_##_attrname##_min_value.attr, \ 299 &attr_##_attrname##_max_value.attr, \ 300 &attr_##_attrname##_scalar_increment.attr, \ 301 &attr_##_attrname##_display_name.attr, \ 302 &attr_##_attrname##_type.attr, \ 303 NULL \ 304 }; \ 305 static const struct attribute_group _attrname##_attr_group = { \ 306 .name = _fsname, .attrs = _attrname##_attrs \ 307 } 308 309/* Default is always the maximum value unless *_def is specified */ 310struct power_limits { 311 u8 ppt_pl1_spl_min; 312 u8 ppt_pl1_spl_def; 313 u8 ppt_pl1_spl_max; 314 u8 ppt_pl2_sppt_min; 315 u8 ppt_pl2_sppt_def; 316 u8 ppt_pl2_sppt_max; 317 u8 ppt_pl3_fppt_min; 318 u8 ppt_pl3_fppt_def; 319 u8 ppt_pl3_fppt_max; 320 u8 ppt_apu_sppt_min; 321 u8 ppt_apu_sppt_def; 322 u8 ppt_apu_sppt_max; 323 u8 ppt_platform_sppt_min; 324 u8 ppt_platform_sppt_def; 325 u8 ppt_platform_sppt_max; 326 /* Nvidia GPU specific, default is always max */ 327 u8 nv_dynamic_boost_def; // unused. exists for macro 328 u8 nv_dynamic_boost_min; 329 u8 nv_dynamic_boost_max; 330 u8 nv_temp_target_def; // unused. exists for macro 331 u8 nv_temp_target_min; 332 u8 nv_temp_target_max; 333 u8 nv_tgp_def; // unused. exists for macro 334 u8 nv_tgp_min; 335 u8 nv_tgp_max; 336}; 337 338struct power_data { 339 const struct power_limits *ac_data; 340 const struct power_limits *dc_data; 341 bool requires_fan_curve; 342}; 343 344/* 345 * For each available attribute there must be a min and a max. 346 * _def is not required and will be assumed to be default == max if missing. 347 */ 348static const struct dmi_system_id power_limits[] = { 349 { 350 .matches = { 351 DMI_MATCH(DMI_BOARD_NAME, "FA401UV"), 352 }, 353 .driver_data = &(struct power_data) { 354 .ac_data = &(struct power_limits) { 355 .ppt_pl1_spl_min = 15, 356 .ppt_pl1_spl_max = 80, 357 .ppt_pl2_sppt_min = 35, 358 .ppt_pl2_sppt_max = 80, 359 .ppt_pl3_fppt_min = 35, 360 .ppt_pl3_fppt_max = 80, 361 .nv_dynamic_boost_min = 5, 362 .nv_dynamic_boost_max = 25, 363 .nv_temp_target_min = 75, 364 .nv_temp_target_max = 87, 365 .nv_tgp_min = 55, 366 .nv_tgp_max = 75, 367 }, 368 .dc_data = &(struct power_limits) { 369 .ppt_pl1_spl_min = 25, 370 .ppt_pl1_spl_max = 35, 371 .ppt_pl2_sppt_min = 31, 372 .ppt_pl2_sppt_max = 44, 373 .ppt_pl3_fppt_min = 45, 374 .ppt_pl3_fppt_max = 65, 375 .nv_temp_target_min = 75, 376 .nv_temp_target_max = 87, 377 }, 378 }, 379 }, 380 { 381 .matches = { 382 DMI_MATCH(DMI_BOARD_NAME, "FA401W"), 383 }, 384 .driver_data = &(struct power_data) { 385 .ac_data = &(struct power_limits) { 386 .ppt_pl1_spl_min = 15, 387 .ppt_pl1_spl_max = 80, 388 .ppt_pl2_sppt_min = 35, 389 .ppt_pl2_sppt_max = 80, 390 .ppt_pl3_fppt_min = 35, 391 .ppt_pl3_fppt_max = 80, 392 .nv_dynamic_boost_min = 5, 393 .nv_dynamic_boost_max = 25, 394 .nv_temp_target_min = 75, 395 .nv_temp_target_max = 87, 396 .nv_tgp_min = 55, 397 .nv_tgp_max = 75, 398 }, 399 .dc_data = &(struct power_limits) { 400 .ppt_pl1_spl_min = 25, 401 .ppt_pl1_spl_max = 30, 402 .ppt_pl2_sppt_min = 31, 403 .ppt_pl2_sppt_max = 44, 404 .ppt_pl3_fppt_min = 45, 405 .ppt_pl3_fppt_max = 65, 406 .nv_temp_target_min = 75, 407 .nv_temp_target_max = 87, 408 }, 409 }, 410 }, 411 { 412 .matches = { 413 DMI_MATCH(DMI_BOARD_NAME, "FA507N"), 414 }, 415 .driver_data = &(struct power_data) { 416 .ac_data = &(struct power_limits) { 417 .ppt_pl1_spl_min = 15, 418 .ppt_pl1_spl_max = 80, 419 .ppt_pl2_sppt_min = 35, 420 .ppt_pl2_sppt_max = 80, 421 .ppt_pl3_fppt_min = 35, 422 .ppt_pl3_fppt_max = 80, 423 .nv_dynamic_boost_min = 5, 424 .nv_dynamic_boost_max = 25, 425 .nv_temp_target_min = 75, 426 .nv_temp_target_max = 87, 427 }, 428 .dc_data = &(struct power_limits) { 429 .ppt_pl1_spl_min = 15, 430 .ppt_pl1_spl_def = 45, 431 .ppt_pl1_spl_max = 65, 432 .ppt_pl2_sppt_min = 35, 433 .ppt_pl2_sppt_def = 54, 434 .ppt_pl2_sppt_max = 65, 435 .ppt_pl3_fppt_min = 35, 436 .ppt_pl3_fppt_max = 65, 437 .nv_temp_target_min = 75, 438 .nv_temp_target_max = 87, 439 }, 440 }, 441 }, 442 { 443 .matches = { 444 DMI_MATCH(DMI_BOARD_NAME, "FA507UV"), 445 }, 446 .driver_data = &(struct power_data) { 447 .ac_data = &(struct power_limits) { 448 .ppt_pl1_spl_min = 15, 449 .ppt_pl1_spl_max = 80, 450 .ppt_pl2_sppt_min = 35, 451 .ppt_pl2_sppt_max = 80, 452 .ppt_pl3_fppt_min = 35, 453 .ppt_pl3_fppt_max = 80, 454 .nv_dynamic_boost_min = 5, 455 .nv_dynamic_boost_max = 25, 456 .nv_temp_target_min = 75, 457 .nv_temp_target_max = 87, 458 .nv_tgp_min = 55, 459 .nv_tgp_max = 115, 460 }, 461 .dc_data = &(struct power_limits) { 462 .ppt_pl1_spl_min = 15, 463 .ppt_pl1_spl_def = 45, 464 .ppt_pl1_spl_max = 65, 465 .ppt_pl2_sppt_min = 35, 466 .ppt_pl2_sppt_def = 54, 467 .ppt_pl2_sppt_max = 65, 468 .ppt_pl3_fppt_min = 35, 469 .ppt_pl3_fppt_max = 65, 470 .nv_temp_target_min = 75, 471 .nv_temp_target_max = 87, 472 }, 473 }, 474 }, 475 { 476 .matches = { 477 DMI_MATCH(DMI_BOARD_NAME, "FA507R"), 478 }, 479 .driver_data = &(struct power_data) { 480 .ac_data = &(struct power_limits) { 481 .ppt_pl1_spl_min = 15, 482 .ppt_pl1_spl_max = 80, 483 .ppt_pl2_sppt_min = 35, 484 .ppt_pl2_sppt_max = 80, 485 .ppt_pl3_fppt_min = 35, 486 .ppt_pl3_fppt_max = 80, 487 .nv_dynamic_boost_min = 5, 488 .nv_dynamic_boost_max = 25, 489 .nv_temp_target_min = 75, 490 .nv_temp_target_max = 87, 491 }, 492 .dc_data = &(struct power_limits) { 493 .ppt_pl1_spl_min = 15, 494 .ppt_pl1_spl_def = 45, 495 .ppt_pl1_spl_max = 65, 496 .ppt_pl2_sppt_min = 35, 497 .ppt_pl2_sppt_def = 54, 498 .ppt_pl2_sppt_max = 65, 499 .ppt_pl3_fppt_min = 35, 500 .ppt_pl3_fppt_max = 65, 501 .nv_temp_target_min = 75, 502 .nv_temp_target_max = 87, 503 }, 504 }, 505 }, 506 { 507 .matches = { 508 DMI_MATCH(DMI_BOARD_NAME, "FA507X"), 509 }, 510 .driver_data = &(struct power_data) { 511 .ac_data = &(struct power_limits) { 512 .ppt_pl1_spl_min = 15, 513 .ppt_pl1_spl_max = 80, 514 .ppt_pl2_sppt_min = 35, 515 .ppt_pl2_sppt_max = 80, 516 .ppt_pl3_fppt_min = 35, 517 .ppt_pl3_fppt_max = 80, 518 .nv_dynamic_boost_min = 5, 519 .nv_dynamic_boost_max = 20, 520 .nv_temp_target_min = 75, 521 .nv_temp_target_max = 87, 522 .nv_tgp_min = 55, 523 .nv_tgp_max = 85, 524 }, 525 .dc_data = &(struct power_limits) { 526 .ppt_pl1_spl_min = 15, 527 .ppt_pl1_spl_def = 45, 528 .ppt_pl1_spl_max = 65, 529 .ppt_pl2_sppt_min = 35, 530 .ppt_pl2_sppt_def = 54, 531 .ppt_pl2_sppt_max = 65, 532 .ppt_pl3_fppt_min = 35, 533 .ppt_pl3_fppt_max = 65, 534 .nv_temp_target_min = 75, 535 .nv_temp_target_max = 87, 536 }, 537 }, 538 }, 539 { 540 .matches = { 541 DMI_MATCH(DMI_BOARD_NAME, "FA507Z"), 542 }, 543 .driver_data = &(struct power_data) { 544 .ac_data = &(struct power_limits) { 545 .ppt_pl1_spl_min = 28, 546 .ppt_pl1_spl_max = 65, 547 .ppt_pl2_sppt_min = 28, 548 .ppt_pl2_sppt_max = 105, 549 .nv_dynamic_boost_min = 5, 550 .nv_dynamic_boost_max = 15, 551 .nv_temp_target_min = 75, 552 .nv_temp_target_max = 87, 553 .nv_tgp_min = 55, 554 .nv_tgp_max = 85, 555 }, 556 .dc_data = &(struct power_limits) { 557 .ppt_pl1_spl_min = 25, 558 .ppt_pl1_spl_max = 45, 559 .ppt_pl2_sppt_min = 35, 560 .ppt_pl2_sppt_max = 60, 561 .nv_temp_target_min = 75, 562 .nv_temp_target_max = 87, 563 }, 564 }, 565 }, 566 { 567 .matches = { 568 DMI_MATCH(DMI_BOARD_NAME, "FA607P"), 569 }, 570 .driver_data = &(struct power_data) { 571 .ac_data = &(struct power_limits) { 572 .ppt_pl1_spl_min = 30, 573 .ppt_pl1_spl_def = 100, 574 .ppt_pl1_spl_max = 135, 575 .ppt_pl2_sppt_min = 30, 576 .ppt_pl2_sppt_def = 115, 577 .ppt_pl2_sppt_max = 135, 578 .ppt_pl3_fppt_min = 30, 579 .ppt_pl3_fppt_max = 135, 580 .nv_dynamic_boost_min = 5, 581 .nv_dynamic_boost_max = 25, 582 .nv_temp_target_min = 75, 583 .nv_temp_target_max = 87, 584 .nv_tgp_min = 55, 585 .nv_tgp_max = 115, 586 }, 587 .dc_data = &(struct power_limits) { 588 .ppt_pl1_spl_min = 25, 589 .ppt_pl1_spl_def = 45, 590 .ppt_pl1_spl_max = 80, 591 .ppt_pl2_sppt_min = 25, 592 .ppt_pl2_sppt_def = 60, 593 .ppt_pl2_sppt_max = 80, 594 .ppt_pl3_fppt_min = 25, 595 .ppt_pl3_fppt_max = 80, 596 .nv_temp_target_min = 75, 597 .nv_temp_target_max = 87, 598 }, 599 }, 600 }, 601 { 602 .matches = { 603 DMI_MATCH(DMI_BOARD_NAME, "FA608UM"), 604 }, 605 .driver_data = &(struct power_data) { 606 .ac_data = &(struct power_limits) { 607 .ppt_pl1_spl_min = 15, 608 .ppt_pl1_spl_def = 45, 609 .ppt_pl1_spl_max = 90, 610 .ppt_pl2_sppt_min = 35, 611 .ppt_pl2_sppt_def = 54, 612 .ppt_pl2_sppt_max = 90, 613 .ppt_pl3_fppt_min = 35, 614 .ppt_pl3_fppt_def = 65, 615 .ppt_pl3_fppt_max = 90, 616 .nv_dynamic_boost_min = 10, 617 .nv_dynamic_boost_max = 15, 618 .nv_temp_target_min = 75, 619 .nv_temp_target_max = 87, 620 .nv_tgp_min = 55, 621 .nv_tgp_max = 100, 622 }, 623 .dc_data = &(struct power_limits) { 624 .ppt_pl1_spl_min = 15, 625 .ppt_pl1_spl_def = 45, 626 .ppt_pl1_spl_max = 65, 627 .ppt_pl2_sppt_min = 35, 628 .ppt_pl2_sppt_def = 54, 629 .ppt_pl2_sppt_max = 65, 630 .ppt_pl3_fppt_min = 35, 631 .ppt_pl3_fppt_max = 65, 632 .nv_temp_target_min = 75, 633 .nv_temp_target_max = 87, 634 }, 635 }, 636 }, 637 { 638 .matches = { 639 DMI_MATCH(DMI_BOARD_NAME, "FA608WI"), 640 }, 641 .driver_data = &(struct power_data) { 642 .ac_data = &(struct power_limits) { 643 .ppt_pl1_spl_min = 15, 644 .ppt_pl1_spl_def = 90, 645 .ppt_pl1_spl_max = 90, 646 .ppt_pl2_sppt_min = 35, 647 .ppt_pl2_sppt_def = 90, 648 .ppt_pl2_sppt_max = 90, 649 .ppt_pl3_fppt_min = 35, 650 .ppt_pl3_fppt_def = 90, 651 .ppt_pl3_fppt_max = 90, 652 .nv_dynamic_boost_min = 5, 653 .nv_dynamic_boost_max = 25, 654 .nv_temp_target_min = 75, 655 .nv_temp_target_max = 87, 656 .nv_tgp_min = 55, 657 .nv_tgp_max = 115, 658 }, 659 .dc_data = &(struct power_limits) { 660 .ppt_pl1_spl_min = 15, 661 .ppt_pl1_spl_def = 45, 662 .ppt_pl1_spl_max = 65, 663 .ppt_pl2_sppt_min = 35, 664 .ppt_pl2_sppt_def = 54, 665 .ppt_pl2_sppt_max = 65, 666 .ppt_pl3_fppt_min = 35, 667 .ppt_pl3_fppt_def = 65, 668 .ppt_pl3_fppt_max = 65, 669 .nv_temp_target_min = 75, 670 .nv_temp_target_max = 87, 671 }, 672 }, 673 }, 674 { 675 .matches = { 676 DMI_MATCH(DMI_BOARD_NAME, "FA617NS"), 677 }, 678 .driver_data = &(struct power_data) { 679 .ac_data = &(struct power_limits) { 680 .ppt_apu_sppt_min = 15, 681 .ppt_apu_sppt_max = 80, 682 .ppt_platform_sppt_min = 30, 683 .ppt_platform_sppt_max = 120, 684 }, 685 .dc_data = &(struct power_limits) { 686 .ppt_apu_sppt_min = 25, 687 .ppt_apu_sppt_max = 35, 688 .ppt_platform_sppt_min = 45, 689 .ppt_platform_sppt_max = 100, 690 }, 691 }, 692 }, 693 { 694 .matches = { 695 DMI_MATCH(DMI_BOARD_NAME, "FA617NT"), 696 }, 697 .driver_data = &(struct power_data) { 698 .ac_data = &(struct power_limits) { 699 .ppt_apu_sppt_min = 15, 700 .ppt_apu_sppt_max = 80, 701 .ppt_platform_sppt_min = 30, 702 .ppt_platform_sppt_max = 115, 703 }, 704 .dc_data = &(struct power_limits) { 705 .ppt_apu_sppt_min = 15, 706 .ppt_apu_sppt_max = 45, 707 .ppt_platform_sppt_min = 30, 708 .ppt_platform_sppt_max = 50, 709 }, 710 }, 711 }, 712 { 713 .matches = { 714 DMI_MATCH(DMI_BOARD_NAME, "FA617XS"), 715 }, 716 .driver_data = &(struct power_data) { 717 .ac_data = &(struct power_limits) { 718 .ppt_apu_sppt_min = 15, 719 .ppt_apu_sppt_max = 80, 720 .ppt_platform_sppt_min = 30, 721 .ppt_platform_sppt_max = 120, 722 .nv_temp_target_min = 75, 723 .nv_temp_target_max = 87, 724 }, 725 .dc_data = &(struct power_limits) { 726 .ppt_apu_sppt_min = 25, 727 .ppt_apu_sppt_max = 35, 728 .ppt_platform_sppt_min = 45, 729 .ppt_platform_sppt_max = 100, 730 .nv_temp_target_min = 75, 731 .nv_temp_target_max = 87, 732 }, 733 }, 734 }, 735 { 736 .matches = { 737 DMI_MATCH(DMI_BOARD_NAME, "FA617XT"), 738 }, 739 .driver_data = &(struct power_data) { 740 .ac_data = &(struct power_limits) { 741 .ppt_apu_sppt_min = 15, 742 .ppt_apu_sppt_max = 80, 743 .ppt_platform_sppt_min = 30, 744 .ppt_platform_sppt_max = 145, 745 }, 746 .dc_data = &(struct power_limits) { 747 .ppt_apu_sppt_min = 25, 748 .ppt_apu_sppt_max = 35, 749 .ppt_platform_sppt_min = 45, 750 .ppt_platform_sppt_max = 100, 751 }, 752 }, 753 }, 754 { 755 .matches = { 756 DMI_MATCH(DMI_BOARD_NAME, "FX507VI"), 757 }, 758 .driver_data = &(struct power_data) { 759 .ac_data = &(struct power_limits) { 760 .ppt_pl1_spl_min = 28, 761 .ppt_pl1_spl_max = 135, 762 .ppt_pl2_sppt_min = 28, 763 .ppt_pl2_sppt_max = 135, 764 .nv_dynamic_boost_min = 5, 765 .nv_dynamic_boost_max = 25, 766 .nv_temp_target_min = 75, 767 .nv_temp_target_max = 87, 768 }, 769 .dc_data = &(struct power_limits) { 770 .ppt_pl1_spl_min = 25, 771 .ppt_pl1_spl_max = 45, 772 .ppt_pl2_sppt_min = 35, 773 .ppt_pl2_sppt_max = 60, 774 .nv_temp_target_min = 75, 775 .nv_temp_target_max = 87, 776 }, 777 .requires_fan_curve = true, 778 }, 779 }, 780 { 781 .matches = { 782 DMI_MATCH(DMI_BOARD_NAME, "FX507VV"), 783 }, 784 .driver_data = &(struct power_data) { 785 .ac_data = &(struct power_limits) { 786 .ppt_pl1_spl_min = 28, 787 .ppt_pl1_spl_def = 115, 788 .ppt_pl1_spl_max = 135, 789 .ppt_pl2_sppt_min = 28, 790 .ppt_pl2_sppt_max = 135, 791 .nv_dynamic_boost_min = 5, 792 .nv_dynamic_boost_max = 25, 793 .nv_temp_target_min = 75, 794 .nv_temp_target_max = 87, 795 }, 796 .dc_data = &(struct power_limits) { 797 .ppt_pl1_spl_min = 25, 798 .ppt_pl1_spl_max = 45, 799 .ppt_pl2_sppt_min = 35, 800 .ppt_pl2_sppt_max = 60, 801 .nv_temp_target_min = 75, 802 .nv_temp_target_max = 87, 803 }, 804 .requires_fan_curve = true, 805 }, 806 }, 807 { 808 .matches = { 809 DMI_MATCH(DMI_BOARD_NAME, "FX507Z"), 810 }, 811 .driver_data = &(struct power_data) { 812 .ac_data = &(struct power_limits) { 813 .ppt_pl1_spl_min = 28, 814 .ppt_pl1_spl_max = 90, 815 .ppt_pl2_sppt_min = 28, 816 .ppt_pl2_sppt_max = 135, 817 .nv_dynamic_boost_min = 5, 818 .nv_dynamic_boost_max = 15, 819 }, 820 .dc_data = &(struct power_limits) { 821 .ppt_pl1_spl_min = 25, 822 .ppt_pl1_spl_max = 45, 823 .ppt_pl2_sppt_min = 35, 824 .ppt_pl2_sppt_max = 60, 825 }, 826 .requires_fan_curve = true, 827 }, 828 }, 829 { 830 .matches = { 831 DMI_MATCH(DMI_BOARD_NAME, "GA401Q"), 832 }, 833 .driver_data = &(struct power_data) { 834 .ac_data = &(struct power_limits) { 835 .ppt_pl1_spl_min = 15, 836 .ppt_pl1_spl_max = 80, 837 .ppt_pl2_sppt_min = 15, 838 .ppt_pl2_sppt_max = 80, 839 }, 840 .dc_data = NULL, 841 }, 842 }, 843 { 844 .matches = { 845 // This model is full AMD. No Nvidia dGPU. 846 DMI_MATCH(DMI_BOARD_NAME, "GA402R"), 847 }, 848 .driver_data = &(struct power_data) { 849 .ac_data = &(struct power_limits) { 850 .ppt_apu_sppt_min = 15, 851 .ppt_apu_sppt_max = 80, 852 .ppt_platform_sppt_min = 30, 853 .ppt_platform_sppt_max = 115, 854 }, 855 .dc_data = &(struct power_limits) { 856 .ppt_apu_sppt_min = 25, 857 .ppt_apu_sppt_def = 30, 858 .ppt_apu_sppt_max = 45, 859 .ppt_platform_sppt_min = 40, 860 .ppt_platform_sppt_max = 60, 861 }, 862 }, 863 }, 864 { 865 .matches = { 866 DMI_MATCH(DMI_BOARD_NAME, "GA402X"), 867 }, 868 .driver_data = &(struct power_data) { 869 .ac_data = &(struct power_limits) { 870 .ppt_pl1_spl_min = 15, 871 .ppt_pl1_spl_def = 35, 872 .ppt_pl1_spl_max = 80, 873 .ppt_pl2_sppt_min = 25, 874 .ppt_pl2_sppt_def = 65, 875 .ppt_pl2_sppt_max = 80, 876 .ppt_pl3_fppt_min = 35, 877 .ppt_pl3_fppt_max = 80, 878 .nv_temp_target_min = 75, 879 .nv_temp_target_max = 87, 880 }, 881 .dc_data = &(struct power_limits) { 882 .ppt_pl1_spl_min = 15, 883 .ppt_pl1_spl_max = 35, 884 .ppt_pl2_sppt_min = 25, 885 .ppt_pl2_sppt_max = 35, 886 .ppt_pl3_fppt_min = 35, 887 .ppt_pl3_fppt_max = 65, 888 .nv_temp_target_min = 75, 889 .nv_temp_target_max = 87, 890 }, 891 .requires_fan_curve = true, 892 }, 893 }, 894 { 895 .matches = { 896 DMI_MATCH(DMI_BOARD_NAME, "GA403UI"), 897 }, 898 .driver_data = &(struct power_data) { 899 .ac_data = &(struct power_limits) { 900 .ppt_pl1_spl_min = 15, 901 .ppt_pl1_spl_max = 80, 902 .ppt_pl2_sppt_min = 25, 903 .ppt_pl2_sppt_max = 80, 904 .ppt_pl3_fppt_min = 35, 905 .ppt_pl3_fppt_max = 80, 906 .nv_dynamic_boost_min = 5, 907 .nv_dynamic_boost_max = 25, 908 .nv_temp_target_min = 75, 909 .nv_temp_target_max = 87, 910 .nv_tgp_min = 55, 911 .nv_tgp_max = 65, 912 }, 913 .dc_data = &(struct power_limits) { 914 .ppt_pl1_spl_min = 15, 915 .ppt_pl1_spl_max = 35, 916 .ppt_pl2_sppt_min = 25, 917 .ppt_pl2_sppt_max = 35, 918 .ppt_pl3_fppt_min = 35, 919 .ppt_pl3_fppt_max = 65, 920 .nv_temp_target_min = 75, 921 .nv_temp_target_max = 87, 922 }, 923 .requires_fan_curve = true, 924 }, 925 }, 926 { 927 .matches = { 928 DMI_MATCH(DMI_BOARD_NAME, "GA403UV"), 929 }, 930 .driver_data = &(struct power_data) { 931 .ac_data = &(struct power_limits) { 932 .ppt_pl1_spl_min = 15, 933 .ppt_pl1_spl_max = 80, 934 .ppt_pl2_sppt_min = 25, 935 .ppt_pl2_sppt_max = 80, 936 .ppt_pl3_fppt_min = 35, 937 .ppt_pl3_fppt_max = 80, 938 .nv_dynamic_boost_min = 5, 939 .nv_dynamic_boost_max = 25, 940 .nv_temp_target_min = 75, 941 .nv_temp_target_max = 87, 942 .nv_tgp_min = 55, 943 .nv_tgp_max = 65, 944 }, 945 .dc_data = &(struct power_limits) { 946 .ppt_pl1_spl_min = 15, 947 .ppt_pl1_spl_max = 35, 948 .ppt_pl2_sppt_min = 25, 949 .ppt_pl2_sppt_max = 35, 950 .ppt_pl3_fppt_min = 35, 951 .ppt_pl3_fppt_max = 65, 952 .nv_temp_target_min = 75, 953 .nv_temp_target_max = 87, 954 }, 955 .requires_fan_curve = true, 956 }, 957 }, 958 { 959 .matches = { 960 DMI_MATCH(DMI_BOARD_NAME, "GA403WM"), 961 }, 962 .driver_data = &(struct power_data) { 963 .ac_data = &(struct power_limits) { 964 .ppt_pl1_spl_min = 15, 965 .ppt_pl1_spl_max = 80, 966 .ppt_pl2_sppt_min = 25, 967 .ppt_pl2_sppt_max = 80, 968 .ppt_pl3_fppt_min = 35, 969 .ppt_pl3_fppt_max = 80, 970 .nv_dynamic_boost_min = 0, 971 .nv_dynamic_boost_max = 15, 972 .nv_temp_target_min = 75, 973 .nv_temp_target_max = 87, 974 .nv_tgp_min = 55, 975 .nv_tgp_max = 85, 976 }, 977 .dc_data = &(struct power_limits) { 978 .ppt_pl1_spl_min = 15, 979 .ppt_pl1_spl_max = 35, 980 .ppt_pl2_sppt_min = 25, 981 .ppt_pl2_sppt_max = 35, 982 .ppt_pl3_fppt_min = 35, 983 .ppt_pl3_fppt_max = 65, 984 .nv_temp_target_min = 75, 985 .nv_temp_target_max = 87, 986 }, 987 .requires_fan_curve = true, 988 }, 989 }, 990 { 991 .matches = { 992 DMI_MATCH(DMI_BOARD_NAME, "GA403WR"), 993 }, 994 .driver_data = &(struct power_data) { 995 .ac_data = &(struct power_limits) { 996 .ppt_pl1_spl_min = 15, 997 .ppt_pl1_spl_max = 80, 998 .ppt_pl2_sppt_min = 25, 999 .ppt_pl2_sppt_max = 80, 1000 .ppt_pl3_fppt_min = 35, 1001 .ppt_pl3_fppt_max = 80, 1002 .nv_dynamic_boost_min = 0, 1003 .nv_dynamic_boost_max = 25, 1004 .nv_temp_target_min = 75, 1005 .nv_temp_target_max = 87, 1006 .nv_tgp_min = 80, 1007 .nv_tgp_max = 95, 1008 }, 1009 .dc_data = &(struct power_limits) { 1010 .ppt_pl1_spl_min = 15, 1011 .ppt_pl1_spl_max = 35, 1012 .ppt_pl2_sppt_min = 25, 1013 .ppt_pl2_sppt_max = 35, 1014 .ppt_pl3_fppt_min = 35, 1015 .ppt_pl3_fppt_max = 65, 1016 .nv_temp_target_min = 75, 1017 .nv_temp_target_max = 87, 1018 }, 1019 .requires_fan_curve = true, 1020 }, 1021 }, 1022 { 1023 .matches = { 1024 DMI_MATCH(DMI_BOARD_NAME, "GA403WW"), 1025 }, 1026 .driver_data = &(struct power_data) { 1027 .ac_data = &(struct power_limits) { 1028 .ppt_pl1_spl_min = 15, 1029 .ppt_pl1_spl_max = 80, 1030 .ppt_pl2_sppt_min = 25, 1031 .ppt_pl2_sppt_max = 80, 1032 .ppt_pl3_fppt_min = 35, 1033 .ppt_pl3_fppt_max = 80, 1034 .nv_dynamic_boost_min = 0, 1035 .nv_dynamic_boost_max = 25, 1036 .nv_temp_target_min = 75, 1037 .nv_temp_target_max = 87, 1038 .nv_tgp_min = 80, 1039 .nv_tgp_max = 95, 1040 }, 1041 .dc_data = &(struct power_limits) { 1042 .ppt_pl1_spl_min = 15, 1043 .ppt_pl1_spl_max = 35, 1044 .ppt_pl2_sppt_min = 25, 1045 .ppt_pl2_sppt_max = 35, 1046 .ppt_pl3_fppt_min = 35, 1047 .ppt_pl3_fppt_max = 65, 1048 .nv_temp_target_min = 75, 1049 .nv_temp_target_max = 87, 1050 }, 1051 .requires_fan_curve = true, 1052 }, 1053 }, 1054 { 1055 .matches = { 1056 DMI_MATCH(DMI_BOARD_NAME, "GA503QR"), 1057 }, 1058 .driver_data = &(struct power_data) { 1059 .ac_data = &(struct power_limits) { 1060 .ppt_pl1_spl_min = 15, 1061 .ppt_pl1_spl_def = 35, 1062 .ppt_pl1_spl_max = 80, 1063 .ppt_pl2_sppt_min = 65, 1064 .ppt_pl2_sppt_max = 80, 1065 }, 1066 }, 1067 }, 1068 { 1069 .matches = { 1070 DMI_MATCH(DMI_BOARD_NAME, "GA503R"), 1071 }, 1072 .driver_data = &(struct power_data) { 1073 .ac_data = &(struct power_limits) { 1074 .ppt_pl1_spl_min = 15, 1075 .ppt_pl1_spl_def = 35, 1076 .ppt_pl1_spl_max = 80, 1077 .ppt_pl2_sppt_min = 35, 1078 .ppt_pl2_sppt_def = 65, 1079 .ppt_pl2_sppt_max = 80, 1080 .ppt_pl3_fppt_min = 35, 1081 .ppt_pl3_fppt_max = 80, 1082 .nv_dynamic_boost_min = 5, 1083 .nv_dynamic_boost_max = 20, 1084 .nv_temp_target_min = 75, 1085 .nv_temp_target_max = 87, 1086 }, 1087 .dc_data = &(struct power_limits) { 1088 .ppt_pl1_spl_min = 15, 1089 .ppt_pl1_spl_def = 25, 1090 .ppt_pl1_spl_max = 65, 1091 .ppt_pl2_sppt_min = 35, 1092 .ppt_pl2_sppt_def = 54, 1093 .ppt_pl2_sppt_max = 60, 1094 .ppt_pl3_fppt_min = 35, 1095 .ppt_pl3_fppt_max = 65, 1096 }, 1097 }, 1098 }, 1099 { 1100 .matches = { 1101 DMI_MATCH(DMI_BOARD_NAME, "GA605W"), 1102 }, 1103 .driver_data = &(struct power_data) { 1104 .ac_data = &(struct power_limits) { 1105 .ppt_pl1_spl_min = 15, 1106 .ppt_pl1_spl_max = 80, 1107 .ppt_pl2_sppt_min = 35, 1108 .ppt_pl2_sppt_max = 80, 1109 .ppt_pl3_fppt_min = 35, 1110 .ppt_pl3_fppt_max = 80, 1111 .nv_dynamic_boost_min = 5, 1112 .nv_dynamic_boost_max = 20, 1113 .nv_temp_target_min = 75, 1114 .nv_temp_target_max = 87, 1115 .nv_tgp_min = 55, 1116 .nv_tgp_max = 85, 1117 }, 1118 .dc_data = &(struct power_limits) { 1119 .ppt_pl1_spl_min = 25, 1120 .ppt_pl1_spl_max = 35, 1121 .ppt_pl2_sppt_min = 31, 1122 .ppt_pl2_sppt_max = 44, 1123 .ppt_pl3_fppt_min = 45, 1124 .ppt_pl3_fppt_max = 65, 1125 .nv_temp_target_min = 75, 1126 .nv_temp_target_max = 87, 1127 }, 1128 .requires_fan_curve = true, 1129 }, 1130 }, 1131 { 1132 .matches = { 1133 DMI_MATCH(DMI_BOARD_NAME, "GU603Z"), 1134 }, 1135 .driver_data = &(struct power_data) { 1136 .ac_data = &(struct power_limits) { 1137 .ppt_pl1_spl_min = 25, 1138 .ppt_pl1_spl_max = 60, 1139 .ppt_pl2_sppt_min = 25, 1140 .ppt_pl2_sppt_max = 135, 1141 .nv_dynamic_boost_min = 5, 1142 .nv_dynamic_boost_max = 20, 1143 .nv_temp_target_min = 75, 1144 .nv_temp_target_max = 87, 1145 }, 1146 .dc_data = &(struct power_limits) { 1147 .ppt_pl1_spl_min = 25, 1148 .ppt_pl1_spl_max = 40, 1149 .ppt_pl2_sppt_min = 25, 1150 .ppt_pl2_sppt_max = 40, 1151 .nv_temp_target_min = 75, 1152 .nv_temp_target_max = 87, 1153 } 1154 }, 1155 }, 1156 { 1157 .matches = { 1158 DMI_MATCH(DMI_BOARD_NAME, "GU604V"), 1159 }, 1160 .driver_data = &(struct power_data) { 1161 .ac_data = &(struct power_limits) { 1162 .ppt_pl1_spl_min = 65, 1163 .ppt_pl1_spl_max = 120, 1164 .ppt_pl2_sppt_min = 65, 1165 .ppt_pl2_sppt_max = 150, 1166 .nv_dynamic_boost_min = 5, 1167 .nv_dynamic_boost_max = 25, 1168 .nv_temp_target_min = 75, 1169 .nv_temp_target_max = 87, 1170 }, 1171 .dc_data = &(struct power_limits) { 1172 .ppt_pl1_spl_min = 25, 1173 .ppt_pl1_spl_max = 40, 1174 .ppt_pl2_sppt_min = 35, 1175 .ppt_pl2_sppt_def = 40, 1176 .ppt_pl2_sppt_max = 60, 1177 .nv_temp_target_min = 75, 1178 .nv_temp_target_max = 87, 1179 }, 1180 }, 1181 }, 1182 { 1183 .matches = { 1184 DMI_MATCH(DMI_BOARD_NAME, "GU605CR"), 1185 }, 1186 .driver_data = &(struct power_data) { 1187 .ac_data = &(struct power_limits) { 1188 .ppt_pl1_spl_min = 30, 1189 .ppt_pl1_spl_max = 85, 1190 .ppt_pl2_sppt_min = 38, 1191 .ppt_pl2_sppt_max = 110, 1192 .nv_dynamic_boost_min = 5, 1193 .nv_dynamic_boost_max = 20, 1194 .nv_temp_target_min = 75, 1195 .nv_temp_target_max = 87, 1196 .nv_tgp_min = 80, 1197 .nv_tgp_def = 90, 1198 .nv_tgp_max = 105, 1199 }, 1200 .dc_data = &(struct power_limits) { 1201 .ppt_pl1_spl_min = 30, 1202 .ppt_pl1_spl_max = 85, 1203 .ppt_pl2_sppt_min = 38, 1204 .ppt_pl2_sppt_max = 110, 1205 .nv_temp_target_min = 75, 1206 .nv_temp_target_max = 87, 1207 }, 1208 .requires_fan_curve = true, 1209 }, 1210 }, 1211 { 1212 .matches = { 1213 DMI_MATCH(DMI_BOARD_NAME, "GU605CW"), 1214 }, 1215 .driver_data = &(struct power_data) { 1216 .ac_data = &(struct power_limits) { 1217 .ppt_pl1_spl_min = 45, 1218 .ppt_pl1_spl_max = 85, 1219 .ppt_pl2_sppt_min = 56, 1220 .ppt_pl2_sppt_max = 110, 1221 .nv_dynamic_boost_min = 5, 1222 .nv_dynamic_boost_max = 20, 1223 .nv_temp_target_min = 75, 1224 .nv_temp_target_max = 87, 1225 .nv_tgp_min = 80, 1226 .nv_tgp_def = 90, 1227 .nv_tgp_max = 110, 1228 }, 1229 .dc_data = &(struct power_limits) { 1230 .ppt_pl1_spl_min = 25, 1231 .ppt_pl1_spl_max = 85, 1232 .ppt_pl2_sppt_min = 32, 1233 .ppt_pl2_sppt_max = 110, 1234 .nv_temp_target_min = 75, 1235 .nv_temp_target_max = 87, 1236 }, 1237 .requires_fan_curve = true, 1238 }, 1239 }, 1240 { 1241 .matches = { 1242 DMI_MATCH(DMI_BOARD_NAME, "GU605CX"), 1243 }, 1244 .driver_data = &(struct power_data) { 1245 .ac_data = &(struct power_limits) { 1246 .ppt_pl1_spl_min = 45, 1247 .ppt_pl1_spl_max = 85, 1248 .ppt_pl2_sppt_min = 56, 1249 .ppt_pl2_sppt_max = 110, 1250 .nv_dynamic_boost_min = 5, 1251 .nv_dynamic_boost_max = 20, 1252 .nv_temp_target_min = 7, 1253 .nv_temp_target_max = 87, 1254 .nv_tgp_min = 95, 1255 .nv_tgp_def = 100, 1256 .nv_tgp_max = 110, 1257 }, 1258 .dc_data = &(struct power_limits) { 1259 .ppt_pl1_spl_min = 25, 1260 .ppt_pl1_spl_max = 85, 1261 .ppt_pl2_sppt_min = 32, 1262 .ppt_pl2_sppt_max = 110, 1263 .nv_temp_target_min = 75, 1264 .nv_temp_target_max = 87, 1265 }, 1266 .requires_fan_curve = true, 1267 }, 1268 }, 1269 { 1270 .matches = { 1271 DMI_MATCH(DMI_BOARD_NAME, "GU605M"), 1272 }, 1273 .driver_data = &(struct power_data) { 1274 .ac_data = &(struct power_limits) { 1275 .ppt_pl1_spl_min = 28, 1276 .ppt_pl1_spl_max = 90, 1277 .ppt_pl2_sppt_min = 28, 1278 .ppt_pl2_sppt_max = 135, 1279 .nv_dynamic_boost_min = 5, 1280 .nv_dynamic_boost_max = 20, 1281 .nv_temp_target_min = 75, 1282 .nv_temp_target_max = 87, 1283 }, 1284 .dc_data = &(struct power_limits) { 1285 .ppt_pl1_spl_min = 25, 1286 .ppt_pl1_spl_max = 35, 1287 .ppt_pl2_sppt_min = 38, 1288 .ppt_pl2_sppt_max = 53, 1289 .nv_temp_target_min = 75, 1290 .nv_temp_target_max = 87, 1291 }, 1292 .requires_fan_curve = true, 1293 }, 1294 }, 1295 { 1296 .matches = { 1297 DMI_MATCH(DMI_BOARD_NAME, "GV301Q"), 1298 }, 1299 .driver_data = &(struct power_data) { 1300 .ac_data = &(struct power_limits) { 1301 .ppt_pl1_spl_min = 15, 1302 .ppt_pl1_spl_max = 45, 1303 .ppt_pl2_sppt_min = 65, 1304 .ppt_pl2_sppt_max = 80, 1305 }, 1306 .dc_data = NULL, 1307 }, 1308 }, 1309 { 1310 .matches = { 1311 DMI_MATCH(DMI_BOARD_NAME, "GV301R"), 1312 }, 1313 .driver_data = &(struct power_data) { 1314 .ac_data = &(struct power_limits) { 1315 .ppt_pl1_spl_min = 15, 1316 .ppt_pl1_spl_max = 45, 1317 .ppt_pl2_sppt_min = 25, 1318 .ppt_pl2_sppt_max = 54, 1319 .ppt_pl3_fppt_min = 35, 1320 .ppt_pl3_fppt_max = 65, 1321 .nv_temp_target_min = 75, 1322 .nv_temp_target_max = 87, 1323 }, 1324 .dc_data = &(struct power_limits) { 1325 .ppt_pl1_spl_min = 15, 1326 .ppt_pl1_spl_max = 35, 1327 .ppt_pl2_sppt_min = 25, 1328 .ppt_pl2_sppt_max = 35, 1329 .ppt_pl3_fppt_min = 35, 1330 .ppt_pl3_fppt_max = 65, 1331 .nv_temp_target_min = 75, 1332 .nv_temp_target_max = 87, 1333 }, 1334 }, 1335 }, 1336 { 1337 .matches = { 1338 DMI_MATCH(DMI_BOARD_NAME, "GV302XV"), 1339 }, 1340 .driver_data = &(struct power_data) { 1341 .ac_data = &(struct power_limits) { 1342 .ppt_pl1_spl_min = 15, 1343 .ppt_pl1_spl_max = 55, 1344 .ppt_pl2_sppt_min = 25, 1345 .ppt_pl2_sppt_max = 60, 1346 .ppt_pl3_fppt_min = 35, 1347 .ppt_pl3_fppt_max = 65, 1348 .nv_temp_target_min = 75, 1349 .nv_temp_target_max = 87, 1350 }, 1351 .dc_data = &(struct power_limits) { 1352 .ppt_pl1_spl_min = 15, 1353 .ppt_pl1_spl_max = 35, 1354 .ppt_pl2_sppt_min = 25, 1355 .ppt_pl2_sppt_max = 35, 1356 .ppt_pl3_fppt_min = 35, 1357 .ppt_pl3_fppt_max = 65, 1358 .nv_temp_target_min = 75, 1359 .nv_temp_target_max = 87, 1360 }, 1361 }, 1362 }, 1363 { 1364 .matches = { 1365 DMI_MATCH(DMI_BOARD_NAME, "GV601R"), 1366 }, 1367 .driver_data = &(struct power_data) { 1368 .ac_data = &(struct power_limits) { 1369 .ppt_pl1_spl_min = 15, 1370 .ppt_pl1_spl_def = 35, 1371 .ppt_pl1_spl_max = 90, 1372 .ppt_pl2_sppt_min = 35, 1373 .ppt_pl2_sppt_def = 54, 1374 .ppt_pl2_sppt_max = 100, 1375 .ppt_pl3_fppt_min = 35, 1376 .ppt_pl3_fppt_def = 80, 1377 .ppt_pl3_fppt_max = 125, 1378 .nv_dynamic_boost_min = 5, 1379 .nv_dynamic_boost_max = 25, 1380 .nv_temp_target_min = 75, 1381 .nv_temp_target_max = 87, 1382 }, 1383 .dc_data = &(struct power_limits) { 1384 .ppt_pl1_spl_min = 15, 1385 .ppt_pl1_spl_def = 28, 1386 .ppt_pl1_spl_max = 65, 1387 .ppt_pl2_sppt_min = 35, 1388 .ppt_pl2_sppt_def = 54, 1389 .ppt_pl2_sppt_max = 60, 1390 .ppt_pl3_fppt_min = 35, 1391 .ppt_pl3_fppt_def = 80, 1392 .ppt_pl3_fppt_max = 65, 1393 .nv_temp_target_min = 75, 1394 .nv_temp_target_max = 87, 1395 }, 1396 }, 1397 }, 1398 { 1399 .matches = { 1400 DMI_MATCH(DMI_BOARD_NAME, "GV601V"), 1401 }, 1402 .driver_data = &(struct power_data) { 1403 .ac_data = &(struct power_limits) { 1404 .ppt_pl1_spl_min = 28, 1405 .ppt_pl1_spl_def = 100, 1406 .ppt_pl1_spl_max = 110, 1407 .ppt_pl2_sppt_min = 28, 1408 .ppt_pl2_sppt_max = 135, 1409 .nv_dynamic_boost_min = 5, 1410 .nv_dynamic_boost_max = 20, 1411 .nv_temp_target_min = 75, 1412 .nv_temp_target_max = 87, 1413 }, 1414 .dc_data = &(struct power_limits) { 1415 .ppt_pl1_spl_min = 25, 1416 .ppt_pl1_spl_max = 40, 1417 .ppt_pl2_sppt_min = 35, 1418 .ppt_pl2_sppt_def = 40, 1419 .ppt_pl2_sppt_max = 60, 1420 .nv_temp_target_min = 75, 1421 .nv_temp_target_max = 87, 1422 }, 1423 }, 1424 }, 1425 { 1426 .matches = { 1427 DMI_MATCH(DMI_BOARD_NAME, "GX650P"), 1428 }, 1429 .driver_data = &(struct power_data) { 1430 .ac_data = &(struct power_limits) { 1431 .ppt_pl1_spl_min = 15, 1432 .ppt_pl1_spl_def = 110, 1433 .ppt_pl1_spl_max = 130, 1434 .ppt_pl2_sppt_min = 35, 1435 .ppt_pl2_sppt_def = 125, 1436 .ppt_pl2_sppt_max = 130, 1437 .ppt_pl3_fppt_min = 35, 1438 .ppt_pl3_fppt_def = 125, 1439 .ppt_pl3_fppt_max = 135, 1440 .nv_dynamic_boost_min = 5, 1441 .nv_dynamic_boost_max = 25, 1442 .nv_temp_target_min = 75, 1443 .nv_temp_target_max = 87, 1444 }, 1445 .dc_data = &(struct power_limits) { 1446 .ppt_pl1_spl_min = 15, 1447 .ppt_pl1_spl_def = 25, 1448 .ppt_pl1_spl_max = 65, 1449 .ppt_pl2_sppt_min = 35, 1450 .ppt_pl2_sppt_def = 35, 1451 .ppt_pl2_sppt_max = 65, 1452 .ppt_pl3_fppt_min = 35, 1453 .ppt_pl3_fppt_def = 42, 1454 .ppt_pl3_fppt_max = 65, 1455 .nv_temp_target_min = 75, 1456 .nv_temp_target_max = 87, 1457 }, 1458 }, 1459 }, 1460 { 1461 .matches = { 1462 DMI_MATCH(DMI_BOARD_NAME, "G513I"), 1463 }, 1464 .driver_data = &(struct power_data) { 1465 .ac_data = &(struct power_limits) { 1466 /* Yes this laptop is very limited */ 1467 .ppt_pl1_spl_min = 15, 1468 .ppt_pl1_spl_max = 80, 1469 .ppt_pl2_sppt_min = 15, 1470 .ppt_pl2_sppt_max = 80, 1471 }, 1472 .dc_data = NULL, 1473 .requires_fan_curve = true, 1474 }, 1475 }, 1476 { 1477 .matches = { 1478 DMI_MATCH(DMI_BOARD_NAME, "G513QM"), 1479 }, 1480 .driver_data = &(struct power_data) { 1481 .ac_data = &(struct power_limits) { 1482 /* Yes this laptop is very limited */ 1483 .ppt_pl1_spl_min = 15, 1484 .ppt_pl1_spl_max = 100, 1485 .ppt_pl2_sppt_min = 15, 1486 .ppt_pl2_sppt_max = 190, 1487 }, 1488 .dc_data = NULL, 1489 .requires_fan_curve = true, 1490 }, 1491 }, 1492 { 1493 .matches = { 1494 DMI_MATCH(DMI_BOARD_NAME, "G513QY"), 1495 }, 1496 .driver_data = &(struct power_data) { 1497 .ac_data = &(struct power_limits) { 1498 /* Advantage Edition Laptop, no PL1 or PL2 limits */ 1499 .ppt_apu_sppt_min = 15, 1500 .ppt_apu_sppt_max = 100, 1501 .ppt_platform_sppt_min = 70, 1502 .ppt_platform_sppt_max = 190, 1503 }, 1504 .dc_data = NULL, 1505 .requires_fan_curve = true, 1506 }, 1507 }, 1508 { 1509 .matches = { 1510 DMI_MATCH(DMI_BOARD_NAME, "G513R"), 1511 }, 1512 .driver_data = &(struct power_data) { 1513 .ac_data = &(struct power_limits) { 1514 .ppt_pl1_spl_min = 35, 1515 .ppt_pl1_spl_max = 90, 1516 .ppt_pl2_sppt_min = 54, 1517 .ppt_pl2_sppt_max = 100, 1518 .ppt_pl3_fppt_min = 54, 1519 .ppt_pl3_fppt_max = 125, 1520 .nv_dynamic_boost_min = 5, 1521 .nv_dynamic_boost_max = 25, 1522 .nv_temp_target_min = 75, 1523 .nv_temp_target_max = 87, 1524 }, 1525 .dc_data = &(struct power_limits) { 1526 .ppt_pl1_spl_min = 28, 1527 .ppt_pl1_spl_max = 50, 1528 .ppt_pl2_sppt_min = 28, 1529 .ppt_pl2_sppt_max = 50, 1530 .ppt_pl3_fppt_min = 28, 1531 .ppt_pl3_fppt_max = 65, 1532 .nv_temp_target_min = 75, 1533 .nv_temp_target_max = 87, 1534 }, 1535 .requires_fan_curve = true, 1536 }, 1537 }, 1538 { 1539 .matches = { 1540 DMI_MATCH(DMI_BOARD_NAME, "G614J"), 1541 }, 1542 .driver_data = &(struct power_data) { 1543 .ac_data = &(struct power_limits) { 1544 .ppt_pl1_spl_min = 28, 1545 .ppt_pl1_spl_max = 140, 1546 .ppt_pl2_sppt_min = 28, 1547 .ppt_pl2_sppt_max = 175, 1548 .nv_temp_target_min = 75, 1549 .nv_temp_target_max = 87, 1550 .nv_dynamic_boost_min = 5, 1551 .nv_dynamic_boost_max = 25, 1552 }, 1553 .dc_data = &(struct power_limits) { 1554 .ppt_pl1_spl_min = 25, 1555 .ppt_pl1_spl_max = 55, 1556 .ppt_pl2_sppt_min = 25, 1557 .ppt_pl2_sppt_max = 70, 1558 .nv_temp_target_min = 75, 1559 .nv_temp_target_max = 87, 1560 }, 1561 .requires_fan_curve = true, 1562 }, 1563 }, 1564 { 1565 .matches = { 1566 DMI_MATCH(DMI_BOARD_NAME, "G615LR"), 1567 }, 1568 .driver_data = &(struct power_data) { 1569 .ac_data = &(struct power_limits) { 1570 .ppt_pl1_spl_min = 28, 1571 .ppt_pl1_spl_def = 140, 1572 .ppt_pl1_spl_max = 175, 1573 .ppt_pl2_sppt_min = 28, 1574 .ppt_pl2_sppt_max = 175, 1575 .nv_temp_target_min = 75, 1576 .nv_temp_target_max = 87, 1577 .nv_dynamic_boost_min = 5, 1578 .nv_dynamic_boost_max = 25, 1579 .nv_tgp_min = 65, 1580 .nv_tgp_max = 115, 1581 }, 1582 .dc_data = &(struct power_limits) { 1583 .ppt_pl1_spl_min = 25, 1584 .ppt_pl1_spl_max = 55, 1585 .ppt_pl2_sppt_min = 25, 1586 .ppt_pl2_sppt_max = 70, 1587 .nv_temp_target_min = 75, 1588 .nv_temp_target_max = 87, 1589 }, 1590 .requires_fan_curve = true, 1591 }, 1592 }, 1593 { 1594 .matches = { 1595 DMI_MATCH(DMI_BOARD_NAME, "G634J"), 1596 }, 1597 .driver_data = &(struct power_data) { 1598 .ac_data = &(struct power_limits) { 1599 .ppt_pl1_spl_min = 28, 1600 .ppt_pl1_spl_max = 140, 1601 .ppt_pl2_sppt_min = 28, 1602 .ppt_pl2_sppt_max = 175, 1603 .nv_temp_target_min = 75, 1604 .nv_temp_target_max = 87, 1605 .nv_dynamic_boost_min = 5, 1606 .nv_dynamic_boost_max = 25, 1607 }, 1608 .dc_data = &(struct power_limits) { 1609 .ppt_pl1_spl_min = 25, 1610 .ppt_pl1_spl_max = 55, 1611 .ppt_pl2_sppt_min = 25, 1612 .ppt_pl2_sppt_max = 70, 1613 .nv_temp_target_min = 75, 1614 .nv_temp_target_max = 87, 1615 }, 1616 .requires_fan_curve = true, 1617 }, 1618 }, 1619 { 1620 .matches = { 1621 DMI_MATCH(DMI_BOARD_NAME, "G713PV"), 1622 }, 1623 .driver_data = &(struct power_data) { 1624 .ac_data = &(struct power_limits) { 1625 .ppt_pl1_spl_min = 30, 1626 .ppt_pl1_spl_def = 120, 1627 .ppt_pl1_spl_max = 130, 1628 .ppt_pl2_sppt_min = 65, 1629 .ppt_pl2_sppt_def = 125, 1630 .ppt_pl2_sppt_max = 130, 1631 .ppt_pl3_fppt_min = 65, 1632 .ppt_pl3_fppt_def = 125, 1633 .ppt_pl3_fppt_max = 130, 1634 .nv_temp_target_min = 75, 1635 .nv_temp_target_max = 87, 1636 .nv_dynamic_boost_min = 5, 1637 .nv_dynamic_boost_max = 25, 1638 }, 1639 .dc_data = &(struct power_limits) { 1640 .ppt_pl1_spl_min = 25, 1641 .ppt_pl1_spl_max = 65, 1642 .ppt_pl2_sppt_min = 25, 1643 .ppt_pl2_sppt_max = 65, 1644 .ppt_pl3_fppt_min = 35, 1645 .ppt_pl3_fppt_max = 75, 1646 .nv_temp_target_min = 75, 1647 .nv_temp_target_max = 87, 1648 }, 1649 .requires_fan_curve = true, 1650 }, 1651 }, 1652 { 1653 .matches = { 1654 DMI_MATCH(DMI_BOARD_NAME, "G733C"), 1655 }, 1656 .driver_data = &(struct power_data) { 1657 .ac_data = &(struct power_limits) { 1658 .ppt_pl1_spl_min = 28, 1659 .ppt_pl1_spl_max = 170, 1660 .ppt_pl2_sppt_min = 28, 1661 .ppt_pl2_sppt_max = 175, 1662 .nv_temp_target_min = 75, 1663 .nv_temp_target_max = 87, 1664 .nv_dynamic_boost_min = 5, 1665 .nv_dynamic_boost_max = 25, 1666 }, 1667 .dc_data = &(struct power_limits) { 1668 .ppt_pl1_spl_min = 28, 1669 .ppt_pl1_spl_max = 35, 1670 .ppt_pl2_sppt_min = 28, 1671 .ppt_pl2_sppt_max = 35, 1672 .nv_temp_target_min = 75, 1673 .nv_temp_target_max = 87, 1674 }, 1675 .requires_fan_curve = true, 1676 }, 1677 }, 1678 { 1679 .matches = { 1680 DMI_MATCH(DMI_BOARD_NAME, "G733P"), 1681 }, 1682 .driver_data = &(struct power_data) { 1683 .ac_data = &(struct power_limits) { 1684 .ppt_pl1_spl_min = 30, 1685 .ppt_pl1_spl_def = 100, 1686 .ppt_pl1_spl_max = 130, 1687 .ppt_pl2_sppt_min = 65, 1688 .ppt_pl2_sppt_def = 125, 1689 .ppt_pl2_sppt_max = 130, 1690 .ppt_pl3_fppt_min = 65, 1691 .ppt_pl3_fppt_def = 125, 1692 .ppt_pl3_fppt_max = 130, 1693 .nv_temp_target_min = 75, 1694 .nv_temp_target_max = 87, 1695 .nv_dynamic_boost_min = 5, 1696 .nv_dynamic_boost_max = 25, 1697 }, 1698 .dc_data = &(struct power_limits) { 1699 .ppt_pl1_spl_min = 25, 1700 .ppt_pl1_spl_max = 65, 1701 .ppt_pl2_sppt_min = 25, 1702 .ppt_pl2_sppt_max = 65, 1703 .ppt_pl3_fppt_min = 35, 1704 .ppt_pl3_fppt_max = 75, 1705 .nv_temp_target_min = 75, 1706 .nv_temp_target_max = 87, 1707 }, 1708 .requires_fan_curve = true, 1709 }, 1710 }, 1711 { 1712 .matches = { 1713 DMI_MATCH(DMI_BOARD_NAME, "G814J"), 1714 }, 1715 .driver_data = &(struct power_data) { 1716 .ac_data = &(struct power_limits) { 1717 .ppt_pl1_spl_min = 28, 1718 .ppt_pl1_spl_max = 140, 1719 .ppt_pl2_sppt_min = 28, 1720 .ppt_pl2_sppt_max = 140, 1721 .nv_dynamic_boost_min = 5, 1722 .nv_dynamic_boost_max = 25, 1723 }, 1724 .dc_data = &(struct power_limits) { 1725 .ppt_pl1_spl_min = 25, 1726 .ppt_pl1_spl_max = 55, 1727 .ppt_pl2_sppt_min = 25, 1728 .ppt_pl2_sppt_max = 70, 1729 }, 1730 .requires_fan_curve = true, 1731 }, 1732 }, 1733 { 1734 .matches = { 1735 DMI_MATCH(DMI_BOARD_NAME, "G834J"), 1736 }, 1737 .driver_data = &(struct power_data) { 1738 .ac_data = &(struct power_limits) { 1739 .ppt_pl1_spl_min = 28, 1740 .ppt_pl1_spl_max = 140, 1741 .ppt_pl2_sppt_min = 28, 1742 .ppt_pl2_sppt_max = 175, 1743 .nv_dynamic_boost_min = 5, 1744 .nv_dynamic_boost_max = 25, 1745 .nv_temp_target_min = 75, 1746 .nv_temp_target_max = 87, 1747 }, 1748 .dc_data = &(struct power_limits) { 1749 .ppt_pl1_spl_min = 25, 1750 .ppt_pl1_spl_max = 55, 1751 .ppt_pl2_sppt_min = 25, 1752 .ppt_pl2_sppt_max = 70, 1753 .nv_temp_target_min = 75, 1754 .nv_temp_target_max = 87, 1755 }, 1756 .requires_fan_curve = true, 1757 }, 1758 }, 1759 { 1760 .matches = { 1761 DMI_MATCH(DMI_BOARD_NAME, "G835LR"), 1762 }, 1763 .driver_data = &(struct power_data) { 1764 .ac_data = &(struct power_limits) { 1765 .ppt_pl1_spl_min = 28, 1766 .ppt_pl1_spl_def = 140, 1767 .ppt_pl1_spl_max = 175, 1768 .ppt_pl2_sppt_min = 28, 1769 .ppt_pl2_sppt_max = 175, 1770 .nv_dynamic_boost_min = 5, 1771 .nv_dynamic_boost_max = 25, 1772 .nv_temp_target_min = 75, 1773 .nv_temp_target_max = 87, 1774 .nv_tgp_min = 65, 1775 .nv_tgp_max = 115, 1776 }, 1777 .dc_data = &(struct power_limits) { 1778 .ppt_pl1_spl_min = 25, 1779 .ppt_pl1_spl_max = 55, 1780 .ppt_pl2_sppt_min = 25, 1781 .ppt_pl2_sppt_max = 70, 1782 .nv_temp_target_min = 75, 1783 .nv_temp_target_max = 87, 1784 }, 1785 .requires_fan_curve = true, 1786 }, 1787 }, 1788 { 1789 .matches = { 1790 DMI_MATCH(DMI_BOARD_NAME, "G835LW"), 1791 }, 1792 .driver_data = &(struct power_data) { 1793 .ac_data = &(struct power_limits) { 1794 .ppt_pl1_spl_min = 28, 1795 .ppt_pl1_spl_def = 140, 1796 .ppt_pl1_spl_max = 175, 1797 .ppt_pl2_sppt_min = 28, 1798 .ppt_pl2_sppt_max = 175, 1799 .nv_dynamic_boost_min = 5, 1800 .nv_dynamic_boost_max = 25, 1801 .nv_temp_target_min = 75, 1802 .nv_temp_target_max = 87, 1803 .nv_tgp_min = 80, 1804 .nv_tgp_max = 150, 1805 }, 1806 .dc_data = &(struct power_limits) { 1807 .ppt_pl1_spl_min = 25, 1808 .ppt_pl1_spl_max = 55, 1809 .ppt_pl2_sppt_min = 25, 1810 .ppt_pl2_sppt_max = 70, 1811 .nv_temp_target_min = 75, 1812 .nv_temp_target_max = 87, 1813 }, 1814 .requires_fan_curve = true, 1815 }, 1816 }, 1817 { 1818 .matches = { 1819 DMI_MATCH(DMI_BOARD_NAME, "H7606W"), 1820 }, 1821 .driver_data = &(struct power_data) { 1822 .ac_data = &(struct power_limits) { 1823 .ppt_pl1_spl_min = 15, 1824 .ppt_pl1_spl_max = 80, 1825 .ppt_pl2_sppt_min = 35, 1826 .ppt_pl2_sppt_max = 80, 1827 .ppt_pl3_fppt_min = 35, 1828 .ppt_pl3_fppt_max = 80, 1829 .nv_dynamic_boost_min = 5, 1830 .nv_dynamic_boost_max = 20, 1831 .nv_temp_target_min = 75, 1832 .nv_temp_target_max = 87, 1833 .nv_tgp_min = 55, 1834 .nv_tgp_max = 85, 1835 }, 1836 .dc_data = &(struct power_limits) { 1837 .ppt_pl1_spl_min = 25, 1838 .ppt_pl1_spl_max = 35, 1839 .ppt_pl2_sppt_min = 31, 1840 .ppt_pl2_sppt_max = 44, 1841 .ppt_pl3_fppt_min = 45, 1842 .ppt_pl3_fppt_max = 65, 1843 .nv_temp_target_min = 75, 1844 .nv_temp_target_max = 87, 1845 }, 1846 }, 1847 }, 1848 { 1849 .matches = { 1850 DMI_MATCH(DMI_BOARD_NAME, "RC71"), 1851 }, 1852 .driver_data = &(struct power_data) { 1853 .ac_data = &(struct power_limits) { 1854 .ppt_pl1_spl_min = 7, 1855 .ppt_pl1_spl_max = 30, 1856 .ppt_pl2_sppt_min = 15, 1857 .ppt_pl2_sppt_max = 43, 1858 .ppt_pl3_fppt_min = 15, 1859 .ppt_pl3_fppt_max = 53, 1860 }, 1861 .dc_data = &(struct power_limits) { 1862 .ppt_pl1_spl_min = 7, 1863 .ppt_pl1_spl_def = 15, 1864 .ppt_pl1_spl_max = 25, 1865 .ppt_pl2_sppt_min = 15, 1866 .ppt_pl2_sppt_def = 20, 1867 .ppt_pl2_sppt_max = 30, 1868 .ppt_pl3_fppt_min = 15, 1869 .ppt_pl3_fppt_def = 25, 1870 .ppt_pl3_fppt_max = 35, 1871 }, 1872 }, 1873 }, 1874 { 1875 .matches = { 1876 DMI_MATCH(DMI_BOARD_NAME, "RC72"), 1877 }, 1878 .driver_data = &(struct power_data) { 1879 .ac_data = &(struct power_limits) { 1880 .ppt_pl1_spl_min = 7, 1881 .ppt_pl1_spl_max = 30, 1882 .ppt_pl2_sppt_min = 15, 1883 .ppt_pl2_sppt_max = 43, 1884 .ppt_pl3_fppt_min = 15, 1885 .ppt_pl3_fppt_max = 53, 1886 }, 1887 .dc_data = &(struct power_limits) { 1888 .ppt_pl1_spl_min = 7, 1889 .ppt_pl1_spl_def = 17, 1890 .ppt_pl1_spl_max = 25, 1891 .ppt_pl2_sppt_min = 15, 1892 .ppt_pl2_sppt_def = 24, 1893 .ppt_pl2_sppt_max = 30, 1894 .ppt_pl3_fppt_min = 15, 1895 .ppt_pl3_fppt_def = 30, 1896 .ppt_pl3_fppt_max = 35, 1897 }, 1898 }, 1899 }, 1900 { 1901 .matches = { 1902 DMI_MATCH(DMI_BOARD_NAME, "RC73XA"), 1903 }, 1904 .driver_data = &(struct power_data) { 1905 .ac_data = &(struct power_limits) { 1906 .ppt_pl1_spl_min = 7, 1907 .ppt_pl1_spl_max = 35, 1908 .ppt_pl2_sppt_min = 14, 1909 .ppt_pl2_sppt_max = 45, 1910 .ppt_pl3_fppt_min = 19, 1911 .ppt_pl3_fppt_max = 55, 1912 }, 1913 .dc_data = &(struct power_limits) { 1914 .ppt_pl1_spl_min = 7, 1915 .ppt_pl1_spl_def = 17, 1916 .ppt_pl1_spl_max = 35, 1917 .ppt_pl2_sppt_min = 13, 1918 .ppt_pl2_sppt_def = 21, 1919 .ppt_pl2_sppt_max = 45, 1920 .ppt_pl3_fppt_min = 19, 1921 .ppt_pl3_fppt_def = 26, 1922 .ppt_pl3_fppt_max = 55, 1923 }, 1924 }, 1925 }, 1926 {} 1927}; 1928 1929#endif /* _ASUS_ARMOURY_H_ */
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