pmf.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * AMD Platform Management Framework Driver
  4 *
  5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
  9 */
 10
 11#ifndef PMF_H
 12#define PMF_H
 13
 14#include <linux/acpi.h>
 15#include <linux/input.h>
 16#include <linux/platform_device.h>
 17#include <linux/platform_profile.h>
 18
 19#define POLICY_BUF_MAX_SZ		0x4b000
 20#define POLICY_SIGN_COOKIE		0x31535024
 21#define POLICY_COOKIE_OFFSET		0x10
 22
 23/* List of supported CPU ids */
 24#define AMD_CPU_ID_RMB                  0x14b5
 25#define AMD_CPU_ID_PS                   0x14e8
 26#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
 27#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
 28
 29struct cookie_header {
 30	u32 sign;
 31	u32 length;
 32} __packed;
 33
 34/* APMF Functions */
 35#define APMF_FUNC_VERIFY_INTERFACE			0
 36#define APMF_FUNC_GET_SYS_PARAMS			1
 37#define APMF_FUNC_SBIOS_REQUESTS			2
 38#define APMF_FUNC_SBIOS_HEARTBEAT			4
 39#define APMF_FUNC_AUTO_MODE					5
 40#define APMF_FUNC_SET_FAN_IDX				7
 41#define APMF_FUNC_OS_POWER_SLIDER_UPDATE		8
 42#define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
 43#define APMF_FUNC_DYN_SLIDER_AC				11
 44#define APMF_FUNC_DYN_SLIDER_DC				12
 45#define APMF_FUNC_NOTIFY_SMART_PC_UPDATES		14
 46#define APMF_FUNC_SBIOS_HEARTBEAT_V2			16
 47
 48/* Message Definitions */
 49#define SET_SPL				0x03 /* SPL: Sustained Power Limit */
 50#define SET_SPPT			0x05 /* SPPT: Slow Package Power Tracking */
 51#define SET_FPPT			0x07 /* FPPT: Fast Package Power Tracking */
 52#define GET_SPL				0x0B
 53#define GET_SPPT			0x0D
 54#define GET_FPPT			0x0F
 55#define SET_DRAM_ADDR_HIGH	0x14
 56#define SET_DRAM_ADDR_LOW	0x15
 57#define SET_TRANSFER_TABLE	0x16
 58#define SET_STT_MIN_LIMIT	0x18 /* STT: Skin Temperature Tracking */
 59#define SET_STT_LIMIT_APU	0x19
 60#define SET_STT_LIMIT_HS2	0x1A
 61#define SET_SPPT_APU_ONLY	0x1D
 62#define GET_SPPT_APU_ONLY	0x1E
 63#define GET_STT_MIN_LIMIT	0x1F
 64#define GET_STT_LIMIT_APU	0x20
 65#define GET_STT_LIMIT_HS2	0x21
 66#define SET_P3T				0x23 /* P3T: Peak Package Power Limit */
 67#define SET_PMF_PPT            0x25
 68#define SET_PMF_PPT_APU_ONLY   0x26
 69
 70/* OS slider update notification */
 71#define DC_BEST_PERF		0
 72#define DC_BETTER_PERF		1
 73#define DC_BATTERY_SAVER	3
 74#define AC_BEST_PERF		4
 75#define AC_BETTER_PERF		5
 76#define AC_BETTER_BATTERY	6
 77
 78/* Fan Index for Auto Mode */
 79#define FAN_INDEX_AUTO		0xFFFFFFFF
 80
 81#define ARG_NONE 0
 82#define AVG_SAMPLE_SIZE 3
 83
 84/* Policy Actions */
 85#define PMF_POLICY_SPL						2
 86#define PMF_POLICY_SPPT						3
 87#define PMF_POLICY_FPPT						4
 88#define PMF_POLICY_SPPT_APU_ONLY				5
 89#define PMF_POLICY_STT_MIN					6
 90#define PMF_POLICY_STT_SKINTEMP_APU				7
 91#define PMF_POLICY_STT_SKINTEMP_HS2				8
 92#define PMF_POLICY_SYSTEM_STATE					9
 93#define PMF_POLICY_BIOS_OUTPUT_1				10
 94#define PMF_POLICY_BIOS_OUTPUT_2				11
 95#define PMF_POLICY_P3T						38
 96#define PMF_POLICY_PMF_PPT					54
 97#define PMF_POLICY_PMF_PPT_APU_ONLY				55
 98#define PMF_POLICY_BIOS_OUTPUT_3				57
 99#define PMF_POLICY_BIOS_OUTPUT_4				58
100#define PMF_POLICY_BIOS_OUTPUT_5				59
101#define PMF_POLICY_BIOS_OUTPUT_6				60
102#define PMF_POLICY_BIOS_OUTPUT_7				61
103#define PMF_POLICY_BIOS_OUTPUT_8				62
104#define PMF_POLICY_BIOS_OUTPUT_9				63
105#define PMF_POLICY_BIOS_OUTPUT_10				64
106
107/* TA macros */
108#define PMF_TA_IF_VERSION_MAJOR				1
109#define TA_PMF_ACTION_MAX					32
110#define TA_PMF_UNDO_MAX						8
111#define TA_OUTPUT_RESERVED_MEM				922
112#define MAX_OPERATION_PARAMS					4
113
114#define TA_ERROR_CRYPTO_INVALID_PARAM				0x20002
115#define TA_ERROR_CRYPTO_BIN_TOO_LARGE				0x2000d
116
117#define PMF_IF_V1		1
118#define PMF_IF_V2		2
119
120#define APTS_MAX_STATES		16
121#define CUSTOM_BIOS_INPUT_BITS	GENMASK(16, 7)
122#define BIOS_INPUTS_MAX		10
123
124/* amd_pmf_send_cmd() set/get */
125#define SET_CMD		false
126#define GET_CMD		true
127
128#define METRICS_TABLE_ID	7
129
130typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data);
131
132static const uuid_t amd_pmf_ta_uuid[] __used = { UUID_INIT(0xd9b39bf2, 0x66bd, 0x4154, 0xaf, 0xb8,
133							   0x8a, 0xcc, 0x2b, 0x2b, 0x60, 0xd6),
134						 UUID_INIT(0x6fd93b77, 0x3fb8, 0x524d, 0xb1, 0x2d,
135							   0xc5, 0x29, 0xb1, 0x3d, 0x85, 0x43),
136					       };
137
138/* APTS PMF BIOS Interface */
139struct amd_pmf_apts_output {
140	u16 table_version;
141	u32 fan_table_idx;
142	u32 pmf_ppt;
143	u32 ppt_pmf_apu_only;
144	u32 stt_min_limit;
145	u8 stt_skin_temp_limit_apu;
146	u8 stt_skin_temp_limit_hs2;
147} __packed;
148
149struct amd_pmf_apts_granular_output {
150	u16 size;
151	struct amd_pmf_apts_output val;
152} __packed;
153
154struct amd_pmf_apts_granular {
155	u16 size;
156	struct amd_pmf_apts_output val[APTS_MAX_STATES];
157};
158
159struct sbios_hb_event_v2 {
160	u16 size;
161	u8 load;
162	u8 unload;
163	u8 suspend;
164	u8 resume;
165} __packed;
166
167enum sbios_hb_v2 {
168	ON_LOAD,
169	ON_UNLOAD,
170	ON_SUSPEND,
171	ON_RESUME,
172};
173
174/* AMD PMF BIOS interfaces */
175struct apmf_verify_interface {
176	u16 size;
177	u16 version;
178	u32 notification_mask;
179	u32 supported_functions;
180} __packed;
181
182struct apmf_system_params {
183	u16 size;
184	u32 valid_mask;
185	u32 flags;
186	u8 command_code;
187	u32 heartbeat_int;
188} __packed;
189
190struct apmf_sbios_req {
191	u16 size;
192	u32 pending_req;
193	u8 rsd;
194	u8 cql_event;
195	u8 amt_event;
196	u32 fppt;
197	u32 sppt;
198	u32 fppt_apu_only;
199	u32 spl;
200	u32 stt_min_limit;
201	u8 skin_temp_apu;
202	u8 skin_temp_hs2;
203} __packed;
204
205/* As per APMF spec 1.3 */
206struct apmf_sbios_req_v1 {
207	u16 size;
208	u32 pending_req;
209	u8 rsvd;
210	u8 cql_event;
211	u8 amt_event;
212	u32 fppt;
213	u32 sppt;
214	u32 sppt_apu_only;
215	u32 spl;
216	u32 stt_min_limit;
217	u8 skin_temp_apu;
218	u8 skin_temp_hs2;
219	u8 enable_cnqf;
220	u32 custom_policy[BIOS_INPUTS_MAX];
221} __packed;
222
223struct apmf_sbios_req_v2 {
224	u16 size;
225	u32 pending_req;
226	u8 rsd;
227	u32 ppt_pmf;
228	u32 ppt_pmf_apu_only;
229	u32 stt_min_limit;
230	u8 skin_temp_apu;
231	u8 skin_temp_hs2;
232	u32 custom_policy[BIOS_INPUTS_MAX];
233} __packed;
234
235struct apmf_fan_idx {
236	u16 size;
237	u8 fan_ctl_mode;
238	u32 fan_ctl_idx;
239} __packed;
240
241struct smu_pmf_metrics_v2 {
242	u16 core_frequency[16];		/* MHz */
243	u16 core_power[16];		/* mW */
244	u16 core_temp[16];		/* centi-C */
245	u16 gfx_temp;			/* centi-C */
246	u16 soc_temp;			/* centi-C */
247	u16 stapm_opn_limit;		/* mW */
248	u16 stapm_cur_limit;		/* mW */
249	u16 infra_cpu_maxfreq;		/* MHz */
250	u16 infra_gfx_maxfreq;		/* MHz */
251	u16 skin_temp;			/* centi-C */
252	u16 gfxclk_freq;		/* MHz */
253	u16 fclk_freq;			/* MHz */
254	u16 gfx_activity;		/* GFX busy % [0-100] */
255	u16 socclk_freq;		/* MHz */
256	u16 vclk_freq;			/* MHz */
257	u16 vcn_activity;		/* VCN busy % [0-100] */
258	u16 vpeclk_freq;		/* MHz */
259	u16 npuclk_freq;		/* MHz */
260	u16 npu_busy[8];		/* NPU busy % [0-100] */
261	u16 dram_reads;			/* MB/sec */
262	u16 dram_writes;		/* MB/sec */
263	u16 core_c0residency[16];	/* C0 residency % [0-100] */
264	u16 npu_power;			/* mW */
265	u32 apu_power;			/* mW */
266	u32 gfx_power;			/* mW */
267	u32 dgpu_power;			/* mW */
268	u32 socket_power;		/* mW */
269	u32 all_core_power;		/* mW */
270	u32 filter_alpha_value;		/* time constant [us] */
271	u32 metrics_counter;
272	u16 memclk_freq;		/* MHz */
273	u16 mpnpuclk_freq;		/* MHz */
274	u16 npu_reads;			/* MB/sec */
275	u16 npu_writes;			/* MB/sec */
276	u32 throttle_residency_prochot;
277	u32 throttle_residency_spl;
278	u32 throttle_residency_fppt;
279	u32 throttle_residency_sppt;
280	u32 throttle_residency_thm_core;
281	u32 throttle_residency_thm_gfx;
282	u32 throttle_residency_thm_soc;
283	u16 psys;
284	u16 spare1;
285	u32 spare[6];
286} __packed;
287
288struct smu_pmf_metrics {
289	u16 gfxclk_freq; /* in MHz */
290	u16 socclk_freq; /* in MHz */
291	u16 vclk_freq; /* in MHz */
292	u16 dclk_freq; /* in MHz */
293	u16 memclk_freq; /* in MHz */
294	u16 spare;
295	u16 gfx_activity; /* in Centi */
296	u16 uvd_activity; /* in Centi */
297	u16 voltage[2]; /* in mV */
298	u16 currents[2]; /* in mA */
299	u16 power[2];/* in mW */
300	u16 core_freq[8]; /* in MHz */
301	u16 core_power[8]; /* in mW */
302	u16 core_temp[8]; /* in centi-Celsius */
303	u16 l3_freq; /* in MHz */
304	u16 l3_temp; /* in centi-Celsius */
305	u16 gfx_temp; /* in centi-Celsius */
306	u16 soc_temp; /* in centi-Celsius */
307	u16 throttler_status;
308	u16 current_socketpower; /* in mW */
309	u16 stapm_orig_limit; /* in W */
310	u16 stapm_cur_limit; /* in W */
311	u32 apu_power; /* in mW */
312	u32 dgpu_power; /* in mW */
313	u16 vdd_tdc_val; /* in mA */
314	u16 soc_tdc_val; /* in mA */
315	u16 vdd_edc_val; /* in mA */
316	u16 soc_edcv_al; /* in mA */
317	u16 infra_cpu_maxfreq; /* in MHz */
318	u16 infra_gfx_maxfreq; /* in MHz */
319	u16 skin_temp; /* in centi-Celsius */
320	u16 device_state;
321	u16 curtemp; /* in centi-Celsius */
322	u16 filter_alpha_value;
323	u16 avg_gfx_clkfrequency;
324	u16 avg_fclk_frequency;
325	u16 avg_gfx_activity;
326	u16 avg_socclk_frequency;
327	u16 avg_vclk_frequency;
328	u16 avg_vcn_activity;
329	u16 avg_dram_reads;
330	u16 avg_dram_writes;
331	u16 avg_socket_power;
332	u16 avg_core_power[2];
333	u16 avg_core_c0residency[16];
334	u16 spare1;
335	u32 metrics_counter;
336} __packed;
337
338enum amd_stt_skin_temp {
339	STT_TEMP_APU,
340	STT_TEMP_HS2,
341	STT_TEMP_COUNT,
342};
343
344enum amd_slider_op {
345	SLIDER_OP_GET,
346	SLIDER_OP_SET,
347};
348
349enum power_source {
350	POWER_SOURCE_AC,
351	POWER_SOURCE_DC,
352	POWER_SOURCE_MAX,
353};
354
355enum power_modes {
356	POWER_MODE_PERFORMANCE,
357	POWER_MODE_BALANCED_POWER,
358	POWER_MODE_POWER_SAVER,
359	POWER_MODE_MAX,
360};
361
362enum power_modes_v2 {
363	POWER_MODE_BEST_PERFORMANCE,
364	POWER_MODE_BALANCED,
365	POWER_MODE_BEST_POWER_EFFICIENCY,
366	POWER_MODE_ENERGY_SAVE,
367	POWER_MODE_V2_MAX,
368};
369
370struct pmf_bios_inputs_prev {
371	u32 custom_bios_inputs[BIOS_INPUTS_MAX];
372};
373
374struct amd_pmf_dev {
375	void __iomem *regbase;
376	void __iomem *smu_virt_addr;
377	void *buf;
378	u32 base_addr;
379	u32 cpu_id;
380	struct device *dev;
381	struct mutex lock; /* protects the PMF interface */
382	u32 supported_func;
383	enum platform_profile_option current_profile;
384	struct device *ppdev; /* platform profile class device */
385	struct dentry *dbgfs_dir;
386	int hb_interval; /* SBIOS heartbeat interval */
387	struct delayed_work heart_beat;
388	struct smu_pmf_metrics m_table;
389	struct smu_pmf_metrics_v2 m_table_v2;
390	struct delayed_work work_buffer;
391	ktime_t start_time;
392	int socket_power_history[AVG_SAMPLE_SIZE];
393	int socket_power_history_idx;
394	bool amt_enabled;
395	struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
396	bool cnqf_enabled;
397	bool cnqf_supported;
398	struct notifier_block pwr_src_notifier;
399	/* Smart PC solution builder */
400	struct dentry *esbin;
401	unsigned char *policy_buf;
402	resource_size_t policy_sz;
403	struct tee_context *tee_ctx;
404	struct tee_shm *fw_shm_pool;
405	u32 session_id;
406	void *shbuf;
407	struct delayed_work pb_work;
408	struct pmf_action_table *prev_data;
409	resource_size_t policy_addr;
410	void __iomem *policy_base;
411	bool smart_pc_enabled;
412	u16 pmf_if_version;
413	struct input_dev *pmf_idev;
414	size_t mtable_size;
415	struct resource *res;
416	struct apmf_sbios_req_v2 req; /* To get custom bios pending request */
417	struct mutex cb_mutex;
418	u32 notifications;
419	struct apmf_sbios_req_v1 req1;
420	struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */
421	bool cb_flag;			     /* To handle first custom BIOS input */
422};
423
424struct apmf_sps_prop_granular_v2 {
425	u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX];
426} __packed;
427
428struct apmf_sps_prop_granular {
429	u32 fppt;
430	u32 sppt;
431	u32 sppt_apu_only;
432	u32 spl;
433	u32 stt_min;
434	u8 stt_skin_temp[STT_TEMP_COUNT];
435	u32 fan_id;
436} __packed;
437
438/* Static Slider */
439struct apmf_static_slider_granular_output {
440	u16 size;
441	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
442} __packed;
443
444struct amd_pmf_static_slider_granular {
445	u16 size;
446	struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
447};
448
449struct apmf_static_slider_granular_output_v2 {
450	u16 size;
451	struct apmf_sps_prop_granular_v2 sps_idx;
452} __packed;
453
454struct amd_pmf_static_slider_granular_v2 {
455	u16 size;
456	struct apmf_sps_prop_granular_v2 sps_idx;
457};
458
459struct os_power_slider {
460	u16 size;
461	u8 slider_event;
462} __packed;
463
464struct amd_pmf_notify_smart_pc_update {
465	u16 size;
466	u32 pending_req;
467	u32 custom_bios[BIOS_INPUTS_MAX];
468} __packed;
469
470struct fan_table_control {
471	bool manual;
472	unsigned long fan_id;
473};
474
475struct power_table_control {
476	u32 spl;
477	u32 sppt;
478	u32 fppt;
479	u32 sppt_apu_only;
480	u32 stt_min;
481	u32 stt_skin_temp[STT_TEMP_COUNT];
482	u32 reserved[16];
483};
484
485/* Auto Mode Layer */
486enum auto_mode_transition_priority {
487	AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
488	AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
489	AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
490	AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
491	AUTO_TRANSITION_MAX,
492};
493
494enum auto_mode_mode {
495	AUTO_QUIET,
496	AUTO_BALANCE,
497	AUTO_PERFORMANCE_ON_LAP,
498	AUTO_PERFORMANCE,
499	AUTO_MODE_MAX,
500};
501
502struct auto_mode_trans_params {
503	u32 time_constant; /* minimum time required to switch to next mode */
504	u32 power_delta; /* delta power to shift mode */
505	u32 power_threshold;
506	u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
507	u32 applied;
508	enum auto_mode_mode target_mode;
509	u32 shifting_up;
510};
511
512struct auto_mode_mode_settings {
513	struct power_table_control power_control;
514	struct fan_table_control fan_control;
515	u32 power_floor;
516};
517
518struct auto_mode_mode_config {
519	struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
520	struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
521	enum auto_mode_mode current_mode;
522};
523
524struct apmf_auto_mode {
525	u16 size;
526	/* time constant */
527	u32 balanced_to_perf;
528	u32 perf_to_balanced;
529	u32 quiet_to_balanced;
530	u32 balanced_to_quiet;
531	/* power floor */
532	u32 pfloor_perf;
533	u32 pfloor_balanced;
534	u32 pfloor_quiet;
535	/* Power delta for mode change */
536	u32 pd_balanced_to_perf;
537	u32 pd_perf_to_balanced;
538	u32 pd_quiet_to_balanced;
539	u32 pd_balanced_to_quiet;
540	/* skin temperature limits */
541	u8 stt_apu_perf_on_lap; /* CQL ON */
542	u8 stt_hs2_perf_on_lap; /* CQL ON */
543	u8 stt_apu_perf;
544	u8 stt_hs2_perf;
545	u8 stt_apu_balanced;
546	u8 stt_hs2_balanced;
547	u8 stt_apu_quiet;
548	u8 stt_hs2_quiet;
549	u32 stt_min_limit_perf_on_lap; /* CQL ON */
550	u32 stt_min_limit_perf;
551	u32 stt_min_limit_balanced;
552	u32 stt_min_limit_quiet;
553	/* SPL based */
554	u32 fppt_perf_on_lap; /* CQL ON */
555	u32 sppt_perf_on_lap; /* CQL ON */
556	u32 spl_perf_on_lap; /* CQL ON */
557	u32 sppt_apu_only_perf_on_lap; /* CQL ON */
558	u32 fppt_perf;
559	u32 sppt_perf;
560	u32 spl_perf;
561	u32 sppt_apu_only_perf;
562	u32 fppt_balanced;
563	u32 sppt_balanced;
564	u32 spl_balanced;
565	u32 sppt_apu_only_balanced;
566	u32 fppt_quiet;
567	u32 sppt_quiet;
568	u32 spl_quiet;
569	u32 sppt_apu_only_quiet;
570	/* Fan ID */
571	u32 fan_id_perf;
572	u32 fan_id_balanced;
573	u32 fan_id_quiet;
574} __packed;
575
576/* CnQF Layer */
577enum cnqf_trans_priority {
578	CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
579	CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
580	CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
581	CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
582	CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
583	CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
584	CNQF_TRANSITION_MAX,
585};
586
587enum cnqf_mode {
588	CNQF_MODE_QUIET,
589	CNQF_MODE_BALANCE,
590	CNQF_MODE_PERFORMANCE,
591	CNQF_MODE_TURBO,
592	CNQF_MODE_MAX,
593};
594
595enum apmf_cnqf_pos {
596	APMF_CNQF_TURBO,
597	APMF_CNQF_PERFORMANCE,
598	APMF_CNQF_BALANCE,
599	APMF_CNQF_QUIET,
600	APMF_CNQF_MAX,
601};
602
603struct cnqf_mode_settings {
604	struct power_table_control power_control;
605	struct fan_table_control fan_control;
606	u32 power_floor;
607};
608
609struct cnqf_tran_params {
610	u32 time_constant; /* minimum time required to switch to next mode */
611	u32 power_threshold;
612	u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
613	u32 total_power;
614	u32 count;
615	bool priority;
616	bool shifting_up;
617	enum cnqf_mode target_mode;
618};
619
620struct cnqf_config {
621	struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
622	struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
623	struct power_table_control defaults;
624	enum cnqf_mode current_mode;
625	u32 power_src;
626	u32 avg_power;
627};
628
629struct apmf_cnqf_power_set {
630	u32 pfloor;
631	u32 fppt;
632	u32 sppt;
633	u32 sppt_apu_only;
634	u32 spl;
635	u32 stt_min_limit;
636	u8 stt_skintemp[STT_TEMP_COUNT];
637	u32 fan_id;
638} __packed;
639
640struct apmf_dyn_slider_output {
641	u16 size;
642	u16 flags;
643	u32 t_perf_to_turbo;
644	u32 t_balanced_to_perf;
645	u32 t_quiet_to_balanced;
646	u32 t_balanced_to_quiet;
647	u32 t_perf_to_balanced;
648	u32 t_turbo_to_perf;
649	struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
650} __packed;
651
652/* Smart PC - TA internals */
653enum system_state {
654	SYSTEM_STATE_S0i3,
655	SYSTEM_STATE_S4,
656	SYSTEM_STATE_SCREEN_LOCK,
657	SYSTEM_STATE_MAX,
658};
659
660enum ta_slider {
661	TA_BEST_BATTERY,
662	TA_BETTER_BATTERY,
663	TA_BETTER_PERFORMANCE,
664	TA_BEST_PERFORMANCE,
665	TA_MAX,
666};
667
668struct amd_pmf_pb_bitmap {
669	const char *name;
670	u32 bit_mask;
671};
672
673static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = {
674	{"NOTIFY_CUSTOM_BIOS_INPUT1",     BIT(5)},
675	{"NOTIFY_CUSTOM_BIOS_INPUT2",     BIT(6)},
676	{"NOTIFY_CUSTOM_BIOS_INPUT3",     BIT(7)},
677	{"NOTIFY_CUSTOM_BIOS_INPUT4",     BIT(8)},
678	{"NOTIFY_CUSTOM_BIOS_INPUT5",     BIT(9)},
679	{"NOTIFY_CUSTOM_BIOS_INPUT6",     BIT(10)},
680	{"NOTIFY_CUSTOM_BIOS_INPUT7",     BIT(11)},
681	{"NOTIFY_CUSTOM_BIOS_INPUT8",     BIT(12)},
682	{"NOTIFY_CUSTOM_BIOS_INPUT9",     BIT(13)},
683	{"NOTIFY_CUSTOM_BIOS_INPUT10",    BIT(14)},
684};
685
686static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = {
687	{"NOTIFY_CUSTOM_BIOS_INPUT1",     BIT(7)},
688	{"NOTIFY_CUSTOM_BIOS_INPUT2",     BIT(8)},
689	{"NOTIFY_CUSTOM_BIOS_INPUT3",     BIT(9)},
690	{"NOTIFY_CUSTOM_BIOS_INPUT4",     BIT(10)},
691	{"NOTIFY_CUSTOM_BIOS_INPUT5",     BIT(11)},
692	{"NOTIFY_CUSTOM_BIOS_INPUT6",     BIT(12)},
693	{"NOTIFY_CUSTOM_BIOS_INPUT7",     BIT(13)},
694	{"NOTIFY_CUSTOM_BIOS_INPUT8",     BIT(14)},
695	{"NOTIFY_CUSTOM_BIOS_INPUT9",     BIT(15)},
696	{"NOTIFY_CUSTOM_BIOS_INPUT10",    BIT(16)},
697};
698
699enum platform_type {
700	PTYPE_UNKNOWN = 0,
701	LID_CLOSE,
702	CLAMSHELL,
703	FLAT,
704	TENT,
705	STAND,
706	TABLET,
707	BOOK,
708	PRESENTATION,
709	PULL_FWD,
710	PTYPE_INVALID = 0xf,
711};
712
713/* Command ids for TA communication */
714enum ta_pmf_command {
715	TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
716	TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
717};
718
719enum ta_pmf_error_type {
720	TA_PMF_TYPE_SUCCESS,
721	TA_PMF_ERROR_TYPE_GENERIC,
722	TA_PMF_ERROR_TYPE_CRYPTO,
723	TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
724	TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
725	TA_PMF_ERROR_TYPE_POLICY_BUILDER,
726	TA_PMF_ERROR_TYPE_PB_CONVERT,
727	TA_PMF_ERROR_TYPE_PB_SETUP,
728	TA_PMF_ERROR_TYPE_PB_ENACT,
729	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
730	TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
731	TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
732	TA_PMF_ERROR_TYPE_MAX,
733};
734
735struct pmf_action_table {
736	enum system_state system_state;
737	u32 spl;		/* in mW */
738	u32 sppt;		/* in mW */
739	u32 sppt_apuonly;	/* in mW */
740	u32 fppt;		/* in mW */
741	u32 stt_minlimit;	/* in mW */
742	u32 stt_skintemp_apu;	/* in C */
743	u32 stt_skintemp_hs2;	/* in C */
744	u32 p3t_limit;		/* in mW */
745	u32 pmf_ppt;		/* in mW */
746	u32 pmf_ppt_apu_only;	/* in mW */
747};
748
749/* Input conditions */
750struct ta_pmf_condition_info {
751	u32 power_source;
752	u32 bat_percentage;
753	u32 power_slider;
754	u32 lid_state;
755	bool user_present;
756	u32 bios_input_1[2];
757	u32 monitor_count;
758	u32 rsvd2[2];
759	u32 bat_design;
760	u32 full_charge_capacity;
761	int drain_rate;
762	bool user_engaged;
763	u32 device_state;
764	u32 socket_power;
765	u32 skin_temperature;
766	u32 rsvd3[2];
767	u32 platform_type;
768	u32 rsvd3_1[2];
769	u32 ambient_light;
770	u32 length;
771	u32 avg_c0residency;
772	u32 max_c0residency;
773	u32 s0i3_entry;
774	u32 gfx_busy;
775	u32 rsvd4[7];
776	bool camera_state;
777	u32 workload_type;
778	u32 display_type;
779	u32 display_state;
780	u32 rsvd5_1[17];
781	u32 bios_input_2[8];
782	u32 rsvd5[125];
783};
784
785struct ta_pmf_load_policy_table {
786	u32 table_size;
787	u8 table[POLICY_BUF_MAX_SZ];
788};
789
790/* TA initialization params */
791struct ta_pmf_init_table {
792	u32 frequency; /* SMU sampling frequency */
793	bool validate;
794	bool sku_check;
795	bool metadata_macrocheck;
796	struct ta_pmf_load_policy_table policies_table;
797};
798
799/* Everything the TA needs to Enact Policies */
800struct ta_pmf_enact_table {
801	struct ta_pmf_condition_info ev_info;
802	u32 name;
803};
804
805struct ta_pmf_action {
806	u32 action_index;
807	u32 value;
808	u32 spl_arg;
809};
810
811/* Output actions from TA */
812struct ta_pmf_enact_result {
813	u32 actions_count;
814	struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
815	u32 undo_count;
816	struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
817};
818
819union ta_pmf_input {
820	struct ta_pmf_enact_table enact_table;
821	struct ta_pmf_init_table init_table;
822};
823
824union ta_pmf_output {
825	struct ta_pmf_enact_result policy_apply_table;
826	u32 rsvd[TA_OUTPUT_RESERVED_MEM];
827};
828
829struct ta_pmf_shared_memory {
830	int command_id;
831	int resp_id;
832	u32 pmf_result;
833	u32 if_version;
834	union ta_pmf_output pmf_output;
835	union ta_pmf_input pmf_input;
836};
837
838/* Core Layer */
839int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
840void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
841int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
842int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
843int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
844int amd_pmf_get_power_source(void);
845int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
846int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
847int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);
848int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag);
849u32 fixp_q88_fromint(u32 val);
850int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev);
851
852/* SPS Layer */
853int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
854void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
855			   struct amd_pmf_static_slider_granular *table);
856int amd_pmf_init_sps(struct amd_pmf_dev *dev);
857int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
858				    struct apmf_static_slider_granular_output *output);
859bool is_pprof_balanced(struct amd_pmf_dev *pmf);
860int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
861const char *amd_pmf_source_as_str(unsigned int state);
862
863const char *amd_pmf_source_as_str(unsigned int state);
864
865int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
866int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
867int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev,
868				       struct apmf_static_slider_granular_output_v2 *data);
869int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev,
870				       struct amd_pmf_apts_granular_output *data, u32 apts_idx);
871
872/* Auto Mode Layer */
873int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
874void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
875void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
876void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
877int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
878int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v1 *req);
879int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req);
880
881void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
882int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
883void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
884
885/* CnQF Layer */
886int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
887int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
888int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
889void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
890int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
891extern const struct attribute_group cnqf_feature_attribute_group;
892
893/* Smart PC builder Layer */
894int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
895void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
896int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
897int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx);
898
899/* Smart PC - TA interfaces */
900void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
901void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
902int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev);
903
904int amd_pmf_tee_init(struct amd_pmf_dev *dev, const uuid_t *uuid);
905void amd_pmf_tee_deinit(struct amd_pmf_dev *dev);
906int amd_pmf_start_policy_engine(struct amd_pmf_dev *dev);
907
908#endif /* PMF_H */