pmc.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * AMD SoC Power Management Controller Driver
  4 *
  5 * Copyright (c) 2023, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Mario Limonciello <mario.limonciello@amd.com>
  9 */
 10
 11#ifndef PMC_H
 12#define PMC_H
 13
 14#include <linux/types.h>
 15#include <linux/mutex.h>
 16
 17/* SMU communication registers */
 18#define AMD_PMC_REGISTER_RESPONSE	0x980
 19#define AMD_PMC_REGISTER_ARGUMENT	0x9BC
 20
 21/* PMC Scratch Registers */
 22#define AMD_PMC_SCRATCH_REG_CZN		0x94
 23#define AMD_PMC_SCRATCH_REG_YC		0xD14
 24#define AMD_PMC_SCRATCH_REG_1AH		0xF14
 25
 26/* STB Registers */
 27#define AMD_PMC_STB_S2IDLE_PREPARE	0xC6000001
 28#define AMD_PMC_STB_S2IDLE_RESTORE	0xC6000002
 29#define AMD_PMC_STB_S2IDLE_CHECK	0xC6000003
 30
 31/* Base address of SMU for mapping physical address to virtual address */
 32#define AMD_PMC_MAPPING_SIZE		0x01000
 33#define AMD_PMC_BASE_ADDR_OFFSET	0x10000
 34#define AMD_PMC_BASE_ADDR_LO		0x13B102E8
 35#define AMD_PMC_BASE_ADDR_HI		0x13B102EC
 36#define AMD_PMC_BASE_ADDR_LO_MASK	GENMASK(15, 0)
 37#define AMD_PMC_BASE_ADDR_HI_MASK	GENMASK(31, 20)
 38
 39/* SMU Response Codes */
 40#define AMD_PMC_RESULT_OK                    0x01
 41#define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
 42#define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
 43#define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
 44#define AMD_PMC_RESULT_FAILED                0xFF
 45
 46/* FCH SSC Registers */
 47#define FCH_S0I3_ENTRY_TIME_L_OFFSET	0x30
 48#define FCH_S0I3_ENTRY_TIME_H_OFFSET	0x34
 49#define FCH_S0I3_EXIT_TIME_L_OFFSET	0x38
 50#define FCH_S0I3_EXIT_TIME_H_OFFSET	0x3C
 51#define FCH_SSC_MAPPING_SIZE		0x800
 52#define FCH_BASE_PHY_ADDR_LOW		0xFED81100
 53#define FCH_BASE_PHY_ADDR_HIGH		0x00000000
 54
 55/* SMU Message Definations */
 56#define SMU_MSG_GETSMUVERSION		0x02
 57#define SMU_MSG_LOG_GETDRAM_ADDR_HI	0x04
 58#define SMU_MSG_LOG_GETDRAM_ADDR_LO	0x05
 59#define SMU_MSG_LOG_START		0x06
 60#define SMU_MSG_LOG_RESET		0x07
 61#define SMU_MSG_LOG_DUMP_DATA		0x08
 62#define SMU_MSG_GET_SUP_CONSTRAINTS	0x09
 63
 64#define PMC_MSG_DELAY_MIN_US		50
 65#define RESPONSE_REGISTER_LOOP_MAX	20000
 66
 67#define DELAY_MIN_US		2000
 68#define DELAY_MAX_US		3000
 69
 70enum s2d_msg_port {
 71	MSG_PORT_PMC,
 72	MSG_PORT_S2D,
 73};
 74
 75struct amd_mp2_dev {
 76	void __iomem *mmio;
 77	void __iomem *vslbase;
 78	void *stbdata;
 79	void *devres_gid;
 80	struct pci_dev *pdev;
 81	dma_addr_t dma_addr;
 82	int stb_len;
 83	bool is_stb_data;
 84};
 85
 86struct stb_arg {
 87	u32 s2d_msg_id;
 88	u32 msg;
 89	u32 arg;
 90	u32 resp;
 91};
 92
 93struct amd_pmc_dev {
 94	void __iomem *regbase;
 95	void __iomem *smu_virt_addr;
 96	void __iomem *stb_virt_addr;
 97	void __iomem *fch_virt_addr;
 98	u32 base_addr;
 99	u32 cpu_id;
100	u32 dram_size;
101	u32 active_ips;
102	const struct amd_pmc_bit_map *ips_ptr;
103	u32 num_ips;
104	u32 smu_msg;
105/* SMU version information */
106	u8 smu_program;
107	u8 major;
108	u8 minor;
109	u8 rev;
110	u8 msg_port;
111	struct device *dev;
112	struct pci_dev *rdev;
113	struct mutex lock; /* generic mutex lock */
114	struct dentry *dbgfs_dir;
115	struct quirk_entry *quirks;
116	bool disable_8042_wakeup;
117	struct amd_mp2_dev *mp2;
118	struct stb_arg stb_arg;
119};
120
121struct amd_pmc_bit_map {
122	const char *name;
123	u32 bit_mask;
124};
125
126struct smu_metrics {
127	u32 table_version;
128	u32 hint_count;
129	u32 s0i3_last_entry_status;
130	u32 timein_s0i2;
131	u64 timeentering_s0i3_lastcapture;
132	u64 timeentering_s0i3_totaltime;
133	u64 timeto_resume_to_os_lastcapture;
134	u64 timeto_resume_to_os_totaltime;
135	u64 timein_s0i3_lastcapture;
136	u64 timein_s0i3_totaltime;
137	u64 timein_swdrips_lastcapture;
138	u64 timein_swdrips_totaltime;
139	u64 timecondition_notmet_lastcapture[32];
140	u64 timecondition_notmet_totaltime[32];
141} __packed;
142
143enum amd_pmc_def {
144	MSG_TEST = 0x01,
145	MSG_OS_HINT_PCO,
146	MSG_OS_HINT_RN,
147};
148
149void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);
150void amd_pmc_quirks_init(struct amd_pmc_dev *dev);
151void amd_mp2_stb_init(struct amd_pmc_dev *dev);
152void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
153
154/* List of supported CPU ids */
155#define AMD_CPU_ID_RV			0x15D0
156#define AMD_CPU_ID_RN			0x1630
157#define AMD_CPU_ID_PCO			AMD_CPU_ID_RV
158#define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
159#define AMD_CPU_ID_VG			0x1645
160#define AMD_CPU_ID_YC			0x14B5
161#define AMD_CPU_ID_CB			0x14D8
162#define AMD_CPU_ID_PS			0x14E8
163#define AMD_CPU_ID_SP			0x14A4
164#define AMD_CPU_ID_SHP			0x153A
165#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
166#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
167#define PCI_DEVICE_ID_AMD_MP2_STB	0x172c
168
169int amd_stb_s2d_init(struct amd_pmc_dev *dev);
170int amd_stb_read(struct amd_pmc_dev *dev, u32 *buf);
171int amd_stb_write(struct amd_pmc_dev *dev, u32 data);
172int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
173
174#endif /* PMC_H */