pmc.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * AMD SoC Power Management Controller Driver
  4 *
  5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
  6 * All Rights Reserved.
  7 *
  8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
  9 */
 10
 11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 12
 13#include <linux/acpi.h>
 14#include <linux/array_size.h>
 15#include <linux/bitfield.h>
 16#include <linux/bits.h>
 17#include <linux/debugfs.h>
 18#include <linux/delay.h>
 19#include <linux/io.h>
 20#include <linux/iopoll.h>
 21#include <linux/limits.h>
 22#include <linux/module.h>
 23#include <linux/pci.h>
 24#include <linux/platform_device.h>
 25#include <linux/rtc.h>
 26#include <linux/serio.h>
 27#include <linux/suspend.h>
 28#include <linux/seq_file.h>
 29#include <linux/uaccess.h>
 30
 31#include <asm/amd/node.h>
 32
 33#include "pmc.h"
 34
 35static const struct amd_pmc_bit_map soc15_ip_blk_v2[] = {
 36	{"DISPLAY",     BIT(0)},
 37	{"CPU",         BIT(1)},
 38	{"GFX",         BIT(2)},
 39	{"VDD",         BIT(3)},
 40	{"VDD_CCX",     BIT(4)},
 41	{"ACP",         BIT(5)},
 42	{"VCN_0",       BIT(6)},
 43	{"VCN_1",       BIT(7)},
 44	{"ISP",         BIT(8)},
 45	{"NBIO",        BIT(9)},
 46	{"DF",          BIT(10)},
 47	{"USB3_0",      BIT(11)},
 48	{"USB3_1",      BIT(12)},
 49	{"LAPIC",       BIT(13)},
 50	{"USB3_2",      BIT(14)},
 51	{"USB4_RT0",	BIT(15)},
 52	{"USB4_RT1",	BIT(16)},
 53	{"USB4_0",      BIT(17)},
 54	{"USB4_1",      BIT(18)},
 55	{"MPM",         BIT(19)},
 56	{"JPEG_0",      BIT(20)},
 57	{"JPEG_1",      BIT(21)},
 58	{"IPU",         BIT(22)},
 59	{"UMSCH",       BIT(23)},
 60	{"VPE",         BIT(24)},
 61};
 62
 63static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 64	{"DISPLAY",	BIT(0)},
 65	{"CPU",		BIT(1)},
 66	{"GFX",		BIT(2)},
 67	{"VDD",		BIT(3)},
 68	{"ACP",		BIT(4)},
 69	{"VCN",		BIT(5)},
 70	{"ISP",		BIT(6)},
 71	{"NBIO",	BIT(7)},
 72	{"DF",		BIT(8)},
 73	{"USB3_0",	BIT(9)},
 74	{"USB3_1",	BIT(10)},
 75	{"LAPIC",	BIT(11)},
 76	{"USB3_2",	BIT(12)},
 77	{"USB3_3",	BIT(13)},
 78	{"USB3_4",	BIT(14)},
 79	{"USB4_0",	BIT(15)},
 80	{"USB4_1",	BIT(16)},
 81	{"MPM",		BIT(17)},
 82	{"JPEG",	BIT(18)},
 83	{"IPU",		BIT(19)},
 84	{"UMSCH",	BIT(20)},
 85	{"VPE",		BIT(21)},
 86};
 87
 88static bool disable_workarounds;
 89module_param(disable_workarounds, bool, 0644);
 90MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
 91
 92static struct amd_pmc_dev pmc;
 93
 94static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 95{
 96	return ioread32(dev->regbase + reg_offset);
 97}
 98
 99static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
100{
101	iowrite32(val, dev->regbase + reg_offset);
102}
103
104static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
105{
106	switch (dev->cpu_id) {
107	case AMD_CPU_ID_PCO:
108	case AMD_CPU_ID_RN:
109	case AMD_CPU_ID_VG:
110	case AMD_CPU_ID_YC:
111	case AMD_CPU_ID_CB:
112		dev->num_ips = 12;
113		dev->ips_ptr = soc15_ip_blk;
114		dev->smu_msg = 0x538;
115		break;
116	case AMD_CPU_ID_PS:
117		dev->num_ips = 21;
118		dev->ips_ptr = soc15_ip_blk;
119		dev->smu_msg = 0x538;
120		break;
121	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
122	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
123		if (boot_cpu_data.x86_model == 0x70) {
124			dev->num_ips = ARRAY_SIZE(soc15_ip_blk_v2);
125			dev->ips_ptr = soc15_ip_blk_v2;
126		} else {
127			dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
128			dev->ips_ptr = soc15_ip_blk;
129		}
130		dev->smu_msg = 0x938;
131		break;
132	}
133}
134
135static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
136{
137	if (dev->cpu_id == AMD_CPU_ID_PCO) {
138		dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
139		return -EINVAL;
140	}
141
142	/* Get Active devices list from SMU */
143	if (!dev->active_ips)
144		amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, true);
145
146	/* Get dram address */
147	if (!dev->smu_virt_addr) {
148		u32 phys_addr_low, phys_addr_hi;
149		u64 smu_phys_addr;
150
151		amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, true);
152		amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, true);
153		smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
154
155		dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
156						  sizeof(struct smu_metrics));
157		if (!dev->smu_virt_addr)
158			return -ENOMEM;
159	}
160
161	memset_io(dev->smu_virt_addr, 0, sizeof(struct smu_metrics));
162
163	/* Start the logging */
164	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, false);
165	amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, false);
166
167	return 0;
168}
169
170static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
171{
172	int rc;
173
174	if (!pdev->smu_virt_addr) {
175		rc = amd_pmc_setup_smu_logging(pdev);
176		if (rc)
177			return rc;
178	}
179
180	if (pdev->cpu_id == AMD_CPU_ID_PCO)
181		return -ENODEV;
182	memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
183	return 0;
184}
185
186static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
187{
188	struct smu_metrics table;
189
190	if (get_metrics_table(pdev, &table))
191		return;
192
193	if (!table.s0i3_last_entry_status)
194		dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
195	pm_report_hw_sleep_time(table.s0i3_last_entry_status ?
196				table.timein_s0i3_lastcapture : 0);
197}
198
199static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
200{
201	int rc;
202	u32 val;
203
204	if (dev->cpu_id == AMD_CPU_ID_PCO)
205		return -ENODEV;
206
207	rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, true);
208	if (rc)
209		return rc;
210
211	dev->smu_program = (val >> 24) & GENMASK(7, 0);
212	dev->major = (val >> 16) & GENMASK(7, 0);
213	dev->minor = (val >> 8) & GENMASK(7, 0);
214	dev->rev = (val >> 0) & GENMASK(7, 0);
215
216	dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
217		dev->smu_program, dev->major, dev->minor, dev->rev);
218
219	return 0;
220}
221
222static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
223				   char *buf)
224{
225	struct amd_pmc_dev *dev = dev_get_drvdata(d);
226	int rc;
227
228	if (!dev->major) {
229		rc = amd_pmc_get_smu_version(dev);
230		if (rc)
231			return rc;
232	}
233	return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
234}
235
236static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
237				   char *buf)
238{
239	struct amd_pmc_dev *dev = dev_get_drvdata(d);
240	int rc;
241
242	if (!dev->major) {
243		rc = amd_pmc_get_smu_version(dev);
244		if (rc)
245			return rc;
246	}
247	return sysfs_emit(buf, "%u\n", dev->smu_program);
248}
249
250static DEVICE_ATTR_RO(smu_fw_version);
251static DEVICE_ATTR_RO(smu_program);
252
253static umode_t pmc_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
254{
255	struct device *dev = kobj_to_dev(kobj);
256	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
257
258	if (pdev->cpu_id == AMD_CPU_ID_PCO)
259		return 0;
260	return 0444;
261}
262
263static struct attribute *pmc_attrs[] = {
264	&dev_attr_smu_fw_version.attr,
265	&dev_attr_smu_program.attr,
266	NULL,
267};
268
269static struct attribute_group pmc_attr_group = {
270	.attrs = pmc_attrs,
271	.is_visible = pmc_attr_is_visible,
272};
273
274static const struct attribute_group *pmc_groups[] = {
275	&pmc_attr_group,
276	NULL,
277};
278
279static int smu_fw_info_show(struct seq_file *s, void *unused)
280{
281	struct amd_pmc_dev *dev = s->private;
282	struct smu_metrics table;
283	int idx;
284
285	if (get_metrics_table(dev, &table))
286		return -EINVAL;
287
288	seq_puts(s, "\n=== SMU Statistics ===\n");
289	seq_printf(s, "Table Version: %d\n", table.table_version);
290	seq_printf(s, "Hint Count: %d\n", table.hint_count);
291	seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
292		   "Unknown/Fail");
293	seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
294	seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
295	seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
296		   table.timeto_resume_to_os_lastcapture);
297
298	seq_puts(s, "\n=== Active time (in us) ===\n");
299	for (idx = 0 ; idx < dev->num_ips ; idx++) {
300		if (dev->ips_ptr[idx].bit_mask & dev->active_ips)
301			seq_printf(s, "%-8s : %lld\n", dev->ips_ptr[idx].name,
302				   table.timecondition_notmet_lastcapture[idx]);
303	}
304
305	return 0;
306}
307DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
308
309static int s0ix_stats_show(struct seq_file *s, void *unused)
310{
311	struct amd_pmc_dev *dev = s->private;
312	u64 entry_time, exit_time, residency;
313
314	/* Use FCH registers to get the S0ix stats */
315	if (!dev->fch_virt_addr) {
316		u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
317		u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
318		u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
319
320		dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
321		if (!dev->fch_virt_addr)
322			return -ENOMEM;
323	}
324
325	entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
326	entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
327
328	exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
329	exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
330
331	/* It's in 48MHz. We need to convert it */
332	residency = exit_time - entry_time;
333	do_div(residency, 48);
334
335	seq_puts(s, "=== S0ix statistics ===\n");
336	seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
337	seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
338	seq_printf(s, "Residency Time: %lld\n", residency);
339
340	return 0;
341}
342DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
343
344static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
345				 struct seq_file *s)
346{
347	u32 val;
348	int rc;
349
350	switch (pdev->cpu_id) {
351	case AMD_CPU_ID_CZN:
352		/* we haven't yet read SMU version */
353		if (!pdev->major) {
354			rc = amd_pmc_get_smu_version(pdev);
355			if (rc)
356				return rc;
357		}
358		if (pdev->major > 56 || (pdev->major >= 55 && pdev->minor >= 37))
359			val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
360		else
361			return -EINVAL;
362		break;
363	case AMD_CPU_ID_YC:
364	case AMD_CPU_ID_CB:
365	case AMD_CPU_ID_PS:
366		val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
367		break;
368	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
369	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
370		val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
371		break;
372	default:
373		return -EINVAL;
374	}
375
376	if (dev)
377		pm_pr_dbg("SMU idlemask s0i3: 0x%x\n", val);
378
379	if (s)
380		seq_printf(s, "SMU idlemask : 0x%x\n", val);
381
382	return 0;
383}
384
385static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
386{
387	return amd_pmc_idlemask_read(s->private, NULL, s);
388}
389DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
390
391static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
392{
393	debugfs_remove_recursive(dev->dbgfs_dir);
394}
395
396static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
397{
398	dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
399	debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
400			    &smu_fw_info_fops);
401	debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
402			    &s0ix_stats_fops);
403	debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
404			    &amd_pmc_idlemask_fops);
405}
406
407static char *amd_pmc_get_msg_port(struct amd_pmc_dev *dev)
408{
409	switch (dev->msg_port) {
410	case MSG_PORT_PMC:
411		return "PMC";
412	case MSG_PORT_S2D:
413		return "S2D";
414	default:
415		return "Invalid message port";
416	}
417}
418
419static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
420{
421	u32 value, message, argument, response;
422
423	if (dev->msg_port == MSG_PORT_S2D) {
424		message = dev->stb_arg.msg;
425		argument = dev->stb_arg.arg;
426		response = dev->stb_arg.resp;
427	} else {
428		message = dev->smu_msg;
429		argument = AMD_PMC_REGISTER_ARGUMENT;
430		response = AMD_PMC_REGISTER_RESPONSE;
431	}
432
433	value = amd_pmc_reg_read(dev, response);
434	dev_dbg(dev->dev, "AMD_%s_REGISTER_RESPONSE:%x\n", amd_pmc_get_msg_port(dev), value);
435
436	value = amd_pmc_reg_read(dev, argument);
437	dev_dbg(dev->dev, "AMD_%s_REGISTER_ARGUMENT:%x\n", amd_pmc_get_msg_port(dev), value);
438
439	value = amd_pmc_reg_read(dev, message);
440	dev_dbg(dev->dev, "AMD_%s_REGISTER_MESSAGE:%x\n", amd_pmc_get_msg_port(dev), value);
441}
442
443int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
444{
445	int rc;
446	u32 val, message, argument, response;
447
448	guard(mutex)(&dev->lock);
449
450	if (dev->msg_port == MSG_PORT_S2D) {
451		message = dev->stb_arg.msg;
452		argument = dev->stb_arg.arg;
453		response = dev->stb_arg.resp;
454	} else {
455		message = dev->smu_msg;
456		argument = AMD_PMC_REGISTER_ARGUMENT;
457		response = AMD_PMC_REGISTER_RESPONSE;
458	}
459
460	/* Wait until we get a valid response */
461	rc = readx_poll_timeout(ioread32, dev->regbase + response,
462				val, val != 0, PMC_MSG_DELAY_MIN_US,
463				PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
464	if (rc) {
465		dev_err(dev->dev, "failed to talk to SMU\n");
466		return rc;
467	}
468
469	/* Write zero to response register */
470	amd_pmc_reg_write(dev, response, 0);
471
472	/* Write argument into response register */
473	amd_pmc_reg_write(dev, argument, arg);
474
475	/* Write message ID to message ID register */
476	amd_pmc_reg_write(dev, message, msg);
477
478	/* Wait until we get a valid response */
479	rc = readx_poll_timeout(ioread32, dev->regbase + response,
480				val, val != 0, PMC_MSG_DELAY_MIN_US,
481				PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
482	if (rc) {
483		dev_err(dev->dev, "SMU response timed out\n");
484		return rc;
485	}
486
487	switch (val) {
488	case AMD_PMC_RESULT_OK:
489		if (ret) {
490			/* PMFW may take longer time to return back the data */
491			usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
492			*data = amd_pmc_reg_read(dev, argument);
493		}
494		break;
495	case AMD_PMC_RESULT_CMD_REJECT_BUSY:
496		dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
497		rc = -EBUSY;
498		break;
499	case AMD_PMC_RESULT_CMD_UNKNOWN:
500		dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
501		rc = -EINVAL;
502		break;
503	case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
504	case AMD_PMC_RESULT_FAILED:
505	default:
506		dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
507		rc = -EIO;
508		break;
509	}
510
511	amd_pmc_dump_registers(dev);
512	return rc;
513}
514
515static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
516{
517	switch (dev->cpu_id) {
518	case AMD_CPU_ID_PCO:
519		return MSG_OS_HINT_PCO;
520	case AMD_CPU_ID_RN:
521	case AMD_CPU_ID_VG:
522	case AMD_CPU_ID_YC:
523	case AMD_CPU_ID_CB:
524	case AMD_CPU_ID_PS:
525	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
526	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
527		return MSG_OS_HINT_RN;
528	}
529	return -EINVAL;
530}
531
532static int amd_pmc_wa_irq1(struct amd_pmc_dev *pdev)
533{
534	struct device *d;
535
536	d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
537	if (!d)
538		return 0;
539	if (device_may_wakeup(d)) {
540		dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
541		disable_irq_wake(1);
542		device_set_wakeup_enable(d, false);
543	}
544	put_device(d);
545
546	return 0;
547}
548
549static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
550{
551	struct rtc_device *rtc_device;
552	time64_t then, now, duration;
553	struct rtc_wkalrm alarm;
554	struct rtc_time tm;
555	int rc;
556
557	/* we haven't yet read SMU version */
558	if (!pdev->major) {
559		rc = amd_pmc_get_smu_version(pdev);
560		if (rc)
561			return rc;
562	}
563
564	if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
565		return 0;
566
567	rtc_device = rtc_class_open("rtc0");
568	if (!rtc_device)
569		return 0;
570	rc = rtc_read_alarm(rtc_device, &alarm);
571	if (rc)
572		return rc;
573	if (!alarm.enabled) {
574		dev_dbg(pdev->dev, "alarm not enabled\n");
575		return 0;
576	}
577	rc = rtc_read_time(rtc_device, &tm);
578	if (rc)
579		return rc;
580	then = rtc_tm_to_time64(&alarm.time);
581	now = rtc_tm_to_time64(&tm);
582	duration = then-now;
583
584	/* in the past */
585	if (then < now)
586		return 0;
587
588	/* will be stored in upper 16 bits of s0i3 hint argument,
589	 * so timer wakeup from s0i3 is limited to ~18 hours or less
590	 */
591	if (duration <= 4 || duration > U16_MAX)
592		return -EINVAL;
593
594	*arg |= (duration << 16);
595	rc = rtc_alarm_irq_enable(rtc_device, 0);
596	pm_pr_dbg("wakeup timer programmed for %lld seconds\n", duration);
597
598	return rc;
599}
600
601static void amd_pmc_s2idle_prepare(void)
602{
603	struct amd_pmc_dev *pdev = &pmc;
604	int rc;
605	u8 msg;
606	u32 arg = 1;
607
608	/* Reset and Start SMU logging - to monitor the s0i3 stats */
609	amd_pmc_setup_smu_logging(pdev);
610
611	/* Activate CZN specific platform bug workarounds */
612	if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
613		rc = amd_pmc_verify_czn_rtc(pdev, &arg);
614		if (rc) {
615			dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
616			return;
617		}
618	}
619
620	msg = amd_pmc_get_os_hint(pdev);
621	rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, false);
622	if (rc) {
623		dev_err(pdev->dev, "suspend failed: %d\n", rc);
624		return;
625	}
626
627	rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
628	if (rc)
629		dev_err(pdev->dev, "error writing to STB: %d\n", rc);
630}
631
632static void amd_pmc_s2idle_check(void)
633{
634	struct amd_pmc_dev *pdev = &pmc;
635	struct smu_metrics table;
636	int rc;
637
638	/* Avoid triggering OVP */
639	if (!get_metrics_table(pdev, &table) && table.s0i3_last_entry_status)
640		msleep(2500);
641
642	/* Dump the IdleMask before we add to the STB */
643	amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
644
645	rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_CHECK);
646	if (rc)
647		dev_err(pdev->dev, "error writing to STB: %d\n", rc);
648}
649
650static int amd_pmc_dump_data(struct amd_pmc_dev *pdev)
651{
652	if (pdev->cpu_id == AMD_CPU_ID_PCO)
653		return -ENODEV;
654
655	return amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, false);
656}
657
658static void amd_pmc_s2idle_restore(void)
659{
660	struct amd_pmc_dev *pdev = &pmc;
661	int rc;
662	u8 msg;
663
664	msg = amd_pmc_get_os_hint(pdev);
665	rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, false);
666	if (rc)
667		dev_err(pdev->dev, "resume failed: %d\n", rc);
668
669	/* Let SMU know that we are looking for stats */
670	amd_pmc_dump_data(pdev);
671
672	rc = amd_stb_write(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
673	if (rc)
674		dev_err(pdev->dev, "error writing to STB: %d\n", rc);
675
676	/* Notify on failed entry */
677	amd_pmc_validate_deepest(pdev);
678
679	amd_pmc_process_restore_quirks(pdev);
680}
681
682static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
683	.prepare = amd_pmc_s2idle_prepare,
684	.check = amd_pmc_s2idle_check,
685	.restore = amd_pmc_s2idle_restore,
686};
687
688static int amd_pmc_suspend_handler(struct device *dev)
689{
690	struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
691	int rc;
692
693	/*
694	 * Must be called only from the same set of dev_pm_ops handlers
695	 * as i8042_pm_suspend() is called: currently just from .suspend.
696	 */
697	if (pdev->disable_8042_wakeup && !disable_workarounds) {
698		rc = amd_pmc_wa_irq1(pdev);
699		if (rc) {
700			dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
701			return rc;
702		}
703	}
704
705	return 0;
706}
707
708static const struct dev_pm_ops amd_pmc_pm = {
709	.suspend = amd_pmc_suspend_handler,
710};
711
712static const struct pci_device_id pmc_pci_ids[] = {
713	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
714	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
715	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
716	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
717	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
718	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
719	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
720	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) },
721	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SHP) },
722	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
723	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
724	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
725	{ }
726};
727
728static int amd_pmc_probe(struct platform_device *pdev)
729{
730	struct amd_pmc_dev *dev = &pmc;
731	struct pci_dev *rdev;
732	u32 base_addr_lo, base_addr_hi;
733	u64 base_addr;
734	int err;
735	u32 val;
736
737	dev->dev = &pdev->dev;
738	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
739	if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
740		err = -ENODEV;
741		goto err_pci_dev_put;
742	}
743
744	dev->cpu_id = rdev->device;
745	if (dev->cpu_id == AMD_CPU_ID_SP || dev->cpu_id == AMD_CPU_ID_SHP) {
746		dev_warn_once(dev->dev, "S0i3 is not supported on this hardware\n");
747		err = -ENODEV;
748		goto err_pci_dev_put;
749	}
750
751	dev->rdev = rdev;
752	err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
753	if (err) {
754		dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_LO);
755		err = pcibios_err_to_errno(err);
756		goto err_pci_dev_put;
757	}
758
759	base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
760	err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
761	if (err) {
762		dev_err(dev->dev, "error reading 0x%x\n", AMD_PMC_BASE_ADDR_HI);
763		err = pcibios_err_to_errno(err);
764		goto err_pci_dev_put;
765	}
766
767	base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
768	base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
769
770	dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
771				    AMD_PMC_MAPPING_SIZE);
772	if (!dev->regbase) {
773		err = -ENOMEM;
774		goto err_pci_dev_put;
775	}
776
777	err = devm_mutex_init(dev->dev, &dev->lock);
778	if (err)
779		goto err_pci_dev_put;
780
781	/* Get num of IP blocks within the SoC */
782	amd_pmc_get_ip_info(dev);
783
784	platform_set_drvdata(pdev, dev);
785	if (IS_ENABLED(CONFIG_SUSPEND)) {
786		err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
787		if (err)
788			dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
789		if (!disable_workarounds)
790			amd_pmc_quirks_init(dev);
791	}
792
793	amd_pmc_dbgfs_register(dev);
794	err = amd_stb_s2d_init(dev);
795	if (err)
796		goto err_pci_dev_put;
797
798	if (IS_ENABLED(CONFIG_AMD_MP2_STB))
799		amd_mp2_stb_init(dev);
800	pm_report_max_hw_sleep(U64_MAX);
801	return 0;
802
803err_pci_dev_put:
804	pci_dev_put(rdev);
805	return err;
806}
807
808static void amd_pmc_remove(struct platform_device *pdev)
809{
810	struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
811
812	if (IS_ENABLED(CONFIG_SUSPEND))
813		acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
814	amd_pmc_dbgfs_unregister(dev);
815	pci_dev_put(dev->rdev);
816	if (IS_ENABLED(CONFIG_AMD_MP2_STB))
817		amd_mp2_stb_deinit(dev);
818}
819
820static const struct acpi_device_id amd_pmc_acpi_ids[] = {
821	{"AMDI0005", 0},
822	{"AMDI0006", 0},
823	{"AMDI0007", 0},
824	{"AMDI0008", 0},
825	{"AMDI0009", 0},
826	{"AMDI000A", 0},
827	{"AMDI000B", 0},
828	{"AMD0004", 0},
829	{"AMD0005", 0},
830	{ }
831};
832MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
833
834static struct platform_driver amd_pmc_driver = {
835	.driver = {
836		.name = "amd_pmc",
837		.acpi_match_table = amd_pmc_acpi_ids,
838		.dev_groups = pmc_groups,
839		.pm = pm_sleep_ptr(&amd_pmc_pm),
840	},
841	.probe = amd_pmc_probe,
842	.remove = amd_pmc_remove,
843};
844module_platform_driver(amd_pmc_driver);
845
846MODULE_LICENSE("GPL v2");
847MODULE_DESCRIPTION("AMD PMC Driver");