pinctrl-tegra.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Driver for the NVIDIA Tegra pinmux
  4 *
  5 * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
  6 */
  7
  8#ifndef __PINMUX_TEGRA_H__
  9#define __PINMUX_TEGRA_H__
 10
 11struct tegra_pingroup_config {
 12	bool is_sfsel;
 13};
 14
 15struct tegra_pmx {
 16	struct device *dev;
 17	struct pinctrl_dev *pctl;
 18
 19	const struct tegra_pinctrl_soc_data *soc;
 20	struct tegra_function *functions;
 21	const char **group_pins;
 22
 23	struct pinctrl_gpio_range gpio_range;
 24	struct pinctrl_desc desc;
 25	int nbanks;
 26	void __iomem **regs;
 27	u32 *backup_regs;
 28	/* Array of size soc->ngroups */
 29	struct tegra_pingroup_config *pingroup_configs;
 30};
 31
 32enum tegra_pinconf_param {
 33	/* argument: tegra_pinconf_pull */
 34	TEGRA_PINCONF_PARAM_PULL,
 35	/* argument: tegra_pinconf_tristate */
 36	TEGRA_PINCONF_PARAM_TRISTATE,
 37	/* argument: Boolean */
 38	TEGRA_PINCONF_PARAM_ENABLE_INPUT,
 39	/* argument: Boolean */
 40	TEGRA_PINCONF_PARAM_OPEN_DRAIN,
 41	/* argument: Boolean */
 42	TEGRA_PINCONF_PARAM_LOCK,
 43	/* argument: Boolean */
 44	TEGRA_PINCONF_PARAM_IORESET,
 45	/* argument: Boolean */
 46	TEGRA_PINCONF_PARAM_RCV_SEL,
 47	/* argument: Boolean */
 48	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
 49	/* argument: Boolean */
 50	TEGRA_PINCONF_PARAM_SCHMITT,
 51	/* argument: Boolean */
 52	TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
 53	/* argument: Integer, range is HW-dependant */
 54	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
 55	/* argument: Integer, range is HW-dependant */
 56	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
 57	/* argument: Integer, range is HW-dependant */
 58	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
 59	/* argument: Integer, range is HW-dependant */
 60	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
 61	/* argument: Integer, range is HW-dependant */
 62	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
 63	/* argument: Boolean */
 64	TEGRA_PINCONF_PARAM_GPIO_MODE,
 65};
 66
 67enum tegra_pinconf_pull {
 68	TEGRA_PINCONFIG_PULL_NONE,
 69	TEGRA_PINCONFIG_PULL_DOWN,
 70	TEGRA_PINCONFIG_PULL_UP,
 71};
 72
 73enum tegra_pinconf_tristate {
 74	TEGRA_PINCONFIG_DRIVEN,
 75	TEGRA_PINCONFIG_TRISTATE,
 76};
 77
 78#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
 79#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
 80#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
 81
 82/**
 83 * struct tegra_function - Tegra pinctrl mux function
 84 * @name: The name of the function, exported to pinctrl core.
 85 * @groups: An array of pin groups that may select this function.
 86 * @ngroups: The number of entries in @groups.
 87 */
 88struct tegra_function {
 89	const char *name;
 90	const char **groups;
 91	unsigned ngroups;
 92};
 93
 94/**
 95 * struct tegra_pingroup - Tegra pin group
 96 * @name		The name of the pin group.
 97 * @pins		An array of pin IDs included in this pin group.
 98 * @npins		The number of entries in @pins.
 99 * @funcs		The mux functions which can be muxed onto this group.
100 * @mux_reg:		Mux register offset.
101 *			This register contains the mux, einput, odrain, lock,
102 *			ioreset, rcv_sel parameters.
103 * @mux_bank:		Mux register bank.
104 * @mux_bit:		Mux register bit.
105 * @pupd_reg:		Pull-up/down register offset.
106 * @pupd_bank:		Pull-up/down register bank.
107 * @pupd_bit:		Pull-up/down register bit.
108 * @tri_reg:		Tri-state register offset.
109 * @tri_bank:		Tri-state register bank.
110 * @tri_bit:		Tri-state register bit.
111 * @einput_bit:		Enable-input register bit.
112 * @odrain_bit:		Open-drain register bit.
113 * @lock_bit:		Lock register bit.
114 * @ioreset_bit:	IO reset register bit.
115 * @rcv_sel_bit:	Receiver select bit.
116 * @drv_reg:		Drive fields register offset.
117 *			This register contains hsm, schmitt, lpmd, drvdn,
118 *			drvup, slwr, slwf, and drvtype parameters.
119 * @drv_bank:		Drive fields register bank.
120 * @hsm_bit:		High Speed Mode register bit.
121 * @sfsel_bit:		GPIO/SFIO selection register bit.
122 * @schmitt_bit:	Schmitt register bit.
123 * @lpmd_bit:		Low Power Mode register bit.
124 * @drvdn_bit:		Drive Down register bit.
125 * @drvdn_width:	Drive Down field width.
126 * @drvup_bit:		Drive Up register bit.
127 * @drvup_width:	Drive Up field width.
128 * @slwr_bit:		Slew Rising register bit.
129 * @slwr_width:		Slew Rising field width.
130 * @slwf_bit:		Slew Falling register bit.
131 * @slwf_width:		Slew Falling field width.
132 * @lpdr_bit:		Base driver enabling bit.
133 * @drvtype_bit:	Drive type register bit.
134 * @parked_bitmask:	Parked register mask. 0 if unsupported.
135 *
136 * -1 in a *_reg field means that feature is unsupported for this group.
137 * *_bank and *_reg values are irrelevant when *_reg is -1.
138 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
139 *
140 * A representation of a group of pins (possibly just one pin) in the Tegra
141 * pin controller. Each group allows some parameter or parameters to be
142 * configured. The most common is mux function selection. Many others exist
143 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
144 * certain groups may only support configuring certain parameters, hence
145 * each parameter is optional.
146 */
147struct tegra_pingroup {
148	const char *name;
149	const unsigned *pins;
150	u8 npins;
151	u8 funcs[4];
152	s32 mux_reg;
153	s32 pupd_reg;
154	s32 tri_reg;
155	s32 drv_reg;
156	u32 mux_bank:2;
157	u32 pupd_bank:2;
158	u32 tri_bank:2;
159	u32 drv_bank:2;
160	s32 mux_bit:6;
161	s32 pupd_bit:6;
162	s32 tri_bit:6;
163	s32 einput_bit:6;
164	s32 odrain_bit:6;
165	s32 lock_bit:6;
166	s32 ioreset_bit:6;
167	s32 rcv_sel_bit:6;
168	s32 hsm_bit:6;
169	s32 sfsel_bit:6;
170	s32 schmitt_bit:6;
171	s32 lpmd_bit:6;
172	s32 drvdn_bit:6;
173	s32 drvup_bit:6;
174	s32 slwr_bit:6;
175	s32 slwf_bit:6;
176	s32 lpdr_bit:6;
177	s32 drvtype_bit:6;
178	s32 drvdn_width:6;
179	s32 drvup_width:6;
180	s32 slwr_width:6;
181	s32 slwf_width:6;
182	u32 parked_bitmask;
183};
184
185/**
186 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
187 * @ngpios:		The number of GPIO pins the pin controller HW affects.
188 * @gpio_compatible:	Device-tree GPIO compatible string.
189 * @pins:		An array describing all pins the pin controller affects.
190 *			All pins which are also GPIOs must be listed first within the
191 *			array, and be numbered identically to the GPIO controller's
192 *			numbering.
193 * @npins:		The number of entries in @pins.
194 * @functions:		An array describing all mux functions the SoC supports.
195 * @nfunctions:		The number of entries in @functions.
196 * @groups:		An array describing all pin groups the pin SoC supports.
197 * @ngroups:		The number of entries in @groups.
198 * @hsm_in_mux:		High-speed mode field. Only applicable to devices with one pin per group.
199 * @schmitt_in_mux:	Schmitt trigger field. Only applicable to devices with one pin per group.
200 * @drvtype_in_mux:	Drivetype field. Only applicable to devices with one pin per group.
201 * @sfsel_in_mux:	Special function selection field.
202 *			Only applicable to devices with one pin per group.
203 */
204struct tegra_pinctrl_soc_data {
205	unsigned ngpios;
206	const char *gpio_compatible;
207	const struct pinctrl_pin_desc *pins;
208	unsigned npins;
209	const char * const *functions;
210	unsigned nfunctions;
211	const struct tegra_pingroup *groups;
212	unsigned ngroups;
213	bool hsm_in_mux;
214	bool schmitt_in_mux;
215	bool drvtype_in_mux;
216	bool sfsel_in_mux;
217};
218
219extern const struct dev_pm_ops tegra_pinctrl_pm;
220
221int tegra_pinctrl_probe(struct platform_device *pdev,
222			const struct tegra_pinctrl_soc_data *soc_data);
223#endif