pinctrl-tegra-xusb.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
  4 */
  5
  6#include <linux/delay.h>
  7#include <linux/io.h>
  8#include <linux/module.h>
  9#include <linux/of.h>
 10#include <linux/phy/phy.h>
 11#include <linux/platform_device.h>
 12#include <linux/reset.h>
 13#include <linux/seq_file.h>
 14#include <linux/slab.h>
 15
 16#include <linux/pinctrl/pinconf.h>
 17#include <linux/pinctrl/pinctrl.h>
 18#include <linux/pinctrl/pinmux.h>
 19
 20#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 21
 22#include "../core.h"
 23#include "../pinctrl-utils.h"
 24
 25#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
 26#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
 27#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
 28#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
 29
 30#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
 31#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
 32#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
 33#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
 34
 35#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
 36#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
 37#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
 38#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
 39
 40#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
 41#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
 42#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
 43#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
 44#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
 45#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
 46
 47#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
 48#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
 49#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
 50
 51struct tegra_xusb_padctl_function {
 52	const char *name;
 53	const char * const *groups;
 54	unsigned int num_groups;
 55};
 56
 57struct tegra_xusb_padctl_soc {
 58	const struct pinctrl_pin_desc *pins;
 59	unsigned int num_pins;
 60
 61	const struct tegra_xusb_padctl_function *functions;
 62	unsigned int num_functions;
 63
 64	const struct tegra_xusb_padctl_lane *lanes;
 65	unsigned int num_lanes;
 66};
 67
 68struct tegra_xusb_padctl_lane {
 69	const char *name;
 70
 71	unsigned int offset;
 72	unsigned int shift;
 73	unsigned int mask;
 74	unsigned int iddq;
 75
 76	const unsigned int *funcs;
 77	unsigned int num_funcs;
 78};
 79
 80struct tegra_xusb_padctl {
 81	struct device *dev;
 82	void __iomem *regs;
 83	struct mutex lock;
 84	struct reset_control *rst;
 85
 86	const struct tegra_xusb_padctl_soc *soc;
 87	struct pinctrl_dev *pinctrl;
 88	struct pinctrl_desc desc;
 89
 90	struct phy_provider *provider;
 91	struct phy *phys[2];
 92
 93	unsigned int enable;
 94};
 95
 96static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
 97				 unsigned long offset)
 98{
 99	writel(value, padctl->regs + offset);
100}
101
102static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
103			       unsigned long offset)
104{
105	return readl(padctl->regs + offset);
106}
107
108static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
109{
110	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
111
112	return padctl->soc->num_pins;
113}
114
115static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
116						    unsigned int group)
117{
118	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
119
120	return padctl->soc->pins[group].name;
121}
122
123static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
124					    unsigned group,
125					    const unsigned **pins,
126					    unsigned *num_pins)
127{
128	/*
129	 * For the tegra-xusb pad controller groups are synonymous
130	 * with lanes/pins and there is always one lane/pin per group.
131	 */
132	*pins = &pinctrl->desc->pins[group].number;
133	*num_pins = 1;
134
135	return 0;
136}
137
138enum tegra_xusb_padctl_param {
139	TEGRA_XUSB_PADCTL_IDDQ,
140};
141
142static const struct tegra_xusb_padctl_property {
143	const char *name;
144	enum tegra_xusb_padctl_param param;
145} properties[] = {
146	{ "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
147};
148
149#define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
150#define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
151#define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
152
153static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
154					   struct device_node *np,
155					   struct pinctrl_map **maps,
156					   unsigned int *reserved_maps,
157					   unsigned int *num_maps)
158{
159	unsigned int i, reserve = 0, num_configs = 0;
160	unsigned long config, *configs = NULL;
161	const char *function, *group;
162	struct property *prop;
163	int err = 0;
164	u32 value;
165
166	err = of_property_read_string(np, "nvidia,function", &function);
167	if (err < 0) {
168		if (err != -EINVAL)
169			return err;
170
171		function = NULL;
172	}
173
174	for (i = 0; i < ARRAY_SIZE(properties); i++) {
175		err = of_property_read_u32(np, properties[i].name, &value);
176		if (err < 0) {
177			if (err == -EINVAL)
178				continue;
179
180			goto out;
181		}
182
183		config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
184
185		err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
186					       &num_configs, config);
187		if (err < 0)
188			goto out;
189	}
190
191	if (function)
192		reserve++;
193
194	if (num_configs)
195		reserve++;
196
197	err = of_property_count_strings(np, "nvidia,lanes");
198	if (err < 0)
199		goto out;
200
201	reserve *= err;
202
203	err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
204					num_maps, reserve);
205	if (err < 0)
206		goto out;
207
208	of_property_for_each_string(np, "nvidia,lanes", prop, group) {
209		if (function) {
210			err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
211					reserved_maps, num_maps, group,
212					function);
213			if (err < 0)
214				goto out;
215		}
216
217		if (num_configs) {
218			err = pinctrl_utils_add_map_configs(padctl->pinctrl,
219					maps, reserved_maps, num_maps, group,
220					configs, num_configs,
221					PIN_MAP_TYPE_CONFIGS_GROUP);
222			if (err < 0)
223				goto out;
224		}
225	}
226
227	err = 0;
228
229out:
230	kfree(configs);
231	return err;
232}
233
234static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
235					    struct device_node *parent,
236					    struct pinctrl_map **maps,
237					    unsigned int *num_maps)
238{
239	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
240	unsigned int reserved_maps = 0;
241	int err;
242
243	*num_maps = 0;
244	*maps = NULL;
245
246	for_each_child_of_node_scoped(parent, np) {
247		err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
248						      &reserved_maps,
249						      num_maps);
250		if (err < 0)
251			return err;
252	}
253
254	return 0;
255}
256
257static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
258	.get_groups_count = tegra_xusb_padctl_get_groups_count,
259	.get_group_name = tegra_xusb_padctl_get_group_name,
260	.get_group_pins = tegra_xusb_padctl_get_group_pins,
261	.dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
262	.dt_free_map = pinctrl_utils_free_map,
263};
264
265static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
266{
267	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
268
269	return padctl->soc->num_functions;
270}
271
272static const char *
273tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
274				    unsigned int function)
275{
276	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
277
278	return padctl->soc->functions[function].name;
279}
280
281static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
282						 unsigned int function,
283						 const char * const **groups,
284						 unsigned * const num_groups)
285{
286	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
287
288	*num_groups = padctl->soc->functions[function].num_groups;
289	*groups = padctl->soc->functions[function].groups;
290
291	return 0;
292}
293
294static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
295					unsigned int function,
296					unsigned int group)
297{
298	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
299	const struct tegra_xusb_padctl_lane *lane;
300	unsigned int i;
301	u32 value;
302
303	lane = &padctl->soc->lanes[group];
304
305	for (i = 0; i < lane->num_funcs; i++)
306		if (lane->funcs[i] == function)
307			break;
308
309	if (i >= lane->num_funcs)
310		return -EINVAL;
311
312	value = padctl_readl(padctl, lane->offset);
313	value &= ~(lane->mask << lane->shift);
314	value |= i << lane->shift;
315	padctl_writel(padctl, value, lane->offset);
316
317	return 0;
318}
319
320static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
321	.get_functions_count = tegra_xusb_padctl_get_functions_count,
322	.get_function_name = tegra_xusb_padctl_get_function_name,
323	.get_function_groups = tegra_xusb_padctl_get_function_groups,
324	.set_mux = tegra_xusb_padctl_pinmux_set,
325};
326
327static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
328					       unsigned int group,
329					       unsigned long *config)
330{
331	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
332	const struct tegra_xusb_padctl_lane *lane;
333	enum tegra_xusb_padctl_param param;
334	u32 value;
335
336	param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
337	lane = &padctl->soc->lanes[group];
338
339	switch (param) {
340	case TEGRA_XUSB_PADCTL_IDDQ:
341		/* lanes with iddq == 0 don't support this parameter */
342		if (lane->iddq == 0)
343			return -EINVAL;
344
345		value = padctl_readl(padctl, lane->offset);
346
347		if (value & BIT(lane->iddq))
348			value = 0;
349		else
350			value = 1;
351
352		*config = TEGRA_XUSB_PADCTL_PACK(param, value);
353		break;
354
355	default:
356		dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
357			param);
358		return -ENOTSUPP;
359	}
360
361	return 0;
362}
363
364static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
365					       unsigned int group,
366					       unsigned long *configs,
367					       unsigned int num_configs)
368{
369	struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
370	const struct tegra_xusb_padctl_lane *lane;
371	enum tegra_xusb_padctl_param param;
372	unsigned long value;
373	unsigned int i;
374	u32 regval;
375
376	lane = &padctl->soc->lanes[group];
377
378	for (i = 0; i < num_configs; i++) {
379		param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
380		value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
381
382		switch (param) {
383		case TEGRA_XUSB_PADCTL_IDDQ:
384			/* lanes with iddq == 0 don't support this parameter */
385			if (lane->iddq == 0)
386				return -EINVAL;
387
388			regval = padctl_readl(padctl, lane->offset);
389
390			if (value)
391				regval &= ~BIT(lane->iddq);
392			else
393				regval |= BIT(lane->iddq);
394
395			padctl_writel(padctl, regval, lane->offset);
396			break;
397
398		default:
399			dev_err(padctl->dev,
400				"invalid configuration parameter: %04x\n",
401				param);
402			return -ENOTSUPP;
403		}
404	}
405
406	return 0;
407}
408
409#ifdef CONFIG_DEBUG_FS
410static const char *strip_prefix(const char *s)
411{
412	const char *comma = strchr(s, ',');
413	if (!comma)
414		return s;
415
416	return comma + 1;
417}
418
419static void
420tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
421					 struct seq_file *s,
422					 unsigned int group)
423{
424	unsigned int i;
425
426	for (i = 0; i < ARRAY_SIZE(properties); i++) {
427		unsigned long config, value;
428		int err;
429
430		config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
431
432		err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
433							  &config);
434		if (err < 0)
435			continue;
436
437		value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
438
439		seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
440			   value);
441	}
442}
443
444static void
445tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
446					  struct seq_file *s,
447					  unsigned long config)
448{
449	enum tegra_xusb_padctl_param param;
450	const char *name = "unknown";
451	unsigned long value;
452	unsigned int i;
453
454	param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
455	value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
456
457	for (i = 0; i < ARRAY_SIZE(properties); i++) {
458		if (properties[i].param == param) {
459			name = properties[i].name;
460			break;
461		}
462	}
463
464	seq_printf(s, "%s=%lu", strip_prefix(name), value);
465}
466#endif
467
468static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
469	.pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
470	.pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
471#ifdef CONFIG_DEBUG_FS
472	.pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
473	.pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
474#endif
475};
476
477static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
478{
479	u32 value;
480
481	mutex_lock(&padctl->lock);
482
483	if (padctl->enable++ > 0)
484		goto out;
485
486	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
487	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
488	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
489
490	usleep_range(100, 200);
491
492	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
493	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
494	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
495
496	usleep_range(100, 200);
497
498	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
499	value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
500	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
501
502out:
503	mutex_unlock(&padctl->lock);
504	return 0;
505}
506
507static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
508{
509	u32 value;
510
511	mutex_lock(&padctl->lock);
512
513	if (WARN_ON(padctl->enable == 0))
514		goto out;
515
516	if (--padctl->enable > 0)
517		goto out;
518
519	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
520	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
521	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
522
523	usleep_range(100, 200);
524
525	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
526	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
527	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
528
529	usleep_range(100, 200);
530
531	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
532	value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
533	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
534
535out:
536	mutex_unlock(&padctl->lock);
537	return 0;
538}
539
540static int tegra_xusb_phy_init(struct phy *phy)
541{
542	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
543
544	return tegra_xusb_padctl_enable(padctl);
545}
546
547static int tegra_xusb_phy_exit(struct phy *phy)
548{
549	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
550
551	return tegra_xusb_padctl_disable(padctl);
552}
553
554static int pcie_phy_power_on(struct phy *phy)
555{
556	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
557	unsigned long timeout;
558	int err = -ETIMEDOUT;
559	u32 value;
560
561	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
562	value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
563	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
564
565	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
566	value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
567		 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
568		 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
569	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
570
571	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
572	value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
573	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
574
575	timeout = jiffies + msecs_to_jiffies(50);
576
577	while (time_before(jiffies, timeout)) {
578		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
579		if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
580			err = 0;
581			break;
582		}
583
584		usleep_range(100, 200);
585	}
586
587	return err;
588}
589
590static int pcie_phy_power_off(struct phy *phy)
591{
592	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
593	u32 value;
594
595	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
596	value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
597	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
598
599	return 0;
600}
601
602static const struct phy_ops pcie_phy_ops = {
603	.init = tegra_xusb_phy_init,
604	.exit = tegra_xusb_phy_exit,
605	.power_on = pcie_phy_power_on,
606	.power_off = pcie_phy_power_off,
607	.owner = THIS_MODULE,
608};
609
610static int sata_phy_power_on(struct phy *phy)
611{
612	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
613	unsigned long timeout;
614	int err = -ETIMEDOUT;
615	u32 value;
616
617	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
618	value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
619	value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
620	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
621
622	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
623	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
624	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
625	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
626
627	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
628	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
629	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
630
631	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
632	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
633	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
634
635	timeout = jiffies + msecs_to_jiffies(50);
636
637	while (time_before(jiffies, timeout)) {
638		value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
639		if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
640			err = 0;
641			break;
642		}
643
644		usleep_range(100, 200);
645	}
646
647	return err;
648}
649
650static int sata_phy_power_off(struct phy *phy)
651{
652	struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
653	u32 value;
654
655	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
656	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
657	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
658
659	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
660	value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
661	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
662
663	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
664	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
665	value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
666	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
667
668	value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
669	value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
670	value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
671	padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
672
673	return 0;
674}
675
676static const struct phy_ops sata_phy_ops = {
677	.init = tegra_xusb_phy_init,
678	.exit = tegra_xusb_phy_exit,
679	.power_on = sata_phy_power_on,
680	.power_off = sata_phy_power_off,
681	.owner = THIS_MODULE,
682};
683
684static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
685					   const struct of_phandle_args *args)
686{
687	struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
688	unsigned int index = args->args[0];
689
690	if (args->args_count <= 0)
691		return ERR_PTR(-EINVAL);
692
693	if (index >= ARRAY_SIZE(padctl->phys))
694		return ERR_PTR(-EINVAL);
695
696	return padctl->phys[index];
697}
698
699#define PIN_OTG_0   0
700#define PIN_OTG_1   1
701#define PIN_OTG_2   2
702#define PIN_ULPI_0  3
703#define PIN_HSIC_0  4
704#define PIN_HSIC_1  5
705#define PIN_PCIE_0  6
706#define PIN_PCIE_1  7
707#define PIN_PCIE_2  8
708#define PIN_PCIE_3  9
709#define PIN_PCIE_4 10
710#define PIN_SATA_0 11
711
712static const struct pinctrl_pin_desc tegra124_pins[] = {
713	PINCTRL_PIN(PIN_OTG_0,  "otg-0"),
714	PINCTRL_PIN(PIN_OTG_1,  "otg-1"),
715	PINCTRL_PIN(PIN_OTG_2,  "otg-2"),
716	PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
717	PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
718	PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
719	PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
720	PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
721	PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
722	PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
723	PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
724	PINCTRL_PIN(PIN_SATA_0, "sata-0"),
725};
726
727static const char * const tegra124_snps_groups[] = {
728	"otg-0",
729	"otg-1",
730	"otg-2",
731	"ulpi-0",
732	"hsic-0",
733	"hsic-1",
734};
735
736static const char * const tegra124_xusb_groups[] = {
737	"otg-0",
738	"otg-1",
739	"otg-2",
740	"ulpi-0",
741	"hsic-0",
742	"hsic-1",
743};
744
745static const char * const tegra124_uart_groups[] = {
746	"otg-0",
747	"otg-1",
748	"otg-2",
749};
750
751static const char * const tegra124_pcie_groups[] = {
752	"pcie-0",
753	"pcie-1",
754	"pcie-2",
755	"pcie-3",
756	"pcie-4",
757};
758
759static const char * const tegra124_usb3_groups[] = {
760	"pcie-0",
761	"pcie-1",
762	"sata-0",
763};
764
765static const char * const tegra124_sata_groups[] = {
766	"sata-0",
767};
768
769static const char * const tegra124_rsvd_groups[] = {
770	"otg-0",
771	"otg-1",
772	"otg-2",
773	"pcie-0",
774	"pcie-1",
775	"pcie-2",
776	"pcie-3",
777	"pcie-4",
778	"sata-0",
779};
780
781#define TEGRA124_FUNCTION(_name)					\
782	{								\
783		.name = #_name,						\
784		.num_groups = ARRAY_SIZE(tegra124_##_name##_groups),	\
785		.groups = tegra124_##_name##_groups,			\
786	}
787
788static struct tegra_xusb_padctl_function tegra124_functions[] = {
789	TEGRA124_FUNCTION(snps),
790	TEGRA124_FUNCTION(xusb),
791	TEGRA124_FUNCTION(uart),
792	TEGRA124_FUNCTION(pcie),
793	TEGRA124_FUNCTION(usb3),
794	TEGRA124_FUNCTION(sata),
795	TEGRA124_FUNCTION(rsvd),
796};
797
798enum tegra124_function {
799	TEGRA124_FUNC_SNPS,
800	TEGRA124_FUNC_XUSB,
801	TEGRA124_FUNC_UART,
802	TEGRA124_FUNC_PCIE,
803	TEGRA124_FUNC_USB3,
804	TEGRA124_FUNC_SATA,
805	TEGRA124_FUNC_RSVD,
806};
807
808static const unsigned int tegra124_otg_functions[] = {
809	TEGRA124_FUNC_SNPS,
810	TEGRA124_FUNC_XUSB,
811	TEGRA124_FUNC_UART,
812	TEGRA124_FUNC_RSVD,
813};
814
815static const unsigned int tegra124_usb_functions[] = {
816	TEGRA124_FUNC_SNPS,
817	TEGRA124_FUNC_XUSB,
818};
819
820static const unsigned int tegra124_pci_functions[] = {
821	TEGRA124_FUNC_PCIE,
822	TEGRA124_FUNC_USB3,
823	TEGRA124_FUNC_SATA,
824	TEGRA124_FUNC_RSVD,
825};
826
827#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs)	\
828	{								\
829		.name = _name,						\
830		.offset = _offset,					\
831		.shift = _shift,					\
832		.mask = _mask,						\
833		.iddq = _iddq,						\
834		.num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions),	\
835		.funcs = tegra124_##_funcs##_functions,			\
836	}
837
838static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
839	TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
840	TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
841	TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
842	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
843	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
844	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
845	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
846	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
847	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
848	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
849	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
850	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
851};
852
853static const struct tegra_xusb_padctl_soc tegra124_soc = {
854	.num_pins = ARRAY_SIZE(tegra124_pins),
855	.pins = tegra124_pins,
856	.num_functions = ARRAY_SIZE(tegra124_functions),
857	.functions = tegra124_functions,
858	.num_lanes = ARRAY_SIZE(tegra124_lanes),
859	.lanes = tegra124_lanes,
860};
861
862static const struct of_device_id tegra_xusb_padctl_of_match[] = {
863	{ .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
864	{ }
865};
866MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
867
868/* predeclare these in order to silence sparse */
869int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
870int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
871
872int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
873{
874	struct tegra_xusb_padctl *padctl;
875	const struct of_device_id *match;
876	struct phy *phy;
877	int err;
878
879	padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
880	if (!padctl)
881		return -ENOMEM;
882
883	platform_set_drvdata(pdev, padctl);
884	mutex_init(&padctl->lock);
885	padctl->dev = &pdev->dev;
886
887	/*
888	 * Note that we can't replace this by of_device_get_match_data()
889	 * because we need the separate matching table for this legacy code on
890	 * Tegra124. of_device_get_match_data() would attempt to use the table
891	 * from the updated driver and fail.
892	 */
893	match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
894	padctl->soc = match->data;
895
896	padctl->regs = devm_platform_ioremap_resource(pdev, 0);
897	if (IS_ERR(padctl->regs))
898		return PTR_ERR(padctl->regs);
899
900	padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
901	if (IS_ERR(padctl->rst))
902		return PTR_ERR(padctl->rst);
903
904	err = reset_control_deassert(padctl->rst);
905	if (err < 0)
906		return err;
907
908	memset(&padctl->desc, 0, sizeof(padctl->desc));
909	padctl->desc.name = dev_name(padctl->dev);
910	padctl->desc.pins = tegra124_pins;
911	padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
912	padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
913	padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
914	padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
915	padctl->desc.owner = THIS_MODULE;
916
917	padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
918						padctl);
919	if (IS_ERR(padctl->pinctrl)) {
920		dev_err(&pdev->dev, "failed to register pincontrol\n");
921		err = PTR_ERR(padctl->pinctrl);
922		goto reset;
923	}
924
925	phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
926	if (IS_ERR(phy)) {
927		err = PTR_ERR(phy);
928		goto reset;
929	}
930
931	padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
932	phy_set_drvdata(phy, padctl);
933
934	phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
935	if (IS_ERR(phy)) {
936		err = PTR_ERR(phy);
937		goto reset;
938	}
939
940	padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
941	phy_set_drvdata(phy, padctl);
942
943	padctl->provider = devm_of_phy_provider_register(&pdev->dev,
944							 tegra_xusb_padctl_xlate);
945	if (IS_ERR(padctl->provider)) {
946		err = PTR_ERR(padctl->provider);
947		dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
948		goto reset;
949	}
950
951	return 0;
952
953reset:
954	reset_control_assert(padctl->rst);
955	return err;
956}
957EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
958
959int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
960{
961	struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
962	int err;
963
964	err = reset_control_assert(padctl->rst);
965	if (err < 0)
966		dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
967
968	return err;
969}
970EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);