pinctrl-sunxi.c

   1/*
   2 * Allwinner A1X SoCs pinctrl driver.
   3 *
   4 * Copyright (C) 2012 Maxime Ripard
   5 *
   6 * Maxime Ripard <maxime.ripard@free-electrons.com>
   7 *
   8 * This file is licensed under the terms of the GNU General Public
   9 * License version 2.  This program is licensed "as is" without any
  10 * warranty of any kind, whether express or implied.
  11 */
  12
  13#include <linux/clk.h>
  14#include <linux/export.h>
  15#include <linux/gpio/driver.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/irqchip/chained_irq.h>
  19#include <linux/irqdomain.h>
  20#include <linux/of.h>
  21#include <linux/of_clk.h>
  22#include <linux/platform_device.h>
  23#include <linux/regulator/consumer.h>
  24#include <linux/slab.h>
  25
  26#include <linux/pinctrl/consumer.h>
  27#include <linux/pinctrl/machine.h>
  28#include <linux/pinctrl/pinconf-generic.h>
  29#include <linux/pinctrl/pinconf.h>
  30#include <linux/pinctrl/pinctrl.h>
  31#include <linux/pinctrl/pinmux.h>
  32
  33#include <dt-bindings/pinctrl/sun4i-a10.h>
  34
  35#include "../core.h"
  36#include "pinctrl-sunxi.h"
  37
  38/*
  39 * These lock classes tell lockdep that GPIO IRQs are in a different
  40 * category than their parents, so it won't report false recursion.
  41 */
  42static struct lock_class_key sunxi_pinctrl_irq_lock_class;
  43static struct lock_class_key sunxi_pinctrl_irq_request_class;
  44
  45static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  46static struct irq_chip sunxi_pinctrl_level_irq_chip;
  47
  48/*
  49 * The sunXi PIO registers are organized as a series of banks, with registers
  50 * for each bank in the following order:
  51 *  - Mux config
  52 *  - Data value
  53 *  - Drive level
  54 *  - Pull direction
  55 *
  56 * Multiple consecutive registers are used for fields wider than one bit.
  57 *
  58 * The following functions calculate the register and the bit offset to access.
  59 * They take a pin number which is relative to the start of the current device.
  60 */
  61
  62/*
  63 * When using the extended register layout, Bank K does not fit into the
  64 * space used for the other banks. Instead it lives at offset 0x500.
  65 */
  66static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin)
  67{
  68	u32 offset = 0;
  69
  70	if (pin >= PK_BASE) {
  71		pin -= PK_BASE;
  72		offset = PIO_BANK_K_OFFSET;
  73	}
  74
  75	return offset + (pin / PINS_PER_BANK) * pctl->bank_mem_size;
  76}
  77
  78static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
  79			  u32 pin, u32 *reg, u32 *shift, u32 *mask)
  80{
  81	u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH;
  82
  83	*reg   = sunxi_bank_offset(pctl, pin) + MUX_REGS_OFFSET +
  84		 offset / BITS_PER_TYPE(u32) * sizeof(u32);
  85	*shift = offset % BITS_PER_TYPE(u32);
  86	*mask  = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
  87}
  88
  89static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
  90			   u32 pin, u32 *reg, u32 *shift, u32 *mask)
  91{
  92	u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH;
  93
  94	*reg   = sunxi_bank_offset(pctl, pin) + DATA_REGS_OFFSET +
  95		 offset / BITS_PER_TYPE(u32) * sizeof(u32);
  96	*shift = offset % BITS_PER_TYPE(u32);
  97	*mask  = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
  98}
  99
 100static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
 101			     u32 pin, u32 *reg, u32 *shift, u32 *mask)
 102{
 103	u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
 104
 105	*reg   = sunxi_bank_offset(pctl, pin) + DLEVEL_REGS_OFFSET +
 106		 offset / BITS_PER_TYPE(u32) * sizeof(u32);
 107	*shift = offset % BITS_PER_TYPE(u32);
 108	*mask  = (BIT(pctl->dlevel_field_width) - 1) << *shift;
 109}
 110
 111static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
 112			   u32 pin, u32 *reg, u32 *shift, u32 *mask)
 113{
 114	u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH;
 115
 116	*reg   = sunxi_bank_offset(pctl, pin) + pctl->pull_regs_offset +
 117		 offset / BITS_PER_TYPE(u32) * sizeof(u32);
 118	*shift = offset % BITS_PER_TYPE(u32);
 119	*mask  = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
 120}
 121
 122static struct sunxi_pinctrl_group *
 123sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
 124{
 125	int i;
 126
 127	for (i = 0; i < pctl->ngroups; i++) {
 128		struct sunxi_pinctrl_group *grp = pctl->groups + i;
 129
 130		if (!strcmp(grp->name, group))
 131			return grp;
 132	}
 133
 134	return NULL;
 135}
 136
 137static struct sunxi_pinctrl_function *
 138sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
 139				    const char *name)
 140{
 141	struct sunxi_pinctrl_function *func = pctl->functions;
 142	int i;
 143
 144	for (i = 0; i < pctl->nfunctions; i++) {
 145		if (!func[i].name)
 146			break;
 147
 148		if (!strcmp(func[i].name, name))
 149			return func + i;
 150	}
 151
 152	return NULL;
 153}
 154
 155static struct sunxi_desc_function *
 156sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
 157					 const char *pin_name,
 158					 const char *func_name)
 159{
 160	int i;
 161
 162	for (i = 0; i < pctl->desc->npins; i++) {
 163		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 164
 165		if (!strcmp(pin->pin.name, pin_name)) {
 166			struct sunxi_desc_function *func = pin->functions;
 167
 168			while (func->name) {
 169				if (!strcmp(func->name, func_name) &&
 170					(!func->variant ||
 171					func->variant & pctl->variant))
 172					return func;
 173
 174				func++;
 175			}
 176		}
 177	}
 178
 179	return NULL;
 180}
 181
 182static struct sunxi_desc_function *
 183sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
 184					const u16 pin_num,
 185					const char *func_name)
 186{
 187	int i;
 188
 189	for (i = 0; i < pctl->desc->npins; i++) {
 190		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 191
 192		if (pin->pin.number == pin_num) {
 193			struct sunxi_desc_function *func = pin->functions;
 194
 195			while (func->name) {
 196				if (!strcmp(func->name, func_name))
 197					return func;
 198
 199				func++;
 200			}
 201		}
 202	}
 203
 204	return NULL;
 205}
 206
 207static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 208{
 209	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 210
 211	return pctl->ngroups;
 212}
 213
 214static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 215					      unsigned group)
 216{
 217	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 218
 219	return pctl->groups[group].name;
 220}
 221
 222static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 223				      unsigned group,
 224				      const unsigned **pins,
 225				      unsigned *num_pins)
 226{
 227	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 228
 229	*pins = (unsigned *)&pctl->groups[group].pin;
 230	*num_pins = 1;
 231
 232	return 0;
 233}
 234
 235static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 236{
 237	return of_property_present(node, "bias-pull-up") ||
 238		of_property_present(node, "bias-pull-down") ||
 239		of_property_present(node, "bias-disable") ||
 240		of_property_present(node, "allwinner,pull");
 241}
 242
 243static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 244{
 245	return of_property_present(node, "drive-strength") ||
 246		of_property_present(node, "allwinner,drive");
 247}
 248
 249static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 250{
 251	u32 val;
 252
 253	/* Try the new style binding */
 254	if (of_property_present(node, "bias-pull-up"))
 255		return PIN_CONFIG_BIAS_PULL_UP;
 256
 257	if (of_property_present(node, "bias-pull-down"))
 258		return PIN_CONFIG_BIAS_PULL_DOWN;
 259
 260	if (of_property_present(node, "bias-disable"))
 261		return PIN_CONFIG_BIAS_DISABLE;
 262
 263	/* And fall back to the old binding */
 264	if (of_property_read_u32(node, "allwinner,pull", &val))
 265		return -EINVAL;
 266
 267	switch (val) {
 268	case SUN4I_PINCTRL_NO_PULL:
 269		return PIN_CONFIG_BIAS_DISABLE;
 270	case SUN4I_PINCTRL_PULL_UP:
 271		return PIN_CONFIG_BIAS_PULL_UP;
 272	case SUN4I_PINCTRL_PULL_DOWN:
 273		return PIN_CONFIG_BIAS_PULL_DOWN;
 274	}
 275
 276	return -EINVAL;
 277}
 278
 279static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 280{
 281	u32 val;
 282
 283	/* Try the new style binding */
 284	if (!of_property_read_u32(node, "drive-strength", &val)) {
 285		/* We can't go below 10mA ... */
 286		if (val < 10)
 287			return -EINVAL;
 288
 289		/* ... and only up to 40 mA ... */
 290		if (val > 40)
 291			val = 40;
 292
 293		/* by steps of 10 mA */
 294		return rounddown(val, 10);
 295	}
 296
 297	/* And then fall back to the old binding */
 298	if (of_property_read_u32(node, "allwinner,drive", &val))
 299		return -EINVAL;
 300
 301	return (val + 1) * 10;
 302}
 303
 304static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 305{
 306	const char *function;
 307	int ret;
 308
 309	/* Try the generic binding */
 310	ret = of_property_read_string(node, "function", &function);
 311	if (!ret)
 312		return function;
 313
 314	/* And fall back to our legacy one */
 315	ret = of_property_read_string(node, "allwinner,function", &function);
 316	if (!ret)
 317		return function;
 318
 319	return NULL;
 320}
 321
 322static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 323					      int *npins)
 324{
 325	int count;
 326
 327	/* Try the generic binding */
 328	count = of_property_count_strings(node, "pins");
 329	if (count > 0) {
 330		*npins = count;
 331		return "pins";
 332	}
 333
 334	/* And fall back to our legacy one */
 335	count = of_property_count_strings(node, "allwinner,pins");
 336	if (count > 0) {
 337		*npins = count;
 338		return "allwinner,pins";
 339	}
 340
 341	return NULL;
 342}
 343
 344static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 345						   unsigned int *len)
 346{
 347	unsigned long *pinconfig;
 348	unsigned int configlen = 0, idx = 0;
 349	int ret;
 350
 351	if (sunxi_pctrl_has_drive_prop(node))
 352		configlen++;
 353	if (sunxi_pctrl_has_bias_prop(node))
 354		configlen++;
 355
 356	/*
 357	 * If we don't have any configuration, bail out
 358	 */
 359	if (!configlen)
 360		return NULL;
 361
 362	pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
 363	if (!pinconfig)
 364		return ERR_PTR(-ENOMEM);
 365
 366	if (sunxi_pctrl_has_drive_prop(node)) {
 367		int drive = sunxi_pctrl_parse_drive_prop(node);
 368		if (drive < 0) {
 369			ret = drive;
 370			goto err_free;
 371		}
 372
 373		pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 374							  drive);
 375	}
 376
 377	if (sunxi_pctrl_has_bias_prop(node)) {
 378		int pull = sunxi_pctrl_parse_bias_prop(node);
 379		int arg = 0;
 380		if (pull < 0) {
 381			ret = pull;
 382			goto err_free;
 383		}
 384
 385		if (pull != PIN_CONFIG_BIAS_DISABLE)
 386			arg = 1; /* hardware uses weak pull resistors */
 387
 388		pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 389	}
 390
 391
 392	*len = configlen;
 393	return pinconfig;
 394
 395err_free:
 396	kfree(pinconfig);
 397	return ERR_PTR(ret);
 398}
 399
 400static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 401				      struct device_node *node,
 402				      struct pinctrl_map **map,
 403				      unsigned *num_maps)
 404{
 405	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 406	unsigned long *pinconfig;
 407	struct property *prop;
 408	const char *function, *pin_prop;
 409	const char *group;
 410	int ret, npins, nmaps, configlen = 0, i = 0;
 411	struct pinctrl_map *new_map;
 412
 413	*map = NULL;
 414	*num_maps = 0;
 415
 416	function = sunxi_pctrl_parse_function_prop(node);
 417	if (!function) {
 418		dev_err(pctl->dev, "missing function property in node %pOFn\n",
 419			node);
 420		return -EINVAL;
 421	}
 422
 423	pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 424	if (!pin_prop) {
 425		dev_err(pctl->dev, "missing pins property in node %pOFn\n",
 426			node);
 427		return -EINVAL;
 428	}
 429
 430	/*
 431	 * We have two maps for each pin: one for the function, one
 432	 * for the configuration (bias, strength, etc).
 433	 *
 434	 * We might be slightly overshooting, since we might not have
 435	 * any configuration.
 436	 */
 437	nmaps = npins * 2;
 438	*map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
 439	if (!*map)
 440		return -ENOMEM;
 441
 442	pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 443	if (IS_ERR(pinconfig)) {
 444		ret = PTR_ERR(pinconfig);
 445		goto err_free_map;
 446	}
 447
 448	of_property_for_each_string(node, pin_prop, prop, group) {
 449		struct sunxi_pinctrl_group *grp =
 450			sunxi_pinctrl_find_group_by_name(pctl, group);
 451
 452		if (!grp) {
 453			dev_err(pctl->dev, "unknown pin %s", group);
 454			continue;
 455		}
 456
 457		if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 458							      grp->name,
 459							      function)) {
 460			dev_err(pctl->dev, "unsupported function %s on pin %s",
 461				function, group);
 462			continue;
 463		}
 464
 465		(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 466		(*map)[i].data.mux.group = group;
 467		(*map)[i].data.mux.function = function;
 468
 469		i++;
 470
 471		if (pinconfig) {
 472			(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 473			(*map)[i].data.configs.group_or_pin = group;
 474			(*map)[i].data.configs.configs = pinconfig;
 475			(*map)[i].data.configs.num_configs = configlen;
 476			i++;
 477		}
 478	}
 479
 480	*num_maps = i;
 481
 482	/*
 483	 * We know have the number of maps we need, we can resize our
 484	 * map array
 485	 */
 486	new_map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 487	if (!new_map) {
 488		ret = -ENOMEM;
 489		goto err_free_map;
 490	}
 491
 492	*map = new_map;
 493
 494	return 0;
 495
 496err_free_map:
 497	kfree(*map);
 498	*map = NULL;
 499	return ret;
 500}
 501
 502static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 503				    struct pinctrl_map *map,
 504				    unsigned num_maps)
 505{
 506	int i;
 507
 508	/* pin config is never in the first map */
 509	for (i = 1; i < num_maps; i++) {
 510		if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 511			continue;
 512
 513		/*
 514		 * All the maps share the same pin config,
 515		 * free only the first one we find.
 516		 */
 517		kfree(map[i].data.configs.configs);
 518		break;
 519	}
 520
 521	kfree(map);
 522}
 523
 524static const struct pinctrl_ops sunxi_pctrl_ops = {
 525	.dt_node_to_map		= sunxi_pctrl_dt_node_to_map,
 526	.dt_free_map		= sunxi_pctrl_dt_free_map,
 527	.get_groups_count	= sunxi_pctrl_get_groups_count,
 528	.get_group_name		= sunxi_pctrl_get_group_name,
 529	.get_group_pins		= sunxi_pctrl_get_group_pins,
 530};
 531
 532static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
 533			   u32 pin, enum pin_config_param param,
 534			   u32 *reg, u32 *shift, u32 *mask)
 535{
 536	switch (param) {
 537	case PIN_CONFIG_DRIVE_STRENGTH:
 538		sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
 539		break;
 540
 541	case PIN_CONFIG_BIAS_PULL_UP:
 542	case PIN_CONFIG_BIAS_PULL_DOWN:
 543	case PIN_CONFIG_BIAS_DISABLE:
 544		sunxi_pull_reg(pctl, pin, reg, shift, mask);
 545		break;
 546
 547	default:
 548		return -ENOTSUPP;
 549	}
 550
 551	return 0;
 552}
 553
 554static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 555			   unsigned long *config)
 556{
 557	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 558	enum pin_config_param param = pinconf_to_config_param(*config);
 559	u32 reg, shift, mask, val;
 560	u16 arg;
 561	int ret;
 562
 563	pin -= pctl->desc->pin_base;
 564
 565	ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
 566	if (ret < 0)
 567		return ret;
 568
 569	val = (readl(pctl->membase + reg) & mask) >> shift;
 570
 571	switch (pinconf_to_config_param(*config)) {
 572	case PIN_CONFIG_DRIVE_STRENGTH:
 573		arg = (val + 1) * 10;
 574		break;
 575
 576	case PIN_CONFIG_BIAS_PULL_UP:
 577		if (val != SUN4I_PINCTRL_PULL_UP)
 578			return -EINVAL;
 579		arg = 1; /* hardware is weak pull-up */
 580		break;
 581
 582	case PIN_CONFIG_BIAS_PULL_DOWN:
 583		if (val != SUN4I_PINCTRL_PULL_DOWN)
 584			return -EINVAL;
 585		arg = 1; /* hardware is weak pull-down */
 586		break;
 587
 588	case PIN_CONFIG_BIAS_DISABLE:
 589		if (val != SUN4I_PINCTRL_NO_PULL)
 590			return -EINVAL;
 591		arg = 0;
 592		break;
 593
 594	default:
 595		/* sunxi_pconf_reg should catch anything unsupported */
 596		WARN_ON(1);
 597		return -ENOTSUPP;
 598	}
 599
 600	*config = pinconf_to_config_packed(param, arg);
 601
 602	return 0;
 603}
 604
 605static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 606				 unsigned group,
 607				 unsigned long *config)
 608{
 609	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 610	struct sunxi_pinctrl_group *g = &pctl->groups[group];
 611
 612	/* We only support 1 pin per group. Chain it to the pin callback */
 613	return sunxi_pconf_get(pctldev, g->pin, config);
 614}
 615
 616static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 617			   unsigned long *configs, unsigned num_configs)
 618{
 619	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 620	int i;
 621
 622	pin -= pctl->desc->pin_base;
 623
 624	for (i = 0; i < num_configs; i++) {
 625		u32 arg, reg, shift, mask, val;
 626		enum pin_config_param param;
 627		unsigned long flags;
 628		int ret;
 629
 630		param = pinconf_to_config_param(configs[i]);
 631		arg = pinconf_to_config_argument(configs[i]);
 632
 633		ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
 634		if (ret < 0)
 635			return ret;
 636
 637		switch (param) {
 638		case PIN_CONFIG_DRIVE_STRENGTH:
 639			if (arg < 10 || arg > 40)
 640				return -EINVAL;
 641			/*
 642			 * We convert from mA to what the register expects:
 643			 *   0: 10mA
 644			 *   1: 20mA
 645			 *   2: 30mA
 646			 *   3: 40mA
 647			 */
 648			val = arg / 10 - 1;
 649			break;
 650		case PIN_CONFIG_BIAS_DISABLE:
 651			val = 0;
 652			break;
 653		case PIN_CONFIG_BIAS_PULL_UP:
 654			if (arg == 0)
 655				return -EINVAL;
 656			val = 1;
 657			break;
 658		case PIN_CONFIG_BIAS_PULL_DOWN:
 659			if (arg == 0)
 660				return -EINVAL;
 661			val = 2;
 662			break;
 663		default:
 664			/* sunxi_pconf_reg should catch anything unsupported */
 665			WARN_ON(1);
 666			return -ENOTSUPP;
 667		}
 668
 669		raw_spin_lock_irqsave(&pctl->lock, flags);
 670		writel((readl(pctl->membase + reg) & ~mask) | val << shift,
 671		       pctl->membase + reg);
 672		raw_spin_unlock_irqrestore(&pctl->lock, flags);
 673	} /* for each config */
 674
 675	return 0;
 676}
 677
 678static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
 679				 unsigned long *configs, unsigned num_configs)
 680{
 681	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 682	struct sunxi_pinctrl_group *g = &pctl->groups[group];
 683
 684	/* We only support 1 pin per group. Chain it to the pin callback */
 685	return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
 686}
 687
 688static const struct pinconf_ops sunxi_pconf_ops = {
 689	.is_generic		= true,
 690	.pin_config_get		= sunxi_pconf_get,
 691	.pin_config_set		= sunxi_pconf_set,
 692	.pin_config_group_get	= sunxi_pconf_group_get,
 693	.pin_config_group_set	= sunxi_pconf_group_set,
 694};
 695
 696static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 697					 unsigned pin,
 698					 struct regulator *supply)
 699{
 700	unsigned short bank;
 701	unsigned long flags;
 702	u32 val, reg;
 703	int uV;
 704
 705	if (!pctl->desc->io_bias_cfg_variant)
 706		return 0;
 707
 708	uV = regulator_get_voltage(supply);
 709	if (uV < 0)
 710		return uV;
 711
 712	/* Might be dummy regulator with no voltage set */
 713	if (uV == 0)
 714		return 0;
 715
 716	pin -= pctl->desc->pin_base;
 717	bank = pin / PINS_PER_BANK;
 718
 719	switch (pctl->desc->io_bias_cfg_variant) {
 720	case BIAS_VOLTAGE_GRP_CONFIG:
 721		/*
 722		 * Configured value must be equal or greater to actual
 723		 * voltage.
 724		 */
 725		if (uV <= 1800000)
 726			val = 0x0; /* 1.8V */
 727		else if (uV <= 2500000)
 728			val = 0x6; /* 2.5V */
 729		else if (uV <= 2800000)
 730			val = 0x9; /* 2.8V */
 731		else if (uV <= 3000000)
 732			val = 0xA; /* 3.0V */
 733		else
 734			val = 0xD; /* 3.3V */
 735
 736		reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 737		reg &= ~IO_BIAS_MASK;
 738		writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
 739		return 0;
 740	case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
 741		val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
 742
 743		raw_spin_lock_irqsave(&pctl->lock, flags);
 744		reg = readl(pctl->membase + pctl->pow_mod_sel_offset +
 745			    PIO_POW_MOD_CTL_OFS);
 746		reg &= ~BIT(bank);
 747		writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset +
 748		       PIO_POW_MOD_CTL_OFS);
 749		raw_spin_unlock_irqrestore(&pctl->lock, flags);
 750
 751		fallthrough;
 752	case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
 753		val = uV <= 1800000 ? 1 : 0;
 754
 755		raw_spin_lock_irqsave(&pctl->lock, flags);
 756		reg = readl(pctl->membase + pctl->pow_mod_sel_offset);
 757		reg &= ~(1 << bank);
 758		writel(reg | val << bank,
 759		       pctl->membase + pctl->pow_mod_sel_offset);
 760		raw_spin_unlock_irqrestore(&pctl->lock, flags);
 761		return 0;
 762	default:
 763		return -EINVAL;
 764	}
 765}
 766
 767static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 768{
 769	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 770
 771	return pctl->nfunctions;
 772}
 773
 774static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 775					   unsigned function)
 776{
 777	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 778
 779	return pctl->functions[function].name;
 780}
 781
 782static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 783				     unsigned function,
 784				     const char * const **groups,
 785				     unsigned * const num_groups)
 786{
 787	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 788
 789	*groups = pctl->functions[function].groups;
 790	*num_groups = pctl->functions[function].ngroups;
 791
 792	return 0;
 793}
 794
 795static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 796				 unsigned pin,
 797				 u8 config)
 798{
 799	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 800	u32 reg, shift, mask;
 801	unsigned long flags;
 802
 803	pin -= pctl->desc->pin_base;
 804	sunxi_mux_reg(pctl, pin, &reg, &shift, &mask);
 805
 806	raw_spin_lock_irqsave(&pctl->lock, flags);
 807
 808	writel((readl(pctl->membase + reg) & ~mask) | config << shift,
 809	       pctl->membase + reg);
 810
 811	raw_spin_unlock_irqrestore(&pctl->lock, flags);
 812}
 813
 814static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 815			     unsigned function,
 816			     unsigned group)
 817{
 818	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 819	struct sunxi_pinctrl_group *g = pctl->groups + group;
 820	struct sunxi_pinctrl_function *func = pctl->functions + function;
 821	struct sunxi_desc_function *desc =
 822		sunxi_pinctrl_desc_find_function_by_name(pctl,
 823							 g->name,
 824							 func->name);
 825
 826	if (!desc)
 827		return -EINVAL;
 828
 829	sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 830
 831	return 0;
 832}
 833
 834static int
 835sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 836			struct pinctrl_gpio_range *range,
 837			unsigned offset,
 838			bool input)
 839{
 840	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 841	struct sunxi_desc_function *desc;
 842	const char *func;
 843
 844	if (input)
 845		func = "gpio_in";
 846	else
 847		func = "gpio_out";
 848
 849	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 850	if (!desc)
 851		return -EINVAL;
 852
 853	sunxi_pmx_set(pctldev, offset, desc->muxval);
 854
 855	return 0;
 856}
 857
 858static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
 859{
 860	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 861	unsigned short bank = offset / PINS_PER_BANK;
 862	unsigned short bank_offset = bank - pctl->desc->pin_base /
 863					    PINS_PER_BANK;
 864	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 865	struct regulator *reg = s_reg->regulator;
 866	char supply[16];
 867	int ret;
 868
 869	if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators)))
 870		return -EINVAL;
 871
 872	if (reg) {
 873		refcount_inc(&s_reg->refcount);
 874		return 0;
 875	}
 876
 877	snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
 878	reg = regulator_get(pctl->dev, supply);
 879	if (IS_ERR(reg))
 880		return dev_err_probe(pctl->dev, PTR_ERR(reg),
 881				     "Couldn't get bank P%c regulator\n",
 882				     'A' + bank);
 883
 884	ret = regulator_enable(reg);
 885	if (ret) {
 886		dev_err(pctl->dev,
 887			"Couldn't enable bank P%c regulator\n", 'A' + bank);
 888		goto out;
 889	}
 890
 891	sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
 892
 893	s_reg->regulator = reg;
 894	refcount_set(&s_reg->refcount, 1);
 895
 896	return 0;
 897
 898out:
 899	regulator_put(s_reg->regulator);
 900
 901	return ret;
 902}
 903
 904static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
 905{
 906	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 907	unsigned short bank = offset / PINS_PER_BANK;
 908	unsigned short bank_offset = bank - pctl->desc->pin_base /
 909					    PINS_PER_BANK;
 910	struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 911
 912	if (!refcount_dec_and_test(&s_reg->refcount))
 913		return 0;
 914
 915	regulator_disable(s_reg->regulator);
 916	regulator_put(s_reg->regulator);
 917	s_reg->regulator = NULL;
 918
 919	return 0;
 920}
 921
 922static const struct pinmux_ops sunxi_pmx_ops = {
 923	.get_functions_count	= sunxi_pmx_get_funcs_cnt,
 924	.get_function_name	= sunxi_pmx_get_func_name,
 925	.get_function_groups	= sunxi_pmx_get_func_groups,
 926	.set_mux		= sunxi_pmx_set_mux,
 927	.gpio_set_direction	= sunxi_pmx_gpio_set_direction,
 928	.request		= sunxi_pmx_request,
 929	.free			= sunxi_pmx_free,
 930	.strict			= true,
 931};
 932
 933static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 934					unsigned offset)
 935{
 936	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 937
 938	return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
 939					    chip->base + offset, true);
 940}
 941
 942static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 943{
 944	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 945	bool set_mux = pctl->desc->irq_read_needs_mux &&
 946		gpiochip_line_is_irq(chip, offset);
 947	u32 pin = offset + chip->base;
 948	u32 reg, shift, mask, val;
 949
 950	sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
 951
 952	if (set_mux)
 953		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 954
 955	val = (readl(pctl->membase + reg) & mask) >> shift;
 956
 957	if (set_mux)
 958		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 959
 960	return val;
 961}
 962
 963static int sunxi_pinctrl_gpio_set(struct gpio_chip *chip, unsigned int offset,
 964				  int value)
 965{
 966	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 967	u32 reg, shift, mask, val;
 968	unsigned long flags;
 969
 970	sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
 971
 972	raw_spin_lock_irqsave(&pctl->lock, flags);
 973
 974	val = readl(pctl->membase + reg);
 975
 976	if (value)
 977		val |= mask;
 978	else
 979		val &= ~mask;
 980
 981	writel(val, pctl->membase + reg);
 982
 983	raw_spin_unlock_irqrestore(&pctl->lock, flags);
 984
 985	return 0;
 986}
 987
 988static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 989					unsigned offset, int value)
 990{
 991	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 992
 993	sunxi_pinctrl_gpio_set(chip, offset, value);
 994	return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
 995					    chip->base + offset, false);
 996}
 997
 998static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 999				const struct of_phandle_args *gpiospec,
1000				u32 *flags)
1001{
1002	int pin, base;
1003
1004	base = PINS_PER_BANK * gpiospec->args[0];
1005	pin = base + gpiospec->args[1];
1006
1007	if (pin > gc->ngpio)
1008		return -EINVAL;
1009
1010	if (flags)
1011		*flags = gpiospec->args[2];
1012
1013	return pin;
1014}
1015
1016static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1017{
1018	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
1019	struct sunxi_desc_function *desc;
1020	unsigned pinnum = pctl->desc->pin_base + offset;
1021	unsigned irqnum;
1022
1023	if (offset >= chip->ngpio)
1024		return -ENXIO;
1025
1026	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
1027	if (!desc)
1028		return -EINVAL;
1029
1030	irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
1031
1032	dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
1033		chip->label, offset + chip->base, irqnum);
1034
1035	return irq_find_mapping(pctl->domain, irqnum);
1036}
1037
1038static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
1039{
1040	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1041	struct sunxi_desc_function *func;
1042	int ret;
1043
1044	func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
1045					pctl->irq_array[d->hwirq], "irq");
1046	if (!func)
1047		return -EINVAL;
1048
1049	ret = gpiochip_lock_as_irq(pctl->chip,
1050			pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1051	if (ret) {
1052		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
1053			irqd_to_hwirq(d));
1054		return ret;
1055	}
1056
1057	/* Change muxing to INT mode */
1058	sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
1059
1060	return 0;
1061}
1062
1063static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
1064{
1065	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1066
1067	gpiochip_unlock_as_irq(pctl->chip,
1068			      pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1069}
1070
1071static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
1072{
1073	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1074	u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
1075	u8 index = sunxi_irq_cfg_offset(d->hwirq);
1076	unsigned long flags;
1077	u32 regval;
1078	u8 mode;
1079
1080	switch (type) {
1081	case IRQ_TYPE_EDGE_RISING:
1082		mode = IRQ_EDGE_RISING;
1083		break;
1084	case IRQ_TYPE_EDGE_FALLING:
1085		mode = IRQ_EDGE_FALLING;
1086		break;
1087	case IRQ_TYPE_EDGE_BOTH:
1088		mode = IRQ_EDGE_BOTH;
1089		break;
1090	case IRQ_TYPE_LEVEL_HIGH:
1091		mode = IRQ_LEVEL_HIGH;
1092		break;
1093	case IRQ_TYPE_LEVEL_LOW:
1094		mode = IRQ_LEVEL_LOW;
1095		break;
1096	default:
1097		return -EINVAL;
1098	}
1099
1100	raw_spin_lock_irqsave(&pctl->lock, flags);
1101
1102	if (type & IRQ_TYPE_LEVEL_MASK)
1103		irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1104						 handle_fasteoi_irq, NULL);
1105	else
1106		irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1107						 handle_edge_irq, NULL);
1108
1109	regval = readl(pctl->membase + reg);
1110	regval &= ~(IRQ_CFG_IRQ_MASK << index);
1111	writel(regval | (mode << index), pctl->membase + reg);
1112
1113	raw_spin_unlock_irqrestore(&pctl->lock, flags);
1114
1115	return 0;
1116}
1117
1118static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1119{
1120	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1121	u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1122	u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1123
1124	/* Clear the IRQ */
1125	writel(1 << status_idx, pctl->membase + status_reg);
1126}
1127
1128static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1129{
1130	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1131	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1132	u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1133	unsigned long flags;
1134	u32 val;
1135
1136	raw_spin_lock_irqsave(&pctl->lock, flags);
1137
1138	/* Mask the IRQ */
1139	val = readl(pctl->membase + reg);
1140	writel(val & ~(1 << idx), pctl->membase + reg);
1141
1142	raw_spin_unlock_irqrestore(&pctl->lock, flags);
1143}
1144
1145static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1146{
1147	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1148	u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1149	u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1150	unsigned long flags;
1151	u32 val;
1152
1153	raw_spin_lock_irqsave(&pctl->lock, flags);
1154
1155	/* Unmask the IRQ */
1156	val = readl(pctl->membase + reg);
1157	writel(val | (1 << idx), pctl->membase + reg);
1158
1159	raw_spin_unlock_irqrestore(&pctl->lock, flags);
1160}
1161
1162static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1163{
1164	sunxi_pinctrl_irq_ack(d);
1165	sunxi_pinctrl_irq_unmask(d);
1166}
1167
1168static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1169{
1170	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1171	u8 bank = d->hwirq / IRQ_PER_BANK;
1172
1173	return irq_set_irq_wake(pctl->irq[bank], on);
1174}
1175
1176static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1177	.name		= "sunxi_pio_edge",
1178	.irq_ack	= sunxi_pinctrl_irq_ack,
1179	.irq_mask	= sunxi_pinctrl_irq_mask,
1180	.irq_unmask	= sunxi_pinctrl_irq_unmask,
1181	.irq_request_resources = sunxi_pinctrl_irq_request_resources,
1182	.irq_release_resources = sunxi_pinctrl_irq_release_resources,
1183	.irq_set_type	= sunxi_pinctrl_irq_set_type,
1184	.irq_set_wake	= sunxi_pinctrl_irq_set_wake,
1185	.flags		= IRQCHIP_MASK_ON_SUSPEND,
1186};
1187
1188static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1189	.name		= "sunxi_pio_level",
1190	.irq_eoi	= sunxi_pinctrl_irq_ack,
1191	.irq_mask	= sunxi_pinctrl_irq_mask,
1192	.irq_unmask	= sunxi_pinctrl_irq_unmask,
1193	/* Define irq_enable / disable to avoid spurious irqs for drivers
1194	 * using these to suppress irqs while they clear the irq source */
1195	.irq_enable	= sunxi_pinctrl_irq_ack_unmask,
1196	.irq_disable	= sunxi_pinctrl_irq_mask,
1197	.irq_request_resources = sunxi_pinctrl_irq_request_resources,
1198	.irq_release_resources = sunxi_pinctrl_irq_release_resources,
1199	.irq_set_type	= sunxi_pinctrl_irq_set_type,
1200	.irq_set_wake	= sunxi_pinctrl_irq_set_wake,
1201	.flags		= IRQCHIP_EOI_THREADED |
1202			  IRQCHIP_MASK_ON_SUSPEND |
1203			  IRQCHIP_EOI_IF_HANDLED,
1204};
1205
1206static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1207				      struct device_node *node,
1208				      const u32 *intspec,
1209				      unsigned int intsize,
1210				      unsigned long *out_hwirq,
1211				      unsigned int *out_type)
1212{
1213	struct sunxi_pinctrl *pctl = d->host_data;
1214	struct sunxi_desc_function *desc;
1215	int pin, base;
1216
1217	if (intsize < 3)
1218		return -EINVAL;
1219
1220	base = PINS_PER_BANK * intspec[0];
1221	pin = pctl->desc->pin_base + base + intspec[1];
1222
1223	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1224	if (!desc)
1225		return -EINVAL;
1226
1227	*out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1228	*out_type = intspec[2];
1229
1230	return 0;
1231}
1232
1233static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1234	.xlate		= sunxi_pinctrl_irq_of_xlate,
1235};
1236
1237static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1238{
1239	unsigned int irq = irq_desc_get_irq(desc);
1240	struct irq_chip *chip = irq_desc_get_chip(desc);
1241	struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1242	unsigned long bank, reg, val;
1243
1244	for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1245		if (irq == pctl->irq[bank])
1246			break;
1247
1248	WARN_ON(bank == pctl->desc->irq_banks);
1249
1250	chained_irq_enter(chip, desc);
1251
1252	reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1253	val = readl(pctl->membase + reg);
1254
1255	if (val) {
1256		int irqoffset;
1257
1258		for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1259			generic_handle_domain_irq(pctl->domain,
1260						  bank * IRQ_PER_BANK + irqoffset);
1261	}
1262
1263	chained_irq_exit(chip, desc);
1264}
1265
1266static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1267					const char *name)
1268{
1269	struct sunxi_pinctrl_function *func = pctl->functions;
1270
1271	while (func->name) {
1272		/* function already there */
1273		if (strcmp(func->name, name) == 0) {
1274			func->ngroups++;
1275			return -EEXIST;
1276		}
1277		func++;
1278	}
1279
1280	func->name = name;
1281	func->ngroups = 1;
1282
1283	pctl->nfunctions++;
1284
1285	return 0;
1286}
1287
1288static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1289{
1290	struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1291	void *ptr;
1292	int i;
1293
1294	/*
1295	 * Allocate groups
1296	 *
1297	 * We assume that the number of groups is the number of pins
1298	 * given in the data array.
1299
1300	 * This will not always be true, since some pins might not be
1301	 * available in the current variant, but fortunately for us,
1302	 * this means that the number of pins is the maximum group
1303	 * number we will ever see.
1304	 */
1305	pctl->groups = devm_kcalloc(&pdev->dev,
1306				    pctl->desc->npins, sizeof(*pctl->groups),
1307				    GFP_KERNEL);
1308	if (!pctl->groups)
1309		return -ENOMEM;
1310
1311	for (i = 0; i < pctl->desc->npins; i++) {
1312		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1313		struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1314
1315		if (pin->variant && !(pctl->variant & pin->variant))
1316			continue;
1317
1318		group->name = pin->pin.name;
1319		group->pin = pin->pin.number;
1320
1321		/* And now we count the actual number of pins / groups */
1322		pctl->ngroups++;
1323	}
1324
1325	/*
1326	 * Find an upper bound for the maximum number of functions: in
1327	 * the worst case we have gpio_in, gpio_out, irq and up to seven
1328	 * special functions per pin, plus one entry for the sentinel.
1329	 * We'll reallocate that later anyway.
1330	 */
1331	pctl->functions = kcalloc(7 * pctl->ngroups + 4,
1332				  sizeof(*pctl->functions),
1333				  GFP_KERNEL);
1334	if (!pctl->functions)
1335		return -ENOMEM;
1336
1337	/* Count functions and their associated groups */
1338	for (i = 0; i < pctl->desc->npins; i++) {
1339		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1340		struct sunxi_desc_function *func;
1341
1342		if (pin->variant && !(pctl->variant & pin->variant))
1343			continue;
1344
1345		for (func = pin->functions; func->name; func++) {
1346			if (func->variant && !(pctl->variant & func->variant))
1347				continue;
1348
1349			/* Create interrupt mapping while we're at it */
1350			if (!strcmp(func->name, "irq")) {
1351				int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1352				pctl->irq_array[irqnum] = pin->pin.number;
1353			}
1354
1355			sunxi_pinctrl_add_function(pctl, func->name);
1356		}
1357	}
1358
1359	/* And now allocated and fill the array for real */
1360	ptr = krealloc(pctl->functions,
1361		       pctl->nfunctions * sizeof(*pctl->functions),
1362		       GFP_KERNEL);
1363	if (!ptr) {
1364		kfree(pctl->functions);
1365		pctl->functions = NULL;
1366		return -ENOMEM;
1367	}
1368	pctl->functions = ptr;
1369
1370	for (i = 0; i < pctl->desc->npins; i++) {
1371		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1372		struct sunxi_desc_function *func;
1373
1374		if (pin->variant && !(pctl->variant & pin->variant))
1375			continue;
1376
1377		for (func = pin->functions; func->name; func++) {
1378			struct sunxi_pinctrl_function *func_item;
1379			const char **func_grp;
1380
1381			if (func->variant && !(pctl->variant & func->variant))
1382				continue;
1383
1384			func_item = sunxi_pinctrl_find_function_by_name(pctl,
1385									func->name);
1386			if (!func_item) {
1387				kfree(pctl->functions);
1388				return -EINVAL;
1389			}
1390
1391			if (!func_item->groups) {
1392				func_item->groups =
1393					devm_kcalloc(&pdev->dev,
1394						     func_item->ngroups,
1395						     sizeof(*func_item->groups),
1396						     GFP_KERNEL);
1397				if (!func_item->groups) {
1398					kfree(pctl->functions);
1399					return -ENOMEM;
1400				}
1401			}
1402
1403			func_grp = func_item->groups;
1404			while (*func_grp)
1405				func_grp++;
1406
1407			*func_grp = pin->pin.name;
1408		}
1409	}
1410
1411	return 0;
1412}
1413
1414static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1415{
1416	unsigned long clock = clk_get_rate(clk);
1417	unsigned int best_diff, best_div;
1418	int i;
1419
1420	best_diff = abs(freq - clock);
1421	best_div = 0;
1422
1423	for (i = 1; i < 8; i++) {
1424		int cur_diff = abs(freq - (clock >> i));
1425
1426		if (cur_diff < best_diff) {
1427			best_diff = cur_diff;
1428			best_div = i;
1429		}
1430	}
1431
1432	*diff = best_diff;
1433	return best_div;
1434}
1435
1436static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1437					struct device_node *node)
1438{
1439	unsigned int hosc_diff, losc_diff;
1440	unsigned int hosc_div, losc_div;
1441	struct clk *hosc, *losc;
1442	u8 div, src;
1443	int i, ret;
1444
1445	/* Deal with old DTs that didn't have the oscillators */
1446	if (of_clk_get_parent_count(node) != 3)
1447		return 0;
1448
1449	/* If we don't have any setup, bail out */
1450	if (!of_property_present(node, "input-debounce"))
1451		return 0;
1452
1453	losc = devm_clk_get(pctl->dev, "losc");
1454	if (IS_ERR(losc))
1455		return PTR_ERR(losc);
1456
1457	hosc = devm_clk_get(pctl->dev, "hosc");
1458	if (IS_ERR(hosc))
1459		return PTR_ERR(hosc);
1460
1461	for (i = 0; i < pctl->desc->irq_banks; i++) {
1462		unsigned long debounce_freq;
1463		u32 debounce;
1464
1465		ret = of_property_read_u32_index(node, "input-debounce",
1466						 i, &debounce);
1467		if (ret)
1468			return ret;
1469
1470		if (!debounce)
1471			continue;
1472
1473		debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1474		losc_div = sunxi_pinctrl_get_debounce_div(losc,
1475							  debounce_freq,
1476							  &losc_diff);
1477
1478		hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1479							  debounce_freq,
1480							  &hosc_diff);
1481
1482		if (hosc_diff < losc_diff) {
1483			div = hosc_div;
1484			src = 1;
1485		} else {
1486			div = losc_div;
1487			src = 0;
1488		}
1489
1490		writel(src | div << 4,
1491		       pctl->membase +
1492		       sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1493	}
1494
1495	return 0;
1496}
1497
1498int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
1499				  const struct sunxi_pinctrl_desc *desc,
1500				  unsigned long flags)
1501{
1502	struct device_node *node = pdev->dev.of_node;
1503	struct pinctrl_desc *pctrl_desc;
1504	struct pinctrl_pin_desc *pins;
1505	struct sunxi_pinctrl *pctl;
1506	struct pinmux_ops *pmxops;
1507	int i, ret, last_pin, pin_idx;
1508	struct clk *clk;
1509
1510	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1511	if (!pctl)
1512		return -ENOMEM;
1513	platform_set_drvdata(pdev, pctl);
1514
1515	raw_spin_lock_init(&pctl->lock);
1516
1517	pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1518	if (IS_ERR(pctl->membase))
1519		return PTR_ERR(pctl->membase);
1520
1521	pctl->dev = &pdev->dev;
1522	pctl->desc = desc;
1523	pctl->variant = flags & SUNXI_PINCTRL_VARIANT_MASK;
1524	if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) {
1525		pctl->bank_mem_size = D1_BANK_MEM_SIZE;
1526		pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
1527		pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
1528	} else {
1529		pctl->bank_mem_size = BANK_MEM_SIZE;
1530		pctl->pull_regs_offset = PULL_REGS_OFFSET;
1531		pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
1532	}
1533	if (flags & SUNXI_PINCTRL_ELEVEN_BANKS)
1534		pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG;
1535	else
1536		pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG;
1537
1538	pctl->irq_array = devm_kcalloc(&pdev->dev,
1539				       IRQ_PER_BANK * pctl->desc->irq_banks,
1540				       sizeof(*pctl->irq_array),
1541				       GFP_KERNEL);
1542	if (!pctl->irq_array)
1543		return -ENOMEM;
1544
1545	ret = sunxi_pinctrl_build_state(pdev);
1546	if (ret) {
1547		dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1548		return ret;
1549	}
1550
1551	pins = devm_kcalloc(&pdev->dev,
1552			    pctl->desc->npins, sizeof(*pins),
1553			    GFP_KERNEL);
1554	if (!pins)
1555		return -ENOMEM;
1556
1557	for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1558		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1559
1560		if (pin->variant && !(pctl->variant & pin->variant))
1561			continue;
1562
1563		pins[pin_idx++] = pin->pin;
1564	}
1565
1566	pctrl_desc = devm_kzalloc(&pdev->dev,
1567				  sizeof(*pctrl_desc),
1568				  GFP_KERNEL);
1569	if (!pctrl_desc)
1570		return -ENOMEM;
1571
1572	pctrl_desc->name = dev_name(&pdev->dev);
1573	pctrl_desc->owner = THIS_MODULE;
1574	pctrl_desc->pins = pins;
1575	pctrl_desc->npins = pctl->ngroups;
1576	pctrl_desc->confops = &sunxi_pconf_ops;
1577	pctrl_desc->pctlops = &sunxi_pctrl_ops;
1578
1579	pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1580			      GFP_KERNEL);
1581	if (!pmxops)
1582		return -ENOMEM;
1583
1584	if (desc->disable_strict_mode)
1585		pmxops->strict = false;
1586
1587	pctrl_desc->pmxops = pmxops;
1588
1589	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1590	if (IS_ERR(pctl->pctl_dev)) {
1591		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1592		return PTR_ERR(pctl->pctl_dev);
1593	}
1594
1595	pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1596	if (!pctl->chip)
1597		return -ENOMEM;
1598
1599	last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1600	pctl->chip->owner = THIS_MODULE;
1601	pctl->chip->request = gpiochip_generic_request;
1602	pctl->chip->free = gpiochip_generic_free;
1603	pctl->chip->set_config = gpiochip_generic_config;
1604	pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1605	pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1606	pctl->chip->get = sunxi_pinctrl_gpio_get;
1607	pctl->chip->set = sunxi_pinctrl_gpio_set;
1608	pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1609	pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1610	pctl->chip->of_gpio_n_cells = 3;
1611	pctl->chip->can_sleep = false;
1612	pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1613			    pctl->desc->pin_base;
1614	pctl->chip->label = dev_name(&pdev->dev);
1615	pctl->chip->parent = &pdev->dev;
1616	pctl->chip->base = pctl->desc->pin_base;
1617
1618	ret = gpiochip_add_data(pctl->chip, pctl);
1619	if (ret)
1620		return ret;
1621
1622	for (i = 0; i < pctl->desc->npins; i++) {
1623		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1624
1625		ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1626					     pin->pin.number - pctl->desc->pin_base,
1627					     pin->pin.number, 1);
1628		if (ret)
1629			goto gpiochip_error;
1630	}
1631
1632	ret = of_clk_get_parent_count(node);
1633	clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb");
1634	if (IS_ERR(clk)) {
1635		ret = PTR_ERR(clk);
1636		goto gpiochip_error;
1637	}
1638
1639	pctl->irq = devm_kcalloc(&pdev->dev,
1640				 pctl->desc->irq_banks,
1641				 sizeof(*pctl->irq),
1642				 GFP_KERNEL);
1643	if (!pctl->irq) {
1644		ret = -ENOMEM;
1645		goto gpiochip_error;
1646	}
1647
1648	for (i = 0; i < pctl->desc->irq_banks; i++) {
1649		pctl->irq[i] = platform_get_irq(pdev, i);
1650		if (pctl->irq[i] < 0) {
1651			ret = pctl->irq[i];
1652			goto gpiochip_error;
1653		}
1654	}
1655
1656	pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev),
1657						pctl->desc->irq_banks * IRQ_PER_BANK,
1658						&sunxi_pinctrl_irq_domain_ops, pctl);
1659	if (!pctl->domain) {
1660		dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1661		ret = -ENOMEM;
1662		goto gpiochip_error;
1663	}
1664
1665	for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1666		int irqno = irq_create_mapping(pctl->domain, i);
1667
1668		irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
1669				      &sunxi_pinctrl_irq_request_class);
1670		irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1671					 handle_edge_irq);
1672		irq_set_chip_data(irqno, pctl);
1673	}
1674
1675	for (i = 0; i < pctl->desc->irq_banks; i++) {
1676		/* Mask and clear all IRQs before registering a handler */
1677		writel(0, pctl->membase +
1678			  sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1679		writel(0xffffffff,
1680		       pctl->membase +
1681		       sunxi_irq_status_reg_from_bank(pctl->desc, i));
1682
1683		irq_set_chained_handler_and_data(pctl->irq[i],
1684						 sunxi_pinctrl_irq_handler,
1685						 pctl);
1686	}
1687
1688	sunxi_pinctrl_setup_debounce(pctl, node);
1689
1690	dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1691
1692	return 0;
1693
1694gpiochip_error:
1695	gpiochip_remove(pctl->chip);
1696	return ret;
1697}