pinctrl-stm32.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) Maxime Coquelin 2015
   4 * Copyright (C) STMicroelectronics 2017
   5 * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6 *
   7 * Heavily based on Mediatek's pinctrl driver
   8 */
   9#include <linux/bitfield.h>
  10#include <linux/clk.h>
  11#include <linux/export.h>
  12#include <linux/gpio/driver.h>
  13#include <linux/hwspinlock.h>
  14#include <linux/io.h>
  15#include <linux/irq.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/module.h>
  18#include <linux/of.h>
  19#include <linux/of_address.h>
  20#include <linux/of_irq.h>
  21#include <linux/platform_device.h>
  22#include <linux/property.h>
  23#include <linux/regmap.h>
  24#include <linux/reset.h>
  25#include <linux/seq_file.h>
  26#include <linux/slab.h>
  27#include <linux/string_choices.h>
  28
  29#include <linux/pinctrl/consumer.h>
  30#include <linux/pinctrl/machine.h>
  31#include <linux/pinctrl/pinconf-generic.h>
  32#include <linux/pinctrl/pinconf.h>
  33#include <linux/pinctrl/pinctrl.h>
  34#include <linux/pinctrl/pinmux.h>
  35
  36#include "../core.h"
  37#include "../pinconf.h"
  38#include "../pinctrl-utils.h"
  39#include "pinctrl-stm32.h"
  40
  41#define STM32_GPIO_CID1		1
  42
  43#define STM32_GPIO_MODER	0x00
  44#define STM32_GPIO_TYPER	0x04
  45#define STM32_GPIO_SPEEDR	0x08
  46#define STM32_GPIO_PUPDR	0x0c
  47#define STM32_GPIO_IDR		0x10
  48#define STM32_GPIO_ODR		0x14
  49#define STM32_GPIO_BSRR		0x18
  50#define STM32_GPIO_LCKR		0x1c
  51#define STM32_GPIO_AFRL		0x20
  52#define STM32_GPIO_AFRH		0x24
  53#define STM32_GPIO_SECCFGR	0x30
  54#define STM32_GPIO_DELAYRL	0x40
  55#define STM32_GPIO_ADVCFGRL	0x48
  56#define STM32_GPIO_CIDCFGR(x)	(0x50 + (0x8 * (x)))
  57#define STM32_GPIO_SEMCR(x)	(0x54 + (0x8 * (x)))
  58
  59/* Unitary delay for STM32_GPIO_DELAYRL */
  60#define STM32_GPIO_DELAYRL_PS	250
  61
  62#define STM32_GPIO_ADVCFGR_DLYPATH_MASK		BIT(0)
  63#define STM32_GPIO_ADVCFGR_DE_MASK		BIT(1)
  64#define STM32_GPIO_ADVCFGR_INVCLK_MASK		BIT(2)
  65#define STM32_GPIO_ADVCFGR_RET_MASK		BIT(3)
  66#define STM32_GPIO_ADVCFGR_IO_SYNC_MASK		\
  67	(STM32_GPIO_ADVCFGR_DE_MASK		\
  68	 | STM32_GPIO_ADVCFGR_INVCLK_MASK	\
  69	 | STM32_GPIO_ADVCFGR_RET_MASK)
  70
  71#define STM32_GPIO_CIDCFGR_CFEN		BIT(0)
  72#define STM32_GPIO_CIDCFGR_SEMEN	BIT(1)
  73#define STM32_GPIO_CIDCFGR_SCID_MASK	GENMASK(5, 4)
  74#define STM32_GPIO_CIDCFGR_SEMWL_CID1	BIT(16 + STM32_GPIO_CID1)
  75
  76#define STM32_GPIO_SEMCR_SEM_MUTEX	BIT(0)
  77#define STM32_GPIO_SEMCR_SEMCID_MASK	GENMASK(5, 4)
  78
  79#define STM32_GPIO_PINS_PER_BANK 16
  80#define STM32_GPIO_IRQ_LINE	 16
  81
  82#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
  83
  84/* Vendor specific pin configuration */
  85#define STM32_GPIO_PIN_CONFIG_IO_SYNC	(PIN_CONFIG_END + 1)
  86
  87#define gpio_range_to_bank(chip) \
  88		container_of(chip, struct stm32_gpio_bank, range)
  89
  90#define HWSPNLCK_TIMEOUT	1000 /* usec */
  91
  92static const char * const stm32_gpio_functions[] = {
  93	"gpio", "af0", "af1",
  94	"af2", "af3", "af4",
  95	"af5", "af6", "af7",
  96	"af8", "af9", "af10",
  97	"af11", "af12", "af13",
  98	"af14", "af15", "analog",
  99	"reserved",
 100};
 101
 102static const char * const stm32_gpio_io_sync[] = {
 103	"pass-through",
 104	"clock inverted",
 105	"data on rising edge",
 106	"data on falling edge",
 107	"data on both edges",
 108};
 109
 110static u8 io_sync_2_advcfgr[] = {
 111	/* data or clock GPIO pass-through */
 112	[0] = 0,
 113	/* clock GPIO inverted */
 114	[1] = STM32_GPIO_ADVCFGR_INVCLK_MASK,
 115	/* data GPIO re-sampled on clock rising edge */
 116	[2] = STM32_GPIO_ADVCFGR_RET_MASK,
 117	/* data GPIO re-sampled on clock falling edge */
 118	[3] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_INVCLK_MASK,
 119	/* data GPIO re-sampled on both clock edges */
 120	[4] = STM32_GPIO_ADVCFGR_RET_MASK | STM32_GPIO_ADVCFGR_DE_MASK,
 121};
 122
 123static const struct pinconf_generic_params stm32_gpio_bindings[] = {
 124	{"st,io-sync", STM32_GPIO_PIN_CONFIG_IO_SYNC, 0,
 125	 stm32_gpio_io_sync, ARRAY_SIZE(stm32_gpio_io_sync)},
 126};
 127
 128struct stm32_pinctrl_group {
 129	const char *name;
 130	unsigned long config;
 131	unsigned pin;
 132};
 133
 134struct stm32_pin_backup {
 135	unsigned int alt:4;
 136	unsigned int mode:2;
 137	unsigned int bias:2;
 138	unsigned int speed:2;
 139	unsigned int drive:1;
 140	unsigned int value:1;
 141	unsigned int advcfg:4;
 142	unsigned int skew_delay:4;
 143};
 144
 145struct stm32_gpio_bank {
 146	void __iomem *base;
 147	struct reset_control *rstc;
 148	spinlock_t lock;
 149	struct gpio_chip gpio_chip;
 150	struct pinctrl_gpio_range range;
 151	struct fwnode_handle *fwnode;
 152	struct irq_domain *domain;
 153	u32 bank_nr;
 154	u32 bank_ioport_nr;
 155	struct stm32_pin_backup pin_backup[STM32_GPIO_PINS_PER_BANK];
 156	u8 irq_type[STM32_GPIO_PINS_PER_BANK];
 157	bool secure_control;
 158	bool io_sync_control;
 159	bool rif_control;
 160};
 161
 162struct stm32_pinctrl {
 163	struct device *dev;
 164	struct pinctrl_dev *pctl_dev;
 165	struct pinctrl_desc pctl_desc;
 166	struct stm32_pinctrl_group *groups;
 167	unsigned ngroups;
 168	const char **grp_names;
 169	struct stm32_gpio_bank *banks;
 170	struct clk_bulk_data *clks;
 171	unsigned nbanks;
 172	const struct stm32_pinctrl_match_data *match_data;
 173	struct irq_domain	*domain;
 174	struct regmap		*regmap;
 175	struct regmap_field	*irqmux[STM32_GPIO_PINS_PER_BANK];
 176	struct hwspinlock *hwlock;
 177	struct stm32_desc_pin *pins;
 178	u32 npins;
 179	u32 pkg;
 180	u16 irqmux_map;
 181	spinlock_t irqmux_lock;
 182};
 183
 184static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt);
 185
 186static inline int stm32_gpio_pin(int gpio)
 187{
 188	return gpio % STM32_GPIO_PINS_PER_BANK;
 189}
 190
 191static inline u32 stm32_gpio_get_mode(u32 function)
 192{
 193	switch (function) {
 194	case STM32_PIN_GPIO:
 195		return 0;
 196	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
 197		return 2;
 198	case STM32_PIN_ANALOG:
 199		return 3;
 200	}
 201
 202	return 0;
 203}
 204
 205static inline u32 stm32_gpio_get_alt(u32 function)
 206{
 207	switch (function) {
 208	case STM32_PIN_GPIO:
 209		return 0;
 210	case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
 211		return function - 1;
 212	case STM32_PIN_ANALOG:
 213		return 0;
 214	}
 215
 216	return 0;
 217}
 218
 219static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
 220				    u32 offset, u32 value)
 221{
 222	bank->pin_backup[offset].value = value;
 223}
 224
 225static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
 226				   u32 mode, u32 alt)
 227{
 228	bank->pin_backup[offset].mode = mode;
 229	bank->pin_backup[offset].alt = alt;
 230}
 231
 232static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
 233				      u32 drive)
 234{
 235	bank->pin_backup[offset].drive = drive;
 236}
 237
 238static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
 239				    u32 speed)
 240{
 241	bank->pin_backup[offset].speed = speed;
 242}
 243
 244static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
 245				   u32 bias)
 246{
 247	bank->pin_backup[offset].bias = bias;
 248}
 249
 250static void stm32_gpio_backup_advcfg(struct stm32_gpio_bank *bank, u32 offset, u32 mask, u32 value)
 251{
 252	u32 val;
 253
 254	val = bank->pin_backup[offset].advcfg;
 255	val &= ~mask;
 256	val |= value & mask;
 257	bank->pin_backup[offset].advcfg = val;
 258}
 259
 260static void stm32_gpio_backup_skew_delay(struct stm32_gpio_bank *bank, u32 offset, u32 delay)
 261{
 262	bank->pin_backup[offset].skew_delay = delay;
 263}
 264
 265/* RIF functions */
 266
 267static bool stm32_gpio_rif_valid(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
 268{
 269	u32 cid;
 270
 271	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
 272
 273	if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
 274		return true;
 275
 276	if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
 277		if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
 278			return true;
 279
 280		return false;
 281	}
 282
 283	if (cid & STM32_GPIO_CIDCFGR_SEMWL_CID1)
 284		return true;
 285
 286	return false;
 287}
 288
 289static bool stm32_gpio_rif_acquire_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
 290{
 291	u32 cid, sem;
 292
 293	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
 294
 295	if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
 296		return true;
 297
 298	if (!(cid & STM32_GPIO_CIDCFGR_SEMEN)) {
 299		if (FIELD_GET(STM32_GPIO_CIDCFGR_SCID_MASK, cid) == STM32_GPIO_CID1)
 300			return true;
 301
 302		return false;
 303	}
 304
 305	if (!(cid & STM32_GPIO_CIDCFGR_SEMWL_CID1))
 306		return false;
 307
 308	sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
 309	if (sem & STM32_GPIO_SEMCR_SEM_MUTEX) {
 310		if (FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
 311			return true;
 312
 313		return false;
 314	}
 315
 316	writel_relaxed(STM32_GPIO_SEMCR_SEM_MUTEX, bank->base + STM32_GPIO_SEMCR(gpio_nr));
 317
 318	sem = readl_relaxed(bank->base + STM32_GPIO_SEMCR(gpio_nr));
 319	if (sem & STM32_GPIO_SEMCR_SEM_MUTEX &&
 320	    FIELD_GET(STM32_GPIO_SEMCR_SEMCID_MASK, sem) == STM32_GPIO_CID1)
 321		return true;
 322
 323	return false;
 324}
 325
 326static void stm32_gpio_rif_release_semaphore(struct stm32_gpio_bank *bank, unsigned int gpio_nr)
 327{
 328	u32 cid;
 329
 330	cid = readl_relaxed(bank->base + STM32_GPIO_CIDCFGR(gpio_nr));
 331
 332	if (!(cid & STM32_GPIO_CIDCFGR_CFEN))
 333		return;
 334
 335	if (cid & STM32_GPIO_CIDCFGR_SEMEN)
 336		writel_relaxed(0, bank->base + STM32_GPIO_SEMCR(gpio_nr));
 337}
 338
 339/* GPIO functions */
 340
 341static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
 342	unsigned int offset, u32 value)
 343{
 344	stm32_gpio_backup_value(bank, offset, value);
 345
 346	if (!value)
 347		offset += STM32_GPIO_PINS_PER_BANK;
 348
 349	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
 350}
 351
 352static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
 353{
 354	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 355	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 356	struct pinctrl_gpio_range *range;
 357	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
 358
 359	range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
 360	if (!range) {
 361		dev_err(pctl->dev, "pin %d not in range.\n", pin);
 362		return -EINVAL;
 363	}
 364
 365	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
 366		dev_err(pctl->dev, "pin %d not available.\n", offset);
 367		return -EACCES;
 368	}
 369
 370	return pinctrl_gpio_request(chip, offset);
 371}
 372
 373static void stm32_gpio_free(struct gpio_chip *chip, unsigned int offset)
 374{
 375	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 376
 377	pinctrl_gpio_free(chip, offset);
 378
 379	if (bank->rif_control)
 380		stm32_gpio_rif_release_semaphore(bank, offset);
 381}
 382
 383static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
 384{
 385	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 386
 387	return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
 388}
 389
 390static int stm32_gpio_set(struct gpio_chip *chip, unsigned int offset,
 391			  int value)
 392{
 393	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 394
 395	__stm32_gpio_set(bank, offset, value);
 396
 397	return 0;
 398}
 399
 400static int stm32_gpio_direction_output(struct gpio_chip *chip,
 401	unsigned offset, int value)
 402{
 403	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 404
 405	__stm32_gpio_set(bank, offset, value);
 406
 407	return pinctrl_gpio_direction_output(chip, offset);
 408}
 409
 410
 411static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
 412{
 413	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 414	struct irq_fwspec fwspec;
 415
 416	fwspec.fwnode = bank->fwnode;
 417	fwspec.param_count = 2;
 418	fwspec.param[0] = offset;
 419	fwspec.param[1] = IRQ_TYPE_NONE;
 420
 421	return irq_create_fwspec_mapping(&fwspec);
 422}
 423
 424static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 425{
 426	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 427	int pin = stm32_gpio_pin(offset);
 428	int ret;
 429	u32 mode, alt;
 430
 431	stm32_pmx_get_mode(bank, pin, &mode, &alt);
 432	if ((alt == 0) && (mode == 0))
 433		ret = GPIO_LINE_DIRECTION_IN;
 434	else if ((alt == 0) && (mode == 1))
 435		ret = GPIO_LINE_DIRECTION_OUT;
 436	else
 437		ret = -EINVAL;
 438
 439	return ret;
 440}
 441
 442static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
 443				      unsigned long *valid_mask,
 444				      unsigned int ngpios)
 445{
 446	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
 447	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 448	unsigned int i;
 449	u32 sec;
 450
 451	/* All gpio are valid per default */
 452	bitmap_fill(valid_mask, ngpios);
 453
 454	if (bank->secure_control) {
 455		/* Tag secured pins as invalid */
 456		sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
 457
 458		for (i = 0; i < ngpios; i++) {
 459			if (sec & BIT(i)) {
 460				clear_bit(i, valid_mask);
 461				dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
 462			}
 463		}
 464	}
 465
 466	if (bank->rif_control) {
 467		for (i = 0; i < ngpios; i++) {
 468			if (!test_bit(i, valid_mask))
 469				continue;
 470
 471			if (stm32_gpio_rif_valid(bank, i))
 472				continue;
 473
 474			dev_dbg(pctl->dev, "RIF semaphore ownership conflict, GPIO %u", i);
 475			clear_bit(i, valid_mask);
 476		}
 477	}
 478
 479	return 0;
 480}
 481
 482static const struct gpio_chip stm32_gpio_template = {
 483	.request		= stm32_gpio_request,
 484	.free			= stm32_gpio_free,
 485	.get			= stm32_gpio_get,
 486	.set			= stm32_gpio_set,
 487	.direction_input	= pinctrl_gpio_direction_input,
 488	.direction_output	= stm32_gpio_direction_output,
 489	.to_irq			= stm32_gpio_to_irq,
 490	.get_direction		= stm32_gpio_get_direction,
 491	.set_config		= gpiochip_generic_config,
 492	.init_valid_mask	= stm32_gpio_init_valid_mask,
 493};
 494
 495static void stm32_gpio_irq_trigger(struct irq_data *d)
 496{
 497	struct stm32_gpio_bank *bank = d->domain->host_data;
 498	int level;
 499
 500	/* Do not access the GPIO if this is not LEVEL triggered IRQ. */
 501	if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
 502		return;
 503
 504	/* If level interrupt type then retrig */
 505	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
 506	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
 507	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
 508		irq_chip_retrigger_hierarchy(d);
 509}
 510
 511static void stm32_gpio_irq_eoi(struct irq_data *d)
 512{
 513	irq_chip_eoi_parent(d);
 514	stm32_gpio_irq_trigger(d);
 515};
 516
 517static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
 518{
 519	struct stm32_gpio_bank *bank = d->domain->host_data;
 520	u32 parent_type;
 521
 522	switch (type) {
 523	case IRQ_TYPE_EDGE_RISING:
 524	case IRQ_TYPE_EDGE_FALLING:
 525	case IRQ_TYPE_EDGE_BOTH:
 526		parent_type = type;
 527		break;
 528	case IRQ_TYPE_LEVEL_HIGH:
 529		parent_type = IRQ_TYPE_EDGE_RISING;
 530		break;
 531	case IRQ_TYPE_LEVEL_LOW:
 532		parent_type = IRQ_TYPE_EDGE_FALLING;
 533		break;
 534	default:
 535		return -EINVAL;
 536	}
 537
 538	bank->irq_type[d->hwirq] = type;
 539
 540	return irq_chip_set_type_parent(d, parent_type);
 541};
 542
 543static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
 544{
 545	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
 546	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 547	int ret;
 548
 549	ret = pinctrl_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
 550	if (ret)
 551		return ret;
 552
 553	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
 554	if (ret) {
 555		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
 556			irq_data->hwirq);
 557		return ret;
 558	}
 559
 560	return 0;
 561}
 562
 563static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
 564{
 565	struct stm32_gpio_bank *bank = irq_data->domain->host_data;
 566
 567	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
 568}
 569
 570static void stm32_gpio_irq_unmask(struct irq_data *d)
 571{
 572	irq_chip_unmask_parent(d);
 573	stm32_gpio_irq_trigger(d);
 574}
 575
 576static struct irq_chip stm32_gpio_irq_chip = {
 577	.name		= "stm32gpio",
 578	.irq_eoi	= stm32_gpio_irq_eoi,
 579	.irq_ack	= irq_chip_ack_parent,
 580	.irq_mask	= irq_chip_mask_parent,
 581	.irq_unmask	= stm32_gpio_irq_unmask,
 582	.irq_set_type	= stm32_gpio_set_type,
 583	.irq_set_wake	= irq_chip_set_wake_parent,
 584	.irq_request_resources = stm32_gpio_irq_request_resources,
 585	.irq_release_resources = stm32_gpio_irq_release_resources,
 586	.irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
 587};
 588
 589static int stm32_gpio_domain_translate(struct irq_domain *d,
 590				       struct irq_fwspec *fwspec,
 591				       unsigned long *hwirq,
 592				       unsigned int *type)
 593{
 594	if ((fwspec->param_count != 2) ||
 595	    (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
 596		return -EINVAL;
 597
 598	*hwirq = fwspec->param[0];
 599	*type = fwspec->param[1];
 600	return 0;
 601}
 602
 603static int stm32_gpio_domain_activate(struct irq_domain *d,
 604				      struct irq_data *irq_data, bool reserve)
 605{
 606	struct stm32_gpio_bank *bank = d->host_data;
 607	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 608	int ret = 0;
 609
 610	if (pctl->hwlock) {
 611		ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 612						    HWSPNLCK_TIMEOUT);
 613		if (ret) {
 614			dev_err(pctl->dev, "Can't get hwspinlock\n");
 615			return ret;
 616		}
 617	}
 618
 619	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
 620
 621	if (pctl->hwlock)
 622		hwspin_unlock_in_atomic(pctl->hwlock);
 623
 624	return ret;
 625}
 626
 627static int stm32_gpio_domain_alloc(struct irq_domain *d,
 628				   unsigned int virq,
 629				   unsigned int nr_irqs, void *data)
 630{
 631	struct stm32_gpio_bank *bank = d->host_data;
 632	struct irq_fwspec *fwspec = data;
 633	struct irq_fwspec parent_fwspec;
 634	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 635	irq_hw_number_t hwirq = fwspec->param[0];
 636	unsigned long flags;
 637	int ret = 0;
 638
 639	/*
 640	 * Check first that the IRQ MUX of that line is free.
 641	 * gpio irq mux is shared between several banks, protect with a lock
 642	 */
 643	spin_lock_irqsave(&pctl->irqmux_lock, flags);
 644
 645	if (pctl->irqmux_map & BIT(hwirq)) {
 646		dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
 647		ret = -EBUSY;
 648	} else {
 649		pctl->irqmux_map |= BIT(hwirq);
 650	}
 651
 652	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
 653	if (ret)
 654		return ret;
 655
 656	parent_fwspec.fwnode = d->parent->fwnode;
 657	parent_fwspec.param_count = 2;
 658	parent_fwspec.param[0] = fwspec->param[0];
 659	parent_fwspec.param[1] = fwspec->param[1];
 660
 661	irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
 662				      bank);
 663
 664	return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
 665}
 666
 667static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
 668				   unsigned int nr_irqs)
 669{
 670	struct stm32_gpio_bank *bank = d->host_data;
 671	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 672	struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
 673	unsigned long flags, hwirq = irq_data->hwirq;
 674
 675	irq_domain_free_irqs_common(d, virq, nr_irqs);
 676
 677	spin_lock_irqsave(&pctl->irqmux_lock, flags);
 678	pctl->irqmux_map &= ~BIT(hwirq);
 679	spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
 680}
 681
 682static const struct irq_domain_ops stm32_gpio_domain_ops = {
 683	.translate	= stm32_gpio_domain_translate,
 684	.alloc		= stm32_gpio_domain_alloc,
 685	.free		= stm32_gpio_domain_free,
 686	.activate	= stm32_gpio_domain_activate,
 687};
 688
 689/* Pinctrl functions */
 690static struct stm32_pinctrl_group *
 691stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
 692{
 693	int i;
 694
 695	for (i = 0; i < pctl->ngroups; i++) {
 696		struct stm32_pinctrl_group *grp = pctl->groups + i;
 697
 698		if (grp->pin == pin)
 699			return grp;
 700	}
 701
 702	return NULL;
 703}
 704
 705static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
 706		u32 pin_num, u32 fnum)
 707{
 708	int i, k;
 709
 710	for (i = 0; i < pctl->npins; i++) {
 711		const struct stm32_desc_pin *pin = pctl->pins + i;
 712		const struct stm32_desc_function *func = pin->functions;
 713
 714		if (pin->pin.number != pin_num)
 715			continue;
 716
 717		if (fnum == STM32_PIN_RSVD)
 718			return true;
 719
 720		for (k = 0; k < STM32_CONFIG_NUM; k++) {
 721			if (func->num == fnum)
 722				return true;
 723			func++;
 724		}
 725
 726		break;
 727	}
 728
 729	dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
 730
 731	return false;
 732}
 733
 734static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
 735		u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
 736		struct pinctrl_map **map, unsigned *reserved_maps,
 737		unsigned *num_maps)
 738{
 739	if (*num_maps == *reserved_maps)
 740		return -ENOSPC;
 741
 742	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
 743	(*map)[*num_maps].data.mux.group = grp->name;
 744
 745	if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
 746		return -EINVAL;
 747
 748	(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
 749	(*num_maps)++;
 750
 751	return 0;
 752}
 753
 754static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 755				      struct device_node *node,
 756				      struct pinctrl_map **map,
 757				      unsigned *reserved_maps,
 758				      unsigned *num_maps)
 759{
 760	struct stm32_pinctrl *pctl;
 761	struct stm32_pinctrl_group *grp;
 762	struct property *pins;
 763	u32 pinfunc, pin, func;
 764	unsigned long *configs;
 765	unsigned int num_configs;
 766	bool has_config = 0;
 767	unsigned reserve = 0;
 768	int num_pins, num_funcs, maps_per_pin, i, err = 0;
 769
 770	pctl = pinctrl_dev_get_drvdata(pctldev);
 771
 772	pins = of_find_property(node, "pinmux", NULL);
 773	if (!pins) {
 774		dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
 775				node);
 776		return -EINVAL;
 777	}
 778
 779	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
 780		&num_configs);
 781	if (err)
 782		return err;
 783
 784	if (num_configs)
 785		has_config = 1;
 786
 787	num_pins = pins->length / sizeof(u32);
 788	num_funcs = num_pins;
 789	maps_per_pin = 0;
 790	if (num_funcs)
 791		maps_per_pin++;
 792	if (has_config && num_pins >= 1)
 793		maps_per_pin++;
 794
 795	if (!num_pins || !maps_per_pin) {
 796		err = -EINVAL;
 797		goto exit;
 798	}
 799
 800	reserve = num_pins * maps_per_pin;
 801
 802	err = pinctrl_utils_reserve_map(pctldev, map,
 803			reserved_maps, num_maps, reserve);
 804	if (err)
 805		goto exit;
 806
 807	for (i = 0; i < num_pins; i++) {
 808		err = of_property_read_u32_index(node, "pinmux",
 809				i, &pinfunc);
 810		if (err)
 811			goto exit;
 812
 813		pin = STM32_GET_PIN_NO(pinfunc);
 814		func = STM32_GET_PIN_FUNC(pinfunc);
 815
 816		if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
 817			err = -EINVAL;
 818			goto exit;
 819		}
 820
 821		grp = stm32_pctrl_find_group_by_pin(pctl, pin);
 822		if (!grp) {
 823			dev_err(pctl->dev, "unable to match pin %d to group\n",
 824					pin);
 825			err = -EINVAL;
 826			goto exit;
 827		}
 828
 829		err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
 830				reserved_maps, num_maps);
 831		if (err)
 832			goto exit;
 833
 834		if (has_config) {
 835			err = pinctrl_utils_add_map_configs(pctldev, map,
 836					reserved_maps, num_maps, grp->name,
 837					configs, num_configs,
 838					PIN_MAP_TYPE_CONFIGS_GROUP);
 839			if (err)
 840				goto exit;
 841		}
 842	}
 843
 844exit:
 845	kfree(configs);
 846	return err;
 847}
 848
 849static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 850				 struct device_node *np_config,
 851				 struct pinctrl_map **map, unsigned *num_maps)
 852{
 853	unsigned reserved_maps;
 854	int ret;
 855
 856	*map = NULL;
 857	*num_maps = 0;
 858	reserved_maps = 0;
 859
 860	for_each_child_of_node_scoped(np_config, np) {
 861		ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
 862				&reserved_maps, num_maps);
 863		if (ret < 0) {
 864			pinctrl_utils_free_map(pctldev, *map, *num_maps);
 865			return ret;
 866		}
 867	}
 868
 869	return 0;
 870}
 871
 872static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 873{
 874	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 875
 876	return pctl->ngroups;
 877}
 878
 879static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 880					      unsigned group)
 881{
 882	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 883
 884	return pctl->groups[group].name;
 885}
 886
 887static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 888				      unsigned group,
 889				      const unsigned **pins,
 890				      unsigned *num_pins)
 891{
 892	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 893
 894	*pins = (unsigned *)&pctl->groups[group].pin;
 895	*num_pins = 1;
 896
 897	return 0;
 898}
 899
 900static const struct pinctrl_ops stm32_pctrl_ops = {
 901	.dt_node_to_map		= stm32_pctrl_dt_node_to_map,
 902	.dt_free_map		= pinctrl_utils_free_map,
 903	.get_groups_count	= stm32_pctrl_get_groups_count,
 904	.get_group_name		= stm32_pctrl_get_group_name,
 905	.get_group_pins		= stm32_pctrl_get_group_pins,
 906};
 907
 908
 909/* Pinmux functions */
 910
 911static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 912{
 913	return ARRAY_SIZE(stm32_gpio_functions);
 914}
 915
 916static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
 917					   unsigned selector)
 918{
 919	return stm32_gpio_functions[selector];
 920}
 921
 922static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 923				     unsigned function,
 924				     const char * const **groups,
 925				     unsigned * const num_groups)
 926{
 927	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 928
 929	*groups = pctl->grp_names;
 930	*num_groups = pctl->ngroups;
 931
 932	return 0;
 933}
 934
 935static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
 936			      int pin, u32 mode, u32 alt)
 937{
 938	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 939	u32 val;
 940	int alt_shift = (pin % 8) * 4;
 941	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
 942	unsigned long flags;
 943	int err = 0;
 944
 945	spin_lock_irqsave(&bank->lock, flags);
 946
 947	if (pctl->hwlock) {
 948		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
 949						    HWSPNLCK_TIMEOUT);
 950		if (err) {
 951			dev_err(pctl->dev, "Can't get hwspinlock\n");
 952			goto unlock;
 953		}
 954	}
 955
 956	val = readl_relaxed(bank->base + alt_offset);
 957	val &= ~GENMASK(alt_shift + 3, alt_shift);
 958	val |= (alt << alt_shift);
 959	writel_relaxed(val, bank->base + alt_offset);
 960
 961	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
 962	val &= ~GENMASK(pin * 2 + 1, pin * 2);
 963	val |= mode << (pin * 2);
 964	writel_relaxed(val, bank->base + STM32_GPIO_MODER);
 965
 966	if (pctl->hwlock)
 967		hwspin_unlock_in_atomic(pctl->hwlock);
 968
 969	stm32_gpio_backup_mode(bank, pin, mode, alt);
 970
 971unlock:
 972	spin_unlock_irqrestore(&bank->lock, flags);
 973
 974	return err;
 975}
 976
 977static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, u32 *alt)
 978{
 979	u32 val;
 980	int alt_shift = (pin % 8) * 4;
 981	int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
 982
 983	val = readl_relaxed(bank->base + alt_offset);
 984	val &= GENMASK(alt_shift + 3, alt_shift);
 985	*alt = val >> alt_shift;
 986
 987	val = readl_relaxed(bank->base + STM32_GPIO_MODER);
 988	val &= GENMASK(pin * 2 + 1, pin * 2);
 989	*mode = val >> (pin * 2);
 990}
 991
 992static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
 993			    unsigned function,
 994			    unsigned group)
 995{
 996	bool ret;
 997	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 998	struct stm32_pinctrl_group *g = pctl->groups + group;
 999	struct pinctrl_gpio_range *range;
1000	struct stm32_gpio_bank *bank;
1001	u32 mode, alt;
1002	int pin;
1003
1004	ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
1005	if (!ret)
1006		return -EINVAL;
1007
1008	range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
1009	if (!range) {
1010		dev_err(pctl->dev, "No gpio range defined.\n");
1011		return -EINVAL;
1012	}
1013
1014	if (function == STM32_PIN_RSVD) {
1015		dev_dbg(pctl->dev, "Reserved pins, skipping HW update.\n");
1016		return 0;
1017	}
1018
1019	bank = gpiochip_get_data(range->gc);
1020	pin = stm32_gpio_pin(g->pin);
1021
1022	mode = stm32_gpio_get_mode(function);
1023	alt = stm32_gpio_get_alt(function);
1024
1025	return stm32_pmx_set_mode(bank, pin, mode, alt);
1026}
1027
1028static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1029			struct pinctrl_gpio_range *range, unsigned gpio,
1030			bool input)
1031{
1032	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
1033	int pin = stm32_gpio_pin(gpio);
1034
1035	return stm32_pmx_set_mode(bank, pin, !input, 0);
1036}
1037
1038static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
1039{
1040	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1041	unsigned int offset = stm32_gpio_pin(gpio);
1042	struct pinctrl_gpio_range *range;
1043	struct stm32_gpio_bank *bank;
1044
1045	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
1046	if (!range) {
1047		dev_err(pctl->dev, "No gpio range defined.\n");
1048		return -EINVAL;
1049	}
1050
1051	if (!gpiochip_line_is_valid(range->gc, offset)) {
1052		dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
1053		return -EACCES;
1054	}
1055
1056	bank = gpiochip_get_data(range->gc);
1057	if (!bank)
1058		return -ENODEV;
1059
1060	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
1061		dev_err(pctl->dev, "pin %d not available.\n", offset);
1062		return -EACCES;
1063	}
1064
1065	return 0;
1066}
1067
1068static const struct pinmux_ops stm32_pmx_ops = {
1069	.get_functions_count	= stm32_pmx_get_funcs_cnt,
1070	.get_function_name	= stm32_pmx_get_func_name,
1071	.get_function_groups	= stm32_pmx_get_func_groups,
1072	.set_mux		= stm32_pmx_set_mux,
1073	.gpio_set_direction	= stm32_pmx_gpio_set_direction,
1074	.request		= stm32_pmx_request,
1075	.strict			= true,
1076};
1077
1078/* Pinconf functions */
1079
1080static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
1081				   unsigned offset, u32 drive)
1082{
1083	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1084	unsigned long flags;
1085	u32 val;
1086	int err = 0;
1087
1088	spin_lock_irqsave(&bank->lock, flags);
1089
1090	if (pctl->hwlock) {
1091		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1092						    HWSPNLCK_TIMEOUT);
1093		if (err) {
1094			dev_err(pctl->dev, "Can't get hwspinlock\n");
1095			goto unlock;
1096		}
1097	}
1098
1099	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
1100	val &= ~BIT(offset);
1101	val |= drive << offset;
1102	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
1103
1104	if (pctl->hwlock)
1105		hwspin_unlock_in_atomic(pctl->hwlock);
1106
1107	stm32_gpio_backup_driving(bank, offset, drive);
1108
1109unlock:
1110	spin_unlock_irqrestore(&bank->lock, flags);
1111
1112	return err;
1113}
1114
1115static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
1116	unsigned int offset)
1117{
1118	u32 val;
1119
1120	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
1121	val &= BIT(offset);
1122
1123	return (val >> offset);
1124}
1125
1126static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
1127				 unsigned offset, u32 speed)
1128{
1129	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1130	unsigned long flags;
1131	u32 val;
1132	int err = 0;
1133
1134	spin_lock_irqsave(&bank->lock, flags);
1135
1136	if (pctl->hwlock) {
1137		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1138						    HWSPNLCK_TIMEOUT);
1139		if (err) {
1140			dev_err(pctl->dev, "Can't get hwspinlock\n");
1141			goto unlock;
1142		}
1143	}
1144
1145	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
1146	val &= ~GENMASK(offset * 2 + 1, offset * 2);
1147	val |= speed << (offset * 2);
1148	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
1149
1150	if (pctl->hwlock)
1151		hwspin_unlock_in_atomic(pctl->hwlock);
1152
1153	stm32_gpio_backup_speed(bank, offset, speed);
1154
1155unlock:
1156	spin_unlock_irqrestore(&bank->lock, flags);
1157
1158	return err;
1159}
1160
1161static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
1162	unsigned int offset)
1163{
1164	u32 val;
1165
1166	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
1167	val &= GENMASK(offset * 2 + 1, offset * 2);
1168
1169	return (val >> (offset * 2));
1170}
1171
1172static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1173				unsigned offset, u32 bias)
1174{
1175	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1176	unsigned long flags;
1177	u32 val;
1178	int err = 0;
1179
1180	spin_lock_irqsave(&bank->lock, flags);
1181
1182	if (pctl->hwlock) {
1183		err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1184						    HWSPNLCK_TIMEOUT);
1185		if (err) {
1186			dev_err(pctl->dev, "Can't get hwspinlock\n");
1187			goto unlock;
1188		}
1189	}
1190
1191	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1192	val &= ~GENMASK(offset * 2 + 1, offset * 2);
1193	val |= bias << (offset * 2);
1194	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1195
1196	if (pctl->hwlock)
1197		hwspin_unlock_in_atomic(pctl->hwlock);
1198
1199	stm32_gpio_backup_bias(bank, offset, bias);
1200
1201unlock:
1202	spin_unlock_irqrestore(&bank->lock, flags);
1203
1204	return err;
1205}
1206
1207static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1208	unsigned int offset)
1209{
1210	u32 val;
1211
1212	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1213	val &= GENMASK(offset * 2 + 1, offset * 2);
1214
1215	return (val >> (offset * 2));
1216}
1217
1218static void
1219stm32_pconf_set_advcfgr_nolock(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
1220{
1221	int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
1222	int advcfgr_shift = (offset % 8) * 4;
1223	u32 val;
1224
1225	val = readl_relaxed(bank->base + advcfgr_offset);
1226	val &= ~(mask << advcfgr_shift);
1227	val |= (value & mask) << advcfgr_shift;
1228	writel_relaxed(val, bank->base + advcfgr_offset);
1229
1230	stm32_gpio_backup_advcfg(bank, offset, mask, value);
1231}
1232
1233static int stm32_pconf_set_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask, u32 value)
1234{
1235	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1236	unsigned long flags;
1237	int err = 0;
1238
1239	if (!bank->io_sync_control)
1240		return -ENOTSUPP;
1241
1242	spin_lock_irqsave(&bank->lock, flags);
1243
1244	if (pctl->hwlock) {
1245		err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
1246		if (err) {
1247			dev_err(pctl->dev, "Can't get hwspinlock\n");
1248			goto unlock;
1249		}
1250	}
1251
1252	stm32_pconf_set_advcfgr_nolock(bank, offset, mask, value);
1253
1254	if (pctl->hwlock)
1255		hwspin_unlock_in_atomic(pctl->hwlock);
1256
1257unlock:
1258	spin_unlock_irqrestore(&bank->lock, flags);
1259
1260	return err;
1261}
1262
1263static u32 stm32_pconf_get_advcfgr(struct stm32_gpio_bank *bank, int offset, u32 mask)
1264{
1265	int advcfgr_offset = STM32_GPIO_ADVCFGRL + (offset / 8) * 4;
1266	int advcfgr_shift = (offset % 8) * 4;
1267	u32 val;
1268
1269	if (!bank->io_sync_control)
1270		return 0;
1271
1272	val = readl_relaxed(bank->base + advcfgr_offset);
1273	val >>= advcfgr_shift;
1274
1275	return val & mask;
1276}
1277
1278static int stm32_pconf_set_io_sync(struct stm32_gpio_bank *bank, int offset, u32 io_sync)
1279{
1280	if (io_sync >= ARRAY_SIZE(io_sync_2_advcfgr))
1281		return -EINVAL;
1282
1283	return stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
1284		io_sync_2_advcfgr[io_sync]);
1285}
1286
1287static const char *stm32_pconf_get_io_sync_str(struct stm32_gpio_bank *bank, int offset)
1288{
1289	u32 io_sync = stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK);
1290
1291	if (io_sync & STM32_GPIO_ADVCFGR_RET_MASK) {
1292		if (io_sync & STM32_GPIO_ADVCFGR_DE_MASK)
1293			return "data GPIO re-sampled on both clock edges";
1294
1295		if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
1296			return "data GPIO re-sampled on clock falling edge";
1297
1298		return "data GPIO re-sampled on clock rising edge";
1299	}
1300
1301	if (io_sync & STM32_GPIO_ADVCFGR_INVCLK_MASK)
1302		return "clock GPIO inverted";
1303
1304	return NULL;
1305}
1306
1307static int
1308stm32_pconf_set_skew_delay(struct stm32_gpio_bank *bank, int offset, u32 delay, bool is_dir_input)
1309{
1310	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1311	int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
1312	int delay_shift = (offset % 8) * 4;
1313	unsigned long flags;
1314	int err = 0;
1315	u32 val;
1316
1317	if (!bank->io_sync_control)
1318		return -ENOTSUPP;
1319
1320	spin_lock_irqsave(&bank->lock, flags);
1321
1322	if (pctl->hwlock) {
1323		err = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT);
1324		if (err) {
1325			dev_err(pctl->dev, "Can't get hwspinlock\n");
1326			goto unlock;
1327		}
1328	}
1329
1330	val = readl_relaxed(bank->base + delay_offset);
1331	val &= ~GENMASK(delay_shift + 3, delay_shift);
1332	val |= (delay << delay_shift);
1333	writel_relaxed(val, bank->base + delay_offset);
1334
1335	stm32_gpio_backup_skew_delay(bank, offset, delay);
1336
1337	stm32_pconf_set_advcfgr_nolock(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK,
1338				       is_dir_input ? STM32_GPIO_ADVCFGR_DLYPATH_MASK : 0);
1339
1340	if (pctl->hwlock)
1341		hwspin_unlock_in_atomic(pctl->hwlock);
1342
1343unlock:
1344	spin_unlock_irqrestore(&bank->lock, flags);
1345
1346	return err;
1347}
1348
1349static u32 stm32_pconf_get_skew_delay_val(struct stm32_gpio_bank *bank, int offset)
1350{
1351	int delay_offset = STM32_GPIO_DELAYRL + (offset / 8) * 4;
1352	int delay_shift = (offset % 8) * 4;
1353	u32 val;
1354
1355	val = readl_relaxed(bank->base + delay_offset);
1356	val &= GENMASK(delay_shift + 3, delay_shift);
1357
1358	return val >> delay_shift;
1359}
1360
1361static const char *stm32_pconf_get_skew_dir_str(struct stm32_gpio_bank *bank, int offset)
1362{
1363	return stm32_pconf_get_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_DLYPATH_MASK) ?
1364		"input" : "output";
1365}
1366
1367static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1368	unsigned int offset, bool dir)
1369{
1370	bool val;
1371
1372	if (dir)
1373		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1374			 BIT(offset));
1375	else
1376		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1377			 BIT(offset));
1378
1379	return val;
1380}
1381
1382static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1383		unsigned int pin, unsigned long config)
1384{
1385	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1386	unsigned int param = pinconf_to_config_param(config);
1387	u32 arg = pinconf_to_config_argument(config);
1388	struct pinctrl_gpio_range *range;
1389	struct stm32_gpio_bank *bank;
1390	int offset, ret = 0;
1391
1392	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1393	if (!range) {
1394		dev_err(pctl->dev, "No gpio range defined.\n");
1395		return -EINVAL;
1396	}
1397
1398	bank = gpiochip_get_data(range->gc);
1399	offset = stm32_gpio_pin(pin);
1400
1401	if (!gpiochip_line_is_valid(range->gc, offset)) {
1402		dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1403		return -EACCES;
1404	}
1405
1406	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
1407		dev_err(pctl->dev, "pin %d not available.\n", offset);
1408		return -EACCES;
1409	}
1410
1411	switch (param) {
1412	case PIN_CONFIG_DRIVE_PUSH_PULL:
1413		ret = stm32_pconf_set_driving(bank, offset, 0);
1414		break;
1415	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1416		ret = stm32_pconf_set_driving(bank, offset, 1);
1417		break;
1418	case PIN_CONFIG_SLEW_RATE:
1419		ret = stm32_pconf_set_speed(bank, offset, arg);
1420		break;
1421	case PIN_CONFIG_BIAS_DISABLE:
1422		ret = stm32_pconf_set_bias(bank, offset, 0);
1423		break;
1424	case PIN_CONFIG_BIAS_PULL_UP:
1425		ret = stm32_pconf_set_bias(bank, offset, 1);
1426		break;
1427	case PIN_CONFIG_BIAS_PULL_DOWN:
1428		ret = stm32_pconf_set_bias(bank, offset, 2);
1429		break;
1430	case PIN_CONFIG_LEVEL:
1431		__stm32_gpio_set(bank, offset, arg);
1432		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1433		break;
1434	case PIN_CONFIG_SKEW_DELAY_INPUT_PS:
1435		arg /= STM32_GPIO_DELAYRL_PS;
1436		ret = stm32_pconf_set_skew_delay(bank, offset, arg, true);
1437		break;
1438	case PIN_CONFIG_SKEW_DELAY_OUTPUT_PS:
1439		arg /= STM32_GPIO_DELAYRL_PS;
1440		ret = stm32_pconf_set_skew_delay(bank, offset, arg, false);
1441		break;
1442	case STM32_GPIO_PIN_CONFIG_IO_SYNC:
1443		ret = stm32_pconf_set_io_sync(bank, offset, arg);
1444		break;
1445	default:
1446		ret = -ENOTSUPP;
1447	}
1448
1449	return ret;
1450}
1451
1452static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1453				 unsigned group,
1454				 unsigned long *config)
1455{
1456	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1457
1458	*config = pctl->groups[group].config;
1459
1460	return 0;
1461}
1462
1463static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1464				 unsigned long *configs, unsigned num_configs)
1465{
1466	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1467	struct stm32_pinctrl_group *g = &pctl->groups[group];
1468	int i, ret;
1469
1470	for (i = 0; i < num_configs; i++) {
1471		mutex_lock(&pctldev->mutex);
1472		ret = stm32_pconf_parse_conf(pctldev, g->pin, configs[i]);
1473		mutex_unlock(&pctldev->mutex);
1474		if (ret < 0)
1475			return ret;
1476
1477		g->config = configs[i];
1478	}
1479
1480	return 0;
1481}
1482
1483static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1484			   unsigned long *configs, unsigned int num_configs)
1485{
1486	int i, ret;
1487
1488	for (i = 0; i < num_configs; i++) {
1489		ret = stm32_pconf_parse_conf(pctldev, pin, configs[i]);
1490		if (ret < 0)
1491			return ret;
1492	}
1493
1494	return 0;
1495}
1496
1497static struct stm32_desc_pin *
1498stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1499				       unsigned int pin_number)
1500{
1501	struct stm32_desc_pin *pins = pctl->pins;
1502	int i;
1503
1504	for (i = 0; i < pctl->npins; i++) {
1505		if (pins->pin.number == pin_number)
1506			return pins;
1507		pins++;
1508	}
1509	return NULL;
1510}
1511
1512static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1513				 struct seq_file *s,
1514				 unsigned int pin)
1515{
1516	struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1517	const struct stm32_desc_pin *pin_desc;
1518	struct pinctrl_gpio_range *range;
1519	struct stm32_gpio_bank *bank;
1520	int offset;
1521	u32 mode, alt, drive, speed, bias;
1522	static const char * const modes[] = {
1523			"input", "output", "alternate", "analog" };
1524	static const char * const speeds[] = {
1525			"low", "medium", "high", "very high" };
1526	static const char * const biasing[] = {
1527			"floating", "pull up", "pull down", "" };
1528	bool val;
1529
1530	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1531	if (!range)
1532		return;
1533
1534	bank = gpiochip_get_data(range->gc);
1535	offset = stm32_gpio_pin(pin);
1536
1537	if (!gpiochip_line_is_valid(range->gc, offset)) {
1538		seq_puts(s, "NO ACCESS");
1539		return;
1540	}
1541
1542	stm32_pmx_get_mode(bank, offset, &mode, &alt);
1543	bias = stm32_pconf_get_bias(bank, offset);
1544
1545	seq_printf(s, "%s ", modes[mode]);
1546
1547	switch (mode) {
1548	/* input */
1549	case 0:
1550		val = stm32_pconf_get(bank, offset, true);
1551		seq_printf(s, "- %s - %s",
1552			   str_high_low(val),
1553			   biasing[bias]);
1554		break;
1555
1556	/* output */
1557	case 1:
1558		drive = stm32_pconf_get_driving(bank, offset);
1559		speed = stm32_pconf_get_speed(bank, offset);
1560		val = stm32_pconf_get(bank, offset, false);
1561		seq_printf(s, "- %s - %s - %s - %s %s",
1562			   str_high_low(val),
1563			   drive ? "open drain" : "push pull",
1564			   biasing[bias],
1565			   speeds[speed], "speed");
1566		break;
1567
1568	/* alternate */
1569	case 2:
1570		drive = stm32_pconf_get_driving(bank, offset);
1571		speed = stm32_pconf_get_speed(bank, offset);
1572		pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1573		if (!pin_desc)
1574			return;
1575
1576		seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1577			   pin_desc->functions[alt + 1].name,
1578			   drive ? "open drain" : "push pull",
1579			   biasing[bias],
1580			   speeds[speed], "speed");
1581		break;
1582
1583	/* analog */
1584	case 3:
1585		break;
1586	}
1587
1588	if (bank->io_sync_control) {
1589		const char *io_sync_str, *skew_dir_str;
1590		u32 skew_delay;
1591
1592		io_sync_str = stm32_pconf_get_io_sync_str(bank, offset);
1593		skew_dir_str = stm32_pconf_get_skew_dir_str(bank, offset);
1594		skew_delay = stm32_pconf_get_skew_delay_val(bank, offset);
1595
1596		if (io_sync_str)
1597			seq_printf(s, " - IO-sync: %s", io_sync_str);
1598
1599		if (skew_delay)
1600			seq_printf(s, " - Skew-delay: %u (%u ps) %s", skew_delay,
1601				   skew_delay * STM32_GPIO_DELAYRL_PS, skew_dir_str);
1602	}
1603}
1604
1605static const struct pinconf_ops stm32_pconf_ops = {
1606	.pin_config_group_get	= stm32_pconf_group_get,
1607	.pin_config_group_set	= stm32_pconf_group_set,
1608	.pin_config_set		= stm32_pconf_set,
1609	.pin_config_dbg_show	= stm32_pconf_dbg_show,
1610};
1611
1612static struct stm32_desc_pin *stm32_pctrl_get_desc_pin_from_gpio(struct stm32_pinctrl *pctl,
1613								 struct stm32_gpio_bank *bank,
1614								 unsigned int offset)
1615{
1616	unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset;
1617	struct stm32_desc_pin *pin_desc;
1618	int i;
1619
1620	/* With few exceptions (e.g. bank 'Z'), pin number matches with pin index in array */
1621	if (stm32_pin_nb < pctl->npins) {
1622		pin_desc = pctl->pins + stm32_pin_nb;
1623		if (pin_desc->pin.number == stm32_pin_nb)
1624			return pin_desc;
1625	}
1626
1627	/* Otherwise, loop all array to find the pin with the right number */
1628	for (i = 0; i < pctl->npins; i++) {
1629		pin_desc = pctl->pins + i;
1630		if (pin_desc->pin.number == stm32_pin_nb)
1631			return pin_desc;
1632	}
1633	return NULL;
1634}
1635
1636static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1637{
1638	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1639	int bank_ioport_nr;
1640	struct pinctrl_gpio_range *range = &bank->range;
1641	struct fwnode_reference_args args;
1642	struct device *dev = pctl->dev;
1643	struct resource res;
1644	int npins = STM32_GPIO_PINS_PER_BANK;
1645	int bank_nr, err, i = 0;
1646	struct stm32_desc_pin *stm32_pin;
1647	char **names;
1648
1649	if (!IS_ERR(bank->rstc))
1650		reset_control_deassert(bank->rstc);
1651
1652	if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1653		return -ENODEV;
1654
1655	bank->base = devm_ioremap_resource(dev, &res);
1656	if (IS_ERR(bank->base))
1657		return PTR_ERR(bank->base);
1658
1659	bank->gpio_chip = stm32_gpio_template;
1660
1661	fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1662
1663	if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1664		bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1665		bank->gpio_chip.base = args.args[1];
1666
1667		/* get the last defined gpio line (offset + nb of pins) */
1668		npins = args.args[0] + args.args[2];
1669		while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1670			npins = max(npins, (int)(args.args[0] + args.args[2]));
1671	} else {
1672		bank_nr = pctl->nbanks;
1673		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1674		range->name = bank->gpio_chip.label;
1675		range->id = bank_nr;
1676		range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1677		range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1678		range->npins = npins;
1679		range->gc = &bank->gpio_chip;
1680		pinctrl_add_gpio_range(pctl->pctl_dev,
1681				       &pctl->banks[bank_nr].range);
1682	}
1683
1684	if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1685		bank_ioport_nr = bank_nr;
1686
1687	bank->gpio_chip.base = -1;
1688
1689	bank->gpio_chip.ngpio = npins;
1690	bank->gpio_chip.fwnode = fwnode;
1691	bank->gpio_chip.parent = dev;
1692	bank->bank_nr = bank_nr;
1693	bank->bank_ioport_nr = bank_ioport_nr;
1694	bank->secure_control = pctl->match_data->secure_control;
1695	bank->io_sync_control = pctl->match_data->io_sync_control;
1696	bank->rif_control = pctl->match_data->rif_control;
1697	spin_lock_init(&bank->lock);
1698
1699	if (pctl->domain) {
1700		/* create irq hierarchical domain */
1701		bank->fwnode = fwnode;
1702
1703		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1704							   bank->fwnode, &stm32_gpio_domain_ops,
1705							   bank);
1706
1707		if (!bank->domain)
1708			return -ENODEV;
1709	}
1710
1711	names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
1712	if (!names)
1713		return -ENOMEM;
1714
1715	for (i = 0; i < npins; i++) {
1716		stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
1717		if (stm32_pin && stm32_pin->pin.name) {
1718			names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
1719			if (!names[i])
1720				return -ENOMEM;
1721		} else {
1722			names[i] = NULL;
1723		}
1724	}
1725
1726	bank->gpio_chip.names = (const char * const *)names;
1727
1728	err = gpiochip_add_data(&bank->gpio_chip, bank);
1729	if (err) {
1730		dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1731		return err;
1732	}
1733
1734	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1735	return 0;
1736}
1737
1738static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1739{
1740	struct device_node *np = pdev->dev.of_node;
1741	struct device_node *parent;
1742	struct irq_domain *domain;
1743
1744	if (!of_property_present(np, "interrupt-parent"))
1745		return NULL;
1746
1747	parent = of_irq_find_parent(np);
1748	if (!parent)
1749		return ERR_PTR(-ENXIO);
1750
1751	domain = irq_find_host(parent);
1752	of_node_put(parent);
1753	if (!domain)
1754		/* domain not registered yet */
1755		return ERR_PTR(-EPROBE_DEFER);
1756
1757	return domain;
1758}
1759
1760static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1761			   struct stm32_pinctrl *pctl)
1762{
1763	struct device_node *np = pdev->dev.of_node;
1764	struct device *dev = &pdev->dev;
1765	struct regmap *rm;
1766	int offset, ret, i;
1767	int mask, mask_width;
1768
1769	pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1770	if (IS_ERR(pctl->regmap))
1771		return PTR_ERR(pctl->regmap);
1772
1773	rm = pctl->regmap;
1774
1775	ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1776	if (ret)
1777		return ret;
1778
1779	ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1780	if (ret)
1781		mask = SYSCFG_IRQMUX_MASK;
1782
1783	mask_width = fls(mask);
1784
1785	for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1786		struct reg_field mux;
1787
1788		mux.reg = offset + (i / 4) * 4;
1789		mux.lsb = (i % 4) * mask_width;
1790		mux.msb = mux.lsb + mask_width - 1;
1791
1792		dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1793			i, mux.reg, mux.lsb, mux.msb);
1794
1795		pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1796		if (IS_ERR(pctl->irqmux[i]))
1797			return PTR_ERR(pctl->irqmux[i]);
1798	}
1799
1800	return 0;
1801}
1802
1803static int stm32_pctrl_build_state(struct platform_device *pdev)
1804{
1805	struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1806	int i;
1807
1808	pctl->ngroups = pctl->npins;
1809
1810	/* Allocate groups */
1811	pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1812				    sizeof(*pctl->groups), GFP_KERNEL);
1813	if (!pctl->groups)
1814		return -ENOMEM;
1815
1816	/* We assume that one pin is one group, use pin name as group name. */
1817	pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1818				       sizeof(*pctl->grp_names), GFP_KERNEL);
1819	if (!pctl->grp_names)
1820		return -ENOMEM;
1821
1822	for (i = 0; i < pctl->npins; i++) {
1823		const struct stm32_desc_pin *pin = pctl->pins + i;
1824		struct stm32_pinctrl_group *group = pctl->groups + i;
1825
1826		group->name = pin->pin.name;
1827		group->pin = pin->pin.number;
1828		pctl->grp_names[i] = pin->pin.name;
1829	}
1830
1831	return 0;
1832}
1833
1834static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1835				       struct stm32_desc_pin *pins)
1836{
1837	const struct stm32_desc_pin *p;
1838	int i, nb_pins_available = 0;
1839
1840	for (i = 0; i < pctl->match_data->npins; i++) {
1841		p = pctl->match_data->pins + i;
1842		if (pctl->pkg && !(pctl->pkg & p->pkg))
1843			continue;
1844		pins->pin = p->pin;
1845		memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1846		       STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1847		pins++;
1848		nb_pins_available++;
1849	}
1850
1851	pctl->npins = nb_pins_available;
1852
1853	return 0;
1854}
1855
1856int stm32_pctl_probe(struct platform_device *pdev)
1857{
1858	const struct stm32_pinctrl_match_data *match_data;
1859	struct fwnode_handle *child;
1860	struct device *dev = &pdev->dev;
1861	struct stm32_pinctrl *pctl;
1862	struct pinctrl_pin_desc *pins;
1863	int i, ret, hwlock_id;
1864	unsigned int banks;
1865
1866	match_data = device_get_match_data(dev);
1867	if (!match_data)
1868		return -EINVAL;
1869
1870	pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1871	if (!pctl)
1872		return -ENOMEM;
1873
1874	platform_set_drvdata(pdev, pctl);
1875
1876	/* check for IRQ controller (may require deferred probe) */
1877	pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1878	if (IS_ERR(pctl->domain))
1879		return PTR_ERR(pctl->domain);
1880	if (!pctl->domain)
1881		dev_warn(dev, "pinctrl without interrupt support\n");
1882
1883	/* hwspinlock is optional */
1884	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1885	if (hwlock_id < 0) {
1886		if (hwlock_id == -EPROBE_DEFER)
1887			return hwlock_id;
1888	} else {
1889		pctl->hwlock = devm_hwspin_lock_request_specific(dev, hwlock_id);
1890	}
1891
1892	spin_lock_init(&pctl->irqmux_lock);
1893
1894	pctl->dev = dev;
1895	pctl->match_data = match_data;
1896
1897	/*  get optional package information */
1898	if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1899		dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1900
1901	pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1902				  sizeof(*pctl->pins), GFP_KERNEL);
1903	if (!pctl->pins)
1904		return -ENOMEM;
1905
1906	ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1907	if (ret)
1908		return ret;
1909
1910	ret = stm32_pctrl_build_state(pdev);
1911	if (ret) {
1912		dev_err(dev, "build state failed: %d\n", ret);
1913		return -EINVAL;
1914	}
1915
1916	if (pctl->domain) {
1917		ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1918		if (ret)
1919			return ret;
1920	}
1921
1922	pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1923			    GFP_KERNEL);
1924	if (!pins)
1925		return -ENOMEM;
1926
1927	for (i = 0; i < pctl->npins; i++)
1928		pins[i] = pctl->pins[i].pin;
1929
1930	pctl->pctl_desc.name = dev_name(&pdev->dev);
1931	pctl->pctl_desc.owner = THIS_MODULE;
1932	pctl->pctl_desc.pins = pins;
1933	pctl->pctl_desc.npins = pctl->npins;
1934	pctl->pctl_desc.link_consumers = true;
1935	pctl->pctl_desc.confops = &stm32_pconf_ops;
1936	pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1937	pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1938	pctl->pctl_desc.num_custom_params = ARRAY_SIZE(stm32_gpio_bindings);
1939	pctl->pctl_desc.custom_params = stm32_gpio_bindings;
1940	pctl->dev = &pdev->dev;
1941
1942	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1943					       pctl);
1944
1945	if (IS_ERR(pctl->pctl_dev)) {
1946		dev_err(&pdev->dev, "Failed pinctrl registration\n");
1947		return PTR_ERR(pctl->pctl_dev);
1948	}
1949
1950	banks = gpiochip_node_count(dev);
1951	if (!banks) {
1952		dev_err(dev, "at least one GPIO bank is required\n");
1953		return -EINVAL;
1954	}
1955	pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1956			GFP_KERNEL);
1957	if (!pctl->banks)
1958		return -ENOMEM;
1959
1960	pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks),
1961				  GFP_KERNEL);
1962	if (!pctl->clks)
1963		return -ENOMEM;
1964
1965	i = 0;
1966	for_each_gpiochip_node(dev, child) {
1967		struct stm32_gpio_bank *bank = &pctl->banks[i];
1968		struct device_node *np = to_of_node(child);
1969
1970		bank->rstc = of_reset_control_get_exclusive(np, NULL);
1971		if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1972			fwnode_handle_put(child);
1973			return -EPROBE_DEFER;
1974		}
1975
1976		pctl->clks[i].clk = of_clk_get_by_name(np, NULL);
1977		if (IS_ERR(pctl->clks[i].clk)) {
1978			fwnode_handle_put(child);
1979			return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk),
1980					     "failed to get clk\n");
1981		}
1982		pctl->clks[i].id = "pctl";
1983		i++;
1984	}
1985
1986	ret = clk_bulk_prepare_enable(banks, pctl->clks);
1987	if (ret) {
1988		dev_err(dev, "failed to prepare_enable clk (%d)\n", ret);
1989		return ret;
1990	}
1991
1992	for_each_gpiochip_node(dev, child) {
1993		ret = stm32_gpiolib_register_bank(pctl, child);
1994		if (ret) {
1995			fwnode_handle_put(child);
1996			goto err_register;
1997		}
1998
1999		pctl->nbanks++;
2000	}
2001
2002	dev_info(dev, "Pinctrl STM32 initialized\n");
2003
2004	return 0;
2005err_register:
2006	for (i = 0; i < pctl->nbanks; i++) {
2007		struct stm32_gpio_bank *bank = &pctl->banks[i];
2008
2009		gpiochip_remove(&bank->gpio_chip);
2010	}
2011
2012	clk_bulk_disable_unprepare(banks, pctl->clks);
2013	return ret;
2014}
2015EXPORT_SYMBOL(stm32_pctl_probe);
2016
2017static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
2018					struct stm32_pinctrl *pctl, u32 pin)
2019{
2020	const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
2021	u32 mode, offset = stm32_gpio_pin(pin);
2022	struct pinctrl_gpio_range *range;
2023	struct stm32_gpio_bank *bank;
2024	bool pin_is_irq;
2025	int ret;
2026
2027	range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
2028	if (!range)
2029		return 0;
2030
2031	bank = gpiochip_get_data(range->gc);
2032
2033	if (!gpiochip_line_is_valid(range->gc, offset))
2034		return 0;
2035
2036	if (bank->rif_control && !stm32_gpio_rif_acquire_semaphore(bank, offset)) {
2037		dev_err(pctl->dev, "pin %d not available.\n", offset);
2038		return -EACCES;
2039	}
2040
2041	pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
2042
2043	if (!desc || (!pin_is_irq && !desc->gpio_owner))
2044		return 0;
2045
2046	mode = bank->pin_backup[offset].mode;
2047	ret = stm32_pmx_set_mode(bank, offset, mode, bank->pin_backup[offset].alt);
2048	if (ret)
2049		return ret;
2050
2051	if (mode == 1)
2052		__stm32_gpio_set(bank, offset, bank->pin_backup[offset].value);
2053
2054	ret = stm32_pconf_set_driving(bank, offset, bank->pin_backup[offset].drive);
2055	if (ret)
2056		return ret;
2057
2058	ret = stm32_pconf_set_speed(bank, offset, bank->pin_backup[offset].speed);
2059	if (ret)
2060		return ret;
2061
2062	ret = stm32_pconf_set_bias(bank, offset, bank->pin_backup[offset].bias);
2063	if (ret)
2064		return ret;
2065
2066	if (bank->io_sync_control) {
2067		bool is_input = bank->pin_backup[offset].advcfg & STM32_GPIO_ADVCFGR_DLYPATH_MASK;
2068
2069		ret = stm32_pconf_set_skew_delay(bank, offset,
2070						 bank->pin_backup[offset].skew_delay,
2071						 is_input);
2072		if (ret)
2073			return ret;
2074
2075		ret = stm32_pconf_set_advcfgr(bank, offset, STM32_GPIO_ADVCFGR_IO_SYNC_MASK,
2076					      bank->pin_backup[offset].advcfg);
2077		if (ret)
2078			return ret;
2079	}
2080
2081	if (pin_is_irq)
2082		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
2083
2084	return 0;
2085}
2086
2087int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
2088{
2089	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
2090
2091	clk_bulk_disable(pctl->nbanks, pctl->clks);
2092
2093	return 0;
2094}
2095EXPORT_SYMBOL(stm32_pinctrl_suspend);
2096
2097int __maybe_unused stm32_pinctrl_resume(struct device *dev)
2098{
2099	struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
2100	struct stm32_pinctrl_group *g = pctl->groups;
2101	int i, ret;
2102
2103	ret = clk_bulk_enable(pctl->nbanks, pctl->clks);
2104	if (ret)
2105		return ret;
2106
2107	for (i = 0; i < pctl->ngroups; i++, g++)
2108		stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
2109
2110	return 0;
2111}
2112EXPORT_SYMBOL(stm32_pinctrl_resume);
2113
2114MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@foss.st.com>");
2115MODULE_DESCRIPTION("STM32 core pinctrl driver");
2116MODULE_LICENSE("GPL");