pinctrl-starfive-jh7110-sys.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
  4 *
  5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
  6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
  7 */
  8
  9#include <linux/bits.h>
 10#include <linux/clk.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/io.h>
 13#include <linux/mod_devicetable.h>
 14#include <linux/module.h>
 15#include <linux/mutex.h>
 16#include <linux/platform_device.h>
 17#include <linux/reset.h>
 18#include <linux/spinlock.h>
 19
 20#include <linux/pinctrl/pinctrl.h>
 21#include <linux/pinctrl/pinmux.h>
 22
 23#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
 24
 25#include "../core.h"
 26#include "../pinctrl-utils.h"
 27#include "../pinmux.h"
 28#include "../pinconf.h"
 29#include "pinctrl-starfive-jh7110.h"
 30
 31#define JH7110_SYS_NGPIO		64
 32
 33#define JH7110_SYS_REGS_NUM		174
 34
 35/* registers */
 36#define JH7110_SYS_DOEN			0x000
 37#define JH7110_SYS_DOUT			0x040
 38#define JH7110_SYS_GPI			0x080
 39#define JH7110_SYS_GPIOIN		0x118
 40
 41#define JH7110_SYS_GPIOEN		0x0dc
 42#define JH7110_SYS_GPIOIS0		0x0e0
 43#define JH7110_SYS_GPIOIS1		0x0e4
 44#define JH7110_SYS_GPIOIC0		0x0e8
 45#define JH7110_SYS_GPIOIC1		0x0ec
 46#define JH7110_SYS_GPIOIBE0		0x0f0
 47#define JH7110_SYS_GPIOIBE1		0x0f4
 48#define JH7110_SYS_GPIOIEV0		0x0f8
 49#define JH7110_SYS_GPIOIEV1		0x0fc
 50#define JH7110_SYS_GPIOIE0		0x100
 51#define JH7110_SYS_GPIOIE1		0x104
 52#define JH7110_SYS_GPIORIS0		0x108
 53#define JH7110_SYS_GPIORIS1		0x10c
 54#define JH7110_SYS_GPIOMIS0		0x110
 55#define JH7110_SYS_GPIOMIS1		0x114
 56
 57#define JH7110_SYS_GPO_PDA_0_74_CFG	0x120
 58#define JH7110_SYS_GPO_PDA_89_94_CFG	0x284
 59
 60static const struct pinctrl_pin_desc jh7110_sys_pins[] = {
 61	PINCTRL_PIN(PAD_GPIO0,		"GPIO0"),
 62	PINCTRL_PIN(PAD_GPIO1,		"GPIO1"),
 63	PINCTRL_PIN(PAD_GPIO2,		"GPIO2"),
 64	PINCTRL_PIN(PAD_GPIO3,		"GPIO3"),
 65	PINCTRL_PIN(PAD_GPIO4,		"GPIO4"),
 66	PINCTRL_PIN(PAD_GPIO5,		"GPIO5"),
 67	PINCTRL_PIN(PAD_GPIO6,		"GPIO6"),
 68	PINCTRL_PIN(PAD_GPIO7,		"GPIO7"),
 69	PINCTRL_PIN(PAD_GPIO8,		"GPIO8"),
 70	PINCTRL_PIN(PAD_GPIO9,		"GPIO9"),
 71	PINCTRL_PIN(PAD_GPIO10,		"GPIO10"),
 72	PINCTRL_PIN(PAD_GPIO11,		"GPIO11"),
 73	PINCTRL_PIN(PAD_GPIO12,		"GPIO12"),
 74	PINCTRL_PIN(PAD_GPIO13,		"GPIO13"),
 75	PINCTRL_PIN(PAD_GPIO14,		"GPIO14"),
 76	PINCTRL_PIN(PAD_GPIO15,		"GPIO15"),
 77	PINCTRL_PIN(PAD_GPIO16,		"GPIO16"),
 78	PINCTRL_PIN(PAD_GPIO17,		"GPIO17"),
 79	PINCTRL_PIN(PAD_GPIO18,		"GPIO18"),
 80	PINCTRL_PIN(PAD_GPIO19,		"GPIO19"),
 81	PINCTRL_PIN(PAD_GPIO20,		"GPIO20"),
 82	PINCTRL_PIN(PAD_GPIO21,		"GPIO21"),
 83	PINCTRL_PIN(PAD_GPIO22,		"GPIO22"),
 84	PINCTRL_PIN(PAD_GPIO23,		"GPIO23"),
 85	PINCTRL_PIN(PAD_GPIO24,		"GPIO24"),
 86	PINCTRL_PIN(PAD_GPIO25,		"GPIO25"),
 87	PINCTRL_PIN(PAD_GPIO26,		"GPIO26"),
 88	PINCTRL_PIN(PAD_GPIO27,		"GPIO27"),
 89	PINCTRL_PIN(PAD_GPIO28,		"GPIO28"),
 90	PINCTRL_PIN(PAD_GPIO29,		"GPIO29"),
 91	PINCTRL_PIN(PAD_GPIO30,		"GPIO30"),
 92	PINCTRL_PIN(PAD_GPIO31,		"GPIO31"),
 93	PINCTRL_PIN(PAD_GPIO32,		"GPIO32"),
 94	PINCTRL_PIN(PAD_GPIO33,		"GPIO33"),
 95	PINCTRL_PIN(PAD_GPIO34,		"GPIO34"),
 96	PINCTRL_PIN(PAD_GPIO35,		"GPIO35"),
 97	PINCTRL_PIN(PAD_GPIO36,		"GPIO36"),
 98	PINCTRL_PIN(PAD_GPIO37,		"GPIO37"),
 99	PINCTRL_PIN(PAD_GPIO38,		"GPIO38"),
100	PINCTRL_PIN(PAD_GPIO39,		"GPIO39"),
101	PINCTRL_PIN(PAD_GPIO40,		"GPIO40"),
102	PINCTRL_PIN(PAD_GPIO41,		"GPIO41"),
103	PINCTRL_PIN(PAD_GPIO42,		"GPIO42"),
104	PINCTRL_PIN(PAD_GPIO43,		"GPIO43"),
105	PINCTRL_PIN(PAD_GPIO44,		"GPIO44"),
106	PINCTRL_PIN(PAD_GPIO45,		"GPIO45"),
107	PINCTRL_PIN(PAD_GPIO46,		"GPIO46"),
108	PINCTRL_PIN(PAD_GPIO47,		"GPIO47"),
109	PINCTRL_PIN(PAD_GPIO48,		"GPIO48"),
110	PINCTRL_PIN(PAD_GPIO49,		"GPIO49"),
111	PINCTRL_PIN(PAD_GPIO50,		"GPIO50"),
112	PINCTRL_PIN(PAD_GPIO51,		"GPIO51"),
113	PINCTRL_PIN(PAD_GPIO52,		"GPIO52"),
114	PINCTRL_PIN(PAD_GPIO53,		"GPIO53"),
115	PINCTRL_PIN(PAD_GPIO54,		"GPIO54"),
116	PINCTRL_PIN(PAD_GPIO55,		"GPIO55"),
117	PINCTRL_PIN(PAD_GPIO56,		"GPIO56"),
118	PINCTRL_PIN(PAD_GPIO57,		"GPIO57"),
119	PINCTRL_PIN(PAD_GPIO58,		"GPIO58"),
120	PINCTRL_PIN(PAD_GPIO59,		"GPIO59"),
121	PINCTRL_PIN(PAD_GPIO60,		"GPIO60"),
122	PINCTRL_PIN(PAD_GPIO61,		"GPIO61"),
123	PINCTRL_PIN(PAD_GPIO62,		"GPIO62"),
124	PINCTRL_PIN(PAD_GPIO63,		"GPIO63"),
125	PINCTRL_PIN(PAD_SD0_CLK,	"SD0_CLK"),
126	PINCTRL_PIN(PAD_SD0_CMD,	"SD0_CMD"),
127	PINCTRL_PIN(PAD_SD0_DATA0,	"SD0_DATA0"),
128	PINCTRL_PIN(PAD_SD0_DATA1,	"SD0_DATA1"),
129	PINCTRL_PIN(PAD_SD0_DATA2,	"SD0_DATA2"),
130	PINCTRL_PIN(PAD_SD0_DATA3,	"SD0_DATA3"),
131	PINCTRL_PIN(PAD_SD0_DATA4,	"SD0_DATA4"),
132	PINCTRL_PIN(PAD_SD0_DATA5,	"SD0_DATA5"),
133	PINCTRL_PIN(PAD_SD0_DATA6,	"SD0_DATA6"),
134	PINCTRL_PIN(PAD_SD0_DATA7,	"SD0_DATA7"),
135	PINCTRL_PIN(PAD_SD0_STRB,	"SD0_STRB"),
136	PINCTRL_PIN(PAD_GMAC1_MDC,	"GMAC1_MDC"),
137	PINCTRL_PIN(PAD_GMAC1_MDIO,	"GMAC1_MDIO"),
138	PINCTRL_PIN(PAD_GMAC1_RXD0,	"GMAC1_RXD0"),
139	PINCTRL_PIN(PAD_GMAC1_RXD1,	"GMAC1_RXD1"),
140	PINCTRL_PIN(PAD_GMAC1_RXD2,	"GMAC1_RXD2"),
141	PINCTRL_PIN(PAD_GMAC1_RXD3,	"GMAC1_RXD3"),
142	PINCTRL_PIN(PAD_GMAC1_RXDV,	"GMAC1_RXDV"),
143	PINCTRL_PIN(PAD_GMAC1_RXC,	"GMAC1_RXC"),
144	PINCTRL_PIN(PAD_GMAC1_TXD0,	"GMAC1_TXD0"),
145	PINCTRL_PIN(PAD_GMAC1_TXD1,	"GMAC1_TXD1"),
146	PINCTRL_PIN(PAD_GMAC1_TXD2,	"GMAC1_TXD2"),
147	PINCTRL_PIN(PAD_GMAC1_TXD3,	"GMAC1_TXD3"),
148	PINCTRL_PIN(PAD_GMAC1_TXEN,	"GMAC1_TXEN"),
149	PINCTRL_PIN(PAD_GMAC1_TXC,	"GMAC1_TXC"),
150	PINCTRL_PIN(PAD_QSPI_SCLK,	"QSPI_SCLK"),
151	PINCTRL_PIN(PAD_QSPI_CS0,	"QSPI_CS0"),
152	PINCTRL_PIN(PAD_QSPI_DATA0,	"QSPI_DATA0"),
153	PINCTRL_PIN(PAD_QSPI_DATA1,	"QSPI_DATA1"),
154	PINCTRL_PIN(PAD_QSPI_DATA2,	"QSPI_DATA2"),
155	PINCTRL_PIN(PAD_QSPI_DATA3,	"QSPI_DATA3"),
156};
157
158struct jh7110_func_sel {
159	u16 offset;
160	u8 shift;
161	u8 max;
162};
163
164static const struct jh7110_func_sel
165	jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
166	[PAD_GMAC1_RXC] = { 0x29c,  0, 1 },
167	[PAD_GPIO10]    = { 0x29c,  2, 3 },
168	[PAD_GPIO11]    = { 0x29c,  5, 3 },
169	[PAD_GPIO12]    = { 0x29c,  8, 3 },
170	[PAD_GPIO13]    = { 0x29c, 11, 3 },
171	[PAD_GPIO14]    = { 0x29c, 14, 3 },
172	[PAD_GPIO15]    = { 0x29c, 17, 3 },
173	[PAD_GPIO16]    = { 0x29c, 20, 3 },
174	[PAD_GPIO17]    = { 0x29c, 23, 3 },
175	[PAD_GPIO18]    = { 0x29c, 26, 3 },
176	[PAD_GPIO19]    = { 0x29c, 29, 3 },
177
178	[PAD_GPIO20]    = { 0x2a0,  0, 3 },
179	[PAD_GPIO21]    = { 0x2a0,  3, 3 },
180	[PAD_GPIO22]    = { 0x2a0,  6, 3 },
181	[PAD_GPIO23]    = { 0x2a0,  9, 3 },
182	[PAD_GPIO24]    = { 0x2a0, 12, 3 },
183	[PAD_GPIO25]    = { 0x2a0, 15, 3 },
184	[PAD_GPIO26]    = { 0x2a0, 18, 3 },
185	[PAD_GPIO27]    = { 0x2a0, 21, 3 },
186	[PAD_GPIO28]    = { 0x2a0, 24, 3 },
187	[PAD_GPIO29]    = { 0x2a0, 27, 3 },
188
189	[PAD_GPIO30]    = { 0x2a4,  0, 3 },
190	[PAD_GPIO31]    = { 0x2a4,  3, 3 },
191	[PAD_GPIO32]    = { 0x2a4,  6, 3 },
192	[PAD_GPIO33]    = { 0x2a4,  9, 3 },
193	[PAD_GPIO34]    = { 0x2a4, 12, 3 },
194	[PAD_GPIO35]    = { 0x2a4, 15, 3 },
195	[PAD_GPIO36]    = { 0x2a4, 17, 3 },
196	[PAD_GPIO37]    = { 0x2a4, 20, 3 },
197	[PAD_GPIO38]    = { 0x2a4, 23, 3 },
198	[PAD_GPIO39]    = { 0x2a4, 26, 3 },
199	[PAD_GPIO40]    = { 0x2a4, 29, 3 },
200
201	[PAD_GPIO41]    = { 0x2a8,  0, 3 },
202	[PAD_GPIO42]    = { 0x2a8,  3, 3 },
203	[PAD_GPIO43]    = { 0x2a8,  6, 3 },
204	[PAD_GPIO44]    = { 0x2a8,  9, 3 },
205	[PAD_GPIO45]    = { 0x2a8, 12, 3 },
206	[PAD_GPIO46]    = { 0x2a8, 15, 3 },
207	[PAD_GPIO47]    = { 0x2a8, 18, 3 },
208	[PAD_GPIO48]    = { 0x2a8, 21, 3 },
209	[PAD_GPIO49]    = { 0x2a8, 24, 3 },
210	[PAD_GPIO50]    = { 0x2a8, 27, 3 },
211	[PAD_GPIO51]    = { 0x2a8, 30, 3 },
212
213	[PAD_GPIO52]    = { 0x2ac,  0, 3 },
214	[PAD_GPIO53]    = { 0x2ac,  2, 3 },
215	[PAD_GPIO54]    = { 0x2ac,  4, 3 },
216	[PAD_GPIO55]    = { 0x2ac,  6, 3 },
217	[PAD_GPIO56]    = { 0x2ac,  9, 3 },
218	[PAD_GPIO57]    = { 0x2ac, 12, 3 },
219	[PAD_GPIO58]    = { 0x2ac, 15, 3 },
220	[PAD_GPIO59]    = { 0x2ac, 18, 3 },
221	[PAD_GPIO60]    = { 0x2ac, 21, 3 },
222	[PAD_GPIO61]    = { 0x2ac, 24, 3 },
223	[PAD_GPIO62]    = { 0x2ac, 27, 3 },
224	[PAD_GPIO63]    = { 0x2ac, 30, 3 },
225
226	[PAD_GPIO6]     = { 0x2b0,  0, 3 },
227	[PAD_GPIO7]     = { 0x2b0,  2, 3 },
228	[PAD_GPIO8]     = { 0x2b0,  5, 3 },
229	[PAD_GPIO9]     = { 0x2b0,  8, 3 },
230};
231
232struct jh7110_vin_group_sel {
233	u16 offset;
234	u8 shift;
235	u8 group;
236};
237
238static const struct jh7110_vin_group_sel
239	jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
240	[PAD_GPIO6]     = { 0x2b4, 21, 0 },
241	[PAD_GPIO7]     = { 0x2b4, 18, 0 },
242	[PAD_GPIO8]     = { 0x2b4, 15, 0 },
243	[PAD_GPIO9]     = { 0x2b0, 11, 0 },
244	[PAD_GPIO10]    = { 0x2b0, 20, 0 },
245	[PAD_GPIO11]    = { 0x2b0, 23, 0 },
246	[PAD_GPIO12]    = { 0x2b0, 26, 0 },
247	[PAD_GPIO13]    = { 0x2b0, 29, 0 },
248	[PAD_GPIO14]    = { 0x2b4,  0, 0 },
249	[PAD_GPIO15]    = { 0x2b4,  3, 0 },
250	[PAD_GPIO16]    = { 0x2b4,  6, 0 },
251	[PAD_GPIO17]    = { 0x2b4,  9, 0 },
252	[PAD_GPIO18]    = { 0x2b4, 12, 0 },
253	[PAD_GPIO19]    = { 0x2b0, 14, 0 },
254	[PAD_GPIO20]    = { 0x2b0, 17, 0 },
255
256	[PAD_GPIO21]    = { 0x2b4, 21, 1 },
257	[PAD_GPIO22]    = { 0x2b4, 18, 1 },
258	[PAD_GPIO23]    = { 0x2b4, 15, 1 },
259	[PAD_GPIO24]    = { 0x2b0, 11, 1 },
260	[PAD_GPIO25]    = { 0x2b0, 20, 1 },
261	[PAD_GPIO26]    = { 0x2b0, 23, 1 },
262	[PAD_GPIO27]    = { 0x2b0, 26, 1 },
263	[PAD_GPIO28]    = { 0x2b0, 29, 1 },
264	[PAD_GPIO29]    = { 0x2b4,  0, 1 },
265	[PAD_GPIO30]    = { 0x2b4,  3, 1 },
266	[PAD_GPIO31]    = { 0x2b4,  6, 1 },
267	[PAD_GPIO32]    = { 0x2b4,  9, 1 },
268	[PAD_GPIO33]    = { 0x2b4, 12, 1 },
269	[PAD_GPIO34]    = { 0x2b0, 14, 1 },
270	[PAD_GPIO35]    = { 0x2b0, 17, 1 },
271
272	[PAD_GPIO36]    = { 0x2b4, 21, 2 },
273	[PAD_GPIO37]    = { 0x2b4, 18, 2 },
274	[PAD_GPIO38]    = { 0x2b4, 15, 2 },
275	[PAD_GPIO39]    = { 0x2b0, 11, 2 },
276	[PAD_GPIO40]    = { 0x2b0, 20, 2 },
277	[PAD_GPIO41]    = { 0x2b0, 23, 2 },
278	[PAD_GPIO42]    = { 0x2b0, 26, 2 },
279	[PAD_GPIO43]    = { 0x2b0, 29, 2 },
280	[PAD_GPIO44]    = { 0x2b4,  0, 2 },
281	[PAD_GPIO45]    = { 0x2b4,  3, 2 },
282	[PAD_GPIO46]    = { 0x2b4,  6, 2 },
283	[PAD_GPIO47]    = { 0x2b4,  9, 2 },
284	[PAD_GPIO48]    = { 0x2b4, 12, 2 },
285	[PAD_GPIO49]    = { 0x2b0, 14, 2 },
286	[PAD_GPIO50]    = { 0x2b0, 17, 2 },
287};
288
289static void jh7110_set_function(struct jh7110_pinctrl *sfp,
290				unsigned int pin, u32 func)
291{
292	const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
293	unsigned long flags;
294	void __iomem *reg;
295	u32 mask;
296
297	if (!fs->offset)
298		return;
299
300	if (func > fs->max)
301		return;
302
303	reg = sfp->base + fs->offset;
304	func = func << fs->shift;
305	mask = 0x3U << fs->shift;
306
307	raw_spin_lock_irqsave(&sfp->lock, flags);
308	func |= readl_relaxed(reg) & ~mask;
309	writel_relaxed(func, reg);
310	raw_spin_unlock_irqrestore(&sfp->lock, flags);
311}
312
313static void jh7110_set_vin_group(struct jh7110_pinctrl *sfp,
314				 unsigned int pin)
315{
316	const struct jh7110_vin_group_sel *gs = &jh7110_sys_vin_group_sel[pin];
317	unsigned long flags;
318	void __iomem *reg;
319	u32 mask;
320	u32 grp;
321
322	if (!gs->offset)
323		return;
324
325	reg = sfp->base + gs->offset;
326	grp = gs->group << gs->shift;
327	mask = 0x3U << gs->shift;
328
329	raw_spin_lock_irqsave(&sfp->lock, flags);
330	grp |= readl_relaxed(reg) & ~mask;
331	writel_relaxed(grp, reg);
332	raw_spin_unlock_irqrestore(&sfp->lock, flags);
333}
334
335static int jh7110_sys_set_one_pin_mux(struct jh7110_pinctrl *sfp,
336				      unsigned int pin,
337				      unsigned int din, u32 dout,
338				      u32 doen, u32 func)
339{
340	if (pin < sfp->gc.ngpio && func == 0)
341		jh7110_set_gpiomux(sfp, pin, din, dout, doen);
342
343	jh7110_set_function(sfp, pin, func);
344
345	if (pin < sfp->gc.ngpio && func == 2)
346		jh7110_set_vin_group(sfp, pin);
347
348	return 0;
349}
350
351static int jh7110_sys_get_padcfg_base(struct jh7110_pinctrl *sfp,
352				      unsigned int pin)
353{
354	if (pin < PAD_GMAC1_MDC)
355		return JH7110_SYS_GPO_PDA_0_74_CFG;
356	else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
357		return JH7110_SYS_GPO_PDA_89_94_CFG;
358	else
359		return -1;
360}
361
362static void jh7110_sys_irq_handler(struct irq_desc *desc)
363{
364	struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
365	struct irq_chip *chip = irq_desc_get_chip(desc);
366	unsigned long mis;
367	unsigned int pin;
368
369	chained_irq_enter(chip, desc);
370
371	mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS0);
372	for_each_set_bit(pin, &mis, 32)
373		generic_handle_domain_irq(sfp->gc.irq.domain, pin);
374
375	mis = readl_relaxed(sfp->base + JH7110_SYS_GPIOMIS1);
376	for_each_set_bit(pin, &mis, 32)
377		generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
378
379	chained_irq_exit(chip, desc);
380}
381
382static int jh7110_sys_init_hw(struct gpio_chip *gc)
383{
384	struct jh7110_pinctrl *sfp = container_of(gc,
385			struct jh7110_pinctrl, gc);
386
387	/* mask all GPIO interrupts */
388	writel(0U, sfp->base + JH7110_SYS_GPIOIE0);
389	writel(0U, sfp->base + JH7110_SYS_GPIOIE1);
390	/* clear edge interrupt flags */
391	writel(~0U, sfp->base + JH7110_SYS_GPIOIC0);
392	writel(~0U, sfp->base + JH7110_SYS_GPIOIC1);
393	/* enable GPIO interrupts */
394	writel(1U, sfp->base + JH7110_SYS_GPIOEN);
395	return 0;
396}
397
398static const struct jh7110_gpio_irq_reg jh7110_sys_irq_reg = {
399	.is_reg_base	= JH7110_SYS_GPIOIS0,
400	.ic_reg_base	= JH7110_SYS_GPIOIC0,
401	.ibe_reg_base	= JH7110_SYS_GPIOIBE0,
402	.iev_reg_base	= JH7110_SYS_GPIOIEV0,
403	.ie_reg_base	= JH7110_SYS_GPIOIE0,
404	.ris_reg_base	= JH7110_SYS_GPIORIS0,
405	.mis_reg_base	= JH7110_SYS_GPIOMIS0,
406};
407
408static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = {
409	.pins		= jh7110_sys_pins,
410	.npins		= ARRAY_SIZE(jh7110_sys_pins),
411	.ngpios		= JH7110_SYS_NGPIO,
412	.dout_reg_base	= JH7110_SYS_DOUT,
413	.dout_mask	= GENMASK(6, 0),
414	.doen_reg_base	= JH7110_SYS_DOEN,
415	.doen_mask	= GENMASK(5, 0),
416	.gpi_reg_base	= JH7110_SYS_GPI,
417	.gpi_mask	= GENMASK(6, 0),
418	.gpioin_reg_base	   = JH7110_SYS_GPIOIN,
419	.irq_reg		   = &jh7110_sys_irq_reg,
420	.nsaved_regs		   = JH7110_SYS_REGS_NUM,
421	.jh7110_set_one_pin_mux  = jh7110_sys_set_one_pin_mux,
422	.jh7110_get_padcfg_base  = jh7110_sys_get_padcfg_base,
423	.jh7110_gpio_irq_handler = jh7110_sys_irq_handler,
424	.jh7110_gpio_init_hw	 = jh7110_sys_init_hw,
425};
426
427static const struct of_device_id jh7110_sys_pinctrl_of_match[] = {
428	{
429		.compatible = "starfive,jh7110-sys-pinctrl",
430		.data = &jh7110_sys_pinctrl_info,
431	},
432	{ /* sentinel */ }
433};
434MODULE_DEVICE_TABLE(of, jh7110_sys_pinctrl_of_match);
435
436static struct platform_driver jh7110_sys_pinctrl_driver = {
437	.probe = jh7110_pinctrl_probe,
438	.driver = {
439		.name = "starfive-jh7110-sys-pinctrl",
440		.of_match_table = jh7110_sys_pinctrl_of_match,
441		.pm = pm_sleep_ptr(&jh7110_pinctrl_pm_ops),
442	},
443};
444module_platform_driver(jh7110_sys_pinctrl_driver);
445
446MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC sys controller");
447MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
448MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
449MODULE_LICENSE("GPL");