pinctrl-starfive-jh7110-aon.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
  4 *
  5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
  6 */
  7
  8#include <linux/err.h>
  9#include <linux/gpio/driver.h>
 10#include <linux/init.h>
 11#include <linux/interrupt.h>
 12#include <linux/io.h>
 13#include <linux/mod_devicetable.h>
 14#include <linux/module.h>
 15#include <linux/pinctrl/pinconf.h>
 16#include <linux/pinctrl/pinconf-generic.h>
 17#include <linux/pinctrl/pinctrl.h>
 18#include <linux/pinctrl/pinmux.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/regmap.h>
 22#include <linux/slab.h>
 23
 24#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
 25
 26#include "../core.h"
 27#include "../pinconf.h"
 28#include "../pinmux.h"
 29#include "pinctrl-starfive-jh7110.h"
 30
 31#define JH7110_AON_NGPIO		4
 32
 33#define JH7110_AON_REGS_NUM		37
 34
 35/* registers */
 36#define JH7110_AON_DOEN			0x0
 37#define JH7110_AON_DOUT			0x4
 38#define JH7110_AON_GPI			0x8
 39#define JH7110_AON_GPIOIN		0x2c
 40
 41#define JH7110_AON_GPIOEN		0xc
 42#define JH7110_AON_GPIOIS		0x10
 43#define JH7110_AON_GPIOIC		0x14
 44#define JH7110_AON_GPIOIBE		0x18
 45#define JH7110_AON_GPIOIEV		0x1c
 46#define JH7110_AON_GPIOIE		0x20
 47#define JH7110_AON_GPIORIS		0x28
 48#define JH7110_AON_GPIOMIS		0x28
 49
 50#define JH7110_AON_GPO_PDA_0_5_CFG	0x30
 51
 52static const struct pinctrl_pin_desc jh7110_aon_pins[] = {
 53	PINCTRL_PIN(PAD_TESTEN,		"TESTEN"),
 54	PINCTRL_PIN(PAD_RGPIO0,		"RGPIO0"),
 55	PINCTRL_PIN(PAD_RGPIO1,		"RGPIO1"),
 56	PINCTRL_PIN(PAD_RGPIO2,		"RGPIO2"),
 57	PINCTRL_PIN(PAD_RGPIO3,		"RGPIO3"),
 58	PINCTRL_PIN(PAD_RSTN,		"RSTN"),
 59	PINCTRL_PIN(PAD_GMAC0_MDC,	"GMAC0_MDC"),
 60	PINCTRL_PIN(PAD_GMAC0_MDIO,	"GMAC0_MDIO"),
 61	PINCTRL_PIN(PAD_GMAC0_RXD0,	"GMAC0_RXD0"),
 62	PINCTRL_PIN(PAD_GMAC0_RXD1,	"GMAC0_RXD1"),
 63	PINCTRL_PIN(PAD_GMAC0_RXD2,	"GMAC0_RXD2"),
 64	PINCTRL_PIN(PAD_GMAC0_RXD3,	"GMAC0_RXD3"),
 65	PINCTRL_PIN(PAD_GMAC0_RXDV,	"GMAC0_RXDV"),
 66	PINCTRL_PIN(PAD_GMAC0_RXC,	"GMAC0_RXC"),
 67	PINCTRL_PIN(PAD_GMAC0_TXD0,	"GMAC0_TXD0"),
 68	PINCTRL_PIN(PAD_GMAC0_TXD1,	"GMAC0_TXD1"),
 69	PINCTRL_PIN(PAD_GMAC0_TXD2,	"GMAC0_TXD2"),
 70	PINCTRL_PIN(PAD_GMAC0_TXD3,	"GMAC0_TXD3"),
 71	PINCTRL_PIN(PAD_GMAC0_TXEN,	"GMAC0_TXEN"),
 72	PINCTRL_PIN(PAD_GMAC0_TXC,	"GMAC0_TXC"),
 73};
 74
 75static int jh7110_aon_set_one_pin_mux(struct jh7110_pinctrl *sfp,
 76				      unsigned int pin,
 77				      unsigned int din, u32 dout,
 78				      u32 doen, u32 func)
 79{
 80	if (pin < sfp->gc.ngpio && func == 0)
 81		jh7110_set_gpiomux(sfp, pin, din, dout, doen);
 82
 83	return 0;
 84}
 85
 86static int jh7110_aon_get_padcfg_base(struct jh7110_pinctrl *sfp,
 87				      unsigned int pin)
 88{
 89	if (pin < PAD_GMAC0_MDC)
 90		return JH7110_AON_GPO_PDA_0_5_CFG;
 91
 92	return -1;
 93}
 94
 95static void jh7110_aon_irq_handler(struct irq_desc *desc)
 96{
 97	struct jh7110_pinctrl *sfp = jh7110_from_irq_desc(desc);
 98	struct irq_chip *chip = irq_desc_get_chip(desc);
 99	unsigned long mis;
100	unsigned int pin;
101
102	chained_irq_enter(chip, desc);
103
104	mis = readl_relaxed(sfp->base + JH7110_AON_GPIOMIS);
105	for_each_set_bit(pin, &mis, JH7110_AON_NGPIO)
106		generic_handle_domain_irq(sfp->gc.irq.domain, pin);
107
108	chained_irq_exit(chip, desc);
109}
110
111static int jh7110_aon_init_hw(struct gpio_chip *gc)
112{
113	struct jh7110_pinctrl *sfp = container_of(gc,
114			struct jh7110_pinctrl, gc);
115
116	/* mask all GPIO interrupts */
117	writel_relaxed(0, sfp->base + JH7110_AON_GPIOIE);
118	/* clear edge interrupt flags */
119	writel_relaxed(0, sfp->base + JH7110_AON_GPIOIC);
120	writel_relaxed(0x0f, sfp->base + JH7110_AON_GPIOIC);
121	/* enable GPIO interrupts */
122	writel_relaxed(1, sfp->base + JH7110_AON_GPIOEN);
123	return 0;
124}
125
126static const struct jh7110_gpio_irq_reg jh7110_aon_irq_reg = {
127	.is_reg_base	= JH7110_AON_GPIOIS,
128	.ic_reg_base	= JH7110_AON_GPIOIC,
129	.ibe_reg_base	= JH7110_AON_GPIOIBE,
130	.iev_reg_base	= JH7110_AON_GPIOIEV,
131	.ie_reg_base	= JH7110_AON_GPIOIE,
132	.ris_reg_base	= JH7110_AON_GPIORIS,
133	.mis_reg_base	= JH7110_AON_GPIOMIS,
134};
135
136static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = {
137	.pins		= jh7110_aon_pins,
138	.npins		= ARRAY_SIZE(jh7110_aon_pins),
139	.ngpios		= JH7110_AON_NGPIO,
140	.dout_reg_base	= JH7110_AON_DOUT,
141	.dout_mask	= GENMASK(3, 0),
142	.doen_reg_base	= JH7110_AON_DOEN,
143	.doen_mask	= GENMASK(2, 0),
144	.gpi_reg_base	= JH7110_AON_GPI,
145	.gpi_mask	= GENMASK(3, 0),
146	.gpioin_reg_base	   = JH7110_AON_GPIOIN,
147	.irq_reg		   = &jh7110_aon_irq_reg,
148	.nsaved_regs		   = JH7110_AON_REGS_NUM,
149	.jh7110_set_one_pin_mux  = jh7110_aon_set_one_pin_mux,
150	.jh7110_get_padcfg_base  = jh7110_aon_get_padcfg_base,
151	.jh7110_gpio_irq_handler = jh7110_aon_irq_handler,
152	.jh7110_gpio_init_hw	 = jh7110_aon_init_hw,
153};
154
155static const struct of_device_id jh7110_aon_pinctrl_of_match[] = {
156	{
157		.compatible = "starfive,jh7110-aon-pinctrl",
158		.data = &jh7110_aon_pinctrl_info,
159	},
160	{ /* sentinel */ }
161};
162MODULE_DEVICE_TABLE(of, jh7110_aon_pinctrl_of_match);
163
164static struct platform_driver jh7110_aon_pinctrl_driver = {
165	.probe = jh7110_pinctrl_probe,
166	.driver = {
167		.name = "starfive-jh7110-aon-pinctrl",
168		.of_match_table = jh7110_aon_pinctrl_of_match,
169		.pm = pm_sleep_ptr(&jh7110_pinctrl_pm_ops),
170	},
171};
172module_platform_driver(jh7110_aon_pinctrl_driver);
173
174MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
175MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
176MODULE_LICENSE("GPL");