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pinctrl-k1.c
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linux-6.19.14/drivers/pinctrl/spacemit/pinctrl-k1.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */ 3 4#include <linux/bits.h> 5#include <linux/clk.h> 6#include <linux/cleanup.h> 7#include <linux/io.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10#include <linux/seq_file.h> 11#include <linux/spinlock.h> 12#include <linux/module.h> 13#include <linux/mutex.h> 14 15#include <linux/pinctrl/pinconf-generic.h> 16#include <linux/pinctrl/pinconf.h> 17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinmux.h> 19 20#include "../core.h" 21#include "../pinctrl-utils.h" 22#include "../pinconf.h" 23#include "../pinmux.h" 24#include "pinctrl-k1.h" 25 26/* 27 * +---------+----------+-----------+--------+--------+----------+--------+ 28 * | pull | drive | schmitter | slew | edge | strong | mux | 29 * | up/down | strength | trigger | rate | detect | pull | mode | 30 * +---------+----------+-----------+--------+--------+----------+--------+ 31 * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits 32 */ 33 34#define PAD_MUX GENMASK(2, 0) 35#define PAD_STRONG_PULL BIT(3) 36#define PAD_EDGE_RISE BIT(4) 37#define PAD_EDGE_FALL BIT(5) 38#define PAD_EDGE_CLEAR BIT(6) 39#define PAD_SLEW_RATE GENMASK(12, 11) 40#define PAD_SLEW_RATE_EN BIT(7) 41#define PAD_SCHMITT GENMASK(9, 8) 42#define PAD_DRIVE GENMASK(12, 10) 43#define PAD_PULLDOWN BIT(13) 44#define PAD_PULLUP BIT(14) 45#define PAD_PULL_EN BIT(15) 46 47struct spacemit_pin { 48 u16 pin; 49 u16 flags; 50 u8 gpiofunc; 51}; 52 53struct spacemit_pinctrl { 54 struct device *dev; 55 struct pinctrl_dev *pctl_dev; 56 const struct spacemit_pinctrl_data *data; 57 struct pinctrl_desc pdesc; 58 59 struct mutex mutex; 60 raw_spinlock_t lock; 61 62 void __iomem *regs; 63}; 64 65struct spacemit_pinctrl_data { 66 const struct pinctrl_pin_desc *pins; 67 const struct spacemit_pin *data; 68 u16 npins; 69}; 70 71struct spacemit_pin_mux_config { 72 const struct spacemit_pin *pin; 73 u32 config; 74}; 75 76struct spacemit_pin_drv_strength { 77 u8 val; 78 u32 mA; 79}; 80 81/* map pin id to pinctrl register offset, refer MFPR definition */ 82static unsigned int spacemit_pin_to_offset(unsigned int pin) 83{ 84 unsigned int offset = 0; 85 86 switch (pin) { 87 case 0 ... 85: 88 offset = pin + 1; 89 break; 90 case 86 ... 92: 91 offset = pin + 37; 92 break; 93 case 93 ... 97: 94 offset = pin + 24; 95 break; 96 case 98: 97 offset = 93; 98 break; 99 case 99: 100 offset = 92; 101 break; 102 case 100: 103 offset = 91; 104 break; 105 case 101: 106 offset = 90; 107 break; 108 case 102: 109 offset = 95; 110 break; 111 case 103: 112 offset = 94; 113 break; 114 case 104 ... 110: 115 offset = pin + 6; 116 break; 117 case 111 ... 127: 118 offset = pin + 20; 119 break; 120 default: 121 break; 122 } 123 124 return offset << 2; 125} 126 127static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl, 128 unsigned int pin) 129{ 130 return pctrl->regs + spacemit_pin_to_offset(pin); 131} 132 133static u16 spacemit_dt_get_pin(u32 value) 134{ 135 return value >> 16; 136} 137 138static u16 spacemit_dt_get_pin_mux(u32 value) 139{ 140 return value & GENMASK(15, 0); 141} 142 143static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl, 144 unsigned long pin) 145{ 146 const struct spacemit_pin *pdata = pctrl->data->data; 147 int i; 148 149 for (i = 0; i < pctrl->data->npins; i++) { 150 if (pin == pdata[i].pin) 151 return &pdata[i]; 152 } 153 154 return NULL; 155} 156 157static inline enum spacemit_pin_io_type spacemit_to_pin_io_type( 158 const struct spacemit_pin *pin) 159{ 160 return K1_PIN_GET_IO_TYPE(pin->flags); 161} 162 163/* External: IO voltage via external source, can be 1.8V or 3.3V */ 164static const char * const io_type_desc[] = { 165 "None", 166 "Fixed/1V8", 167 "Fixed/3V3", 168 "External", 169}; 170 171static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev, 172 struct seq_file *seq, unsigned int pin) 173{ 174 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 175 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 176 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 177 void __iomem *reg; 178 u32 value; 179 180 seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); 181 seq_printf(seq, "type: %s ", io_type_desc[type]); 182 183 reg = spacemit_pin_to_reg(pctrl, pin); 184 value = readl(reg); 185 seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value); 186} 187 188/* use IO high level output current as the table */ 189static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = { 190 { 0, 11 }, 191 { 2, 21 }, 192 { 4, 32 }, 193 { 6, 42 }, 194}; 195 196static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = { 197 { 0, 7 }, 198 { 2, 10 }, 199 { 4, 13 }, 200 { 6, 16 }, 201 { 1, 19 }, 202 { 3, 23 }, 203 { 5, 26 }, 204 { 7, 29 }, 205}; 206 207static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl, 208 u32 num, u32 mA) 209{ 210 int i; 211 212 for (i = 0; i < num; i++) 213 if (mA <= tbl[i].mA) 214 return tbl[i].val; 215 216 return tbl[num - 1].val; 217} 218 219static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl, 220 u32 num, u32 val) 221{ 222 int i; 223 224 for (i = 0; i < num; i++) 225 if (val == tbl[i].val) 226 return tbl[i].mA; 227 228 return 0; 229} 230 231static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type, 232 u32 mA) 233{ 234 switch (type) { 235 case IO_TYPE_1V8: 236 return spacemit_get_ds_value(spacemit_ds_1v8_tbl, 237 ARRAY_SIZE(spacemit_ds_1v8_tbl), 238 mA); 239 case IO_TYPE_3V3: 240 return spacemit_get_ds_value(spacemit_ds_3v3_tbl, 241 ARRAY_SIZE(spacemit_ds_3v3_tbl), 242 mA); 243 default: 244 return 0; 245 } 246} 247 248static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type, 249 u32 value) 250{ 251 switch (type) { 252 case IO_TYPE_1V8: 253 return spacemit_get_ds_mA(spacemit_ds_1v8_tbl, 254 ARRAY_SIZE(spacemit_ds_1v8_tbl), 255 value & 0x6); 256 case IO_TYPE_3V3: 257 return spacemit_get_ds_mA(spacemit_ds_3v3_tbl, 258 ARRAY_SIZE(spacemit_ds_3v3_tbl), 259 value); 260 default: 261 return 0; 262 } 263} 264 265static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev, 266 struct device_node *dn, 267 struct spacemit_pin_mux_config *pinmuxs, 268 int num_pins, const char *grpname) 269{ 270 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 271 struct device *dev = pctrl->dev; 272 enum spacemit_pin_io_type type; 273 u32 power = 0, i; 274 275 of_property_read_u32(dn, "power-source", &power); 276 277 for (i = 0; i < num_pins; i++) { 278 type = spacemit_to_pin_io_type(pinmuxs[i].pin); 279 280 if (type != IO_TYPE_EXTERNAL) 281 continue; 282 283 switch (power) { 284 case PIN_POWER_STATE_1V8: 285 case PIN_POWER_STATE_3V3: 286 break; 287 default: 288 dev_err(dev, "group %s has unsupported power\n", 289 grpname); 290 return -ENOTSUPP; 291 } 292 } 293 294 return 0; 295} 296 297static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 298 struct device_node *np, 299 struct pinctrl_map **maps, 300 unsigned int *num_maps) 301{ 302 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 303 struct device *dev = pctrl->dev; 304 struct device_node *child; 305 struct pinctrl_map *map; 306 const char **grpnames; 307 const char *grpname; 308 int ngroups = 0; 309 int nmaps = 0; 310 int ret; 311 312 for_each_available_child_of_node(np, child) 313 ngroups += 1; 314 315 grpnames = devm_kcalloc(dev, ngroups, sizeof(*grpnames), GFP_KERNEL); 316 if (!grpnames) 317 return -ENOMEM; 318 319 map = kcalloc(ngroups * 2, sizeof(*map), GFP_KERNEL); 320 if (!map) 321 return -ENOMEM; 322 323 ngroups = 0; 324 guard(mutex)(&pctrl->mutex); 325 for_each_available_child_of_node_scoped(np, child) { 326 struct spacemit_pin_mux_config *pinmuxs; 327 unsigned int config, *pins; 328 int i, npins; 329 330 npins = of_property_count_u32_elems(child, "pinmux"); 331 332 if (npins < 1) { 333 dev_err(dev, "invalid pinctrl group %pOFn.%pOFn\n", 334 np, child); 335 return -EINVAL; 336 } 337 338 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", 339 np, child); 340 if (!grpname) 341 return -ENOMEM; 342 343 grpnames[ngroups++] = grpname; 344 345 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL); 346 if (!pins) 347 return -ENOMEM; 348 349 pinmuxs = devm_kcalloc(dev, npins, sizeof(*pinmuxs), GFP_KERNEL); 350 if (!pinmuxs) 351 return -ENOMEM; 352 353 for (i = 0; i < npins; i++) { 354 ret = of_property_read_u32_index(child, "pinmux", 355 i, &config); 356 357 if (ret) 358 return -EINVAL; 359 360 pins[i] = spacemit_dt_get_pin(config); 361 pinmuxs[i].config = config; 362 pinmuxs[i].pin = spacemit_get_pin(pctrl, pins[i]); 363 364 if (!pinmuxs[i].pin) 365 return dev_err_probe(dev, -ENODEV, "failed to get pin %d\n", pins[i]); 366 } 367 368 ret = spacemit_pctrl_check_power(pctldev, child, pinmuxs, 369 npins, grpname); 370 if (ret < 0) 371 return ret; 372 373 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; 374 map[nmaps].data.mux.function = np->name; 375 map[nmaps].data.mux.group = grpname; 376 nmaps += 1; 377 378 ret = pinctrl_generic_add_group(pctldev, grpname, 379 pins, npins, pinmuxs); 380 if (ret < 0) 381 return dev_err_probe(dev, ret, "failed to add group %s: %d\n", grpname, ret); 382 383 ret = pinconf_generic_parse_dt_config(child, pctldev, 384 &map[nmaps].data.configs.configs, 385 &map[nmaps].data.configs.num_configs); 386 if (ret) 387 return dev_err_probe(dev, ret, "failed to parse pin config of group %s\n", 388 grpname); 389 390 if (map[nmaps].data.configs.num_configs == 0) 391 continue; 392 393 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; 394 map[nmaps].data.configs.group_or_pin = grpname; 395 nmaps += 1; 396 } 397 398 ret = pinmux_generic_add_function(pctldev, np->name, 399 grpnames, ngroups, NULL); 400 if (ret < 0) { 401 pinctrl_utils_free_map(pctldev, map, nmaps); 402 return dev_err_probe(dev, ret, "error adding function %s\n", np->name); 403 } 404 405 *maps = map; 406 *num_maps = nmaps; 407 408 return 0; 409} 410 411static const struct pinctrl_ops spacemit_pctrl_ops = { 412 .get_groups_count = pinctrl_generic_get_group_count, 413 .get_group_name = pinctrl_generic_get_group_name, 414 .get_group_pins = pinctrl_generic_get_group_pins, 415 .pin_dbg_show = spacemit_pctrl_dbg_show, 416 .dt_node_to_map = spacemit_pctrl_dt_node_to_map, 417 .dt_free_map = pinctrl_utils_free_map, 418}; 419 420static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev, 421 unsigned int fsel, unsigned int gsel) 422{ 423 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 424 const struct group_desc *group; 425 const struct spacemit_pin_mux_config *configs; 426 unsigned int i, mux; 427 void __iomem *reg; 428 429 group = pinctrl_generic_get_group(pctldev, gsel); 430 if (!group) 431 return -EINVAL; 432 433 configs = group->data; 434 435 for (i = 0; i < group->grp.npins; i++) { 436 const struct spacemit_pin *spin = configs[i].pin; 437 u32 value = configs[i].config; 438 439 reg = spacemit_pin_to_reg(pctrl, spin->pin); 440 mux = spacemit_dt_get_pin_mux(value); 441 442 guard(raw_spinlock_irqsave)(&pctrl->lock); 443 value = readl_relaxed(reg) & ~PAD_MUX; 444 writel_relaxed(mux | value, reg); 445 } 446 447 return 0; 448} 449 450static int spacemit_request_gpio(struct pinctrl_dev *pctldev, 451 struct pinctrl_gpio_range *range, 452 unsigned int pin) 453{ 454 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 455 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 456 void __iomem *reg; 457 458 reg = spacemit_pin_to_reg(pctrl, pin); 459 guard(raw_spinlock_irqsave)(&pctrl->lock); 460 writel_relaxed(spin->gpiofunc, reg); 461 462 return 0; 463} 464 465static const struct pinmux_ops spacemit_pmx_ops = { 466 .get_functions_count = pinmux_generic_get_function_count, 467 .get_function_name = pinmux_generic_get_function_name, 468 .get_function_groups = pinmux_generic_get_function_groups, 469 .set_mux = spacemit_pmx_set_mux, 470 .gpio_request_enable = spacemit_request_gpio, 471 .strict = true, 472}; 473 474static int spacemit_pinconf_get(struct pinctrl_dev *pctldev, 475 unsigned int pin, unsigned long *config) 476{ 477 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 478 int param = pinconf_to_config_param(*config); 479 u32 value, arg = 0; 480 481 if (!pin) 482 return -EINVAL; 483 484 value = readl(spacemit_pin_to_reg(pctrl, pin)); 485 486 switch (param) { 487 case PIN_CONFIG_SLEW_RATE: 488 if (FIELD_GET(PAD_SLEW_RATE_EN, value)) 489 arg = FIELD_GET(PAD_SLEW_RATE, value) + 2; 490 else 491 arg = 0; 492 break; 493 default: 494 return -EINVAL; 495 } 496 497 *config = pinconf_to_config_packed(param, arg); 498 499 return 0; 500} 501 502#define ENABLE_DRV_STRENGTH BIT(1) 503#define ENABLE_SLEW_RATE BIT(2) 504static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin, 505 unsigned long *configs, 506 unsigned int num_configs, 507 u32 *value) 508{ 509 enum spacemit_pin_io_type type; 510 int i, param; 511 u32 v = 0, voltage = 0, arg, val; 512 u32 flag = 0, drv_strength, slew_rate; 513 514 if (!spin) 515 return -EINVAL; 516 517 for (i = 0; i < num_configs; i++) { 518 param = pinconf_to_config_param(configs[i]); 519 arg = pinconf_to_config_argument(configs[i]); 520 521 switch (param) { 522 case PIN_CONFIG_BIAS_DISABLE: 523 v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP); 524 v &= ~PAD_STRONG_PULL; 525 break; 526 case PIN_CONFIG_BIAS_PULL_DOWN: 527 v &= ~(PAD_PULLUP | PAD_STRONG_PULL); 528 v |= (PAD_PULL_EN | PAD_PULLDOWN); 529 break; 530 case PIN_CONFIG_BIAS_PULL_UP: 531 v &= ~PAD_PULLDOWN; 532 v |= (PAD_PULL_EN | PAD_PULLUP); 533 534 if (arg == 1) 535 v |= PAD_STRONG_PULL; 536 break; 537 case PIN_CONFIG_DRIVE_STRENGTH: 538 flag |= ENABLE_DRV_STRENGTH; 539 drv_strength = arg; 540 break; 541 case PIN_CONFIG_INPUT_SCHMITT: 542 v &= ~PAD_SCHMITT; 543 v |= FIELD_PREP(PAD_SCHMITT, arg); 544 break; 545 case PIN_CONFIG_POWER_SOURCE: 546 voltage = arg; 547 break; 548 case PIN_CONFIG_SLEW_RATE: 549 if (arg) { 550 flag |= ENABLE_SLEW_RATE; 551 v |= PAD_SLEW_RATE_EN; 552 slew_rate = arg; 553 } else { 554 v &= ~PAD_SLEW_RATE_EN; 555 } 556 break; 557 default: 558 return -EINVAL; 559 } 560 } 561 562 if (flag & ENABLE_DRV_STRENGTH) { 563 type = spacemit_to_pin_io_type(spin); 564 565 /* fix external io type */ 566 if (type == IO_TYPE_EXTERNAL) { 567 switch (voltage) { 568 case 1800: 569 type = IO_TYPE_1V8; 570 break; 571 case 3300: 572 type = IO_TYPE_3V3; 573 break; 574 default: 575 return -EINVAL; 576 } 577 } 578 579 val = spacemit_get_driver_strength(type, drv_strength); 580 581 v &= ~PAD_DRIVE; 582 v |= FIELD_PREP(PAD_DRIVE, val); 583 } 584 585 if (flag & ENABLE_SLEW_RATE) { 586 /* check, driver strength & slew rate */ 587 if (flag & ENABLE_DRV_STRENGTH) { 588 val = FIELD_GET(PAD_SLEW_RATE, v) + 2; 589 if (slew_rate > 1 && slew_rate != val) { 590 pr_err("slew rate conflict with drive strength\n"); 591 return -EINVAL; 592 } 593 } else { 594 v &= ~PAD_SLEW_RATE; 595 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0; 596 v |= FIELD_PREP(PAD_SLEW_RATE, slew_rate); 597 } 598 } 599 600 *value = v; 601 602 return 0; 603} 604 605static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl, 606 unsigned int pin, u32 value) 607{ 608 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 609 void __iomem *reg; 610 unsigned int mux; 611 612 if (!pin) 613 return -EINVAL; 614 615 reg = spacemit_pin_to_reg(pctrl, spin->pin); 616 617 guard(raw_spinlock_irqsave)(&pctrl->lock); 618 mux = readl_relaxed(reg) & PAD_MUX; 619 writel_relaxed(mux | value, reg); 620 621 return 0; 622} 623 624static int spacemit_pinconf_set(struct pinctrl_dev *pctldev, 625 unsigned int pin, unsigned long *configs, 626 unsigned int num_configs) 627{ 628 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 629 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 630 u32 value; 631 632 if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) 633 return -EINVAL; 634 635 return spacemit_pin_set_config(pctrl, pin, value); 636} 637 638static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev, 639 unsigned int gsel, 640 unsigned long *configs, 641 unsigned int num_configs) 642{ 643 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 644 const struct spacemit_pin *spin; 645 const struct group_desc *group; 646 u32 value; 647 int i; 648 649 group = pinctrl_generic_get_group(pctldev, gsel); 650 if (!group) 651 return -EINVAL; 652 653 spin = spacemit_get_pin(pctrl, group->grp.pins[0]); 654 if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value)) 655 return -EINVAL; 656 657 for (i = 0; i < group->grp.npins; i++) 658 spacemit_pin_set_config(pctrl, group->grp.pins[i], value); 659 660 return 0; 661} 662 663static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value) 664{ 665 u32 normal, strong; 666 667 if (!FIELD_GET(PAD_PULL_EN, value)) { 668 seq_puts(seq, ", bias pull disabled"); 669 return; 670 } 671 672 if (FIELD_GET(PAD_PULLDOWN, value)) 673 seq_puts(seq, ", bias pull down"); 674 675 normal = FIELD_GET(PAD_PULLUP, value); 676 strong = FIELD_GET(PAD_STRONG_PULL, value); 677 678 if (normal && strong) 679 seq_puts(seq, ", bias strong pull up"); 680 else if (normal) 681 seq_puts(seq, ", bias normal pull up"); 682} 683 684static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev, 685 struct seq_file *seq, unsigned int pin) 686{ 687 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 688 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); 689 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin); 690 void __iomem *reg = spacemit_pin_to_reg(pctrl, pin); 691 u32 value, tmp, mA; 692 693 value = readl(reg); 694 spacemit_pinconf_dbg_pull(seq, value); 695 696 seq_printf(seq, ", io type (%s)", io_type_desc[type]); 697 698 tmp = FIELD_GET(PAD_DRIVE, value); 699 if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) { 700 mA = spacemit_get_drive_strength_mA(type, tmp); 701 seq_printf(seq, ", drive strength (%d mA)", mA); 702 } 703 704 /* drive strength depend on power source, so show all values */ 705 if (type == IO_TYPE_EXTERNAL) 706 seq_printf(seq, ", drive strength (%d or %d mA)", 707 spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp), 708 spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp)); 709 710 seq_printf(seq, ", register (0x%04x)", value); 711} 712 713static const struct pinconf_ops spacemit_pinconf_ops = { 714 .pin_config_get = spacemit_pinconf_get, 715 .pin_config_set = spacemit_pinconf_set, 716 .pin_config_group_set = spacemit_pinconf_group_set, 717 .pin_config_dbg_show = spacemit_pinconf_dbg_show, 718 .is_generic = true, 719}; 720 721static int spacemit_pinctrl_probe(struct platform_device *pdev) 722{ 723 struct device *dev = &pdev->dev; 724 struct spacemit_pinctrl *pctrl; 725 struct clk *func_clk, *bus_clk; 726 const struct spacemit_pinctrl_data *pctrl_data; 727 int ret; 728 729 pctrl_data = device_get_match_data(dev); 730 if (!pctrl_data) 731 return -ENODEV; 732 733 if (pctrl_data->npins == 0) 734 return dev_err_probe(dev, -EINVAL, "invalid pin data\n"); 735 736 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 737 if (!pctrl) 738 return -ENOMEM; 739 740 pctrl->regs = devm_platform_ioremap_resource(pdev, 0); 741 if (IS_ERR(pctrl->regs)) 742 return PTR_ERR(pctrl->regs); 743 744 func_clk = devm_clk_get_enabled(dev, "func"); 745 if (IS_ERR(func_clk)) 746 return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n"); 747 748 bus_clk = devm_clk_get_enabled(dev, "bus"); 749 if (IS_ERR(bus_clk)) 750 return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n"); 751 752 pctrl->pdesc.name = dev_name(dev); 753 pctrl->pdesc.pins = pctrl_data->pins; 754 pctrl->pdesc.npins = pctrl_data->npins; 755 pctrl->pdesc.pctlops = &spacemit_pctrl_ops; 756 pctrl->pdesc.pmxops = &spacemit_pmx_ops; 757 pctrl->pdesc.confops = &spacemit_pinconf_ops; 758 pctrl->pdesc.owner = THIS_MODULE; 759 760 pctrl->data = pctrl_data; 761 pctrl->dev = dev; 762 raw_spin_lock_init(&pctrl->lock); 763 764 ret = devm_mutex_init(dev, &pctrl->mutex); 765 if (ret) 766 return ret; 767 768 platform_set_drvdata(pdev, pctrl); 769 770 ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc, 771 pctrl, &pctrl->pctl_dev); 772 if (ret) 773 return dev_err_probe(dev, ret, 774 "fail to register pinctrl driver\n"); 775 776 return pinctrl_enable(pctrl->pctl_dev); 777} 778 779static const struct pinctrl_pin_desc k1_pin_desc[] = { 780 PINCTRL_PIN(0, "GPIO_00"), 781 PINCTRL_PIN(1, "GPIO_01"), 782 PINCTRL_PIN(2, "GPIO_02"), 783 PINCTRL_PIN(3, "GPIO_03"), 784 PINCTRL_PIN(4, "GPIO_04"), 785 PINCTRL_PIN(5, "GPIO_05"), 786 PINCTRL_PIN(6, "GPIO_06"), 787 PINCTRL_PIN(7, "GPIO_07"), 788 PINCTRL_PIN(8, "GPIO_08"), 789 PINCTRL_PIN(9, "GPIO_09"), 790 PINCTRL_PIN(10, "GPIO_10"), 791 PINCTRL_PIN(11, "GPIO_11"), 792 PINCTRL_PIN(12, "GPIO_12"), 793 PINCTRL_PIN(13, "GPIO_13"), 794 PINCTRL_PIN(14, "GPIO_14"), 795 PINCTRL_PIN(15, "GPIO_15"), 796 PINCTRL_PIN(16, "GPIO_16"), 797 PINCTRL_PIN(17, "GPIO_17"), 798 PINCTRL_PIN(18, "GPIO_18"), 799 PINCTRL_PIN(19, "GPIO_19"), 800 PINCTRL_PIN(20, "GPIO_20"), 801 PINCTRL_PIN(21, "GPIO_21"), 802 PINCTRL_PIN(22, "GPIO_22"), 803 PINCTRL_PIN(23, "GPIO_23"), 804 PINCTRL_PIN(24, "GPIO_24"), 805 PINCTRL_PIN(25, "GPIO_25"), 806 PINCTRL_PIN(26, "GPIO_26"), 807 PINCTRL_PIN(27, "GPIO_27"), 808 PINCTRL_PIN(28, "GPIO_28"), 809 PINCTRL_PIN(29, "GPIO_29"), 810 PINCTRL_PIN(30, "GPIO_30"), 811 PINCTRL_PIN(31, "GPIO_31"), 812 PINCTRL_PIN(32, "GPIO_32"), 813 PINCTRL_PIN(33, "GPIO_33"), 814 PINCTRL_PIN(34, "GPIO_34"), 815 PINCTRL_PIN(35, "GPIO_35"), 816 PINCTRL_PIN(36, "GPIO_36"), 817 PINCTRL_PIN(37, "GPIO_37"), 818 PINCTRL_PIN(38, "GPIO_38"), 819 PINCTRL_PIN(39, "GPIO_39"), 820 PINCTRL_PIN(40, "GPIO_40"), 821 PINCTRL_PIN(41, "GPIO_41"), 822 PINCTRL_PIN(42, "GPIO_42"), 823 PINCTRL_PIN(43, "GPIO_43"), 824 PINCTRL_PIN(44, "GPIO_44"), 825 PINCTRL_PIN(45, "GPIO_45"), 826 PINCTRL_PIN(46, "GPIO_46"), 827 PINCTRL_PIN(47, "GPIO_47"), 828 PINCTRL_PIN(48, "GPIO_48"), 829 PINCTRL_PIN(49, "GPIO_49"), 830 PINCTRL_PIN(50, "GPIO_50"), 831 PINCTRL_PIN(51, "GPIO_51"), 832 PINCTRL_PIN(52, "GPIO_52"), 833 PINCTRL_PIN(53, "GPIO_53"), 834 PINCTRL_PIN(54, "GPIO_54"), 835 PINCTRL_PIN(55, "GPIO_55"), 836 PINCTRL_PIN(56, "GPIO_56"), 837 PINCTRL_PIN(57, "GPIO_57"), 838 PINCTRL_PIN(58, "GPIO_58"), 839 PINCTRL_PIN(59, "GPIO_59"), 840 PINCTRL_PIN(60, "GPIO_60"), 841 PINCTRL_PIN(61, "GPIO_61"), 842 PINCTRL_PIN(62, "GPIO_62"), 843 PINCTRL_PIN(63, "GPIO_63"), 844 PINCTRL_PIN(64, "GPIO_64"), 845 PINCTRL_PIN(65, "GPIO_65"), 846 PINCTRL_PIN(66, "GPIO_66"), 847 PINCTRL_PIN(67, "GPIO_67"), 848 PINCTRL_PIN(68, "GPIO_68"), 849 PINCTRL_PIN(69, "GPIO_69"), 850 PINCTRL_PIN(70, "GPIO_70/PRI_TDI"), 851 PINCTRL_PIN(71, "GPIO_71/PRI_TMS"), 852 PINCTRL_PIN(72, "GPIO_72/PRI_TCK"), 853 PINCTRL_PIN(73, "GPIO_73/PRI_TDO"), 854 PINCTRL_PIN(74, "GPIO_74"), 855 PINCTRL_PIN(75, "GPIO_75"), 856 PINCTRL_PIN(76, "GPIO_76"), 857 PINCTRL_PIN(77, "GPIO_77"), 858 PINCTRL_PIN(78, "GPIO_78"), 859 PINCTRL_PIN(79, "GPIO_79"), 860 PINCTRL_PIN(80, "GPIO_80"), 861 PINCTRL_PIN(81, "GPIO_81"), 862 PINCTRL_PIN(82, "GPIO_82"), 863 PINCTRL_PIN(83, "GPIO_83"), 864 PINCTRL_PIN(84, "GPIO_84"), 865 PINCTRL_PIN(85, "GPIO_85"), 866 PINCTRL_PIN(86, "GPIO_86"), 867 PINCTRL_PIN(87, "GPIO_87"), 868 PINCTRL_PIN(88, "GPIO_88"), 869 PINCTRL_PIN(89, "GPIO_89"), 870 PINCTRL_PIN(90, "GPIO_90"), 871 PINCTRL_PIN(91, "GPIO_91"), 872 PINCTRL_PIN(92, "GPIO_92"), 873 PINCTRL_PIN(93, "GPIO_93/PWR_SCL"), 874 PINCTRL_PIN(94, "GPIO_94/PWR_SDA"), 875 PINCTRL_PIN(95, "GPIO_95/VCX0_EN"), 876 PINCTRL_PIN(96, "GPIO_96/DVL0"), 877 PINCTRL_PIN(97, "GPIO_97/DVL1"), 878 PINCTRL_PIN(98, "GPIO_98/QSPI_DAT3"), 879 PINCTRL_PIN(99, "GPIO_99/QSPI_DAT2"), 880 PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"), 881 PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"), 882 PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"), 883 PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"), 884 PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"), 885 PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"), 886 PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"), 887 PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"), 888 PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"), 889 PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"), 890 PINCTRL_PIN(110, "GPIO_110"), 891 PINCTRL_PIN(111, "GPIO_111"), 892 PINCTRL_PIN(112, "GPIO_112"), 893 PINCTRL_PIN(113, "GPIO_113"), 894 PINCTRL_PIN(114, "GPIO_114"), 895 PINCTRL_PIN(115, "GPIO_115"), 896 PINCTRL_PIN(116, "GPIO_116"), 897 PINCTRL_PIN(117, "GPIO_117"), 898 PINCTRL_PIN(118, "GPIO_118"), 899 PINCTRL_PIN(119, "GPIO_119"), 900 PINCTRL_PIN(120, "GPIO_120"), 901 PINCTRL_PIN(121, "GPIO_121"), 902 PINCTRL_PIN(122, "GPIO_122"), 903 PINCTRL_PIN(123, "GPIO_123"), 904 PINCTRL_PIN(124, "GPIO_124"), 905 PINCTRL_PIN(125, "GPIO_125"), 906 PINCTRL_PIN(126, "GPIO_126"), 907 PINCTRL_PIN(127, "GPIO_127"), 908}; 909 910static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = { 911 K1_FUNC_PIN(0, 0, IO_TYPE_1V8), 912 K1_FUNC_PIN(1, 0, IO_TYPE_1V8), 913 K1_FUNC_PIN(2, 0, IO_TYPE_1V8), 914 K1_FUNC_PIN(3, 0, IO_TYPE_1V8), 915 K1_FUNC_PIN(4, 0, IO_TYPE_1V8), 916 K1_FUNC_PIN(5, 0, IO_TYPE_1V8), 917 K1_FUNC_PIN(6, 0, IO_TYPE_1V8), 918 K1_FUNC_PIN(7, 0, IO_TYPE_1V8), 919 K1_FUNC_PIN(8, 0, IO_TYPE_1V8), 920 K1_FUNC_PIN(9, 0, IO_TYPE_1V8), 921 K1_FUNC_PIN(10, 0, IO_TYPE_1V8), 922 K1_FUNC_PIN(11, 0, IO_TYPE_1V8), 923 K1_FUNC_PIN(12, 0, IO_TYPE_1V8), 924 K1_FUNC_PIN(13, 0, IO_TYPE_1V8), 925 K1_FUNC_PIN(14, 0, IO_TYPE_1V8), 926 K1_FUNC_PIN(15, 0, IO_TYPE_1V8), 927 K1_FUNC_PIN(16, 0, IO_TYPE_1V8), 928 K1_FUNC_PIN(17, 0, IO_TYPE_1V8), 929 K1_FUNC_PIN(18, 0, IO_TYPE_1V8), 930 K1_FUNC_PIN(19, 0, IO_TYPE_1V8), 931 K1_FUNC_PIN(20, 0, IO_TYPE_1V8), 932 K1_FUNC_PIN(21, 0, IO_TYPE_1V8), 933 K1_FUNC_PIN(22, 0, IO_TYPE_1V8), 934 K1_FUNC_PIN(23, 0, IO_TYPE_1V8), 935 K1_FUNC_PIN(24, 0, IO_TYPE_1V8), 936 K1_FUNC_PIN(25, 0, IO_TYPE_1V8), 937 K1_FUNC_PIN(26, 0, IO_TYPE_1V8), 938 K1_FUNC_PIN(27, 0, IO_TYPE_1V8), 939 K1_FUNC_PIN(28, 0, IO_TYPE_1V8), 940 K1_FUNC_PIN(29, 0, IO_TYPE_1V8), 941 K1_FUNC_PIN(30, 0, IO_TYPE_1V8), 942 K1_FUNC_PIN(31, 0, IO_TYPE_1V8), 943 K1_FUNC_PIN(32, 0, IO_TYPE_1V8), 944 K1_FUNC_PIN(33, 0, IO_TYPE_1V8), 945 K1_FUNC_PIN(34, 0, IO_TYPE_1V8), 946 K1_FUNC_PIN(35, 0, IO_TYPE_1V8), 947 K1_FUNC_PIN(36, 0, IO_TYPE_1V8), 948 K1_FUNC_PIN(37, 0, IO_TYPE_1V8), 949 K1_FUNC_PIN(38, 0, IO_TYPE_1V8), 950 K1_FUNC_PIN(39, 0, IO_TYPE_1V8), 951 K1_FUNC_PIN(40, 0, IO_TYPE_1V8), 952 K1_FUNC_PIN(41, 0, IO_TYPE_1V8), 953 K1_FUNC_PIN(42, 0, IO_TYPE_1V8), 954 K1_FUNC_PIN(43, 0, IO_TYPE_1V8), 955 K1_FUNC_PIN(44, 0, IO_TYPE_1V8), 956 K1_FUNC_PIN(45, 0, IO_TYPE_1V8), 957 K1_FUNC_PIN(46, 0, IO_TYPE_1V8), 958 K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL), 959 K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL), 960 K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL), 961 K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL), 962 K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL), 963 K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL), 964 K1_FUNC_PIN(53, 0, IO_TYPE_1V8), 965 K1_FUNC_PIN(54, 0, IO_TYPE_1V8), 966 K1_FUNC_PIN(55, 0, IO_TYPE_1V8), 967 K1_FUNC_PIN(56, 0, IO_TYPE_1V8), 968 K1_FUNC_PIN(57, 0, IO_TYPE_1V8), 969 K1_FUNC_PIN(58, 0, IO_TYPE_1V8), 970 K1_FUNC_PIN(59, 0, IO_TYPE_1V8), 971 K1_FUNC_PIN(60, 0, IO_TYPE_1V8), 972 K1_FUNC_PIN(61, 0, IO_TYPE_1V8), 973 K1_FUNC_PIN(62, 0, IO_TYPE_1V8), 974 K1_FUNC_PIN(63, 0, IO_TYPE_1V8), 975 K1_FUNC_PIN(64, 0, IO_TYPE_1V8), 976 K1_FUNC_PIN(65, 0, IO_TYPE_1V8), 977 K1_FUNC_PIN(66, 0, IO_TYPE_1V8), 978 K1_FUNC_PIN(67, 0, IO_TYPE_1V8), 979 K1_FUNC_PIN(68, 0, IO_TYPE_1V8), 980 K1_FUNC_PIN(69, 0, IO_TYPE_1V8), 981 K1_FUNC_PIN(70, 1, IO_TYPE_1V8), 982 K1_FUNC_PIN(71, 1, IO_TYPE_1V8), 983 K1_FUNC_PIN(72, 1, IO_TYPE_1V8), 984 K1_FUNC_PIN(73, 1, IO_TYPE_1V8), 985 K1_FUNC_PIN(74, 0, IO_TYPE_1V8), 986 K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL), 987 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), 988 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), 989 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), 990 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), 991 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), 992 K1_FUNC_PIN(81, 0, IO_TYPE_1V8), 993 K1_FUNC_PIN(82, 0, IO_TYPE_1V8), 994 K1_FUNC_PIN(83, 0, IO_TYPE_1V8), 995 K1_FUNC_PIN(84, 0, IO_TYPE_1V8), 996 K1_FUNC_PIN(85, 0, IO_TYPE_1V8), 997 K1_FUNC_PIN(86, 0, IO_TYPE_1V8), 998 K1_FUNC_PIN(87, 0, IO_TYPE_1V8), 999 K1_FUNC_PIN(88, 0, IO_TYPE_1V8), 1000 K1_FUNC_PIN(89, 0, IO_TYPE_1V8), 1001 K1_FUNC_PIN(90, 0, IO_TYPE_1V8), 1002 K1_FUNC_PIN(91, 0, IO_TYPE_1V8), 1003 K1_FUNC_PIN(92, 0, IO_TYPE_1V8), 1004 K1_FUNC_PIN(93, 1, IO_TYPE_1V8), 1005 K1_FUNC_PIN(94, 1, IO_TYPE_1V8), 1006 K1_FUNC_PIN(95, 1, IO_TYPE_1V8), 1007 K1_FUNC_PIN(96, 1, IO_TYPE_1V8), 1008 K1_FUNC_PIN(97, 1, IO_TYPE_1V8), 1009 K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL), 1010 K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL), 1011 K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL), 1012 K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL), 1013 K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL), 1014 K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL), 1015 K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL), 1016 K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL), 1017 K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL), 1018 K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL), 1019 K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL), 1020 K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL), 1021 K1_FUNC_PIN(110, 0, IO_TYPE_1V8), 1022 K1_FUNC_PIN(111, 0, IO_TYPE_1V8), 1023 K1_FUNC_PIN(112, 0, IO_TYPE_1V8), 1024 K1_FUNC_PIN(113, 0, IO_TYPE_1V8), 1025 K1_FUNC_PIN(114, 0, IO_TYPE_1V8), 1026 K1_FUNC_PIN(115, 0, IO_TYPE_1V8), 1027 K1_FUNC_PIN(116, 0, IO_TYPE_1V8), 1028 K1_FUNC_PIN(117, 0, IO_TYPE_1V8), 1029 K1_FUNC_PIN(118, 0, IO_TYPE_1V8), 1030 K1_FUNC_PIN(119, 0, IO_TYPE_1V8), 1031 K1_FUNC_PIN(120, 0, IO_TYPE_1V8), 1032 K1_FUNC_PIN(121, 0, IO_TYPE_1V8), 1033 K1_FUNC_PIN(122, 0, IO_TYPE_1V8), 1034 K1_FUNC_PIN(123, 0, IO_TYPE_1V8), 1035 K1_FUNC_PIN(124, 0, IO_TYPE_1V8), 1036 K1_FUNC_PIN(125, 0, IO_TYPE_1V8), 1037 K1_FUNC_PIN(126, 0, IO_TYPE_1V8), 1038 K1_FUNC_PIN(127, 0, IO_TYPE_1V8), 1039}; 1040 1041static const struct spacemit_pinctrl_data k1_pinctrl_data = { 1042 .pins = k1_pin_desc, 1043 .data = k1_pin_data, 1044 .npins = ARRAY_SIZE(k1_pin_desc), 1045}; 1046 1047static const struct of_device_id k1_pinctrl_ids[] = { 1048 { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data }, 1049 { /* sentinel */ } 1050}; 1051MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); 1052 1053static struct platform_driver k1_pinctrl_driver = { 1054 .probe = spacemit_pinctrl_probe, 1055 .driver = { 1056 .name = "k1-pinctrl", 1057 .suppress_bind_attrs = true, 1058 .of_match_table = k1_pinctrl_ids, 1059 }, 1060}; 1061builtin_platform_driver(k1_pinctrl_driver); 1062 1063MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>"); 1064MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); 1065MODULE_LICENSE("GPL");
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