pinctrl-exynos.c

   1// SPDX-License-Identifier: GPL-2.0+
   2//
   3// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   4//
   5// Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6//		http://www.samsung.com
   7// Copyright (c) 2012 Linaro Ltd
   8//		http://www.linaro.org
   9//
  10// Author: Thomas Abraham <thomas.ab@samsung.com>
  11//
  12// This file contains the Samsung Exynos specific information required by the
  13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  14// external gpio and wakeup interrupt support.
  15
  16#include <linux/clk.h>
  17#include <linux/device.h>
  18#include <linux/interrupt.h>
  19#include <linux/irqdomain.h>
  20#include <linux/irq.h>
  21#include <linux/irqchip/chained_irq.h>
  22#include <linux/of.h>
  23#include <linux/of_irq.h>
  24#include <linux/slab.h>
  25#include <linux/spinlock.h>
  26#include <linux/string_choices.h>
  27#include <linux/regmap.h>
  28#include <linux/err.h>
  29#include <linux/soc/samsung/exynos-pmu.h>
  30#include <linux/soc/samsung/exynos-regs-pmu.h>
  31
  32#include "pinctrl-samsung.h"
  33#include "pinctrl-exynos.h"
  34
  35#define MAX_WAKEUP_REG 3
  36
  37struct exynos_irq_chip {
  38	struct irq_chip chip;
  39
  40	u32 eint_con;
  41	u32 eint_mask;
  42	u32 eint_pend;
  43	u32 eint_num_wakeup_reg;
  44	u32 eint_wake_mask_reg;
  45	void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata,
  46				     struct exynos_irq_chip *irq_chip);
  47};
  48
  49static u32 eint_wake_mask_values[MAX_WAKEUP_REG] = { EXYNOS_EINT_WAKEUP_MASK_DISABLED,
  50						     EXYNOS_EINT_WAKEUP_MASK_DISABLED,
  51						     EXYNOS_EINT_WAKEUP_MASK_DISABLED};
  52
  53static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
  54{
  55	return container_of(chip, struct exynos_irq_chip, chip);
  56}
  57
  58static void exynos_irq_mask(struct irq_data *irqd)
  59{
  60	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  61	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  62	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  63	unsigned long reg_mask;
  64	unsigned int mask;
  65	unsigned long flags;
  66
  67	if (bank->eint_mask_offset)
  68		reg_mask = bank->pctl_offset + bank->eint_mask_offset;
  69	else
  70		reg_mask = our_chip->eint_mask + bank->eint_offset;
  71
  72	if (clk_enable(bank->drvdata->pclk)) {
  73		dev_err(bank->gpio_chip.parent,
  74			"unable to enable clock for masking IRQ\n");
  75		return;
  76	}
  77
  78	raw_spin_lock_irqsave(&bank->slock, flags);
  79
  80	mask = readl(bank->eint_base + reg_mask);
  81	mask |= 1 << irqd->hwirq;
  82	writel(mask, bank->eint_base + reg_mask);
  83
  84	raw_spin_unlock_irqrestore(&bank->slock, flags);
  85
  86	clk_disable(bank->drvdata->pclk);
  87}
  88
  89static void exynos_irq_ack(struct irq_data *irqd)
  90{
  91	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
  92	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
  93	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  94	unsigned long reg_pend;
  95
  96	if (bank->eint_pend_offset)
  97		reg_pend = bank->pctl_offset + bank->eint_pend_offset;
  98	else
  99		reg_pend = our_chip->eint_pend + bank->eint_offset;
 100
 101	if (clk_enable(bank->drvdata->pclk)) {
 102		dev_err(bank->gpio_chip.parent,
 103			"unable to enable clock to ack IRQ\n");
 104		return;
 105	}
 106
 107	writel(1 << irqd->hwirq, bank->eint_base + reg_pend);
 108
 109	clk_disable(bank->drvdata->pclk);
 110}
 111
 112static void exynos_irq_unmask(struct irq_data *irqd)
 113{
 114	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 115	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 116	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 117	unsigned long reg_mask;
 118	unsigned int mask;
 119	unsigned long flags;
 120
 121	/*
 122	 * Ack level interrupts right before unmask
 123	 *
 124	 * If we don't do this we'll get a double-interrupt.  Level triggered
 125	 * interrupts must not fire an interrupt if the level is not
 126	 * _currently_ active, even if it was active while the interrupt was
 127	 * masked.
 128	 */
 129	if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
 130		exynos_irq_ack(irqd);
 131
 132	if (bank->eint_mask_offset)
 133		reg_mask = bank->pctl_offset + bank->eint_mask_offset;
 134	else
 135		reg_mask = our_chip->eint_mask + bank->eint_offset;
 136
 137	if (clk_enable(bank->drvdata->pclk)) {
 138		dev_err(bank->gpio_chip.parent,
 139			"unable to enable clock for unmasking IRQ\n");
 140		return;
 141	}
 142
 143	raw_spin_lock_irqsave(&bank->slock, flags);
 144
 145	mask = readl(bank->eint_base + reg_mask);
 146	mask &= ~(1 << irqd->hwirq);
 147	writel(mask, bank->eint_base + reg_mask);
 148
 149	raw_spin_unlock_irqrestore(&bank->slock, flags);
 150
 151	clk_disable(bank->drvdata->pclk);
 152}
 153
 154static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
 155{
 156	struct irq_chip *chip = irq_data_get_irq_chip(irqd);
 157	struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
 158	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 159	unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
 160	unsigned int con, trig_type;
 161	unsigned long reg_con;
 162	int ret;
 163
 164	switch (type) {
 165	case IRQ_TYPE_EDGE_RISING:
 166		trig_type = EXYNOS_EINT_EDGE_RISING;
 167		break;
 168	case IRQ_TYPE_EDGE_FALLING:
 169		trig_type = EXYNOS_EINT_EDGE_FALLING;
 170		break;
 171	case IRQ_TYPE_EDGE_BOTH:
 172		trig_type = EXYNOS_EINT_EDGE_BOTH;
 173		break;
 174	case IRQ_TYPE_LEVEL_HIGH:
 175		trig_type = EXYNOS_EINT_LEVEL_HIGH;
 176		break;
 177	case IRQ_TYPE_LEVEL_LOW:
 178		trig_type = EXYNOS_EINT_LEVEL_LOW;
 179		break;
 180	default:
 181		pr_err("unsupported external interrupt type\n");
 182		return -EINVAL;
 183	}
 184
 185	if (type & IRQ_TYPE_EDGE_BOTH)
 186		irq_set_handler_locked(irqd, handle_edge_irq);
 187	else
 188		irq_set_handler_locked(irqd, handle_level_irq);
 189
 190	if (bank->eint_con_offset)
 191		reg_con = bank->pctl_offset + bank->eint_con_offset;
 192	else
 193		reg_con = our_chip->eint_con + bank->eint_offset;
 194
 195	ret = clk_enable(bank->drvdata->pclk);
 196	if (ret) {
 197		dev_err(bank->gpio_chip.parent,
 198			"unable to enable clock for configuring IRQ type\n");
 199		return ret;
 200	}
 201
 202	con = readl(bank->eint_base + reg_con);
 203	con &= ~(EXYNOS_EINT_CON_MASK << shift);
 204	con |= trig_type << shift;
 205	writel(con, bank->eint_base + reg_con);
 206
 207	clk_disable(bank->drvdata->pclk);
 208
 209	return 0;
 210}
 211
 212static int exynos_irq_set_affinity(struct irq_data *irqd,
 213				   const struct cpumask *dest, bool force)
 214{
 215	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 216	struct samsung_pinctrl_drv_data *d = bank->drvdata;
 217	struct irq_data *parent = irq_get_irq_data(d->irq);
 218
 219	if (parent)
 220		return parent->chip->irq_set_affinity(parent, dest, force);
 221
 222	return -EINVAL;
 223}
 224
 225static int exynos_irq_request_resources(struct irq_data *irqd)
 226{
 227	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 228	const struct samsung_pin_bank_type *bank_type = bank->type;
 229	unsigned long reg_con, flags;
 230	unsigned int shift, mask, con;
 231	int ret;
 232
 233	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
 234	if (ret) {
 235		dev_err(bank->gpio_chip.parent,
 236			"unable to lock pin %s-%lu IRQ\n",
 237			bank->name, irqd->hwirq);
 238		return ret;
 239	}
 240
 241	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 242	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 243	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 244
 245	ret = clk_enable(bank->drvdata->pclk);
 246	if (ret) {
 247		dev_err(bank->gpio_chip.parent,
 248			"unable to enable clock for configuring pin %s-%lu\n",
 249			bank->name, irqd->hwirq);
 250		return ret;
 251	}
 252
 253	raw_spin_lock_irqsave(&bank->slock, flags);
 254
 255	con = readl(bank->pctl_base + reg_con);
 256	con &= ~(mask << shift);
 257	con |= EXYNOS_PIN_CON_FUNC_EINT << shift;
 258	writel(con, bank->pctl_base + reg_con);
 259
 260	raw_spin_unlock_irqrestore(&bank->slock, flags);
 261
 262	clk_disable(bank->drvdata->pclk);
 263
 264	return 0;
 265}
 266
 267static void exynos_irq_release_resources(struct irq_data *irqd)
 268{
 269	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 270	const struct samsung_pin_bank_type *bank_type = bank->type;
 271	unsigned long reg_con, flags;
 272	unsigned int shift, mask, con;
 273
 274	reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 275	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
 276	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 277
 278	if (clk_enable(bank->drvdata->pclk)) {
 279		dev_err(bank->gpio_chip.parent,
 280			"unable to enable clock for deconfiguring pin %s-%lu\n",
 281			bank->name, irqd->hwirq);
 282		return;
 283	}
 284
 285	raw_spin_lock_irqsave(&bank->slock, flags);
 286
 287	con = readl(bank->pctl_base + reg_con);
 288	con &= ~(mask << shift);
 289	con |= PIN_CON_FUNC_INPUT << shift;
 290	writel(con, bank->pctl_base + reg_con);
 291
 292	raw_spin_unlock_irqrestore(&bank->slock, flags);
 293
 294	clk_disable(bank->drvdata->pclk);
 295
 296	gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
 297}
 298
 299/*
 300 * irq_chip for gpio interrupts.
 301 */
 302static const struct exynos_irq_chip exynos_gpio_irq_chip __initconst = {
 303	.chip = {
 304		.name = "exynos_gpio_irq_chip",
 305		.irq_unmask = exynos_irq_unmask,
 306		.irq_mask = exynos_irq_mask,
 307		.irq_ack = exynos_irq_ack,
 308		.irq_set_type = exynos_irq_set_type,
 309		.irq_set_affinity = exynos_irq_set_affinity,
 310		.irq_request_resources = exynos_irq_request_resources,
 311		.irq_release_resources = exynos_irq_release_resources,
 312	},
 313	.eint_con = EXYNOS_GPIO_ECON_OFFSET,
 314	.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
 315	.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
 316	/* eint_wake_mask_values not used */
 317};
 318
 319static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
 320					irq_hw_number_t hw)
 321{
 322	struct samsung_pin_bank *b = h->host_data;
 323
 324	irq_set_chip_data(virq, b);
 325	irq_set_chip_and_handler(virq, &b->irq_chip->chip,
 326					handle_level_irq);
 327	return 0;
 328}
 329
 330/*
 331 * irq domain callbacks for external gpio and wakeup interrupt controllers.
 332 */
 333static const struct irq_domain_ops exynos_eint_irqd_ops = {
 334	.map	= exynos_eint_irq_map,
 335	.xlate	= irq_domain_xlate_twocell,
 336};
 337
 338static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 339{
 340	struct samsung_pinctrl_drv_data *d = data;
 341	struct samsung_pin_bank *bank = d->pin_banks;
 342	unsigned int svc, group, pin;
 343	int ret;
 344
 345	if (clk_enable(bank->drvdata->pclk)) {
 346		dev_err(bank->gpio_chip.parent,
 347			"unable to enable clock for handling IRQ\n");
 348		return IRQ_NONE;
 349	}
 350
 351	if (bank->eint_con_offset)
 352		svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET);
 353	else
 354		svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET);
 355
 356	clk_disable(bank->drvdata->pclk);
 357
 358	group = EXYNOS_SVC_GROUP(svc);
 359	pin = svc & EXYNOS_SVC_NUM_MASK;
 360
 361	if (!group)
 362		return IRQ_HANDLED;
 363	bank += (group - 1);
 364
 365	ret = generic_handle_domain_irq(bank->irq_domain, pin);
 366	if (ret)
 367		return IRQ_NONE;
 368
 369	return IRQ_HANDLED;
 370}
 371
 372struct exynos_eint_gpio_save {
 373	u32 eint_con;
 374	u32 eint_fltcon0;
 375	u32 eint_fltcon1;
 376	u32 eint_mask;
 377};
 378
 379static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con)
 380{
 381	unsigned int val, shift;
 382	int i;
 383
 384	val = readl(reg);
 385	for (i = 0; i < cnt; i++) {
 386		shift = i * EXYNOS_FLTCON_LEN;
 387		val &= ~(EXYNOS_FLTCON_DIGITAL << shift);
 388		val |= con << shift;
 389	}
 390	writel(val, reg);
 391}
 392
 393/*
 394 * Set the desired filter (digital or analog delay) and enable it to
 395 * every pin in the bank. Note the filter selection bitfield is only
 396 * found on alive banks. The filter determines to what extent signal
 397 * fluctuations received through the pad are considered glitches.
 398 */
 399static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter)
 400{
 401	unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset;
 402	void __iomem *reg = bank->drvdata->virt_base + off;
 403	unsigned int con = EXYNOS_FLTCON_EN | filter;
 404
 405	for (int n = 0; n < bank->nr_pins; n += 4)
 406		exynos_eint_update_flt_reg(reg + n,
 407					   min(bank->nr_pins - n, 4), con);
 408}
 409
 410/*
 411 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
 412 * @d: driver data of samsung pinctrl driver.
 413 */
 414__init int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 415{
 416	struct samsung_pin_bank *bank;
 417	struct device *dev = d->dev;
 418	int ret;
 419	int i;
 420
 421	if (!d->irq) {
 422		dev_err(dev, "irq number not available\n");
 423		return -EINVAL;
 424	}
 425
 426	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
 427					0, dev_name(dev), d);
 428	if (ret) {
 429		dev_err(dev, "irq request failed\n");
 430		return -ENXIO;
 431	}
 432
 433	bank = d->pin_banks;
 434	for (i = 0; i < d->nr_banks; ++i, ++bank) {
 435		if (bank->eint_type != EINT_TYPE_GPIO)
 436			continue;
 437
 438		bank->irq_chip = devm_kmemdup(dev, &exynos_gpio_irq_chip,
 439					   sizeof(*bank->irq_chip), GFP_KERNEL);
 440		if (!bank->irq_chip) {
 441			ret = -ENOMEM;
 442			goto err_domains;
 443		}
 444		bank->irq_chip->chip.name = bank->name;
 445
 446		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
 447				bank->nr_pins, &exynos_eint_irqd_ops, bank);
 448		if (!bank->irq_domain) {
 449			dev_err(dev, "gpio irq domain add failed\n");
 450			ret = -ENXIO;
 451			goto err_domains;
 452		}
 453
 454		bank->soc_priv = devm_kzalloc(d->dev,
 455			sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
 456		if (!bank->soc_priv) {
 457			irq_domain_remove(bank->irq_domain);
 458			ret = -ENOMEM;
 459			goto err_domains;
 460		}
 461
 462	}
 463
 464	return 0;
 465
 466err_domains:
 467	for (--i, --bank; i >= 0; --i, --bank) {
 468		if (bank->eint_type != EINT_TYPE_GPIO)
 469			continue;
 470		irq_domain_remove(bank->irq_domain);
 471	}
 472
 473	return ret;
 474}
 475
 476#define BITS_PER_U32 32
 477static int gs101_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 478{
 479	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 480	struct samsung_pinctrl_drv_data *d = bank->drvdata;
 481	u32 bit, wakeup_reg, shift;
 482
 483	bit = bank->eint_num + irqd->hwirq;
 484	wakeup_reg = bit / BITS_PER_U32;
 485	shift = bit - (wakeup_reg * BITS_PER_U32);
 486
 487	if (!on)
 488		eint_wake_mask_values[wakeup_reg] |= BIT_U32(shift);
 489	else
 490		eint_wake_mask_values[wakeup_reg] &= ~BIT_U32(shift);
 491
 492	dev_info(d->dev, "wake %s for irq %d\n", str_enabled_disabled(on),
 493		 irqd->irq);
 494
 495	return 0;
 496}
 497
 498static void
 499gs101_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
 500				   struct exynos_irq_chip *irq_chip)
 501{
 502	struct regmap *pmu_regs;
 503
 504	if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
 505		dev_warn(drvdata->dev,
 506			 "No PMU syscon available. Wake-up mask will not be set.\n");
 507		return;
 508	}
 509
 510	pmu_regs = drvdata->retention_ctrl->priv;
 511
 512	dev_dbg(drvdata->dev, "Setting external wakeup interrupt mask:\n");
 513
 514	for (int i = 0; i < irq_chip->eint_num_wakeup_reg; i++) {
 515		dev_dbg(drvdata->dev, "\tWAKEUP_MASK%d[0x%X] value[0x%X]\n",
 516			i, irq_chip->eint_wake_mask_reg + i * 4,
 517			eint_wake_mask_values[i]);
 518		regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg + i * 4,
 519			     eint_wake_mask_values[i]);
 520	}
 521}
 522
 523static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 524{
 525	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 526	unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
 527
 528	pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on),
 529		irqd->irq, bank->name, irqd->hwirq);
 530
 531	if (!on)
 532		eint_wake_mask_values[0] |= bit;
 533	else
 534		eint_wake_mask_values[0] &= ~bit;
 535
 536	return 0;
 537}
 538
 539static void
 540exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
 541				    struct exynos_irq_chip *irq_chip)
 542{
 543	struct regmap *pmu_regs;
 544
 545	if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
 546		dev_warn(drvdata->dev,
 547			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
 548		return;
 549	}
 550
 551	pmu_regs = drvdata->retention_ctrl->priv;
 552	dev_info(drvdata->dev,
 553		 "Setting external wakeup interrupt mask: 0x%x\n",
 554		 eint_wake_mask_values[0]);
 555
 556	regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
 557		     eint_wake_mask_values[0]);
 558}
 559
 560static void
 561s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
 562				    struct exynos_irq_chip *irq_chip)
 563
 564{
 565	void __iomem *clk_base;
 566
 567	if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
 568		dev_warn(drvdata->dev,
 569			 "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
 570		return;
 571	}
 572
 573
 574	clk_base = (void __iomem *) drvdata->retention_ctrl->priv;
 575
 576	__raw_writel(eint_wake_mask_values[0],
 577		     clk_base + irq_chip->eint_wake_mask_reg);
 578}
 579
 580/*
 581 * irq_chip for wakeup interrupts
 582 */
 583static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = {
 584	.chip = {
 585		.name = "s5pv210_wkup_irq_chip",
 586		.irq_unmask = exynos_irq_unmask,
 587		.irq_mask = exynos_irq_mask,
 588		.irq_ack = exynos_irq_ack,
 589		.irq_set_type = exynos_irq_set_type,
 590		.irq_set_wake = exynos_wkup_irq_set_wake,
 591		.irq_request_resources = exynos_irq_request_resources,
 592		.irq_release_resources = exynos_irq_release_resources,
 593	},
 594	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
 595	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
 596	.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
 597	.eint_num_wakeup_reg = 1,
 598	/* Only differences with exynos4210_wkup_irq_chip: */
 599	.eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
 600	.set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask,
 601};
 602
 603static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
 604	.chip = {
 605		.name = "exynos4210_wkup_irq_chip",
 606		.irq_unmask = exynos_irq_unmask,
 607		.irq_mask = exynos_irq_mask,
 608		.irq_ack = exynos_irq_ack,
 609		.irq_set_type = exynos_irq_set_type,
 610		.irq_set_wake = exynos_wkup_irq_set_wake,
 611		.irq_request_resources = exynos_irq_request_resources,
 612		.irq_release_resources = exynos_irq_release_resources,
 613	},
 614	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
 615	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
 616	.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
 617	.eint_num_wakeup_reg = 1,
 618	.eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
 619	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
 620};
 621
 622static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
 623	.chip = {
 624		.name = "exynos7_wkup_irq_chip",
 625		.irq_unmask = exynos_irq_unmask,
 626		.irq_mask = exynos_irq_mask,
 627		.irq_ack = exynos_irq_ack,
 628		.irq_set_type = exynos_irq_set_type,
 629		.irq_set_wake = exynos_wkup_irq_set_wake,
 630		.irq_request_resources = exynos_irq_request_resources,
 631		.irq_release_resources = exynos_irq_release_resources,
 632	},
 633	.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
 634	.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
 635	.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
 636	.eint_num_wakeup_reg = 1,
 637	.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
 638	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
 639};
 640
 641static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = {
 642	.chip = {
 643		.name = "exynosautov920_wkup_irq_chip",
 644		.irq_unmask = exynos_irq_unmask,
 645		.irq_mask = exynos_irq_mask,
 646		.irq_ack = exynos_irq_ack,
 647		.irq_set_type = exynos_irq_set_type,
 648		.irq_set_wake = exynos_wkup_irq_set_wake,
 649		.irq_request_resources = exynos_irq_request_resources,
 650		.irq_release_resources = exynos_irq_release_resources,
 651	},
 652	.eint_num_wakeup_reg = 1,
 653	.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
 654	.set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask,
 655};
 656
 657static const struct exynos_irq_chip gs101_wkup_irq_chip __initconst = {
 658	.chip = {
 659		.name = "gs101_wkup_irq_chip",
 660		.irq_unmask = exynos_irq_unmask,
 661		.irq_mask = exynos_irq_mask,
 662		.irq_ack = exynos_irq_ack,
 663		.irq_set_type = exynos_irq_set_type,
 664		.irq_set_wake = gs101_wkup_irq_set_wake,
 665		.irq_request_resources = exynos_irq_request_resources,
 666		.irq_release_resources = exynos_irq_release_resources,
 667	},
 668	.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
 669	.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
 670	.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
 671	.eint_num_wakeup_reg = 3,
 672	.eint_wake_mask_reg = GS101_EINT_WAKEUP_MASK,
 673	.set_eint_wakeup_mask = gs101_pinctrl_set_eint_wakeup_mask,
 674};
 675
 676/* list of external wakeup controllers supported */
 677static const struct of_device_id exynos_wkup_irq_ids[] = {
 678	{ .compatible = "google,gs101-wakeup-eint",
 679			.data = &gs101_wkup_irq_chip },
 680	{ .compatible = "samsung,s5pv210-wakeup-eint",
 681			.data = &s5pv210_wkup_irq_chip },
 682	{ .compatible = "samsung,exynos4210-wakeup-eint",
 683			.data = &exynos4210_wkup_irq_chip },
 684	{ .compatible = "samsung,exynos7-wakeup-eint",
 685			.data = &exynos7_wkup_irq_chip },
 686	{ .compatible = "samsung,exynos850-wakeup-eint",
 687			.data = &exynos7_wkup_irq_chip },
 688	{ .compatible = "samsung,exynosautov9-wakeup-eint",
 689			.data = &exynos7_wkup_irq_chip },
 690	{ .compatible = "samsung,exynosautov920-wakeup-eint",
 691			.data = &exynosautov920_wkup_irq_chip },
 692	{ }
 693};
 694
 695/* interrupt handler for wakeup interrupts 0..15 */
 696static void exynos_irq_eint0_15(struct irq_desc *desc)
 697{
 698	struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
 699	struct samsung_pin_bank *bank = eintd->bank;
 700	struct irq_chip *chip = irq_desc_get_chip(desc);
 701
 702	chained_irq_enter(chip, desc);
 703
 704	generic_handle_domain_irq(bank->irq_domain, eintd->irq);
 705
 706	chained_irq_exit(chip, desc);
 707}
 708
 709static inline void exynos_irq_demux_eint(unsigned int pend,
 710						struct irq_domain *domain)
 711{
 712	unsigned int irq;
 713
 714	while (pend) {
 715		irq = fls(pend) - 1;
 716		generic_handle_domain_irq(domain, irq);
 717		pend &= ~(1 << irq);
 718	}
 719}
 720
 721/* interrupt handler for wakeup interrupt 16 */
 722static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
 723{
 724	struct irq_chip *chip = irq_desc_get_chip(desc);
 725	struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
 726	unsigned int pend;
 727	unsigned int mask;
 728	int i;
 729
 730	chained_irq_enter(chip, desc);
 731
 732	/*
 733	 * just enable the clock once here, to avoid an enable/disable dance for
 734	 * each bank.
 735	 */
 736	if (eintd->nr_banks) {
 737		struct samsung_pin_bank *b = eintd->banks[0];
 738
 739		if (clk_enable(b->drvdata->pclk)) {
 740			dev_err(b->gpio_chip.parent,
 741				"unable to enable clock for pending IRQs\n");
 742			goto out;
 743		}
 744	}
 745
 746	for (i = 0; i < eintd->nr_banks; ++i) {
 747		struct samsung_pin_bank *b = eintd->banks[i];
 748		pend = readl(b->eint_base + b->irq_chip->eint_pend
 749				+ b->eint_offset);
 750		mask = readl(b->eint_base + b->irq_chip->eint_mask
 751				+ b->eint_offset);
 752		exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
 753	}
 754
 755	if (eintd->nr_banks)
 756		clk_disable(eintd->banks[0]->drvdata->pclk);
 757
 758out:
 759	chained_irq_exit(chip, desc);
 760}
 761
 762static int eint_num;
 763/*
 764 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
 765 * @d: driver data of samsung pinctrl driver.
 766 */
 767__init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 768{
 769	struct device *dev = d->dev;
 770	struct device_node *wkup_np __free(device_node) = NULL;
 771	struct device_node *np;
 772	struct samsung_pin_bank *bank;
 773	struct exynos_weint_data *weint_data;
 774	struct exynos_muxed_weint_data *muxed_data;
 775	const struct exynos_irq_chip *irq_chip;
 776	unsigned int muxed_banks = 0;
 777	unsigned int i;
 778	int idx, irq;
 779
 780	for_each_child_of_node(dev->of_node, np) {
 781		const struct of_device_id *match;
 782
 783		match = of_match_node(exynos_wkup_irq_ids, np);
 784		if (match) {
 785			irq_chip = match->data;
 786			wkup_np = np;
 787			break;
 788		}
 789	}
 790	if (!wkup_np)
 791		return -ENODEV;
 792
 793	bank = d->pin_banks;
 794	for (i = 0; i < d->nr_banks; ++i, ++bank) {
 795		if (bank->eint_type != EINT_TYPE_WKUP)
 796			continue;
 797
 798		bank->irq_chip = devm_kmemdup(dev, irq_chip, sizeof(*irq_chip),
 799					      GFP_KERNEL);
 800		if (!bank->irq_chip)
 801			return -ENOMEM;
 802		bank->irq_chip->chip.name = bank->name;
 803
 804		bank->irq_domain = irq_domain_create_linear(bank->fwnode,
 805				bank->nr_pins, &exynos_eint_irqd_ops, bank);
 806		if (!bank->irq_domain) {
 807			dev_err(dev, "wkup irq domain add failed\n");
 808			return -ENXIO;
 809		}
 810
 811		bank->eint_num = eint_num;
 812		eint_num = eint_num + bank->nr_pins;
 813
 814		if (!fwnode_property_present(bank->fwnode, "interrupts")) {
 815			bank->eint_type = EINT_TYPE_WKUP_MUX;
 816			++muxed_banks;
 817			continue;
 818		}
 819
 820		weint_data = devm_kcalloc(dev,
 821					  bank->nr_pins, sizeof(*weint_data),
 822					  GFP_KERNEL);
 823		if (!weint_data)
 824			return -ENOMEM;
 825
 826		for (idx = 0; idx < bank->nr_pins; ++idx) {
 827			irq = irq_of_parse_and_map(to_of_node(bank->fwnode), idx);
 828			if (!irq) {
 829				dev_err(dev, "irq number for eint-%s-%d not found\n",
 830							bank->name, idx);
 831				continue;
 832			}
 833			weint_data[idx].irq = idx;
 834			weint_data[idx].bank = bank;
 835			irq_set_chained_handler_and_data(irq,
 836							 exynos_irq_eint0_15,
 837							 &weint_data[idx]);
 838		}
 839	}
 840
 841	if (!muxed_banks)
 842		return 0;
 843
 844	irq = irq_of_parse_and_map(wkup_np, 0);
 845	if (!irq) {
 846		dev_err(dev, "irq number for muxed EINTs not found\n");
 847		return 0;
 848	}
 849
 850	muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
 851		+ muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
 852	if (!muxed_data)
 853		return -ENOMEM;
 854	muxed_data->nr_banks = muxed_banks;
 855
 856	irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
 857					 muxed_data);
 858
 859	bank = d->pin_banks;
 860	idx = 0;
 861	for (i = 0; i < d->nr_banks; ++i, ++bank) {
 862		if (bank->eint_type != EINT_TYPE_WKUP_MUX)
 863			continue;
 864
 865		muxed_data->banks[idx++] = bank;
 866	}
 867
 868	return 0;
 869}
 870
 871static void exynos_set_wakeup(struct samsung_pin_bank *bank)
 872{
 873	struct exynos_irq_chip *irq_chip;
 874
 875	if (bank->irq_chip) {
 876		irq_chip = bank->irq_chip;
 877		irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
 878	}
 879}
 880
 881void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
 882{
 883	struct exynos_eint_gpio_save *save = bank->soc_priv;
 884	const void __iomem *regs = bank->eint_base;
 885
 886	if (bank->eint_type == EINT_TYPE_GPIO) {
 887		save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 888				       + bank->eint_offset);
 889		save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 890					   + 2 * bank->eint_offset);
 891		save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 892					   + 2 * bank->eint_offset + 4);
 893		save->eint_mask = readl(regs + bank->irq_chip->eint_mask
 894					+ bank->eint_offset);
 895
 896		pr_debug("%s: save     con %#010x\n",
 897			 bank->name, save->eint_con);
 898		pr_debug("%s: save fltcon0 %#010x\n",
 899			 bank->name, save->eint_fltcon0);
 900		pr_debug("%s: save fltcon1 %#010x\n",
 901			 bank->name, save->eint_fltcon1);
 902		pr_debug("%s: save    mask %#010x\n",
 903			 bank->name, save->eint_mask);
 904	} else if (bank->eint_type == EINT_TYPE_WKUP) {
 905		exynos_set_wakeup(bank);
 906	}
 907}
 908
 909void gs101_pinctrl_suspend(struct samsung_pin_bank *bank)
 910{
 911	struct exynos_eint_gpio_save *save = bank->soc_priv;
 912	const void __iomem *regs = bank->eint_base;
 913
 914	if (bank->eint_type == EINT_TYPE_GPIO) {
 915		save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 916				       + bank->eint_offset);
 917
 918		save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 919					   + bank->eint_fltcon_offset);
 920
 921		/* fltcon1 register only exists for pins 4-7 */
 922		if (bank->nr_pins > 4)
 923			save->eint_fltcon1 = readl(regs +
 924						EXYNOS_GPIO_EFLTCON_OFFSET
 925						+ bank->eint_fltcon_offset + 4);
 926
 927		save->eint_mask = readl(regs + bank->irq_chip->eint_mask
 928					+ bank->eint_offset);
 929
 930		pr_debug("%s: save     con %#010x\n",
 931			 bank->name, save->eint_con);
 932		pr_debug("%s: save fltcon0 %#010x\n",
 933			 bank->name, save->eint_fltcon0);
 934		if (bank->nr_pins > 4)
 935			pr_debug("%s: save fltcon1 %#010x\n",
 936				 bank->name, save->eint_fltcon1);
 937		pr_debug("%s: save    mask %#010x\n",
 938			 bank->name, save->eint_mask);
 939	} else if (bank->eint_type == EINT_TYPE_WKUP) {
 940		exynos_set_wakeup(bank);
 941		exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG);
 942	}
 943}
 944
 945void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
 946{
 947	struct exynos_eint_gpio_save *save = bank->soc_priv;
 948	const void __iomem *regs = bank->eint_base;
 949
 950	if (bank->eint_type == EINT_TYPE_GPIO) {
 951		save->eint_con = readl(regs + bank->pctl_offset +
 952				       bank->eint_con_offset);
 953		save->eint_mask = readl(regs + bank->pctl_offset +
 954					bank->eint_mask_offset);
 955		pr_debug("%s: save     con %#010x\n",
 956			 bank->name, save->eint_con);
 957		pr_debug("%s: save    mask %#010x\n",
 958			 bank->name, save->eint_mask);
 959	} else if (bank->eint_type == EINT_TYPE_WKUP) {
 960		exynos_set_wakeup(bank);
 961	}
 962}
 963
 964void gs101_pinctrl_resume(struct samsung_pin_bank *bank)
 965{
 966	struct exynos_eint_gpio_save *save = bank->soc_priv;
 967
 968	void __iomem *regs = bank->eint_base;
 969	void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET
 970		     + bank->eint_fltcon_offset;
 971
 972	if (bank->eint_type == EINT_TYPE_GPIO) {
 973		pr_debug("%s:     con %#010x => %#010x\n", bank->name,
 974			 readl(regs + EXYNOS_GPIO_ECON_OFFSET
 975			       + bank->eint_offset), save->eint_con);
 976
 977		pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
 978			 readl(eint_fltcfg0), save->eint_fltcon0);
 979
 980		/* fltcon1 register only exists for pins 4-7 */
 981		if (bank->nr_pins > 4)
 982			pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 983				 readl(eint_fltcfg0 + 4), save->eint_fltcon1);
 984
 985		pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
 986			 readl(regs + bank->irq_chip->eint_mask
 987			       + bank->eint_offset), save->eint_mask);
 988
 989		writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 990		       + bank->eint_offset);
 991		writel(save->eint_fltcon0, eint_fltcfg0);
 992
 993		if (bank->nr_pins > 4)
 994			writel(save->eint_fltcon1, eint_fltcfg0 + 4);
 995		writel(save->eint_mask, regs + bank->irq_chip->eint_mask
 996		       + bank->eint_offset);
 997	} else if (bank->eint_type == EINT_TYPE_WKUP) {
 998		exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL);
 999	}
1000}
1001
1002void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
1003{
1004	struct exynos_eint_gpio_save *save = bank->soc_priv;
1005	void __iomem *regs = bank->eint_base;
1006
1007	if (bank->eint_type == EINT_TYPE_GPIO) {
1008		pr_debug("%s:     con %#010x => %#010x\n", bank->name,
1009			 readl(regs + EXYNOS_GPIO_ECON_OFFSET
1010			       + bank->eint_offset), save->eint_con);
1011		pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
1012			 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
1013			       + 2 * bank->eint_offset), save->eint_fltcon0);
1014		pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
1015			 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
1016			       + 2 * bank->eint_offset + 4),
1017			 save->eint_fltcon1);
1018		pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
1019			 readl(regs + bank->irq_chip->eint_mask
1020			       + bank->eint_offset), save->eint_mask);
1021
1022		writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
1023		       + bank->eint_offset);
1024		writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
1025		       + 2 * bank->eint_offset);
1026		writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
1027		       + 2 * bank->eint_offset + 4);
1028		writel(save->eint_mask, regs + bank->irq_chip->eint_mask
1029		       + bank->eint_offset);
1030	}
1031}
1032
1033void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
1034{
1035	struct exynos_eint_gpio_save *save = bank->soc_priv;
1036	void __iomem *regs = bank->eint_base;
1037
1038	if (bank->eint_type == EINT_TYPE_GPIO) {
1039		/* exynosautov920 has eint_con_offset for all but one bank */
1040		if (!bank->eint_con_offset)
1041			exynos_pinctrl_resume(bank);
1042
1043		pr_debug("%s:     con %#010x => %#010x\n", bank->name,
1044			 readl(regs + bank->pctl_offset + bank->eint_con_offset),
1045			 save->eint_con);
1046		pr_debug("%s:    mask %#010x => %#010x\n", bank->name,
1047			 readl(regs + bank->pctl_offset +
1048			       bank->eint_mask_offset), save->eint_mask);
1049
1050		writel(save->eint_con,
1051		       regs + bank->pctl_offset + bank->eint_con_offset);
1052		writel(save->eint_mask,
1053		       regs + bank->pctl_offset + bank->eint_mask_offset);
1054	}
1055}
1056
1057static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
1058{
1059	if (drvdata->retention_ctrl->refcnt)
1060		atomic_inc(drvdata->retention_ctrl->refcnt);
1061}
1062
1063static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
1064{
1065	struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl;
1066	struct regmap *pmu_regs = ctrl->priv;
1067	int i;
1068
1069	if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt))
1070		return;
1071
1072	for (i = 0; i < ctrl->nr_regs; i++)
1073		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
1074}
1075
1076struct samsung_retention_ctrl *
1077exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
1078		      const struct samsung_retention_data *data)
1079{
1080	struct samsung_retention_ctrl *ctrl;
1081	struct regmap *pmu_regs;
1082	int i;
1083
1084	ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
1085	if (!ctrl)
1086		return ERR_PTR(-ENOMEM);
1087
1088	pmu_regs = exynos_get_pmu_regmap();
1089	if (IS_ERR(pmu_regs))
1090		return ERR_CAST(pmu_regs);
1091
1092	ctrl->priv = pmu_regs;
1093	ctrl->regs = data->regs;
1094	ctrl->nr_regs = data->nr_regs;
1095	ctrl->value = data->value;
1096	ctrl->refcnt = data->refcnt;
1097	ctrl->enable = exynos_retention_enable;
1098	ctrl->disable = exynos_retention_disable;
1099
1100	/* Ensure that retention is disabled on driver init */
1101	for (i = 0; i < ctrl->nr_regs; i++)
1102		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
1103
1104	return ctrl;
1105}