pinctrl-rzt2h.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RZ/T2H Pin Control and GPIO driver core
  4 *
  5 * Based on drivers/pinctrl/renesas/pinctrl-rzg2l.c
  6 *
  7 * Copyright (C) 2025 Renesas Electronics Corporation.
  8 */
  9
 10#include <linux/bitfield.h>
 11#include <linux/bitops.h>
 12#include <linux/bits.h>
 13#include <linux/cleanup.h>
 14#include <linux/clk.h>
 15#include <linux/gpio/driver.h>
 16#include <linux/io.h>
 17#include <linux/ioport.h>
 18#include <linux/module.h>
 19#include <linux/mutex.h>
 20#include <linux/of_device.h>
 21#include <linux/platform_device.h>
 22#include <linux/pm_runtime.h>
 23#include <linux/spinlock.h>
 24#include <linux/types.h>
 25
 26#include <linux/pinctrl/consumer.h>
 27#include <linux/pinctrl/pinconf-generic.h>
 28#include <linux/pinctrl/pinconf.h>
 29#include <linux/pinctrl/pinctrl.h>
 30#include <linux/pinctrl/pinmux.h>
 31
 32#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
 33
 34#include "../core.h"
 35#include "../pinconf.h"
 36#include "../pinmux.h"
 37
 38#define DRV_NAME	"pinctrl-rzt2h"
 39
 40#define P(m)		(0x001 * (m))
 41#define PM(m)		(0x200 + 2 * (m))
 42#define PMC(m)		(0x400 + (m))
 43#define PFC(m)		(0x600 + 8 * (m))
 44#define PIN(m)		(0x800 + (m))
 45#define RSELP(m)	(0xc00 + (m))
 46
 47#define PM_MASK			GENMASK(1, 0)
 48#define PM_PIN_MASK(pin)	(PM_MASK << ((pin) * 2))
 49#define PM_INPUT		BIT(0)
 50#define PM_OUTPUT		BIT(1)
 51
 52#define PFC_MASK		GENMASK_ULL(5, 0)
 53#define PFC_PIN_MASK(pin)	(PFC_MASK << ((pin) * 8))
 54#define PFC_FUNC_INTERRUPT	0
 55
 56/*
 57 * Use 16 lower bits [15:0] for pin identifier
 58 * Use 8 higher bits [23:16] for pin mux function
 59 */
 60#define MUX_PIN_ID_MASK		GENMASK(15, 0)
 61#define MUX_FUNC_MASK		GENMASK(23, 16)
 62
 63#define RZT2H_PIN_ID_TO_PORT(id)	((id) / RZT2H_PINS_PER_PORT)
 64#define RZT2H_PIN_ID_TO_PIN(id)		((id) % RZT2H_PINS_PER_PORT)
 65
 66#define RZT2H_MAX_SAFETY_PORTS		12
 67
 68struct rzt2h_pinctrl_data {
 69	unsigned int n_port_pins;
 70	const u8 *port_pin_configs;
 71	unsigned int n_ports;
 72};
 73
 74struct rzt2h_pinctrl {
 75	struct pinctrl_dev		*pctl;
 76	struct pinctrl_desc		desc;
 77	struct pinctrl_pin_desc		*pins;
 78	const struct rzt2h_pinctrl_data	*data;
 79	void __iomem			*base0, *base1;
 80	struct device			*dev;
 81	struct gpio_chip		gpio_chip;
 82	struct pinctrl_gpio_range	gpio_range;
 83	spinlock_t			lock; /* lock read/write registers */
 84	struct mutex			mutex; /* serialize adding groups and functions */
 85	bool				safety_port_enabled;
 86};
 87
 88#define RZT2H_GET_BASE(pctrl, port) \
 89	((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
 90
 91#define RZT2H_PINCTRL_REG_ACCESS(size, type)						\
 92static inline void rzt2h_pinctrl_write##size(struct rzt2h_pinctrl *pctrl, u8 port,	\
 93					     type val, unsigned int offset)		\
 94{											\
 95	write##size(val, RZT2H_GET_BASE(pctrl, port) + offset);				\
 96}											\
 97static inline type rzt2h_pinctrl_read##size(struct rzt2h_pinctrl *pctrl, u8 port,	\
 98					    unsigned int offset)			\
 99{											\
100	return read##size(RZT2H_GET_BASE(pctrl, port) + offset);			\
101}
102
103RZT2H_PINCTRL_REG_ACCESS(b, u8)
104RZT2H_PINCTRL_REG_ACCESS(w, u16)
105RZT2H_PINCTRL_REG_ACCESS(q, u64)
106
107static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
108{
109	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
110	u8 pin = RZT2H_PIN_ID_TO_PIN(offset);
111	u8 pincfg;
112
113	if (offset >= pctrl->data->n_port_pins || port >= pctrl->data->n_ports)
114		return -EINVAL;
115
116	if (!pctrl->safety_port_enabled && port <= RZT2H_MAX_SAFETY_PORTS)
117		return -EINVAL;
118
119	pincfg = pctrl->data->port_pin_configs[port];
120	return (pincfg & BIT(pin)) ? 0 : -EINVAL;
121}
122
123static void rzt2h_pinctrl_set_pfc_mode(struct rzt2h_pinctrl *pctrl,
124				       u8 port, u8 pin, u8 func)
125{
126	u64 reg64;
127	u16 reg16;
128
129	guard(spinlock_irqsave)(&pctrl->lock);
130
131	/* Set pin to 'Non-use (Hi-Z input protection)'  */
132	reg16 = rzt2h_pinctrl_readw(pctrl, port, PM(port));
133	reg16 &= ~PM_PIN_MASK(pin);
134	rzt2h_pinctrl_writew(pctrl, port, reg16, PM(port));
135
136	/* Temporarily switch to GPIO mode with PMC register */
137	reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
138	rzt2h_pinctrl_writeb(pctrl, port, reg16 & ~BIT(pin), PMC(port));
139
140	/* Select Pin function mode with PFC register */
141	reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
142	reg64 &= ~PFC_PIN_MASK(pin);
143	rzt2h_pinctrl_writeq(pctrl, port, reg64 | ((u64)func << (pin * 8)), PFC(port));
144
145	/* Switch to Peripheral pin function with PMC register */
146	reg16 = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
147	rzt2h_pinctrl_writeb(pctrl, port, reg16 | BIT(pin), PMC(port));
148}
149
150static int rzt2h_pinctrl_set_mux(struct pinctrl_dev *pctldev,
151				 unsigned int func_selector,
152				 unsigned int group_selector)
153{
154	struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
155	const struct function_desc *func;
156	struct group_desc *group;
157	const unsigned int *pins;
158	unsigned int i;
159	u8 *psel_val;
160	int ret;
161
162	func = pinmux_generic_get_function(pctldev, func_selector);
163	if (!func)
164		return -EINVAL;
165
166	group = pinctrl_generic_get_group(pctldev, group_selector);
167	if (!group)
168		return -EINVAL;
169
170	psel_val = func->data;
171	pins = group->grp.pins;
172
173	for (i = 0; i < group->grp.npins; i++) {
174		dev_dbg(pctrl->dev, "port:%u pin:%u PSEL:%u\n",
175			RZT2H_PIN_ID_TO_PORT(pins[i]), RZT2H_PIN_ID_TO_PIN(pins[i]),
176			psel_val[i]);
177		ret = rzt2h_validate_pin(pctrl, pins[i]);
178		if (ret)
179			return ret;
180
181		rzt2h_pinctrl_set_pfc_mode(pctrl, RZT2H_PIN_ID_TO_PORT(pins[i]),
182					   RZT2H_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
183	}
184
185	return 0;
186}
187
188static int rzt2h_map_add_config(struct pinctrl_map *map,
189				const char *group_or_pin,
190				enum pinctrl_map_type type,
191				unsigned long *configs,
192				unsigned int num_configs)
193{
194	unsigned long *cfgs;
195
196	cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
197	if (!cfgs)
198		return -ENOMEM;
199
200	map->type = type;
201	map->data.configs.group_or_pin = group_or_pin;
202	map->data.configs.configs = cfgs;
203	map->data.configs.num_configs = num_configs;
204
205	return 0;
206}
207
208static int rzt2h_dt_subnode_to_map(struct pinctrl_dev *pctldev,
209				   struct device_node *np,
210				   struct device_node *parent,
211				   struct pinctrl_map **map,
212				   unsigned int *num_maps,
213				   unsigned int *index)
214{
215	struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
216	struct pinctrl_map *maps = *map;
217	unsigned int nmaps = *num_maps;
218	unsigned long *configs = NULL;
219	unsigned int num_pinmux = 0;
220	unsigned int idx = *index;
221	unsigned int num_pins, i;
222	unsigned int num_configs;
223	struct property *pinmux;
224	struct property *prop;
225	int ret, gsel, fsel;
226	const char **pin_fn;
227	unsigned int *pins;
228	const char *name;
229	const char *pin;
230	u8 *psel_val;
231
232	pinmux = of_find_property(np, "pinmux", NULL);
233	if (pinmux)
234		num_pinmux = pinmux->length / sizeof(u32);
235
236	ret = of_property_count_strings(np, "pins");
237	if (ret == -EINVAL) {
238		num_pins = 0;
239	} else if (ret < 0) {
240		dev_err(pctrl->dev, "Invalid pins list in DT\n");
241		return ret;
242	} else {
243		num_pins = ret;
244	}
245
246	if (!num_pinmux && !num_pins)
247		return 0;
248
249	if (num_pinmux && num_pins) {
250		dev_err(pctrl->dev,
251			"DT node must contain either a pinmux or pins and not both\n");
252		return -EINVAL;
253	}
254
255	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
256	if (ret < 0)
257		return ret;
258
259	if (num_pins && !num_configs) {
260		dev_err(pctrl->dev, "DT node must contain a config\n");
261		ret = -ENODEV;
262		goto done;
263	}
264
265	if (num_pinmux) {
266		nmaps += 1;
267		if (num_configs)
268			nmaps += 1;
269	}
270
271	if (num_pins)
272		nmaps += num_pins;
273
274	maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
275	if (!maps) {
276		ret = -ENOMEM;
277		goto done;
278	}
279
280	*map = maps;
281	*num_maps = nmaps;
282	if (num_pins) {
283		of_property_for_each_string(np, "pins", prop, pin) {
284			ret = rzt2h_map_add_config(&maps[idx], pin,
285						   PIN_MAP_TYPE_CONFIGS_PIN,
286						   configs, num_configs);
287			if (ret < 0)
288				goto done;
289
290			idx++;
291		}
292		ret = 0;
293		goto done;
294	}
295
296	pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
297	psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
298				GFP_KERNEL);
299	pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
300	if (!pins || !psel_val || !pin_fn) {
301		ret = -ENOMEM;
302		goto done;
303	}
304
305	/* Collect pin locations and mux settings from DT properties */
306	for (i = 0; i < num_pinmux; ++i) {
307		u32 value;
308
309		ret = of_property_read_u32_index(np, "pinmux", i, &value);
310		if (ret)
311			goto done;
312		pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
313		psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
314	}
315
316	if (parent) {
317		name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
318				      parent, np);
319		if (!name) {
320			ret = -ENOMEM;
321			goto done;
322		}
323	} else {
324		name = np->name;
325	}
326
327	if (num_configs) {
328		ret = rzt2h_map_add_config(&maps[idx], name,
329					   PIN_MAP_TYPE_CONFIGS_GROUP,
330					   configs, num_configs);
331		if (ret < 0)
332			goto done;
333
334		idx++;
335	}
336
337	scoped_guard(mutex, &pctrl->mutex) {
338		/* Register a single pin group listing all the pins we read from DT */
339		gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
340		if (gsel < 0) {
341			ret = gsel;
342			goto done;
343		}
344
345		/*
346		 * Register a single group function where the 'data' is an array PSEL
347		 * register values read from DT.
348		 */
349		pin_fn[0] = name;
350		fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
351		if (fsel < 0) {
352			ret = fsel;
353			goto remove_group;
354		}
355	}
356
357	maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
358	maps[idx].data.mux.group = name;
359	maps[idx].data.mux.function = name;
360	idx++;
361
362	dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
363	ret = 0;
364	goto done;
365
366remove_group:
367	pinctrl_generic_remove_group(pctldev, gsel);
368done:
369	*index = idx;
370	kfree(configs);
371	return ret;
372}
373
374static void rzt2h_dt_free_map(struct pinctrl_dev *pctldev,
375			      struct pinctrl_map *map,
376			      unsigned int num_maps)
377{
378	unsigned int i;
379
380	if (!map)
381		return;
382
383	for (i = 0; i < num_maps; ++i) {
384		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
385		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
386			kfree(map[i].data.configs.configs);
387	}
388	kfree(map);
389}
390
391static int rzt2h_dt_node_to_map(struct pinctrl_dev *pctldev,
392				struct device_node *np,
393				struct pinctrl_map **map,
394				unsigned int *num_maps)
395{
396	struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
397	unsigned int index;
398	int ret;
399
400	*map = NULL;
401	*num_maps = 0;
402	index = 0;
403
404	for_each_child_of_node_scoped(np, child) {
405		ret = rzt2h_dt_subnode_to_map(pctldev, child, np, map,
406					      num_maps, &index);
407		if (ret < 0)
408			goto done;
409	}
410
411	if (*num_maps == 0) {
412		ret = rzt2h_dt_subnode_to_map(pctldev, np, NULL, map,
413					      num_maps, &index);
414		if (ret < 0)
415			goto done;
416	}
417
418	if (*num_maps)
419		return 0;
420
421	dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
422	ret = -EINVAL;
423
424done:
425	rzt2h_dt_free_map(pctldev, *map, *num_maps);
426	return ret;
427}
428
429static const struct pinctrl_ops rzt2h_pinctrl_pctlops = {
430	.get_groups_count = pinctrl_generic_get_group_count,
431	.get_group_name = pinctrl_generic_get_group_name,
432	.get_group_pins = pinctrl_generic_get_group_pins,
433	.dt_node_to_map = rzt2h_dt_node_to_map,
434	.dt_free_map = rzt2h_dt_free_map,
435};
436
437static const struct pinmux_ops rzt2h_pinctrl_pmxops = {
438	.get_functions_count = pinmux_generic_get_function_count,
439	.get_function_name = pinmux_generic_get_function_name,
440	.get_function_groups = pinmux_generic_get_function_groups,
441	.set_mux = rzt2h_pinctrl_set_mux,
442	.strict = true,
443};
444
445static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
446{
447	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
448	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
449	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
450	int ret;
451	u8 reg;
452
453	ret = rzt2h_validate_pin(pctrl, offset);
454	if (ret)
455		return ret;
456
457	ret = pinctrl_gpio_request(chip, offset);
458	if (ret)
459		return ret;
460
461	guard(spinlock_irqsave)(&pctrl->lock);
462
463	/* Select GPIO mode in PMC Register */
464	reg = rzt2h_pinctrl_readb(pctrl, port, PMC(port));
465	reg &= ~BIT(bit);
466	rzt2h_pinctrl_writeb(pctrl, port, reg, PMC(port));
467
468	return 0;
469}
470
471static void rzt2h_gpio_set_direction(struct rzt2h_pinctrl *pctrl, u32 port,
472				     u8 bit, bool output)
473{
474	u16 reg;
475
476	guard(spinlock_irqsave)(&pctrl->lock);
477
478	reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
479	reg &= ~PM_PIN_MASK(bit);
480
481	reg |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
482	rzt2h_pinctrl_writew(pctrl, port, reg, PM(port));
483}
484
485static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
486{
487	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
488	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
489	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
490	u64 reg64;
491	u16 reg;
492	int ret;
493
494	ret = rzt2h_validate_pin(pctrl, offset);
495	if (ret)
496		return ret;
497
498	guard(spinlock_irqsave)(&pctrl->lock);
499
500	if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
501		/*
502		 * When a GPIO is being requested as an IRQ, the pinctrl
503		 * framework expects to be able to read the GPIO's direction.
504		 * IRQ function is separate from GPIO, and enabling it takes the
505		 * pin out of GPIO mode.
506		 * At this point, .child_to_parent_hwirq() has already been
507		 * called to enable the IRQ function.
508		 * Default to input direction for IRQ function.
509		 */
510		reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
511		reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
512		if (reg64 == PFC_FUNC_INTERRUPT)
513			return GPIO_LINE_DIRECTION_IN;
514
515		return -EINVAL;
516	}
517
518	reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
519	reg = (reg >> (bit * 2)) & PM_MASK;
520	if (reg & PM_OUTPUT)
521		return GPIO_LINE_DIRECTION_OUT;
522	if (reg & PM_INPUT)
523		return GPIO_LINE_DIRECTION_IN;
524
525	return -EINVAL;
526}
527
528static int rzt2h_gpio_set(struct gpio_chip *chip, unsigned int offset,
529			  int value)
530{
531	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
532	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
533	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
534	u8 reg;
535
536	guard(spinlock_irqsave)(&pctrl->lock);
537
538	reg = rzt2h_pinctrl_readb(pctrl, port, P(port));
539	if (value)
540		rzt2h_pinctrl_writeb(pctrl, port, reg | BIT(bit), P(port));
541	else
542		rzt2h_pinctrl_writeb(pctrl, port, reg & ~BIT(bit), P(port));
543
544	return 0;
545}
546
547static int rzt2h_gpio_get(struct gpio_chip *chip, unsigned int offset)
548{
549	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
550	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
551	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
552	u16 reg;
553
554	reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
555	reg = (reg >> (bit * 2)) & PM_MASK;
556	if (reg & PM_INPUT)
557		return !!(rzt2h_pinctrl_readb(pctrl, port, PIN(port)) & BIT(bit));
558	if (reg & PM_OUTPUT)
559		return !!(rzt2h_pinctrl_readb(pctrl, port, P(port)) & BIT(bit));
560
561	return -EINVAL;
562}
563
564static int rzt2h_gpio_direction_input(struct gpio_chip *chip,
565				      unsigned int offset)
566{
567	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
568	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
569	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
570
571	rzt2h_gpio_set_direction(pctrl, port, bit, false);
572
573	return 0;
574}
575
576static int rzt2h_gpio_direction_output(struct gpio_chip *chip,
577				       unsigned int offset, int value)
578{
579	struct rzt2h_pinctrl *pctrl = gpiochip_get_data(chip);
580	u8 port = RZT2H_PIN_ID_TO_PORT(offset);
581	u8 bit = RZT2H_PIN_ID_TO_PIN(offset);
582
583	rzt2h_gpio_set(chip, offset, value);
584	rzt2h_gpio_set_direction(pctrl, port, bit, true);
585
586	return 0;
587}
588
589static void rzt2h_gpio_free(struct gpio_chip *chip, unsigned int offset)
590{
591	pinctrl_gpio_free(chip, offset);
592
593	/*
594	 * Set the GPIO as an input to ensure that the next GPIO request won't
595	 * drive the GPIO pin as an output.
596	 */
597	rzt2h_gpio_direction_input(chip, offset);
598}
599
600static const char * const rzt2h_gpio_names[] = {
601	"P00_0", "P00_1", "P00_2", "P00_3", "P00_4", "P00_5", "P00_6", "P00_7",
602	"P01_0", "P01_1", "P01_2", "P01_3", "P01_4", "P01_5", "P01_6", "P01_7",
603	"P02_0", "P02_1", "P02_2", "P02_3", "P02_4", "P02_5", "P02_6", "P02_7",
604	"P03_0", "P03_1", "P03_2", "P03_3", "P03_4", "P03_5", "P03_6", "P03_7",
605	"P04_0", "P04_1", "P04_2", "P04_3", "P04_4", "P04_5", "P04_6", "P04_7",
606	"P05_0", "P05_1", "P05_2", "P05_3", "P05_4", "P05_5", "P05_6", "P05_7",
607	"P06_0", "P06_1", "P06_2", "P06_3", "P06_4", "P06_5", "P06_6", "P06_7",
608	"P07_0", "P07_1", "P07_2", "P07_3", "P07_4", "P07_5", "P07_6", "P07_7",
609	"P08_0", "P08_1", "P08_2", "P08_3", "P08_4", "P08_5", "P08_6", "P08_7",
610	"P09_0", "P09_1", "P09_2", "P09_3", "P09_4", "P09_5", "P09_6", "P09_7",
611	"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
612	"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
613	"P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
614	"P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
615	"P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
616	"P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
617	"P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
618	"P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
619	"P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
620	"P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
621	"P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
622	"P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
623	"P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
624	"P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
625	"P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
626	"P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
627	"P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
628	"P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
629	"P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
630	"P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
631	"P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
632	"P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
633	"P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
634	"P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
635	"P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
636	"P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
637};
638
639static int rzt2h_gpio_register(struct rzt2h_pinctrl *pctrl)
640{
641	struct pinctrl_gpio_range *range = &pctrl->gpio_range;
642	struct gpio_chip *chip = &pctrl->gpio_chip;
643	struct device *dev = pctrl->dev;
644	struct of_phandle_args of_args;
645	int ret;
646
647	ret = of_parse_phandle_with_fixed_args(dev->of_node, "gpio-ranges", 3, 0, &of_args);
648	if (ret)
649		return dev_err_probe(dev, ret, "Unable to parse gpio-ranges\n");
650
651	of_node_put(of_args.np);
652	if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
653	    of_args.args[2] != pctrl->data->n_port_pins)
654		return dev_err_probe(dev, -EINVAL,
655				     "gpio-ranges does not match selected SOC\n");
656
657	chip->base = -1;
658	chip->parent = dev;
659	chip->owner = THIS_MODULE;
660	chip->ngpio = of_args.args[2];
661	chip->names = rzt2h_gpio_names;
662	chip->request = rzt2h_gpio_request;
663	chip->free = rzt2h_gpio_free;
664	chip->get_direction = rzt2h_gpio_get_direction;
665	chip->direction_input = rzt2h_gpio_direction_input;
666	chip->direction_output = rzt2h_gpio_direction_output;
667	chip->get = rzt2h_gpio_get;
668	chip->set = rzt2h_gpio_set;
669	chip->label = dev_name(dev);
670
671	range->id = 0;
672	range->pin_base = 0;
673	range->base = 0;
674	range->npins = chip->ngpio;
675	range->name = chip->label;
676	range->gc = chip;
677
678	ret = devm_gpiochip_add_data(dev, chip, pctrl);
679	if (ret)
680		return dev_err_probe(dev, ret, "gpiochip registration failed\n");
681
682	return ret;
683}
684
685static int rzt2h_pinctrl_register(struct rzt2h_pinctrl *pctrl)
686{
687	struct pinctrl_desc *desc = &pctrl->desc;
688	struct device *dev = pctrl->dev;
689	struct pinctrl_pin_desc *pins;
690	unsigned int i, j;
691	int ret;
692
693	desc->name = DRV_NAME;
694	desc->npins = pctrl->data->n_port_pins;
695	desc->pctlops = &rzt2h_pinctrl_pctlops;
696	desc->pmxops = &rzt2h_pinctrl_pmxops;
697	desc->owner = THIS_MODULE;
698
699	pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
700	if (!pins)
701		return -ENOMEM;
702
703	pctrl->pins = pins;
704	desc->pins = pins;
705
706	for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
707		pins[i].number = i;
708		pins[i].name = rzt2h_gpio_names[i];
709		if (i && !(i % RZT2H_PINS_PER_PORT))
710			j++;
711	}
712
713	ret = devm_pinctrl_register_and_init(dev, desc, pctrl, &pctrl->pctl);
714	if (ret)
715		return dev_err_probe(dev, ret, "pinctrl registration failed\n");
716
717	ret = pinctrl_enable(pctrl->pctl);
718	if (ret)
719		return dev_err_probe(dev, ret, "pinctrl enable failed\n");
720
721	return rzt2h_gpio_register(pctrl);
722}
723
724static int rzt2h_pinctrl_cfg_regions(struct platform_device *pdev,
725				     struct rzt2h_pinctrl *pctrl)
726{
727	struct resource *res;
728
729	pctrl->base0 = devm_platform_ioremap_resource_byname(pdev, "nsr");
730	if (IS_ERR(pctrl->base0))
731		return PTR_ERR(pctrl->base0);
732
733	/*
734	 * Open-coded instead of using devm_platform_ioremap_resource_byname()
735	 * because the "srs" region is optional.
736	 */
737	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "srs");
738	if (res) {
739		u8 port;
740
741		pctrl->base1 = devm_ioremap_resource(&pdev->dev, res);
742		if (IS_ERR(pctrl->base1))
743			return PTR_ERR(pctrl->base1);
744
745		pctrl->safety_port_enabled = true;
746
747		/* Configure to select safety region 0x812c0xxx */
748		for (port = 0; port <= RZT2H_MAX_SAFETY_PORTS; port++)
749			writeb(0x0, pctrl->base1 + RSELP(port));
750	}
751
752	return 0;
753}
754
755static int rzt2h_pinctrl_probe(struct platform_device *pdev)
756{
757	struct device *dev = &pdev->dev;
758	struct rzt2h_pinctrl *pctrl;
759	int ret;
760
761	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
762	if (!pctrl)
763		return -ENOMEM;
764
765	pctrl->dev = dev;
766	pctrl->data = of_device_get_match_data(dev);
767
768	ret = rzt2h_pinctrl_cfg_regions(pdev, pctrl);
769	if (ret)
770		return ret;
771
772	spin_lock_init(&pctrl->lock);
773	mutex_init(&pctrl->mutex);
774	platform_set_drvdata(pdev, pctrl);
775
776	return rzt2h_pinctrl_register(pctrl);
777}
778
779static const u8 r9a09g077_gpio_configs[] = {
780	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
781	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
782	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f,
783};
784
785static const u8 r9a09g087_gpio_configs[] = {
786	0x1f, 0xff, 0xff, 0x1f, 0x00, 0xfe, 0xff, 0x00, 0x7e, 0xf0, 0xff, 0x01,
787	0xff, 0xff, 0xff, 0x00, 0xe0, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x01,
788	0xe0, 0xff, 0xff, 0x7f, 0x00, 0xfe, 0xff, 0x7f, 0x00, 0xfc, 0x7f,
789};
790
791static struct rzt2h_pinctrl_data r9a09g077_data = {
792	.n_port_pins = ARRAY_SIZE(r9a09g077_gpio_configs) * RZT2H_PINS_PER_PORT,
793	.port_pin_configs = r9a09g077_gpio_configs,
794	.n_ports = ARRAY_SIZE(r9a09g077_gpio_configs),
795};
796
797static struct rzt2h_pinctrl_data r9a09g087_data = {
798	.n_port_pins = ARRAY_SIZE(r9a09g087_gpio_configs) * RZT2H_PINS_PER_PORT,
799	.port_pin_configs = r9a09g087_gpio_configs,
800	.n_ports = ARRAY_SIZE(r9a09g087_gpio_configs),
801};
802
803static const struct of_device_id rzt2h_pinctrl_of_table[] = {
804	{
805		.compatible = "renesas,r9a09g077-pinctrl",
806		.data = &r9a09g077_data,
807	},
808	{
809		.compatible = "renesas,r9a09g087-pinctrl",
810		.data = &r9a09g087_data,
811	},
812	{ /* sentinel */ }
813};
814
815static struct platform_driver rzt2h_pinctrl_driver = {
816	.driver = {
817		.name = DRV_NAME,
818		.of_match_table = of_match_ptr(rzt2h_pinctrl_of_table),
819		.suppress_bind_attrs = true,
820	},
821	.probe = rzt2h_pinctrl_probe,
822};
823
824static int __init rzt2h_pinctrl_init(void)
825{
826	return platform_driver_register(&rzt2h_pinctrl_driver);
827}
828core_initcall(rzt2h_pinctrl_init);
829
830MODULE_LICENSE("GPL");
831MODULE_AUTHOR("Thierry Bultel <thierry.bultel.yh@bp.renesas.com>");
832MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
833MODULE_DESCRIPTION("Pin and gpio controller driver for the RZ/T2H family");