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pinctrl-rzg2l.c
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linux-6.19.14/drivers/pinctrl/renesas/pinctrl-rzg2l.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8#include <linux/bitfield.h> 9#include <linux/bitops.h> 10#include <linux/clk.h> 11#include <linux/gpio/driver.h> 12#include <linux/interrupt.h> 13#include <linux/io.h> 14#include <linux/module.h> 15#include <linux/mutex.h> 16#include <linux/of.h> 17#include <linux/of_irq.h> 18#include <linux/platform_device.h> 19#include <linux/property.h> 20#include <linux/seq_file.h> 21#include <linux/spinlock.h> 22 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinconf.h> 26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinmux.h> 28 29#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> 30#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> 31#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 32 33#include "../core.h" 34#include "../pinconf.h" 35#include "../pinmux.h" 36 37#define DRV_NAME "pinctrl-rzg2l" 38 39/* 40 * Use 16 lower bits [15:0] for pin identifier 41 * Use 16 higher bits [31:16] for pin mux function 42 */ 43#define MUX_PIN_ID_MASK GENMASK(15, 0) 44#define MUX_FUNC_MASK GENMASK(31, 16) 45 46/* PIN capabilities */ 47#define PIN_CFG_IOLH_A BIT(0) 48#define PIN_CFG_IOLH_B BIT(1) 49#define PIN_CFG_SR BIT(2) 50#define PIN_CFG_IEN BIT(3) 51#define PIN_CFG_PUPD BIT(4) 52#define PIN_CFG_IO_VMC_SD0 BIT(5) 53#define PIN_CFG_IO_VMC_SD1 BIT(6) 54#define PIN_CFG_IO_VMC_QSPI BIT(7) 55#define PIN_CFG_IO_VMC_ETH0 BIT(8) 56#define PIN_CFG_IO_VMC_ETH1 BIT(9) 57#define PIN_CFG_NF BIT(10) /* Digital noise filter */ 58#define PIN_CFG_IOLH_C BIT(11) 59#define PIN_CFG_SOFT_PS BIT(12) 60#define PIN_CFG_OEN BIT(13) 61#define PIN_CFG_NOGPIO_INT BIT(14) 62#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */ 63#define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ 64#define PIN_CFG_ELC BIT(17) 65#define PIN_CFG_IOLH_RZV2H BIT(18) 66 67#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ 68#define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ 69 70#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 71 (PIN_CFG_IOLH_##group | \ 72 PIN_CFG_PUPD | \ 73 PIN_CFG_NF) 74 75#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 76 PIN_CFG_SR) 77 78#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 79 PIN_CFG_SOFT_PS) 80 81#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \ 82 PIN_CFG_NOD | \ 83 PIN_CFG_SR | \ 84 PIN_CFG_SMT) 85 86#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) 87 88#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) 89#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) 90#define PIN_CFG_MASK GENMASK_ULL(31, 0) 91 92/* 93 * m indicates the bitmap of supported pins, a is the register index 94 * and f is pin configuration capabilities supported. 95 */ 96#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 98 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 99#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ 100 (RZG2L_VARIABLE_CFG | \ 101 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) 102 103/* 104 * n indicates number of pins in the port, a is the register index 105 * and f is pin configuration capabilities supported. 106 */ 107#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 108#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \ 109 RZG2L_GPIO_PORT_PACK(n, a, 0)) 110 111#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) 112#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) 113/* 114 * p is the register index while referencing to SR/IEN/IOLH/FILxx 115 * registers, b is the register bits (b * 8) and f is the pin 116 * configuration capabilities supported. 117 */ 118#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 121 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 122 123#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 124 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 125 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 126 127#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52) 128#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47) 129#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ 130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \ 131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ 132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) 133 134#define P(off) (0x0000 + (off)) 135#define PM(off) (0x0100 + (off) * 2) 136#define PMC(off) (0x0200 + (off)) 137#define PFC(off) (0x0400 + (off) * 4) 138#define PIN(off) (0x0800 + (off)) 139#define IOLH(off) (0x1000 + (off) * 8) 140#define SR(off) (0x1400 + (off) * 8) 141#define IEN(off) (0x1800 + (off) * 8) 142#define PUPD(off) (0x1C00 + (off) * 8) 143#define ISEL(off) (0x2C00 + (off) * 8) 144#define NOD(off) (0x3000 + (off) * 8) 145#define SMT(off) (0x3400 + (off) * 8) 146#define SD_CH(off, ch) ((off) + (ch) * 4) 147#define ETH_POC(off, ch) ((off) + (ch) * 4) 148#define QSPI (0x3008) 149 150#define PVDD_2500 2 /* I/O domain voltage 2.5V */ 151#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 152#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 153 154#define PWPR_B0WI BIT(7) /* Bit Write Disable */ 155#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 156#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ 157#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ 158 159#define PM_MASK 0x03 160#define PFC_MASK 0x0f 161#define IEN_MASK 0x01 162#define IOLH_MASK 0x03 163#define SR_MASK 0x01 164#define PUPD_MASK 0x03 165#define NOD_MASK 0x01 166#define SMT_MASK 0x01 167 168#define PM_INPUT 0x1 169#define PM_OUTPUT 0x2 170 171#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 172#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 173 174#define RZG2L_TINT_MAX_INTERRUPT 32 175#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 176 177/* Custom pinconf parameters */ 178#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) 179 180static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { 181 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, 182}; 183 184#ifdef CONFIG_DEBUG_FS 185static const struct pin_config_item renesas_rzv2h_conf_items[] = { 186 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), 187}; 188#endif 189 190/* Read/write 8 bits register */ 191#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 192 do { \ 193 if (_read) \ 194 _val = readb(_addr); \ 195 else \ 196 writeb(_val, _addr); \ 197 } while (0) 198 199/* Read/write 16 bits register */ 200#define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 201 do { \ 202 if (_read) \ 203 _val = readw(_addr); \ 204 else \ 205 writew(_val, _addr); \ 206 } while (0) 207 208/* Read/write 32 bits register */ 209#define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 210 do { \ 211 if (_read) \ 212 _val = readl(_addr); \ 213 else \ 214 writel(_val, _addr); \ 215 } while (0) 216 217/** 218 * struct rzg2l_register_offsets - specific register offsets 219 * @pwpr: PWPR register offset 220 * @sd_ch: SD_CH register offset 221 * @eth_poc: ETH_POC register offset 222 * @oen: OEN register offset 223 */ 224struct rzg2l_register_offsets { 225 u16 pwpr; 226 u16 sd_ch; 227 u16 eth_poc; 228 u16 oen; 229}; 230 231/** 232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 233 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 234 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 235 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 236 * @RZG2L_IOLH_IDX_MAX: maximum index 237 */ 238enum rzg2l_iolh_index { 239 RZG2L_IOLH_IDX_1V8 = 0, 240 RZG2L_IOLH_IDX_2V5 = 4, 241 RZG2L_IOLH_IDX_3V3 = 8, 242 RZG2L_IOLH_IDX_MAX = 12, 243}; 244 245/* Maximum number of driver strength entries per power source. */ 246#define RZG2L_IOLH_MAX_DS_ENTRIES (4) 247 248/** 249 * struct rzg2l_hwcfg - hardware configuration data structure 250 * @regs: hardware specific register offsets 251 * @iolh_groupa_ua: IOLH group A uA specific values 252 * @iolh_groupb_ua: IOLH group B uA specific values 253 * @iolh_groupc_ua: IOLH group C uA specific values 254 * @iolh_groupb_oi: IOLH group B output impedance specific values 255 * @tint_start_index: the start index for the TINT interrupts 256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 257 * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR 258 * @func_base: base number for port function (see register PFC) 259 * @oen_max_pin: the maximum pin number supporting output enable 260 * @oen_max_port: the maximum port number supporting output enable 261 */ 262struct rzg2l_hwcfg { 263 const struct rzg2l_register_offsets regs; 264 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 265 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 266 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 267 u16 iolh_groupb_oi[4]; 268 u16 tint_start_index; 269 bool drive_strength_ua; 270 bool oen_pwpr_lock; 271 u8 func_base; 272 u8 oen_max_pin; 273 u8 oen_max_port; 274}; 275 276struct rzg2l_dedicated_configs { 277 const char *name; 278 u64 config; 279}; 280 281struct rzg2l_pinctrl; 282 283struct rzg2l_pinctrl_data { 284 const char * const *port_pins; 285 const u64 *port_pin_configs; 286 unsigned int n_ports; 287 const struct rzg2l_dedicated_configs *dedicated_pins; 288 unsigned int n_port_pins; 289 unsigned int n_dedicated_pins; 290 const struct rzg2l_hwcfg *hwcfg; 291 const u64 *variable_pin_cfg; 292 unsigned int n_variable_pin_cfg; 293 unsigned int num_custom_params; 294 const struct pinconf_generic_params *custom_params; 295#ifdef CONFIG_DEBUG_FS 296 const struct pin_config_item *custom_conf_items; 297#endif 298 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 299 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 300 int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 301 int (*hw_to_bias_param)(unsigned int val); 302 int (*bias_param_to_hw)(enum pin_config_param param); 303}; 304 305/** 306 * struct rzg2l_pinctrl_pin_settings - pin data 307 * @power_source: power source 308 * @drive_strength_ua: drive strength (in micro amps) 309 */ 310struct rzg2l_pinctrl_pin_settings { 311 u16 power_source; 312 u16 drive_strength_ua; 313}; 314 315/** 316 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 317 * @p: P registers cache 318 * @pm: PM registers cache 319 * @pmc: PMC registers cache 320 * @pfc: PFC registers cache 321 * @iolh: IOLH registers cache 322 * @pupd: PUPD registers cache 323 * @ien: IEN registers cache 324 * @smt: SMT registers cache 325 * @sd_ch: SD_CH registers cache 326 * @eth_poc: ET_POC registers cache 327 * @oen: Output Enable register cache 328 * @qspi: QSPI registers cache 329 */ 330struct rzg2l_pinctrl_reg_cache { 331 u8 *p; 332 u16 *pm; 333 u8 *pmc; 334 u32 *pfc; 335 u32 *iolh[2]; 336 u32 *ien[2]; 337 u32 *pupd[2]; 338 u32 *smt; 339 u8 sd_ch[2]; 340 u8 eth_poc[2]; 341 u8 oen; 342 u8 qspi; 343}; 344 345struct rzg2l_pinctrl { 346 struct pinctrl_dev *pctl; 347 struct pinctrl_desc desc; 348 struct pinctrl_pin_desc *pins; 349 350 const struct rzg2l_pinctrl_data *data; 351 void __iomem *base; 352 struct device *dev; 353 354 struct clk *clk; 355 356 struct gpio_chip gpio_chip; 357 struct pinctrl_gpio_range gpio_range; 358 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 359 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 360 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 361 362 raw_spinlock_t lock; /* lock read/write registers */ 363 struct mutex mutex; /* serialize adding groups and functions */ 364 365 struct rzg2l_pinctrl_pin_settings *settings; 366 struct rzg2l_pinctrl_reg_cache *cache; 367 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 368 atomic_t wakeup_path; 369}; 370 371static const u16 available_ps[] = { 1800, 2500, 3300 }; 372 373static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 374 u64 pincfg, 375 unsigned int port, 376 u8 pin) 377{ 378 unsigned int i; 379 380 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 381 u64 cfg = pctrl->data->variable_pin_cfg[i]; 382 383 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && 384 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) 385 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg); 386 } 387 388 return 0; 389} 390 391static const u64 r9a09g047_variable_pin_cfg[] = { 392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), 394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS), 395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS), 396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS), 397 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), 398 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), 399 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), 400 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), 401 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), 403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), 404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), 405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), 406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), 407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), 408 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 409 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), 410 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), 411 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS), 412 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS), 413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), 414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), 415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), 416 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), 417 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 418 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), 419 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), 420 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), 421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), 422 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), 423 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), 424 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), 425 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 426 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 427 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 428 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 429 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 430 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS), 431 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS), 432 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS), 433 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 434 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 435 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 436 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 437 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 438 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 439 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS), 440 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), 441 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), 442 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), 443 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 444 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 445 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 446 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), 447 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 448 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), 449 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), 450 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), 451}; 452 453static const u64 r9a09g057_variable_pin_cfg[] = { 454 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS), 455 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 456 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 457 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 458 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 459 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 460}; 461 462#ifdef CONFIG_RISCV 463static const u64 r9a07g043f_variable_pin_cfg[] = { 464 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 465 PIN_CFG_NF | 466 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 467 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 468 PIN_CFG_NF | 469 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 470 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 471 PIN_CFG_NF | 472 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 473 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 474 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 475 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 476 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 477 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 478 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 479 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 480 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 481 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 482 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 483 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 484 PIN_CFG_NOGPIO_INT), 485 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 486 PIN_CFG_NOGPIO_INT), 487 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 488 PIN_CFG_NOGPIO_INT), 489 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 490 PIN_CFG_NOGPIO_INT), 491 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 492 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 493 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 494 PIN_CFG_NOGPIO_INT), 495 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 496 PIN_CFG_NOGPIO_INT), 497 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 498 PIN_CFG_NOGPIO_INT), 499 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 500 PIN_CFG_NOGPIO_INT), 501 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 502 PIN_CFG_NF | 503 PIN_CFG_NOGPIO_INT), 504}; 505#endif 506 507static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 508{ 509 writeb(val, pctrl->base + offset); 510} 511 512static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 513{ 514 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 515 u8 pwpr; 516 517 pwpr = readb(pctrl->base + regs->pwpr); 518 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); 519 writeb(val, pctrl->base + offset); 520 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 521} 522 523static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, 524 u64 cfg, u32 port, u8 bit) 525{ 526 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 527 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 528 u64 data; 529 530 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 531 return -EINVAL; 532 533 data = pctrl->data->port_pin_configs[port]; 534 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 535 return -EINVAL; 536 537 return 0; 538} 539 540static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 541 u8 pin, u8 off, u8 func) 542{ 543 unsigned long flags; 544 u32 reg, pfc; 545 546 /* Switching to GPIO is not required if reset value is same as func */ 547 raw_spin_lock_irqsave(&pctrl->lock, flags); 548 reg = readb(pctrl->base + PMC(off)); 549 pfc = readl(pctrl->base + PFC(off)); 550 if ((reg & BIT(pin)) && (((pfc >> (pin * 4)) & PFC_MASK) == func)) { 551 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 552 return; 553 } 554 555 /* Set pin to 'Non-use (Hi-Z input protection)' */ 556 reg = readw(pctrl->base + PM(off)); 557 reg &= ~(PM_MASK << (pin * 2)); 558 writew(reg, pctrl->base + PM(off)); 559 560 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 561 562 /* Temporarily switch to GPIO mode with PMC register */ 563 reg = readb(pctrl->base + PMC(off)); 564 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 565 566 /* Select Pin function mode with PFC register */ 567 pfc &= ~(PFC_MASK << (pin * 4)); 568 writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off)); 569 570 /* Switch to Peripheral pin function with PMC register */ 571 reg = readb(pctrl->base + PMC(off)); 572 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 573 574 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 575 576 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 577} 578 579static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 580 unsigned int func_selector, 581 unsigned int group_selector) 582{ 583 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 584 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 585 const struct function_desc *func; 586 unsigned int i, *psel_val; 587 struct group_desc *group; 588 const unsigned int *pins; 589 int ret; 590 591 func = pinmux_generic_get_function(pctldev, func_selector); 592 if (!func) 593 return -EINVAL; 594 group = pinctrl_generic_get_group(pctldev, group_selector); 595 if (!group) 596 return -EINVAL; 597 598 psel_val = func->data; 599 pins = group->grp.pins; 600 601 for (i = 0; i < group->grp.npins; i++) { 602 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 603 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 604 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 605 606 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); 607 if (ret) 608 return ret; 609 610 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", 611 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); 612 613 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); 614 } 615 616 return 0; 617} 618 619static int rzg2l_map_add_config(struct pinctrl_map *map, 620 const char *group_or_pin, 621 enum pinctrl_map_type type, 622 unsigned long *configs, 623 unsigned int num_configs) 624{ 625 unsigned long *cfgs; 626 627 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 628 if (!cfgs) 629 return -ENOMEM; 630 631 map->type = type; 632 map->data.configs.group_or_pin = group_or_pin; 633 map->data.configs.configs = cfgs; 634 map->data.configs.num_configs = num_configs; 635 636 return 0; 637} 638 639static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 640 struct device_node *np, 641 struct device_node *parent, 642 struct pinctrl_map **map, 643 unsigned int *num_maps, 644 unsigned int *index) 645{ 646 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 647 struct pinctrl_map *maps = *map; 648 unsigned int nmaps = *num_maps; 649 unsigned long *configs = NULL; 650 unsigned int *pins, *psel_val; 651 unsigned int num_pinmux = 0; 652 unsigned int idx = *index; 653 unsigned int num_pins, i; 654 unsigned int num_configs; 655 struct property *pinmux; 656 struct property *prop; 657 int ret, gsel, fsel; 658 const char **pin_fn; 659 const char *name; 660 const char *pin; 661 662 pinmux = of_find_property(np, "pinmux", NULL); 663 if (pinmux) 664 num_pinmux = pinmux->length / sizeof(u32); 665 666 ret = of_property_count_strings(np, "pins"); 667 if (ret == -EINVAL) { 668 num_pins = 0; 669 } else if (ret < 0) { 670 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 671 return ret; 672 } else { 673 num_pins = ret; 674 } 675 676 if (!num_pinmux && !num_pins) 677 return 0; 678 679 if (num_pinmux && num_pins) { 680 dev_err(pctrl->dev, 681 "DT node must contain either a pinmux or pins and not both\n"); 682 return -EINVAL; 683 } 684 685 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 686 if (ret < 0) 687 return ret; 688 689 if (num_pins && !num_configs) { 690 dev_err(pctrl->dev, "DT node must contain a config\n"); 691 ret = -ENODEV; 692 goto done; 693 } 694 695 if (num_pinmux) { 696 nmaps += 1; 697 if (num_configs) 698 nmaps += 1; 699 } 700 701 if (num_pins) 702 nmaps += num_pins; 703 704 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 705 if (!maps) { 706 ret = -ENOMEM; 707 goto done; 708 } 709 710 *map = maps; 711 *num_maps = nmaps; 712 if (num_pins) { 713 of_property_for_each_string(np, "pins", prop, pin) { 714 ret = rzg2l_map_add_config(&maps[idx], pin, 715 PIN_MAP_TYPE_CONFIGS_PIN, 716 configs, num_configs); 717 if (ret < 0) 718 goto done; 719 720 idx++; 721 } 722 ret = 0; 723 goto done; 724 } 725 726 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 727 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 728 GFP_KERNEL); 729 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 730 if (!pins || !psel_val || !pin_fn) { 731 ret = -ENOMEM; 732 goto done; 733 } 734 735 /* Collect pin locations and mux settings from DT properties */ 736 for (i = 0; i < num_pinmux; ++i) { 737 u32 value; 738 739 ret = of_property_read_u32_index(np, "pinmux", i, &value); 740 if (ret) 741 goto done; 742 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 743 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 744 } 745 746 if (parent) { 747 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 748 parent, np); 749 if (!name) { 750 ret = -ENOMEM; 751 goto done; 752 } 753 } else { 754 name = np->name; 755 } 756 757 if (num_configs) { 758 ret = rzg2l_map_add_config(&maps[idx], name, 759 PIN_MAP_TYPE_CONFIGS_GROUP, 760 configs, num_configs); 761 if (ret < 0) 762 goto done; 763 764 idx++; 765 } 766 767 mutex_lock(&pctrl->mutex); 768 769 /* Register a single pin group listing all the pins we read from DT */ 770 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 771 if (gsel < 0) { 772 ret = gsel; 773 goto unlock; 774 } 775 776 /* 777 * Register a single group function where the 'data' is an array PSEL 778 * register values read from DT. 779 */ 780 pin_fn[0] = name; 781 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 782 if (fsel < 0) { 783 ret = fsel; 784 goto remove_group; 785 } 786 787 mutex_unlock(&pctrl->mutex); 788 789 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 790 maps[idx].data.mux.group = name; 791 maps[idx].data.mux.function = name; 792 idx++; 793 794 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 795 ret = 0; 796 goto done; 797 798remove_group: 799 pinctrl_generic_remove_group(pctldev, gsel); 800unlock: 801 mutex_unlock(&pctrl->mutex); 802done: 803 *index = idx; 804 kfree(configs); 805 return ret; 806} 807 808static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 809 struct pinctrl_map *map, 810 unsigned int num_maps) 811{ 812 unsigned int i; 813 814 if (!map) 815 return; 816 817 for (i = 0; i < num_maps; ++i) { 818 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 819 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 820 kfree(map[i].data.configs.configs); 821 } 822 kfree(map); 823} 824 825static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 826 struct device_node *np, 827 struct pinctrl_map **map, 828 unsigned int *num_maps) 829{ 830 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 831 unsigned int index; 832 int ret; 833 834 *map = NULL; 835 *num_maps = 0; 836 index = 0; 837 838 for_each_child_of_node_scoped(np, child) { 839 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 840 num_maps, &index); 841 if (ret < 0) 842 goto done; 843 } 844 845 if (*num_maps == 0) { 846 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 847 num_maps, &index); 848 if (ret < 0) 849 goto done; 850 } 851 852 if (*num_maps) 853 return 0; 854 855 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 856 ret = -EINVAL; 857 858done: 859 rzg2l_dt_free_map(pctldev, *map, *num_maps); 860 861 return ret; 862} 863 864static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 865 u8 bit, u32 mask) 866{ 867 void __iomem *addr = pctrl->base + offset; 868 869 /* handle _L/_H for 32-bit register read/write */ 870 if (bit >= 4) { 871 bit -= 4; 872 addr += 4; 873 } 874 875 return (readl(addr) >> (bit * 8)) & mask; 876} 877 878static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 879 u8 bit, u32 mask, u32 val) 880{ 881 void __iomem *addr = pctrl->base + offset; 882 unsigned long flags; 883 u32 reg; 884 885 /* handle _L/_H for 32-bit register read/write */ 886 if (bit >= 4) { 887 bit -= 4; 888 addr += 4; 889 } 890 891 raw_spin_lock_irqsave(&pctrl->lock, flags); 892 reg = readl(addr) & ~(mask << (bit * 8)); 893 writel(reg | (val << (bit * 8)), addr); 894 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 895} 896 897static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) 898{ 899 if (caps & PIN_CFG_IO_VMC_SD0) 900 return SD_CH(regs->sd_ch, 0); 901 if (caps & PIN_CFG_IO_VMC_SD1) 902 return SD_CH(regs->sd_ch, 1); 903 if (caps & PIN_CFG_IO_VMC_ETH0) 904 return ETH_POC(regs->eth_poc, 0); 905 if (caps & PIN_CFG_IO_VMC_ETH1) 906 return ETH_POC(regs->eth_poc, 1); 907 if (caps & PIN_CFG_IO_VMC_QSPI) 908 return QSPI; 909 910 return -EINVAL; 911} 912 913static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 914{ 915 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 916 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 917 int pwr_reg; 918 u8 val; 919 920 if (caps & PIN_CFG_SOFT_PS) 921 return pctrl->settings[pin].power_source; 922 923 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 924 if (pwr_reg < 0) 925 return pwr_reg; 926 927 val = readb(pctrl->base + pwr_reg); 928 switch (val) { 929 case PVDD_1800: 930 return 1800; 931 case PVDD_2500: 932 return 2500; 933 case PVDD_3300: 934 return 3300; 935 default: 936 /* Should not happen. */ 937 return -EINVAL; 938 } 939} 940 941static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 942{ 943 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 944 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 945 int pwr_reg; 946 u8 val; 947 948 if (caps & PIN_CFG_SOFT_PS) { 949 pctrl->settings[pin].power_source = ps; 950 return 0; 951 } 952 953 switch (ps) { 954 case 1800: 955 val = PVDD_1800; 956 break; 957 case 2500: 958 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 959 return -EINVAL; 960 val = PVDD_2500; 961 break; 962 case 3300: 963 val = PVDD_3300; 964 break; 965 default: 966 return -EINVAL; 967 } 968 969 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); 970 if (pwr_reg < 0) 971 return pwr_reg; 972 973 writeb(val, pctrl->base + pwr_reg); 974 pctrl->settings[pin].power_source = ps; 975 976 return 0; 977} 978 979static bool rzg2l_ps_is_supported(u16 ps) 980{ 981 unsigned int i; 982 983 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 984 if (available_ps[i] == ps) 985 return true; 986 } 987 988 return false; 989} 990 991static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 992{ 993 unsigned int i; 994 995 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 996 if (available_ps[i] == ps) 997 break; 998 } 999 1000 /* 1001 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 1002 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 1003 */ 1004 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 1005} 1006 1007static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 1008{ 1009 if (caps & PIN_CFG_IOLH_A) 1010 return hwcfg->iolh_groupa_ua[val]; 1011 1012 if (caps & PIN_CFG_IOLH_B) 1013 return hwcfg->iolh_groupb_ua[val]; 1014 1015 if (caps & PIN_CFG_IOLH_C) 1016 return hwcfg->iolh_groupc_ua[val]; 1017 1018 /* Should not happen. */ 1019 return 0; 1020} 1021 1022static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 1023 enum rzg2l_iolh_index ps_index, u16 ua) 1024{ 1025 const u16 *array = NULL; 1026 unsigned int i; 1027 1028 if (caps & PIN_CFG_IOLH_A) 1029 array = &hwcfg->iolh_groupa_ua[ps_index]; 1030 1031 if (caps & PIN_CFG_IOLH_B) 1032 array = &hwcfg->iolh_groupb_ua[ps_index]; 1033 1034 if (caps & PIN_CFG_IOLH_C) 1035 array = &hwcfg->iolh_groupc_ua[ps_index]; 1036 1037 if (!array) 1038 return -EINVAL; 1039 1040 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1041 if (array[i] == ua) 1042 return i; 1043 } 1044 1045 return -EINVAL; 1046} 1047 1048static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 1049 enum rzg2l_iolh_index iolh_idx, 1050 u16 ds) 1051{ 1052 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1053 const u16 *array = NULL; 1054 unsigned int i; 1055 1056 if (caps & PIN_CFG_IOLH_A) 1057 array = hwcfg->iolh_groupa_ua; 1058 1059 if (caps & PIN_CFG_IOLH_B) 1060 array = hwcfg->iolh_groupb_ua; 1061 1062 if (caps & PIN_CFG_IOLH_C) 1063 array = hwcfg->iolh_groupc_ua; 1064 1065 /* Should not happen. */ 1066 if (!array) 1067 return false; 1068 1069 if (!array[iolh_idx]) 1070 return false; 1071 1072 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1073 if (array[iolh_idx + i] == ds) 1074 return true; 1075 } 1076 1077 return false; 1078} 1079 1080static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1081{ 1082 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1083 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); 1084 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1085 1086 if (pin > pctrl->data->hwcfg->oen_max_pin) 1087 return -EINVAL; 1088 1089 /* 1090 * We can determine which Ethernet interface we're dealing with from 1091 * the caps. 1092 */ 1093 if (caps & PIN_CFG_IO_VMC_ETH0) 1094 return 0; 1095 if (caps & PIN_CFG_IO_VMC_ETH1) 1096 return 1; 1097 1098 return -EINVAL; 1099} 1100 1101static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1102{ 1103 int bit; 1104 1105 if (!pctrl->data->pin_to_oen_bit) 1106 return -EOPNOTSUPP; 1107 1108 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1109 if (bit < 0) 1110 return -EINVAL; 1111 1112 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); 1113} 1114 1115/** 1116 * rzg2l_oen_write_with_pwpr - Write to OEN register with PWPR protection 1117 * @pctrl: pinctrl driver data 1118 * @val: value to write to OEN register 1119 * 1120 * Writes to the OEN register, handling PWPR write protection if required 1121 * by the hardware configuration. Must be called with pctrl->lock held. 1122 */ 1123static void rzg2l_oen_write_with_pwpr(struct rzg2l_pinctrl *pctrl, u8 val) 1124{ 1125 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 1126 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1127 u8 pwpr; 1128 1129 if (pctrl->data->hwcfg->oen_pwpr_lock) { 1130 pwpr = readb(pctrl->base + regs->pwpr); 1131 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1132 } 1133 1134 writeb(val, pctrl->base + oen_offset); 1135 1136 if (pctrl->data->hwcfg->oen_pwpr_lock) 1137 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1138} 1139 1140static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1141{ 1142 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1143 unsigned long flags; 1144 int bit; 1145 u8 val; 1146 1147 if (!pctrl->data->pin_to_oen_bit) 1148 return -EOPNOTSUPP; 1149 1150 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1151 if (bit < 0) 1152 return -EINVAL; 1153 1154 raw_spin_lock_irqsave(&pctrl->lock, flags); 1155 val = readb(pctrl->base + oen_offset); 1156 if (oen) 1157 val &= ~BIT(bit); 1158 else 1159 val |= BIT(bit); 1160 1161 rzg2l_oen_write_with_pwpr(pctrl, val); 1162 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1163 1164 return 0; 1165} 1166 1167static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1168{ 1169 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1170 u8 port, pin, bit; 1171 1172 if (*pin_data & RZG2L_SINGLE_PIN) 1173 return -EINVAL; 1174 1175 port = RZG2L_PIN_ID_TO_PORT(_pin); 1176 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1177 if (pin > pctrl->data->hwcfg->oen_max_pin) 1178 return -EINVAL; 1179 1180 bit = pin * 2; 1181 if (port == pctrl->data->hwcfg->oen_max_port) 1182 bit += 1; 1183 1184 return bit; 1185} 1186 1187static int rzg2l_hw_to_bias_param(unsigned int bias) 1188{ 1189 switch (bias) { 1190 case 0: 1191 return PIN_CONFIG_BIAS_DISABLE; 1192 case 1: 1193 return PIN_CONFIG_BIAS_PULL_UP; 1194 case 2: 1195 return PIN_CONFIG_BIAS_PULL_DOWN; 1196 default: 1197 break; 1198 } 1199 1200 return -EINVAL; 1201} 1202 1203static int rzg2l_bias_param_to_hw(enum pin_config_param param) 1204{ 1205 switch (param) { 1206 case PIN_CONFIG_BIAS_DISABLE: 1207 return 0; 1208 case PIN_CONFIG_BIAS_PULL_UP: 1209 return 1; 1210 case PIN_CONFIG_BIAS_PULL_DOWN: 1211 return 2; 1212 default: 1213 break; 1214 } 1215 1216 return -EINVAL; 1217} 1218 1219static int rzv2h_hw_to_bias_param(unsigned int bias) 1220{ 1221 switch (bias) { 1222 case 0: 1223 case 1: 1224 return PIN_CONFIG_BIAS_DISABLE; 1225 case 2: 1226 return PIN_CONFIG_BIAS_PULL_DOWN; 1227 case 3: 1228 return PIN_CONFIG_BIAS_PULL_UP; 1229 default: 1230 break; 1231 } 1232 1233 return -EINVAL; 1234} 1235 1236static int rzv2h_bias_param_to_hw(enum pin_config_param param) 1237{ 1238 switch (param) { 1239 case PIN_CONFIG_BIAS_DISABLE: 1240 return 0; 1241 case PIN_CONFIG_BIAS_PULL_DOWN: 1242 return 2; 1243 case PIN_CONFIG_BIAS_PULL_UP: 1244 return 3; 1245 default: 1246 break; 1247 } 1248 1249 return -EINVAL; 1250} 1251 1252static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin, 1253 const char * const pin_names[], unsigned int count) 1254{ 1255 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1256 unsigned int i; 1257 1258 for (i = 0; i < count; i++) { 1259 if (!strcmp(pin_desc->name, pin_names[i])) 1260 return i; 1261 } 1262 1263 return -EINVAL; 1264} 1265 1266static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1267{ 1268 static const char * const pin_names[] = { 1269 "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", 1270 "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" 1271 }; 1272 1273 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1274} 1275 1276static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1277{ 1278 static const char * const pin_names[] = { 1279 "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" 1280 }; 1281 1282 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1283} 1284 1285static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1286 unsigned int _pin, 1287 unsigned long *config) 1288{ 1289 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1290 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1291 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1292 u32 param = pinconf_to_config_param(*config); 1293 u64 *pin_data = pin->drv_data; 1294 unsigned int arg = 0; 1295 u32 off; 1296 u32 cfg; 1297 int ret; 1298 u8 bit; 1299 1300 if (!pin_data) 1301 return -EINVAL; 1302 1303 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1304 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1305 if (*pin_data & RZG2L_SINGLE_PIN) { 1306 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1307 } else { 1308 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1309 1310 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1311 return -EINVAL; 1312 } 1313 1314 switch (param) { 1315 case PIN_CONFIG_INPUT_ENABLE: 1316 if (!(cfg & PIN_CFG_IEN)) 1317 return -EINVAL; 1318 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1319 if (!arg) 1320 return -EINVAL; 1321 break; 1322 1323 case PIN_CONFIG_OUTPUT_ENABLE: 1324 if (!(cfg & PIN_CFG_OEN)) 1325 return -EINVAL; 1326 ret = rzg2l_read_oen(pctrl, _pin); 1327 if (ret < 0) 1328 return ret; 1329 arg = ret; 1330 break; 1331 1332 case PIN_CONFIG_POWER_SOURCE: 1333 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1334 if (ret < 0) 1335 return ret; 1336 arg = ret; 1337 break; 1338 1339 case PIN_CONFIG_SLEW_RATE: 1340 if (!(cfg & PIN_CFG_SR)) 1341 return -EINVAL; 1342 1343 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); 1344 break; 1345 1346 case PIN_CONFIG_BIAS_DISABLE: 1347 case PIN_CONFIG_BIAS_PULL_UP: 1348 case PIN_CONFIG_BIAS_PULL_DOWN: 1349 if (!(cfg & PIN_CFG_PUPD)) 1350 return -EINVAL; 1351 1352 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); 1353 ret = pctrl->data->hw_to_bias_param(arg); 1354 if (ret < 0) 1355 return ret; 1356 1357 if (ret != param) 1358 return -EINVAL; 1359 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 1360 arg = 1; 1361 break; 1362 1363 case PIN_CONFIG_DRIVE_STRENGTH: { 1364 unsigned int index; 1365 1366 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1367 return -EINVAL; 1368 1369 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1370 /* 1371 * Drive strenght mA is supported only by group A and only 1372 * for 3V3 port source. 1373 */ 1374 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1375 break; 1376 } 1377 1378 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1379 enum rzg2l_iolh_index iolh_idx; 1380 u8 val; 1381 1382 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1383 !hwcfg->drive_strength_ua) 1384 return -EINVAL; 1385 1386 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1387 if (ret < 0) 1388 return ret; 1389 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1390 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1391 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1392 break; 1393 } 1394 1395 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1396 unsigned int index; 1397 1398 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1399 return -EINVAL; 1400 1401 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1402 arg = hwcfg->iolh_groupb_oi[index]; 1403 break; 1404 } 1405 1406 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1407 case PIN_CONFIG_DRIVE_PUSH_PULL: 1408 if (!(cfg & PIN_CFG_NOD)) 1409 return -EINVAL; 1410 1411 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); 1412 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) 1413 return -EINVAL; 1414 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) 1415 return -EINVAL; 1416 break; 1417 1418 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1419 if (!(cfg & PIN_CFG_SMT)) 1420 return -EINVAL; 1421 1422 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); 1423 if (!arg) 1424 return -EINVAL; 1425 break; 1426 1427 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1428 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1429 return -EINVAL; 1430 1431 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1432 break; 1433 1434 default: 1435 return -ENOTSUPP; 1436 } 1437 1438 *config = pinconf_to_config_packed(param, arg); 1439 1440 return 0; 1441} 1442 1443static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1444 unsigned int _pin, 1445 unsigned long *_configs, 1446 unsigned int num_configs) 1447{ 1448 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1449 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1450 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1451 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1452 u64 *pin_data = pin->drv_data; 1453 unsigned int i, arg, index; 1454 u32 off, param; 1455 u32 cfg; 1456 int ret; 1457 u8 bit; 1458 1459 if (!pin_data) 1460 return -EINVAL; 1461 1462 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1463 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1464 if (*pin_data & RZG2L_SINGLE_PIN) { 1465 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1466 } else { 1467 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1468 1469 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1470 return -EINVAL; 1471 } 1472 1473 for (i = 0; i < num_configs; i++) { 1474 param = pinconf_to_config_param(_configs[i]); 1475 arg = pinconf_to_config_argument(_configs[i]); 1476 switch (param) { 1477 case PIN_CONFIG_INPUT_ENABLE: 1478 1479 if (!(cfg & PIN_CFG_IEN)) 1480 return -EINVAL; 1481 1482 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1483 break; 1484 1485 case PIN_CONFIG_OUTPUT_ENABLE: 1486 if (!(cfg & PIN_CFG_OEN)) 1487 return -EINVAL; 1488 ret = rzg2l_write_oen(pctrl, _pin, !!arg); 1489 if (ret) 1490 return ret; 1491 break; 1492 1493 case PIN_CONFIG_POWER_SOURCE: 1494 settings.power_source = arg; 1495 break; 1496 1497 case PIN_CONFIG_SLEW_RATE: 1498 if (!(cfg & PIN_CFG_SR) || arg > 1) 1499 return -EINVAL; 1500 1501 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); 1502 break; 1503 1504 case PIN_CONFIG_BIAS_DISABLE: 1505 case PIN_CONFIG_BIAS_PULL_UP: 1506 case PIN_CONFIG_BIAS_PULL_DOWN: 1507 if (!(cfg & PIN_CFG_PUPD)) 1508 return -EINVAL; 1509 1510 ret = pctrl->data->bias_param_to_hw(param); 1511 if (ret < 0) 1512 return ret; 1513 1514 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); 1515 break; 1516 1517 case PIN_CONFIG_DRIVE_STRENGTH: 1518 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1519 return -EINVAL; 1520 1521 for (index = RZG2L_IOLH_IDX_3V3; 1522 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1523 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1524 break; 1525 } 1526 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1527 return -EINVAL; 1528 1529 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1530 break; 1531 1532 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1533 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1534 !hwcfg->drive_strength_ua) 1535 return -EINVAL; 1536 1537 settings.drive_strength_ua = arg; 1538 break; 1539 1540 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1541 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1542 return -EINVAL; 1543 1544 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1545 if (arg == hwcfg->iolh_groupb_oi[index]) 1546 break; 1547 } 1548 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1549 return -EINVAL; 1550 1551 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1552 break; 1553 1554 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1555 case PIN_CONFIG_DRIVE_PUSH_PULL: 1556 if (!(cfg & PIN_CFG_NOD)) 1557 return -EINVAL; 1558 1559 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, 1560 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); 1561 break; 1562 1563 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1564 if (!(cfg & PIN_CFG_SMT)) 1565 return -EINVAL; 1566 1567 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); 1568 break; 1569 1570 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1571 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1572 return -EINVAL; 1573 1574 if (arg > 3) 1575 return -EINVAL; 1576 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); 1577 break; 1578 1579 default: 1580 return -EOPNOTSUPP; 1581 } 1582 } 1583 1584 /* Apply power source. */ 1585 if (settings.power_source != pctrl->settings[_pin].power_source) { 1586 ret = rzg2l_ps_is_supported(settings.power_source); 1587 if (!ret) 1588 return -EINVAL; 1589 1590 /* Apply power source. */ 1591 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1592 if (ret) 1593 return ret; 1594 } 1595 1596 /* Apply drive strength. */ 1597 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1598 enum rzg2l_iolh_index iolh_idx; 1599 int val; 1600 1601 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1602 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1603 settings.drive_strength_ua); 1604 if (!ret) 1605 return -EINVAL; 1606 1607 /* Get register value for this PS/DS tuple. */ 1608 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1609 if (val < 0) 1610 return val; 1611 1612 /* Apply drive strength. */ 1613 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1614 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1615 } 1616 1617 return 0; 1618} 1619 1620static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1621 unsigned int group, 1622 unsigned long *configs, 1623 unsigned int num_configs) 1624{ 1625 const unsigned int *pins; 1626 unsigned int i, npins; 1627 int ret; 1628 1629 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1630 if (ret) 1631 return ret; 1632 1633 for (i = 0; i < npins; i++) { 1634 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1635 num_configs); 1636 if (ret) 1637 return ret; 1638 } 1639 1640 return 0; 1641} 1642 1643static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1644 unsigned int group, 1645 unsigned long *config) 1646{ 1647 const unsigned int *pins; 1648 unsigned int i, npins, prev_config = 0; 1649 int ret; 1650 1651 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1652 if (ret) 1653 return ret; 1654 1655 for (i = 0; i < npins; i++) { 1656 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1657 if (ret) 1658 return ret; 1659 1660 /* Check config matching between to pin */ 1661 if (i && prev_config != *config) 1662 return -EOPNOTSUPP; 1663 1664 prev_config = *config; 1665 } 1666 1667 return 0; 1668} 1669 1670static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1671 .get_groups_count = pinctrl_generic_get_group_count, 1672 .get_group_name = pinctrl_generic_get_group_name, 1673 .get_group_pins = pinctrl_generic_get_group_pins, 1674 .dt_node_to_map = rzg2l_dt_node_to_map, 1675 .dt_free_map = rzg2l_dt_free_map, 1676}; 1677 1678static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1679 .get_functions_count = pinmux_generic_get_function_count, 1680 .get_function_name = pinmux_generic_get_function_name, 1681 .get_function_groups = pinmux_generic_get_function_groups, 1682 .set_mux = rzg2l_pinctrl_set_mux, 1683 .strict = true, 1684}; 1685 1686static const struct pinconf_ops rzg2l_pinctrl_confops = { 1687 .is_generic = true, 1688 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1689 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1690 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1691 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1692 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1693}; 1694 1695static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1696{ 1697 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1698 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1699 u64 *pin_data = pin_desc->drv_data; 1700 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1701 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1702 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1703 unsigned long flags; 1704 u8 reg8; 1705 int ret; 1706 1707 ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit); 1708 if (ret) 1709 return ret; 1710 1711 ret = pinctrl_gpio_request(chip, offset); 1712 if (ret) 1713 return ret; 1714 1715 raw_spin_lock_irqsave(&pctrl->lock, flags); 1716 1717 /* Select GPIO mode in PMC Register */ 1718 reg8 = readb(pctrl->base + PMC(off)); 1719 reg8 &= ~BIT(bit); 1720 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); 1721 1722 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1723 1724 return 0; 1725} 1726 1727static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1728 bool output) 1729{ 1730 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1731 u64 *pin_data = pin_desc->drv_data; 1732 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1733 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1734 unsigned long flags; 1735 u16 reg16; 1736 1737 raw_spin_lock_irqsave(&pctrl->lock, flags); 1738 1739 reg16 = readw(pctrl->base + PM(off)); 1740 reg16 &= ~(PM_MASK << (bit * 2)); 1741 1742 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1743 writew(reg16, pctrl->base + PM(off)); 1744 1745 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1746} 1747 1748static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1749{ 1750 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1751 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1752 u64 *pin_data = pin_desc->drv_data; 1753 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1754 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1755 1756 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1757 u16 reg16; 1758 1759 reg16 = readw(pctrl->base + PM(off)); 1760 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1761 if (reg16 == PM_OUTPUT) 1762 return GPIO_LINE_DIRECTION_OUT; 1763 } 1764 1765 return GPIO_LINE_DIRECTION_IN; 1766} 1767 1768static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1769 unsigned int offset) 1770{ 1771 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1772 1773 rzg2l_gpio_set_direction(pctrl, offset, false); 1774 1775 return 0; 1776} 1777 1778static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1779 int value) 1780{ 1781 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1782 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1783 u64 *pin_data = pin_desc->drv_data; 1784 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1785 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1786 unsigned long flags; 1787 u8 reg8; 1788 1789 raw_spin_lock_irqsave(&pctrl->lock, flags); 1790 1791 reg8 = readb(pctrl->base + P(off)); 1792 1793 if (value) 1794 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1795 else 1796 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1797 1798 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1799 1800 return 0; 1801} 1802 1803static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1804 unsigned int offset, int value) 1805{ 1806 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1807 1808 rzg2l_gpio_set(chip, offset, value); 1809 rzg2l_gpio_set_direction(pctrl, offset, true); 1810 1811 return 0; 1812} 1813 1814static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1815{ 1816 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1817 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1818 u64 *pin_data = pin_desc->drv_data; 1819 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1820 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1821 u16 reg16; 1822 1823 reg16 = readw(pctrl->base + PM(off)); 1824 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1825 1826 if (reg16 == PM_INPUT) 1827 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 1828 else if (reg16 == PM_OUTPUT) 1829 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 1830 else 1831 return -EINVAL; 1832} 1833 1834static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 1835{ 1836 unsigned int virq; 1837 1838 pinctrl_gpio_free(chip, offset); 1839 1840 virq = irq_find_mapping(chip->irq.domain, offset); 1841 if (virq) 1842 irq_dispose_mapping(virq); 1843 1844 /* 1845 * Set the GPIO as an input to ensure that the next GPIO request won't 1846 * drive the GPIO pin as an output. 1847 */ 1848 rzg2l_gpio_direction_input(chip, offset); 1849} 1850 1851static const char * const rzg2l_gpio_names[] = { 1852 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 1853 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 1854 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 1855 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 1856 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 1857 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 1858 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 1859 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 1860 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 1861 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 1862 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 1863 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 1864 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 1865 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 1866 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 1867 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 1868 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 1869 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 1870 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 1871 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 1872 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 1873 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 1874 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 1875 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 1876 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 1877 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 1878 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 1879 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 1880 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 1881 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 1882 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 1883 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 1884 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 1885 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 1886 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 1887 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 1888 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 1889 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 1890 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 1891 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 1892 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 1893 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 1894 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 1895 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 1896 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 1897 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 1898 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 1899 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 1900 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 1901}; 1902 1903static const u64 r9a07g044_gpio_configs[] = { 1904 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 1905 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 1906 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 1907 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 1908 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 1909 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 1910 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 1911 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 1912 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 1913 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 1914 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 1915 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1916 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1917 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1918 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1919 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1920 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1921 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 1922 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1923 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1924 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1925 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1926 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1927 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1928 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1929 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1930 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1931 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1932 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1933 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1934 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1935 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1936 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1937 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1938 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1939 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1940 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1941 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1942 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1943 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1944 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1945 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1946 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1947 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1948 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1949 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1950 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1951 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1952 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1953}; 1954 1955static const u64 r9a07g043_gpio_configs[] = { 1956 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1957 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 1958 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1959 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1960 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1961 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1962 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1963 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 1964 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1965 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1966 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1967 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1968 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1969 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1970 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1971 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1972 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1973 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1974 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1975#ifdef CONFIG_RISCV 1976 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 1977 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1978 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 1979 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ 1980 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1981 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 1982 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 1983 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 1984 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ 1985 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ 1986 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF | 1987 PIN_CFG_NOGPIO_INT), /* P25 */ 1988 0x0, /* P26 */ 1989 0x0, /* P27 */ 1990 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 1991#endif 1992}; 1993 1994static const u64 r9a08g045_gpio_configs[] = { 1995 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 1996 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 1997 PIN_CFG_IO_VMC_ETH0)) | 1998 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 1999 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2000 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 2001 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2002 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 2003 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2004 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 2005 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 2006 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 2007 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2008 PIN_CFG_IO_VMC_ETH1)) | 2009 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 2010 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2011 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 2012 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2013 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 2014 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2015 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 2016 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 2017 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 2018 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 2019 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 2020 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 2021 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 2022 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 2023 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 2024}; 2025 2026static const char * const rzg3e_gpio_names[] = { 2027 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2028 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2029 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2030 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2031 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2032 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2033 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2034 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2035 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2036 "", "", "", "", "", "", "", "", 2037 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2038 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2039 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", 2040 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 2041 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", 2042 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", 2043 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", 2044 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", 2045 "", "", "", "", "", "", "", "", 2046 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", 2047 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", 2048 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", 2049 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", 2050 "", "", "", "", "", "", "", "", 2051 "", "", "", "", "", "", "", "", 2052 "", "", "", "", "", "", "", "", 2053 "", "", "", "", "", "", "", "", 2054 "", "", "", "", "", "", "", "", 2055 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", 2056}; 2057 2058static const u64 r9a09g047_gpio_configs[] = { 2059 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2060 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS | 2061 PIN_CFG_ELC), /* P1 */ 2062 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2063 PIN_CFG_NOD), /* P2 */ 2064 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2065 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2066 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2067 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */ 2068 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS | 2069 PIN_CFG_ELC), /* P7 */ 2070 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 2071 0x0, 2072 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ 2073 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ 2074 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ 2075 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ 2076 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ 2077 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ 2078 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ 2079 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 2080 0x0, 2081 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ 2082 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ 2083 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ 2084 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 2085 0x0, 2086 0x0, 2087 0x0, 2088 0x0, 2089 0x0, 2090 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ 2091}; 2092 2093static const char * const rzv2h_gpio_names[] = { 2094 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2095 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2096 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2097 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2098 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2099 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2100 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2101 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2102 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2103 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", 2104 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2105 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2106}; 2107 2108static const u64 r9a09g057_gpio_configs[] = { 2109 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2110 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */ 2111 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2112 PIN_CFG_NOD), /* P2 */ 2113 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2114 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2115 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2116 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS | 2117 PIN_CFG_ELC), /* P6 */ 2118 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */ 2119 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS | 2120 PIN_CFG_ELC), /* P8 */ 2121 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ 2122 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ 2123 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ 2124}; 2125 2126static const struct { 2127 struct rzg2l_dedicated_configs common[35]; 2128 struct rzg2l_dedicated_configs rzg2l_pins[7]; 2129} rzg2l_dedicated_pins = { 2130 .common = { 2131 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2132 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 2133 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2134 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 2135 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2136 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 2137 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 2138 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2139 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2140 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2141 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2142 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 2143 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2144 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 2145 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2146 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 2147 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2148 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 2149 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2150 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 2151 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2152 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 2153 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2154 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 2155 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2156 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 2157 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2158 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 2159 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2160 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 2161 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 2162 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 2163 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2164 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2165 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2166 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2167 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2168 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2169 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2170 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2171 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2172 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2173 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2174 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2175 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2176 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2177 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2178 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2179 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2180 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2181 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2182 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2183 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2184 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 2185 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2186 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 2187 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2188 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 2189 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 2190 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 2191 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 2192 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 2193 }, 2194 .rzg2l_pins = { 2195 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2196 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 2197 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2198 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 2199 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2200 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 2201 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2202 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 2203 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2204 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 2205 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2206 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 2207 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2208 } 2209}; 2210 2211static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 2212 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) }, 2213 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 2214 PIN_CFG_SOFT_PS)) }, 2215 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 2216 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, 2217 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, 2218 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 2219 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2220 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2221 PIN_CFG_IO_VMC_SD0)) }, 2222 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2223 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2224 PIN_CFG_IO_VMC_SD0)) }, 2225 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2226 PIN_CFG_IO_VMC_SD0)) }, 2227 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2228 PIN_CFG_IO_VMC_SD0)) }, 2229 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2230 PIN_CFG_IO_VMC_SD0)) }, 2231 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2232 PIN_CFG_IO_VMC_SD0)) }, 2233 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2234 PIN_CFG_IO_VMC_SD0)) }, 2235 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2236 PIN_CFG_IO_VMC_SD0)) }, 2237 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2238 PIN_CFG_IO_VMC_SD0)) }, 2239 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 2240 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2241 PIN_CFG_IO_VMC_SD1)) }, 2242 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2243 PIN_CFG_IO_VMC_SD1)) }, 2244 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2245 PIN_CFG_IO_VMC_SD1)) }, 2246 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2247 PIN_CFG_IO_VMC_SD1)) }, 2248 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2249 PIN_CFG_IO_VMC_SD1)) }, 2250}; 2251 2252static const struct { 2253 struct rzg2l_dedicated_configs common[77]; 2254 struct rzg2l_dedicated_configs pcie1[1]; 2255} rzv2h_dedicated_pins = { 2256 .common = { 2257 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2258 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2259 PIN_CFG_IEN)) }, 2260 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2261 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2262 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2263 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2264 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2265 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2266 PIN_CFG_PUPD)) }, 2267 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2268 PIN_CFG_PUPD)) }, 2269 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2270 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2271 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2272 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2273 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2274 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2275 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2276 PIN_CFG_PUPD)) }, 2277 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2278 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2279 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, 2280 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, 2281 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, 2282 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2283 PIN_CFG_PUPD)) }, 2284 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2285 PIN_CFG_PUPD)) }, 2286 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2287 PIN_CFG_PUPD)) }, 2288 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2289 PIN_CFG_PUPD)) }, 2290 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2291 PIN_CFG_PUPD)) }, 2292 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2293 PIN_CFG_PUPD)) }, 2294 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2295 PIN_CFG_PUPD)) }, 2296 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2297 PIN_CFG_PUPD)) }, 2298 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2299 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2300 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2301 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2302 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2303 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2304 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2305 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2306 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2307 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2308 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2309 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2310 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2311 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2312 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2313 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2314 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2315 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2316 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2317 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2318 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2319 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2320 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2321 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2322 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2323 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2324 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2325 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2326 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2327 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2328 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2329 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | 2330 PIN_CFG_SR)) }, 2331 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2332 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2333 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2334 PIN_CFG_PUPD)) }, 2335 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, 2336 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | 2337 PIN_CFG_SR | 2338 PIN_CFG_PUPD)) }, 2339 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2340 PIN_CFG_PUPD)) }, 2341 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, 2342 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, 2343 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2344 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2345 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, 2346 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, 2347 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2348 PIN_CFG_PUPD)) }, 2349 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2350 PIN_CFG_PUPD)) }, 2351 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2352 PIN_CFG_PUPD)) }, 2353 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2354 PIN_CFG_PUPD)) }, 2355 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, 2356 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, 2357 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, 2358 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, 2359 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2360 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2361 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2362 PIN_CFG_PUPD)) }, 2363 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, 2364 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | 2365 PIN_CFG_SR | 2366 PIN_CFG_PUPD)) }, 2367 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2368 PIN_CFG_PUPD)) }, 2369 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, 2370 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, 2371 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2372 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2373 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, 2374 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, 2375 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2376 PIN_CFG_PUPD)) }, 2377 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2378 PIN_CFG_PUPD)) }, 2379 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2380 PIN_CFG_PUPD)) }, 2381 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2382 PIN_CFG_PUPD)) }, 2383 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, 2384 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, 2385 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, 2386 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, 2387 }, 2388 .pcie1 = { 2389 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | 2390 PIN_CFG_SR)) }, 2391 }, 2392}; 2393 2394static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { 2395 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, 2396 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2397 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, 2398 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2399 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2400 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2401 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2402 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2403 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2404 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2405 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2406 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2407 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2408 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2409 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2410 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2411 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4, 2412 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2413 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2414 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2415 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2416 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2417 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2418 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2419 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2420 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2421 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2422 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2423 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2424 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2425 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, 2426 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2427 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, 2428 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2429}; 2430 2431static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 2432{ 2433 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 2434 const struct rzg2l_pinctrl_data *data = pctrl->data; 2435 u64 *pin_data = pin_desc->drv_data; 2436 unsigned int gpioint; 2437 unsigned int i; 2438 u32 port, bit; 2439 2440 if (*pin_data & PIN_CFG_NOGPIO_INT) 2441 return -EINVAL; 2442 2443 port = virq / 8; 2444 bit = virq % 8; 2445 2446 if (port >= data->n_ports || 2447 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 2448 return -EINVAL; 2449 2450 gpioint = bit; 2451 for (i = 0; i < port; i++) 2452 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 2453 2454 return gpioint; 2455} 2456 2457static void __rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2458 unsigned int hwirq, bool enable) 2459{ 2460 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 2461 u64 *pin_data = pin_desc->drv_data; 2462 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2463 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 2464 void __iomem *addr; 2465 2466 addr = pctrl->base + ISEL(off); 2467 if (bit >= 4) { 2468 bit -= 4; 2469 addr += 4; 2470 } 2471 2472 if (enable) 2473 writel(readl(addr) | BIT(bit * 8), addr); 2474 else 2475 writel(readl(addr) & ~BIT(bit * 8), addr); 2476} 2477 2478static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2479 unsigned int hwirq, bool enable) 2480{ 2481 unsigned long flags; 2482 2483 raw_spin_lock_irqsave(&pctrl->lock, flags); 2484 __rzg2l_gpio_irq_endisable(pctrl, hwirq, enable); 2485 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 2486} 2487 2488static void rzg2l_gpio_irq_disable(struct irq_data *d) 2489{ 2490 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2491 unsigned int hwirq = irqd_to_hwirq(d); 2492 2493 irq_chip_disable_parent(d); 2494 gpiochip_disable_irq(gc, hwirq); 2495} 2496 2497static void __rzg2l_gpio_irq_enable(struct irq_data *d, bool lock) 2498{ 2499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2500 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2501 unsigned int hwirq = irqd_to_hwirq(d); 2502 2503 gpiochip_enable_irq(gc, hwirq); 2504 if (lock) 2505 rzg2l_gpio_irq_endisable(pctrl, hwirq, true); 2506 else 2507 __rzg2l_gpio_irq_endisable(pctrl, hwirq, true); 2508 irq_chip_enable_parent(d); 2509} 2510 2511static void rzg2l_gpio_irq_enable(struct irq_data *d) 2512{ 2513 __rzg2l_gpio_irq_enable(d, true); 2514} 2515 2516static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 2517{ 2518 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2519 2520 seq_puts(p, dev_name(gc->parent)); 2521} 2522 2523static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 2524{ 2525 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2526 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2527 int ret; 2528 2529 /* It should not happen. */ 2530 if (!data->parent_data) 2531 return -EOPNOTSUPP; 2532 2533 ret = irq_chip_set_wake_parent(data, on); 2534 if (ret) 2535 return ret; 2536 2537 if (on) 2538 atomic_inc(&pctrl->wakeup_path); 2539 else 2540 atomic_dec(&pctrl->wakeup_path); 2541 2542 return 0; 2543} 2544 2545static const struct irq_chip rzg2l_gpio_irqchip = { 2546 .name = "rzg2l-gpio", 2547 .irq_disable = rzg2l_gpio_irq_disable, 2548 .irq_enable = rzg2l_gpio_irq_enable, 2549 .irq_mask = irq_chip_mask_parent, 2550 .irq_unmask = irq_chip_unmask_parent, 2551 .irq_set_type = irq_chip_set_type_parent, 2552 .irq_eoi = irq_chip_eoi_parent, 2553 .irq_print_chip = rzg2l_gpio_irq_print_chip, 2554 .irq_set_affinity = irq_chip_set_affinity_parent, 2555 .irq_set_wake = rzg2l_gpio_irq_set_wake, 2556 .flags = IRQCHIP_IMMUTABLE, 2557 GPIOCHIP_IRQ_RESOURCE_HELPERS, 2558}; 2559 2560static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 2561{ 2562 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 2563 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 2564 u64 *pin_data = pin_desc->drv_data; 2565 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2566 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 2567 u8 reg8; 2568 int ret; 2569 2570 reg8 = readb(pctrl->base + PMC(off)); 2571 if (reg8 & BIT(bit)) { 2572 ret = rzg2l_gpio_request(chip, offset); 2573 if (ret) 2574 return ret; 2575 } 2576 2577 return rzg2l_gpio_direction_input(chip, offset); 2578} 2579 2580static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 2581 unsigned int child, 2582 unsigned int child_type, 2583 unsigned int *parent, 2584 unsigned int *parent_type) 2585{ 2586 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2587 unsigned long flags; 2588 int gpioint, irq; 2589 int ret; 2590 2591 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2592 if (gpioint < 0) 2593 return gpioint; 2594 2595 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2596 if (ret) 2597 return ret; 2598 2599 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2600 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2601 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2602 if (irq < 0) { 2603 ret = -ENOSPC; 2604 goto err; 2605 } 2606 2607 rzg2l_gpio_irq_endisable(pctrl, child, true); 2608 pctrl->hwirq[irq] = child; 2609 irq += pctrl->data->hwcfg->tint_start_index; 2610 2611 /* All these interrupts are level high in the CPU */ 2612 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2613 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2614 return 0; 2615 2616err: 2617 rzg2l_gpio_free(gc, child); 2618 return ret; 2619} 2620 2621static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2622{ 2623 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2624 2625 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2626 struct irq_data *data; 2627 unsigned long flags; 2628 unsigned int virq; 2629 int ret; 2630 2631 if (!pctrl->hwirq[i]) 2632 continue; 2633 2634 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2635 if (!virq) { 2636 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 2637 pctrl->hwirq[i]); 2638 continue; 2639 } 2640 2641 data = irq_domain_get_irq_data(domain, virq); 2642 if (!data) { 2643 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 2644 continue; 2645 } 2646 2647 /* 2648 * This has to be atomically executed to protect against a concurrent 2649 * interrupt. 2650 */ 2651 raw_spin_lock_irqsave(&pctrl->lock, flags); 2652 ret = irq_chip_set_type_parent(data, irqd_get_trigger_type(data)); 2653 if (!ret && !irqd_irq_disabled(data)) 2654 __rzg2l_gpio_irq_enable(data, false); 2655 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 2656 2657 if (ret) 2658 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 2659 } 2660} 2661 2662static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 2663 unsigned int nr_irqs) 2664{ 2665 struct irq_data *d; 2666 2667 d = irq_domain_get_irq_data(domain, virq); 2668 if (d) { 2669 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2670 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2671 irq_hw_number_t hwirq = irqd_to_hwirq(d); 2672 unsigned long flags; 2673 unsigned int i; 2674 2675 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2676 if (pctrl->hwirq[i] == hwirq) { 2677 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 2678 rzg2l_gpio_free(gc, hwirq); 2679 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2680 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 2681 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2682 pctrl->hwirq[i] = 0; 2683 break; 2684 } 2685 } 2686 } 2687 irq_domain_free_irqs_common(domain, virq, nr_irqs); 2688} 2689 2690static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 2691 unsigned long *valid_mask, 2692 unsigned int ngpios) 2693{ 2694 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2695 struct gpio_chip *chip = &pctrl->gpio_chip; 2696 unsigned int offset; 2697 2698 /* Forbid unused lines to be mapped as IRQs */ 2699 for (offset = 0; offset < chip->ngpio; offset++) { 2700 u32 port, bit; 2701 2702 port = offset / 8; 2703 bit = offset % 8; 2704 2705 if (port >= pctrl->data->n_ports || 2706 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 2707 pctrl->data->port_pin_configs[port]))) 2708 clear_bit(offset, valid_mask); 2709 } 2710} 2711 2712static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 2713{ 2714 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 2715 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 2716 2717 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 2718 if (!cache) 2719 return -ENOMEM; 2720 2721 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 2722 if (!dedicated_cache) 2723 return -ENOMEM; 2724 2725 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 2726 if (!cache->p) 2727 return -ENOMEM; 2728 2729 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 2730 if (!cache->pm) 2731 return -ENOMEM; 2732 2733 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 2734 if (!cache->pmc) 2735 return -ENOMEM; 2736 2737 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 2738 if (!cache->pfc) 2739 return -ENOMEM; 2740 2741 cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL); 2742 if (!cache->smt) 2743 return -ENOMEM; 2744 2745 for (u8 i = 0; i < 2; i++) { 2746 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 2747 2748 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 2749 GFP_KERNEL); 2750 if (!cache->iolh[i]) 2751 return -ENOMEM; 2752 2753 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 2754 GFP_KERNEL); 2755 if (!cache->ien[i]) 2756 return -ENOMEM; 2757 2758 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), 2759 GFP_KERNEL); 2760 if (!cache->pupd[i]) 2761 return -ENOMEM; 2762 2763 /* Allocate dedicated cache. */ 2764 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2765 sizeof(*dedicated_cache->iolh[i]), 2766 GFP_KERNEL); 2767 if (!dedicated_cache->iolh[i]) 2768 return -ENOMEM; 2769 2770 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 2771 sizeof(*dedicated_cache->ien[i]), 2772 GFP_KERNEL); 2773 if (!dedicated_cache->ien[i]) 2774 return -ENOMEM; 2775 } 2776 2777 pctrl->cache = cache; 2778 pctrl->dedicated_cache = dedicated_cache; 2779 2780 return 0; 2781} 2782 2783static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 2784{ 2785 struct device_node *np = pctrl->dev->of_node; 2786 struct gpio_chip *chip = &pctrl->gpio_chip; 2787 const char *name = dev_name(pctrl->dev); 2788 struct irq_domain *parent_domain; 2789 struct of_phandle_args of_args; 2790 struct device_node *parent_np; 2791 struct gpio_irq_chip *girq; 2792 int ret; 2793 2794 parent_np = of_irq_find_parent(np); 2795 if (!parent_np) 2796 return -ENXIO; 2797 2798 parent_domain = irq_find_host(parent_np); 2799 of_node_put(parent_np); 2800 if (!parent_domain) 2801 return -EPROBE_DEFER; 2802 2803 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 2804 if (ret) 2805 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); 2806 2807 of_node_put(of_args.np); 2808 2809 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 2810 of_args.args[2] != pctrl->data->n_port_pins) 2811 return dev_err_probe(pctrl->dev, -EINVAL, 2812 "gpio-ranges does not match selected SOC\n"); 2813 2814 chip->names = pctrl->data->port_pins; 2815 chip->request = rzg2l_gpio_request; 2816 chip->free = rzg2l_gpio_free; 2817 chip->get_direction = rzg2l_gpio_get_direction; 2818 chip->direction_input = rzg2l_gpio_direction_input; 2819 chip->direction_output = rzg2l_gpio_direction_output; 2820 chip->get = rzg2l_gpio_get; 2821 chip->set = rzg2l_gpio_set; 2822 chip->label = name; 2823 chip->parent = pctrl->dev; 2824 chip->owner = THIS_MODULE; 2825 chip->base = -1; 2826 chip->ngpio = of_args.args[2]; 2827 2828 girq = &chip->irq; 2829 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 2830 girq->fwnode = dev_fwnode(pctrl->dev); 2831 girq->parent_domain = parent_domain; 2832 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 2833 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 2834 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 2835 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 2836 2837 pctrl->gpio_range.id = 0; 2838 pctrl->gpio_range.pin_base = 0; 2839 pctrl->gpio_range.base = 0; 2840 pctrl->gpio_range.npins = chip->ngpio; 2841 pctrl->gpio_range.name = chip->label; 2842 pctrl->gpio_range.gc = chip; 2843 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 2844 if (ret) 2845 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); 2846 2847 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 2848 2849 return 0; 2850} 2851 2852static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 2853{ 2854 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 2855 struct pinctrl_pin_desc *pins; 2856 unsigned int i, j; 2857 u64 *pin_data; 2858 int ret; 2859 2860 pctrl->desc.name = DRV_NAME; 2861 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 2862 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 2863 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 2864 pctrl->desc.confops = &rzg2l_pinctrl_confops; 2865 pctrl->desc.owner = THIS_MODULE; 2866 if (pctrl->data->num_custom_params) { 2867 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; 2868 pctrl->desc.custom_params = pctrl->data->custom_params; 2869#ifdef CONFIG_DEBUG_FS 2870 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; 2871#endif 2872 } 2873 2874 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 2875 if (!pins) 2876 return -ENOMEM; 2877 2878 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 2879 sizeof(*pin_data), GFP_KERNEL); 2880 if (!pin_data) 2881 return -ENOMEM; 2882 2883 pctrl->pins = pins; 2884 pctrl->desc.pins = pins; 2885 2886 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 2887 pins[i].number = i; 2888 pins[i].name = pctrl->data->port_pins[i]; 2889 if (i && !(i % RZG2L_PINS_PER_PORT)) 2890 j++; 2891 pin_data[i] = pctrl->data->port_pin_configs[j]; 2892 if (pin_data[i] & RZG2L_VARIABLE_CFG) 2893 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 2894 pin_data[i], 2895 j, 2896 i % RZG2L_PINS_PER_PORT); 2897 pins[i].drv_data = &pin_data[i]; 2898 } 2899 2900 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 2901 unsigned int index = pctrl->data->n_port_pins + i; 2902 2903 pins[index].number = index; 2904 pins[index].name = pctrl->data->dedicated_pins[i].name; 2905 pin_data[index] = pctrl->data->dedicated_pins[i].config; 2906 pins[index].drv_data = &pin_data[index]; 2907 } 2908 2909 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 2910 GFP_KERNEL); 2911 if (!pctrl->settings) 2912 return -ENOMEM; 2913 2914 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 2915 if (pin_data[i] & PIN_CFG_SOFT_PS) { 2916 pctrl->settings[i].power_source = 3300; 2917 } else { 2918 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 2919 if (ret < 0) 2920 continue; 2921 pctrl->settings[i].power_source = ret; 2922 } 2923 } 2924 2925 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 2926 if (ret) 2927 return ret; 2928 2929 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 2930 &pctrl->pctl); 2931 if (ret) 2932 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); 2933 2934 ret = pinctrl_enable(pctrl->pctl); 2935 if (ret) 2936 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); 2937 2938 ret = rzg2l_gpio_register(pctrl); 2939 if (ret) 2940 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); 2941 2942 return 0; 2943} 2944 2945static int rzg2l_pinctrl_probe(struct platform_device *pdev) 2946{ 2947 struct rzg2l_pinctrl *pctrl; 2948 int ret; 2949 2950 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 2951 ARRAY_SIZE(rzg2l_gpio_names)); 2952 2953 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 2954 ARRAY_SIZE(rzg2l_gpio_names)); 2955 2956 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 2957 ARRAY_SIZE(rzg2l_gpio_names)); 2958 2959 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > 2960 ARRAY_SIZE(rzg3e_gpio_names)); 2961 2962 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > 2963 ARRAY_SIZE(rzv2h_gpio_names)); 2964 2965 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 2966 if (!pctrl) 2967 return -ENOMEM; 2968 2969 pctrl->dev = &pdev->dev; 2970 2971 pctrl->data = of_device_get_match_data(&pdev->dev); 2972 if (!pctrl->data) 2973 return -EINVAL; 2974 2975 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 2976 if (IS_ERR(pctrl->base)) 2977 return PTR_ERR(pctrl->base); 2978 2979 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 2980 if (IS_ERR(pctrl->clk)) { 2981 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 2982 "failed to enable GPIO clk\n"); 2983 } 2984 2985 raw_spin_lock_init(&pctrl->lock); 2986 spin_lock_init(&pctrl->bitmap_lock); 2987 mutex_init(&pctrl->mutex); 2988 atomic_set(&pctrl->wakeup_path, 0); 2989 2990 platform_set_drvdata(pdev, pctrl); 2991 2992 ret = rzg2l_pinctrl_register(pctrl); 2993 if (ret) 2994 return ret; 2995 2996 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 2997 return 0; 2998} 2999 3000static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 3001{ 3002 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3003 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3004 3005 for (u32 port = 0; port < nports; port++) { 3006 bool has_iolh, has_ien, has_pupd, has_smt; 3007 u32 off, caps; 3008 u8 pincnt; 3009 u64 cfg; 3010 3011 cfg = pctrl->data->port_pin_configs[port]; 3012 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3013 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 3014 3015 caps = FIELD_GET(PIN_CFG_MASK, cfg); 3016 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 3017 has_ien = !!(caps & PIN_CFG_IEN); 3018 has_pupd = !!(caps & PIN_CFG_PUPD); 3019 has_smt = !!(caps & PIN_CFG_SMT); 3020 3021 if (suspend) 3022 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 3023 3024 /* 3025 * Now cache the registers or set them in the order suggested by 3026 * HW manual (section "Operation for GPIO Function"). 3027 */ 3028 if (suspend) 3029 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 3030 else 3031 pctrl->data->pmc_writeb(pctrl, cache->pmc[port], PMC(off)); 3032 3033 if (has_iolh) { 3034 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 3035 cache->iolh[0][port]); 3036 if (pincnt >= 4) { 3037 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 3038 cache->iolh[1][port]); 3039 } 3040 } 3041 3042 if (has_pupd) { 3043 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3044 cache->pupd[0][port]); 3045 if (pincnt >= 4) { 3046 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3047 cache->pupd[1][port]); 3048 } 3049 } 3050 3051 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 3052 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 3053 3054 if (has_ien) { 3055 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3056 cache->ien[0][port]); 3057 if (pincnt >= 4) { 3058 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 3059 cache->ien[1][port]); 3060 } 3061 } 3062 3063 if (has_smt) 3064 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]); 3065 } 3066} 3067 3068static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 3069{ 3070 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 3071 u32 caps; 3072 u32 i; 3073 3074 /* 3075 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 3076 * port offset are close together. 3077 */ 3078 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 3079 bool has_iolh, has_ien; 3080 u32 off, next_off = 0; 3081 u64 cfg, next_cfg; 3082 u8 pincnt; 3083 3084 cfg = pctrl->data->dedicated_pins[i].config; 3085 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3086 if (i + 1 < pctrl->data->n_dedicated_pins) { 3087 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 3088 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 3089 } 3090 3091 if (off == next_off) { 3092 /* Gather caps of all port pins. */ 3093 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 3094 continue; 3095 } 3096 3097 /* And apply them in a single shot. */ 3098 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 3099 has_ien = !!(caps & PIN_CFG_IEN); 3100 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 3101 3102 if (has_iolh) { 3103 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 3104 cache->iolh[0][i]); 3105 } 3106 if (has_ien) { 3107 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3108 cache->ien[0][i]); 3109 } 3110 3111 if (pincnt >= 4) { 3112 if (has_iolh) { 3113 RZG2L_PCTRL_REG_ACCESS32(suspend, 3114 pctrl->base + IOLH(off) + 4, 3115 cache->iolh[1][i]); 3116 } 3117 if (has_ien) { 3118 RZG2L_PCTRL_REG_ACCESS32(suspend, 3119 pctrl->base + IEN(off) + 4, 3120 cache->ien[1][i]); 3121 } 3122 } 3123 caps = 0; 3124 } 3125} 3126 3127static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 3128{ 3129 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3130 unsigned long flags; 3131 3132 raw_spin_lock_irqsave(&pctrl->lock, flags); 3133 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 3134 3135 /* Restore port registers. */ 3136 for (u32 port = 0; port < nports; port++) { 3137 unsigned long pinmap; 3138 u8 pmc = 0, max_pin; 3139 u32 off, pfc = 0; 3140 u64 cfg; 3141 u16 pm; 3142 u8 pin; 3143 3144 cfg = pctrl->data->port_pin_configs[port]; 3145 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3146 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 3147 max_pin = fls(pinmap); 3148 3149 pm = readw(pctrl->base + PM(off)); 3150 for_each_set_bit(pin, &pinmap, max_pin) { 3151 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3152 u32 pfc_val, pfc_mask; 3153 3154 /* Nothing to do if PFC was not configured before. */ 3155 if (!(cache->pmc[port] & BIT(pin))) 3156 continue; 3157 3158 pfc_val = readl(pctrl->base + PFC(off)); 3159 pfc_mask = PFC_MASK << (pin * 4); 3160 /* Nothing to do if reset value of the pin is same as cached value */ 3161 if ((cache->pfc[port] & pfc_mask) == (pfc_val & pfc_mask)) 3162 continue; 3163 3164 /* Set pin to 'Non-use (Hi-Z input protection)' */ 3165 pm &= ~(PM_MASK << (pin * 2)); 3166 writew(pm, pctrl->base + PM(off)); 3167 3168 /* Temporarily switch to GPIO mode with PMC register */ 3169 pmc &= ~BIT(pin); 3170 writeb(pmc, pctrl->base + PMC(off)); 3171 3172 /* Select Pin function mode. */ 3173 pfc &= ~pfc_mask; 3174 pfc |= (cache->pfc[port] & pfc_mask); 3175 writel(pfc, pctrl->base + PFC(off)); 3176 3177 /* Switch to Peripheral pin function. */ 3178 pmc |= BIT(pin); 3179 writeb(pmc, pctrl->base + PMC(off)); 3180 } 3181 } 3182 3183 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 3184 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3185} 3186 3187static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 3188{ 3189 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3190 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3191 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3192 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3193 3194 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 3195 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 3196 3197 for (u8 i = 0; i < 2; i++) { 3198 if (regs->sd_ch) 3199 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 3200 if (regs->eth_poc) 3201 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 3202 } 3203 3204 cache->qspi = readb(pctrl->base + QSPI); 3205 cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); 3206 3207 if (!atomic_read(&pctrl->wakeup_path)) 3208 clk_disable_unprepare(pctrl->clk); 3209 else 3210 device_set_wakeup_path(dev); 3211 3212 return 0; 3213} 3214 3215static int rzg2l_pinctrl_resume_noirq(struct device *dev) 3216{ 3217 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3218 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3219 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3220 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3221 unsigned long flags; 3222 int ret; 3223 3224 if (!atomic_read(&pctrl->wakeup_path)) { 3225 ret = clk_prepare_enable(pctrl->clk); 3226 if (ret) 3227 return ret; 3228 } 3229 3230 writeb(cache->qspi, pctrl->base + QSPI); 3231 3232 raw_spin_lock_irqsave(&pctrl->lock, flags); 3233 rzg2l_oen_write_with_pwpr(pctrl, cache->oen); 3234 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3235 3236 for (u8 i = 0; i < 2; i++) { 3237 if (regs->sd_ch) 3238 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 3239 if (regs->eth_poc) 3240 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 3241 } 3242 3243 rzg2l_pinctrl_pm_setup_pfc(pctrl); 3244 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 3245 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 3246 rzg2l_gpio_irq_restore(pctrl); 3247 3248 return 0; 3249} 3250 3251static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3252{ 3253 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3254 3255 if (lock) { 3256 /* Set the PWPR register to be write-protected */ 3257 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3258 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 3259 } else { 3260 /* Set the PWPR register to allow PFC register to write */ 3261 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3262 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 3263 } 3264} 3265 3266static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3267{ 3268 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3269 u8 pwpr; 3270 3271 if (lock) { 3272 /* Set the PWPR register to be write-protected */ 3273 pwpr = readb(pctrl->base + regs->pwpr); 3274 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 3275 } else { 3276 /* Set the PWPR register to allow PFC and PMC register to write */ 3277 pwpr = readb(pctrl->base + regs->pwpr); 3278 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); 3279 } 3280} 3281 3282static const struct rzg2l_hwcfg rzg2l_hwcfg = { 3283 .regs = { 3284 .pwpr = 0x3014, 3285 .sd_ch = 0x3000, 3286 .eth_poc = 0x300c, 3287 .oen = 0x3018, 3288 }, 3289 .iolh_groupa_ua = { 3290 /* 3v3 power source */ 3291 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 3292 }, 3293 .iolh_groupb_oi = { 100, 66, 50, 33, }, 3294 .tint_start_index = 9, 3295 .oen_max_pin = 0, 3296}; 3297 3298static const struct rzg2l_hwcfg rzg3s_hwcfg = { 3299 .regs = { 3300 .pwpr = 0x3000, 3301 .sd_ch = 0x3004, 3302 .eth_poc = 0x3010, 3303 .oen = 0x3018, 3304 }, 3305 .iolh_groupa_ua = { 3306 /* 1v8 power source */ 3307 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3308 /* 3v3 power source */ 3309 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3310 }, 3311 .iolh_groupb_ua = { 3312 /* 1v8 power source */ 3313 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3314 /* 3v3 power source */ 3315 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3316 }, 3317 .iolh_groupc_ua = { 3318 /* 1v8 power source */ 3319 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3320 /* 2v5 source */ 3321 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3322 /* 3v3 power source */ 3323 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3324 }, 3325 .tint_start_index = 9, 3326 .drive_strength_ua = true, 3327 .func_base = 1, 3328 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 3329 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 3330}; 3331 3332static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3333 .regs = { 3334 .pwpr = 0x3c04, 3335 .oen = 0x3c40, 3336 }, 3337 .tint_start_index = 17, 3338 .oen_pwpr_lock = true, 3339}; 3340 3341static struct rzg2l_pinctrl_data r9a07g043_data = { 3342 .port_pins = rzg2l_gpio_names, 3343 .port_pin_configs = r9a07g043_gpio_configs, 3344 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 3345 .dedicated_pins = rzg2l_dedicated_pins.common, 3346 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 3347 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 3348 .hwcfg = &rzg2l_hwcfg, 3349#ifdef CONFIG_RISCV 3350 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 3351 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 3352#endif 3353 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3354 .pmc_writeb = &rzg2l_pmc_writeb, 3355 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3356 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3357 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3358}; 3359 3360static struct rzg2l_pinctrl_data r9a07g044_data = { 3361 .port_pins = rzg2l_gpio_names, 3362 .port_pin_configs = r9a07g044_gpio_configs, 3363 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 3364 .dedicated_pins = rzg2l_dedicated_pins.common, 3365 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 3366 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 3367 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 3368 .hwcfg = &rzg2l_hwcfg, 3369 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3370 .pmc_writeb = &rzg2l_pmc_writeb, 3371 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3372 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3373 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3374}; 3375 3376static struct rzg2l_pinctrl_data r9a08g045_data = { 3377 .port_pins = rzg2l_gpio_names, 3378 .port_pin_configs = r9a08g045_gpio_configs, 3379 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 3380 .dedicated_pins = rzg3s_dedicated_pins, 3381 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 3382 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 3383 .hwcfg = &rzg3s_hwcfg, 3384 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3385 .pmc_writeb = &rzg2l_pmc_writeb, 3386 .pin_to_oen_bit = &rzg3s_pin_to_oen_bit, 3387 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3388 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3389}; 3390 3391static struct rzg2l_pinctrl_data r9a09g047_data = { 3392 .port_pins = rzg3e_gpio_names, 3393 .port_pin_configs = r9a09g047_gpio_configs, 3394 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs), 3395 .dedicated_pins = rzg3e_dedicated_pins, 3396 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, 3397 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins), 3398 .hwcfg = &rzv2h_hwcfg, 3399 .variable_pin_cfg = r9a09g047_variable_pin_cfg, 3400 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg), 3401 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3402 .custom_params = renesas_rzv2h_custom_bindings, 3403#ifdef CONFIG_DEBUG_FS 3404 .custom_conf_items = renesas_rzv2h_conf_items, 3405#endif 3406 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3407 .pmc_writeb = &rzv2h_pmc_writeb, 3408 .pin_to_oen_bit = &rzg3e_pin_to_oen_bit, 3409 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3410 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3411}; 3412 3413static struct rzg2l_pinctrl_data r9a09g056_data = { 3414 .port_pins = rzv2h_gpio_names, 3415 .port_pin_configs = r9a09g057_gpio_configs, 3416 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3417 .dedicated_pins = rzv2h_dedicated_pins.common, 3418 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3419 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common), 3420 .hwcfg = &rzv2h_hwcfg, 3421 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3422 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3423 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3424 .custom_params = renesas_rzv2h_custom_bindings, 3425#ifdef CONFIG_DEBUG_FS 3426 .custom_conf_items = renesas_rzv2h_conf_items, 3427#endif 3428 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3429 .pmc_writeb = &rzv2h_pmc_writeb, 3430 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3431 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3432 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3433}; 3434 3435static struct rzg2l_pinctrl_data r9a09g057_data = { 3436 .port_pins = rzv2h_gpio_names, 3437 .port_pin_configs = r9a09g057_gpio_configs, 3438 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3439 .dedicated_pins = rzv2h_dedicated_pins.common, 3440 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3441 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) + 3442 ARRAY_SIZE(rzv2h_dedicated_pins.pcie1), 3443 .hwcfg = &rzv2h_hwcfg, 3444 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3445 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3446 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3447 .custom_params = renesas_rzv2h_custom_bindings, 3448#ifdef CONFIG_DEBUG_FS 3449 .custom_conf_items = renesas_rzv2h_conf_items, 3450#endif 3451 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3452 .pmc_writeb = &rzv2h_pmc_writeb, 3453 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3454 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3455 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3456}; 3457 3458static const struct of_device_id rzg2l_pinctrl_of_table[] = { 3459 { 3460 .compatible = "renesas,r9a07g043-pinctrl", 3461 .data = &r9a07g043_data, 3462 }, 3463 { 3464 .compatible = "renesas,r9a07g044-pinctrl", 3465 .data = &r9a07g044_data, 3466 }, 3467 { 3468 .compatible = "renesas,r9a08g045-pinctrl", 3469 .data = &r9a08g045_data, 3470 }, 3471 { 3472 .compatible = "renesas,r9a09g047-pinctrl", 3473 .data = &r9a09g047_data, 3474 }, 3475 { 3476 .compatible = "renesas,r9a09g056-pinctrl", 3477 .data = &r9a09g056_data, 3478 }, 3479 { 3480 .compatible = "renesas,r9a09g057-pinctrl", 3481 .data = &r9a09g057_data, 3482 }, 3483 { /* sentinel */ } 3484}; 3485 3486static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 3487 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 3488}; 3489 3490static struct platform_driver rzg2l_pinctrl_driver = { 3491 .driver = { 3492 .name = DRV_NAME, 3493 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 3494 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 3495 .suppress_bind_attrs = true, 3496 }, 3497 .probe = rzg2l_pinctrl_probe, 3498}; 3499 3500static int __init rzg2l_pinctrl_init(void) 3501{ 3502 return platform_driver_register(&rzg2l_pinctrl_driver); 3503} 3504core_initcall(rzg2l_pinctrl_init); 3505 3506MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 3507MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
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