pinctrl-rza2.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
  4 *
  5 * Copyright (C) 2018 Chris Brandt
  6 */
  7
  8/*
  9 * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
 10 * family.
 11 */
 12
 13#include <linux/bitops.h>
 14#include <linux/gpio/driver.h>
 15#include <linux/io.h>
 16#include <linux/module.h>
 17#include <linux/mutex.h>
 18#include <linux/of.h>
 19#include <linux/pinctrl/consumer.h>
 20#include <linux/pinctrl/pinmux.h>
 21#include <linux/platform_device.h>
 22
 23#include "../core.h"
 24#include "../pinmux.h"
 25
 26#define DRIVER_NAME		"pinctrl-rza2"
 27
 28#define RZA2_PINS_PER_PORT	8
 29#define RZA2_PIN_ID_TO_PORT(id)	((id) / RZA2_PINS_PER_PORT)
 30#define RZA2_PIN_ID_TO_PIN(id)	((id) % RZA2_PINS_PER_PORT)
 31
 32/*
 33 * Use 16 lower bits [15:0] for pin identifier
 34 * Use 16 higher bits [31:16] for pin mux function
 35 */
 36#define MUX_PIN_ID_MASK		GENMASK(15, 0)
 37#define MUX_FUNC_MASK		GENMASK(31, 16)
 38#define MUX_FUNC_OFFS		16
 39#define MUX_FUNC(pinconf)	((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
 40
 41static const char port_names[] = "0123456789ABCDEFGHJKLM";
 42
 43struct rza2_pinctrl_priv {
 44	struct device *dev;
 45	void __iomem *base;
 46
 47	struct pinctrl_pin_desc *pins;
 48	struct pinctrl_desc desc;
 49	struct pinctrl_dev *pctl;
 50	struct pinctrl_gpio_range gpio_range;
 51	int npins;
 52	struct mutex mutex; /* serialize adding groups and functions */
 53};
 54
 55#define RZA2_PDR(port)		(0x0000 + (port) * 2)	/* Direction 16-bit */
 56#define RZA2_PODR(port)		(0x0040 + (port))	/* Output Data 8-bit */
 57#define RZA2_PIDR(port)		(0x0060 + (port))	/* Input Data 8-bit */
 58#define RZA2_PMR(port)		(0x0080 + (port))	/* Mode 8-bit */
 59#define RZA2_DSCR(port)		(0x0140 + (port) * 2)	/* Drive 16-bit */
 60#define RZA2_PFS(port, pin)	(0x0200 + ((port) * 8) + (pin))	/* Fnct 8-bit */
 61
 62#define RZA2_PWPR		0x02ff	/* Write Protect 8-bit */
 63#define RZA2_PFENET		0x0820	/* Ethernet Pins 8-bit */
 64#define RZA2_PPOC		0x0900	/* Dedicated Pins 32-bit */
 65#define RZA2_PHMOMO		0x0980	/* Peripheral Pins 32-bit */
 66#define RZA2_PCKIO		0x09d0	/* CKIO Drive 8-bit */
 67
 68#define RZA2_PDR_INPUT		0x02
 69#define RZA2_PDR_OUTPUT		0x03
 70#define RZA2_PDR_MASK		0x03
 71
 72#define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
 73#define PWPR_PFSWE		BIT(6)	/* PFS Register Write Enable */
 74#define PFS_ISEL		BIT(6)	/* Interrupt Select */
 75
 76static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
 77				  u8 func)
 78{
 79	u16 mask16;
 80	u16 reg16;
 81	u8 reg8;
 82
 83	/* Set pin to 'Non-use (Hi-z input protection)'  */
 84	reg16 = readw(pfc_base + RZA2_PDR(port));
 85	mask16 = RZA2_PDR_MASK << (pin * 2);
 86	reg16 &= ~mask16;
 87	writew(reg16, pfc_base + RZA2_PDR(port));
 88
 89	/* Temporarily switch to GPIO */
 90	reg8 = readb(pfc_base + RZA2_PMR(port));
 91	reg8 &= ~BIT(pin);
 92	writeb(reg8, pfc_base + RZA2_PMR(port));
 93
 94	/* PFS Register Write Protect : OFF */
 95	writeb(0x00, pfc_base + RZA2_PWPR);		/* B0WI=0, PFSWE=0 */
 96	writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR);	/* B0WI=0, PFSWE=1 */
 97
 98	/* Set Pin function (interrupt disabled, ISEL=0) */
 99	writeb(func, pfc_base + RZA2_PFS(port, pin));
100
101	/* PFS Register Write Protect : ON */
102	writeb(0x00, pfc_base + RZA2_PWPR);	/* B0WI=0, PFSWE=0 */
103	writeb(0x80, pfc_base + RZA2_PWPR);	/* B0WI=1, PFSWE=0 */
104
105	/* Port Mode  : Peripheral module pin functions */
106	reg8 = readb(pfc_base + RZA2_PMR(port));
107	reg8 |= BIT(pin);
108	writeb(reg8, pfc_base + RZA2_PMR(port));
109}
110
111static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
112			     u8 dir)
113{
114	u8 port = RZA2_PIN_ID_TO_PORT(offset);
115	u8 pin = RZA2_PIN_ID_TO_PIN(offset);
116	u16 mask16;
117	u16 reg16;
118
119	reg16 = readw(pfc_base + RZA2_PDR(port));
120	mask16 = RZA2_PDR_MASK << (pin * 2);
121	reg16 &= ~mask16;
122
123	if (dir)
124		reg16 |= RZA2_PDR_INPUT << (pin * 2);	/* pin as input */
125	else
126		reg16 |= RZA2_PDR_OUTPUT << (pin * 2);	/* pin as output */
127
128	writew(reg16, pfc_base + RZA2_PDR(port));
129}
130
131static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
132{
133	struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
134	u8 port = RZA2_PIN_ID_TO_PORT(offset);
135	u8 pin = RZA2_PIN_ID_TO_PIN(offset);
136	u16 reg16;
137
138	reg16 = readw(priv->base + RZA2_PDR(port));
139	reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
140
141	if (reg16 == RZA2_PDR_OUTPUT)
142		return GPIO_LINE_DIRECTION_OUT;
143
144	if (reg16 == RZA2_PDR_INPUT)
145		return GPIO_LINE_DIRECTION_IN;
146
147	/*
148	 * This GPIO controller has a default Hi-Z state that is not input or
149	 * output, so force the pin to input now.
150	 */
151	rza2_pin_to_gpio(priv->base, offset, 1);
152
153	return GPIO_LINE_DIRECTION_IN;
154}
155
156static int rza2_chip_direction_input(struct gpio_chip *chip,
157				     unsigned int offset)
158{
159	struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
160
161	rza2_pin_to_gpio(priv->base, offset, 1);
162
163	return 0;
164}
165
166static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
167{
168	struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
169	u8 port = RZA2_PIN_ID_TO_PORT(offset);
170	u8 pin = RZA2_PIN_ID_TO_PIN(offset);
171
172	return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
173}
174
175static int rza2_chip_set(struct gpio_chip *chip, unsigned int offset, int value)
176{
177	struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
178	u8 port = RZA2_PIN_ID_TO_PORT(offset);
179	u8 pin = RZA2_PIN_ID_TO_PIN(offset);
180	u8 new_value;
181
182	new_value = readb(priv->base + RZA2_PODR(port));
183
184	if (value)
185		new_value |= BIT(pin);
186	else
187		new_value &= ~BIT(pin);
188
189	writeb(new_value, priv->base + RZA2_PODR(port));
190
191	return 0;
192}
193
194static int rza2_chip_direction_output(struct gpio_chip *chip,
195				      unsigned int offset, int val)
196{
197	struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
198
199	rza2_chip_set(chip, offset, val);
200	rza2_pin_to_gpio(priv->base, offset, 0);
201
202	return 0;
203}
204
205static const char * const rza2_gpio_names[] = {
206	"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
207	"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
208	"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
209	"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
210	"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
211	"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
212	"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
213	"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
214	"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
215	"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
216	"PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
217	"PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
218	"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
219	"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
220	"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
221	"PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
222	"PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
223	"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
224	/* port I does not exist */
225	"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
226	"PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
227	"PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
228	"PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
229};
230
231static struct gpio_chip chip = {
232	.names = rza2_gpio_names,
233	.base = -1,
234	.request = pinctrl_gpio_request,
235	.free = pinctrl_gpio_free,
236	.get_direction = rza2_chip_get_direction,
237	.direction_input = rza2_chip_direction_input,
238	.direction_output = rza2_chip_direction_output,
239	.get = rza2_chip_get,
240	.set = rza2_chip_set,
241};
242
243static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
244{
245	struct device_node *np = priv->dev->of_node;
246	struct of_phandle_args of_args;
247	int ret;
248
249	chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
250	if (!chip.label)
251		return -ENOMEM;
252
253	chip.parent = priv->dev;
254	chip.ngpio = priv->npins;
255
256	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
257					       &of_args);
258	if (ret) {
259		dev_err(priv->dev, "Unable to parse gpio-ranges\n");
260		return ret;
261	}
262
263	of_node_put(of_args.np);
264
265	if ((of_args.args[0] != 0) ||
266	    (of_args.args[1] != 0) ||
267	    (of_args.args[2] != priv->npins)) {
268		dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
269		return -EINVAL;
270	}
271	priv->gpio_range.id = 0;
272	priv->gpio_range.pin_base = priv->gpio_range.base = 0;
273	priv->gpio_range.npins = priv->npins;
274	priv->gpio_range.name = chip.label;
275	priv->gpio_range.gc = &chip;
276
277	/* Register our gpio chip with gpiolib */
278	ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
279	if (ret)
280		return ret;
281
282	/* Register pin range with pinctrl core */
283	pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
284
285	dev_dbg(priv->dev, "Registered gpio controller\n");
286
287	return 0;
288}
289
290static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
291{
292	struct pinctrl_pin_desc *pins;
293	unsigned int i;
294	int ret;
295
296	pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
297	if (!pins)
298		return -ENOMEM;
299
300	priv->pins = pins;
301	priv->desc.pins = pins;
302	priv->desc.npins = priv->npins;
303
304	for (i = 0; i < priv->npins; i++) {
305		pins[i].number = i;
306		pins[i].name = rza2_gpio_names[i];
307	}
308
309	ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
310					     &priv->pctl);
311	if (ret) {
312		dev_err(priv->dev, "pinctrl registration failed\n");
313		return ret;
314	}
315
316	ret = pinctrl_enable(priv->pctl);
317	if (ret) {
318		dev_err(priv->dev, "pinctrl enable failed\n");
319		return ret;
320	}
321
322	ret = rza2_gpio_register(priv);
323	if (ret) {
324		dev_err(priv->dev, "GPIO registration failed\n");
325		return ret;
326	}
327
328	return 0;
329}
330
331/*
332 * For each DT node, create a single pin mapping. That pin mapping will only
333 * contain a single group of pins, and that group of pins will only have a
334 * single function that can be selected.
335 */
336static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
337			       struct device_node *np,
338			       struct pinctrl_map **map,
339			       unsigned int *num_maps)
340{
341	struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
342	unsigned int *pins, *psel_val;
343	int i, ret, npins, gsel, fsel;
344	struct property *of_pins;
345	const char **pin_fn;
346
347	/* Find out how many pins to map */
348	of_pins = of_find_property(np, "pinmux", NULL);
349	if (!of_pins) {
350		dev_info(priv->dev, "Missing pinmux property\n");
351		return -ENOENT;
352	}
353	npins = of_pins->length / sizeof(u32);
354
355	pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
356	psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
357				GFP_KERNEL);
358	pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
359	if (!pins || !psel_val || !pin_fn)
360		return -ENOMEM;
361
362	/* Collect pin locations and mux settings from DT properties */
363	for (i = 0; i < npins; ++i) {
364		u32 value;
365
366		ret = of_property_read_u32_index(np, "pinmux", i, &value);
367		if (ret)
368			return ret;
369		pins[i] = value & MUX_PIN_ID_MASK;
370		psel_val[i] = MUX_FUNC(value);
371	}
372
373	mutex_lock(&priv->mutex);
374
375	/* Register a single pin group listing all the pins we read from DT */
376	gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
377	if (gsel < 0) {
378		ret = gsel;
379		goto unlock;
380	}
381
382	/*
383	 * Register a single group function where the 'data' is an array PSEL
384	 * register values read from DT.
385	 */
386	pin_fn[0] = np->name;
387	fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
388					   psel_val);
389	if (fsel < 0) {
390		ret = fsel;
391		goto remove_group;
392	}
393
394	dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
395
396	/* Create map where to retrieve function and mux settings from */
397	*num_maps = 0;
398	*map = kzalloc(sizeof(**map), GFP_KERNEL);
399	if (!*map) {
400		ret = -ENOMEM;
401		goto remove_function;
402	}
403
404	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
405	(*map)->data.mux.group = np->name;
406	(*map)->data.mux.function = np->name;
407	*num_maps = 1;
408
409	mutex_unlock(&priv->mutex);
410
411	return 0;
412
413remove_function:
414	pinmux_generic_remove_function(pctldev, fsel);
415
416remove_group:
417	pinctrl_generic_remove_group(pctldev, gsel);
418
419unlock:
420	mutex_unlock(&priv->mutex);
421
422	dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
423
424	return ret;
425}
426
427static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
428			     struct pinctrl_map *map, unsigned int num_maps)
429{
430	kfree(map);
431}
432
433static const struct pinctrl_ops rza2_pinctrl_ops = {
434	.get_groups_count	= pinctrl_generic_get_group_count,
435	.get_group_name		= pinctrl_generic_get_group_name,
436	.get_group_pins		= pinctrl_generic_get_group_pins,
437	.dt_node_to_map		= rza2_dt_node_to_map,
438	.dt_free_map		= rza2_dt_free_map,
439};
440
441static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
442			unsigned int group)
443{
444	struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
445	const struct function_desc *func;
446	unsigned int i, *psel_val;
447	struct group_desc *grp;
448
449	grp = pinctrl_generic_get_group(pctldev, group);
450	if (!grp)
451		return -EINVAL;
452
453	func = pinmux_generic_get_function(pctldev, selector);
454	if (!func)
455		return -EINVAL;
456
457	psel_val = func->data;
458
459	for (i = 0; i < grp->grp.npins; ++i) {
460		dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
461			port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])],
462			RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
463			psel_val[i]);
464		rza2_set_pin_function(
465			priv->base,
466			RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]),
467			RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
468			psel_val[i]);
469	}
470
471	return 0;
472}
473
474static const struct pinmux_ops rza2_pinmux_ops = {
475	.get_functions_count	= pinmux_generic_get_function_count,
476	.get_function_name	= pinmux_generic_get_function_name,
477	.get_function_groups	= pinmux_generic_get_function_groups,
478	.set_mux		= rza2_set_mux,
479	.strict			= true,
480};
481
482static int rza2_pinctrl_probe(struct platform_device *pdev)
483{
484	struct rza2_pinctrl_priv *priv;
485	int ret;
486
487	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
488	if (!priv)
489		return -ENOMEM;
490
491	priv->dev = &pdev->dev;
492
493	priv->base = devm_platform_ioremap_resource(pdev, 0);
494	if (IS_ERR(priv->base))
495		return PTR_ERR(priv->base);
496
497	mutex_init(&priv->mutex);
498
499	platform_set_drvdata(pdev, priv);
500
501	priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
502		      RZA2_PINS_PER_PORT;
503
504	priv->desc.name		= DRIVER_NAME;
505	priv->desc.pctlops	= &rza2_pinctrl_ops;
506	priv->desc.pmxops	= &rza2_pinmux_ops;
507	priv->desc.owner	= THIS_MODULE;
508
509	ret = rza2_pinctrl_register(priv);
510	if (ret)
511		return ret;
512
513	dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
514		 port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
515
516	return 0;
517}
518
519static const struct of_device_id rza2_pinctrl_of_match[] = {
520	{ .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
521	{ /* sentinel */ }
522};
523
524static struct platform_driver rza2_pinctrl_driver = {
525	.driver = {
526		.name = DRIVER_NAME,
527		.of_match_table = rza2_pinctrl_of_match,
528	},
529	.probe = rza2_pinctrl_probe,
530};
531
532static int __init rza2_pinctrl_init(void)
533{
534	return platform_driver_register(&rza2_pinctrl_driver);
535}
536core_initcall(rza2_pinctrl_init);
537
538MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
539MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");