pfc-sh7734.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * SH7734 processor support - PFC hardware block
   4 *
   5 * Copyright (C) 2012  Renesas Solutions Corp.
   6 * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7 */
   8#include <linux/kernel.h>
   9#include <cpu/sh7734.h>
  10
  11#include "sh_pfc.h"
  12
  13#define CPU_ALL_GP(fn, sfx)						\
  14	PORT_GP_32(0, fn, sfx),						\
  15	PORT_GP_32(1, fn, sfx),						\
  16	PORT_GP_32(2, fn, sfx),						\
  17	PORT_GP_32(3, fn, sfx),						\
  18	PORT_GP_32(4, fn, sfx),						\
  19	PORT_GP_12(5, fn, sfx)
  20
  21#undef _GP_DATA
  22#define _GP_DATA(bank, pin, name, sfx, cfg)				\
  23	PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
  24
  25#define _GP_INOUTSEL(bank, pin, name, sfx, cfg)	name##_IN, name##_OUT
  26#define _GP_INDT(bank, pin, name, sfx, cfg)	name##_DATA
  27#define GP_INOUTSEL(bank)	PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
  28#define GP_INDT(bank)		PORT_GP_32_REV(bank, _GP_INDT, unused)
  29
  30enum {
  31	PINMUX_RESERVED = 0,
  32
  33	PINMUX_DATA_BEGIN,
  34	GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
  35	PINMUX_DATA_END,
  36
  37	PINMUX_INPUT_BEGIN,
  38	GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
  39	PINMUX_INPUT_END,
  40
  41	PINMUX_OUTPUT_BEGIN,
  42	GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
  43	PINMUX_OUTPUT_END,
  44
  45	PINMUX_FUNCTION_BEGIN,
  46	GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
  47
  48	/* GPSR0 */
  49	FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
  50	FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
  51	FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
  52	FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
  53	FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
  54	FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
  55	FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
  56	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
  57
  58	/* GPSR1 */
  59	FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
  60	FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
  61	FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
  62	FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
  63	FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
  64	FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
  65	FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
  66	FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
  67
  68	/* GPSR2 */
  69	FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
  70	FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
  71	FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
  72	FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
  73	FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  74	FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
  75	FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
  76	FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
  77
  78	/* GPSR3 */
  79	FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
  80	FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
  81	FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
  82	FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
  83	FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
  84	FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  85	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
  86	FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
  87
  88	/* GPSR4 */
  89	FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
  90	FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
  91	FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
  92	FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  93	FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
  94	FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
  95	FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
  96	FN_USB_OVC0, FN_IP11_18_16,
  97	FN_IP10_22, FN_IP10_24_23,
  98
  99	/* GPSR5 */
 100	FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
 101	FN_IP10_27_26, /* 10 */
 102	FN_IP10_29_28, /* 11 */
 103
 104	/* IPSR0 */
 105	FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
 106	FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
 107	FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
 108	FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
 109	FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
 110	FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
 111	FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
 112	FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
 113	FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
 114	FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
 115	FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
 116	FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
 117	FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
 118	FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
 119	FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
 120	FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
 121
 122	/* IPSR1 */
 123	FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
 124	FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
 125	FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
 126	FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
 127	FN_A25, FN_TX2_D, FN_ST1_D2,
 128	FN_A24, FN_RX2_D, FN_ST1_D1,
 129	FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
 130	FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
 131	FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
 132	FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
 133	FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,	FN_TIOC4D_C,
 134	FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
 135	FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A,	FN_TIOC4B_C,
 136	FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
 137
 138	/* IPSR2 */
 139	FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
 140	FN_D13, FN_RX2_B, FN_FRB_A,	FN_ET0_ETXD6_B,
 141	FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
 142	FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
 143		FN_ET0_ETXD3_B,
 144	FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
 145		FN_ET0_ETXD2_B,
 146	FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
 147		FN_ET0_ETXD1_B,
 148	FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
 149		FN_ET0_GTX_CLK_B,
 150	FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
 151	FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
 152	FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
 153	FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
 154
 155	/* IPSR3 */
 156	FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
 157	FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
 158		FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
 159	FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
 160		FN_ET0_LINK_C, FN_ET0_ETXD5_A,
 161	FN_EX_WAIT0, FN_TCLK1_B,
 162	FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
 163	FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
 164	FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
 165	FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
 166	FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
 167	FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
 168	FN_CS1_A26, FN_QIO3_B,
 169	FN_D15, FN_SCK2_B,
 170
 171	/* IPSR4 */
 172	FN_SCK2_A, FN_VI0_G3,
 173	FN_RTS1_B, FN_VI0_G2,
 174	FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
 175	FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
 176	FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
 177	FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
 178	FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
 179	FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
 180	FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
 181	FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
 182	FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
 183	FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
 184	FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
 185
 186	/* IPSR5 */
 187	FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
 188	FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
 189	FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
 190	FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
 191	FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
 192	FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
 193	FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
 194	FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
 195	FN_REF125CK, FN_ADTRG, FN_RX5_C,
 196	FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
 197
 198	/* IPSR6 */
 199	FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
 200	FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
 201	FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
 202	FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
 203	FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
 204	FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
 205	FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
 206	FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
 207	FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
 208	FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
 209
 210	/* IPSR7 */
 211	FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
 212	FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
 213	FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
 214	FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
 215	FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
 216	FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
 217	FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
 218	FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
 219	FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
 220	FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
 221	FN_DU0_DB4, FN_HIFINT,
 222
 223	/* IPSR8 */
 224	FN_DU0_DB5, FN_HIFDREQ,
 225	FN_DU0_DB6, FN_HIFRDY,
 226	FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
 227	FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
 228	FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
 229	FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
 230	FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
 231	FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
 232	FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
 233	FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
 234	FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
 235	FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
 236	FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
 237	FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
 238
 239	/* IPSR9 */
 240	FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
 241	FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
 242	FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
 243	FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
 244	FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
 245	FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
 246	FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
 247	FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
 248	FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
 249	FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
 250	FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
 251	FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
 252	FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
 253	FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
 254	FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
 255
 256	/* IPSR10 */
 257	FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
 258	FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
 259	FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
 260	FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
 261	FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
 262	FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
 263	FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
 264	FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
 265	FN_CAN_CLK_A, FN_RX4_D,
 266	FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
 267	FN_CAN1_RX_A, FN_IRQ1_B,
 268	FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
 269	FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
 270
 271	/* IPSR11 */
 272	FN_SCL1, FN_SCIF_CLK_C,
 273	FN_SDA1, FN_RX1_E,
 274	FN_SDA0, FN_HIFEBL_A,
 275	FN_SDSELF, FN_RTS1_E,
 276	FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
 277	FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
 278	FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
 279	FN_TX0_A, FN_HSPI_TX_A,
 280	FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
 281	FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
 282	FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
 283	FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
 284	FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
 285	FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
 286	FN_PRESETOUT, FN_ST_CLKOUT,
 287
 288	/* MOD_SEL1 */
 289	FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
 290	FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
 291	FN_SEL_VIN1_0, FN_SEL_VIN1_1,
 292	FN_SEL_HIF_0, FN_SEL_HIF_1,
 293	FN_SEL_RSPI_0, FN_SEL_RSPI_1,
 294	FN_SEL_LCDC_0, FN_SEL_LCDC_1,
 295	FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
 296	FN_SEL_ET0_0, FN_SEL_ET0_1,
 297	FN_SEL_RMII_0, FN_SEL_RMII_1,
 298	FN_SEL_TMU_0, FN_SEL_TMU_1,
 299	FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
 300	FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
 301	FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
 302	FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
 303	FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
 304	FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
 305	FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
 306	FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
 307	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 308	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 309	FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
 310	FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
 311	FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
 312	FN_SEL_MMC_0, FN_SEL_MMC_1,
 313	FN_SEL_INTC_0, FN_SEL_INTC_1,
 314
 315	/* MOD_SEL2 */
 316	FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
 317	FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
 318	FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
 319	FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
 320	FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
 321	FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
 322	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 323	FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 324	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
 325	FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 326	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 327		FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 328	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 329		FN_SEL_SCIF2_3,
 330	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 331		FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
 332	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
 333	FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
 334
 335	PINMUX_FUNCTION_END,
 336
 337	PINMUX_MARK_BEGIN,
 338
 339	CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
 340	WE0_MARK, WE1_MARK,
 341
 342	SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
 343
 344	IRQ2_B_MARK, IRQ3_B_MARK,
 345
 346	/* IPSR0 */
 347	A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
 348	A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
 349	A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
 350	A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
 351	A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
 352	A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
 353	A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
 354	A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
 355	A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
 356	A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
 357	A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
 358	A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
 359	A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
 360	A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
 361	A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
 362	A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
 363
 364	/* IPSR1 */
 365	D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
 366	D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
 367	D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
 368	D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
 369	A25_MARK, TX2_D_MARK, ST1_D2_MARK,
 370	A24_MARK, RX2_D_MARK, ST1_D1_MARK,
 371	A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
 372	A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
 373	A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
 374	A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
 375	A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK,	TIOC4D_C_MARK,
 376	A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
 377	A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
 378	A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
 379
 380	/* IPSR2 */
 381	D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
 382	D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
 383	D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
 384	D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
 385		ET0_ETXD3_B_MARK,
 386	D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
 387		ET0_ETXD2_B_MARK,
 388	D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
 389		FCLE_A_MARK, ET0_ETXD1_B_MARK,
 390	D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
 391		FCE_A_MARK, ET0_GTX_CLK_B_MARK,
 392	D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
 393		FD7_A_MARK,
 394	D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
 395		FD6_A_MARK,
 396	D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
 397	D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
 398		FD4_A_MARK,
 399
 400	/* IPSR3 */
 401	DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
 402	EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
 403		ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
 404	EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
 405		ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
 406	EX_WAIT0_MARK, TCLK1_B_MARK,
 407	RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
 408	EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
 409		ET0_ETXD3_A_MARK,
 410	EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
 411		ET0_ETXD2_A_MARK,
 412	EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
 413		ET0_ETXD1_A_MARK,
 414	EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
 415		ET0_GTX_CLK_A_MARK,
 416	EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
 417		ET0_ETXD0_MARK,
 418	CS1_A26_MARK, QIO3_B_MARK,
 419	D15_MARK, SCK2_B_MARK,
 420
 421	/* IPSR4 */
 422	SCK2_A_MARK, VI0_G3_MARK,
 423	RTS1_B_MARK, VI0_G2_MARK,
 424	CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
 425	TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
 426	RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
 427	SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
 428	RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
 429	CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
 430		ET0_MDC_MARK,
 431	HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
 432		RMII0_MDC_A_MARK, ET0_COL_MARK,
 433	HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
 434		RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
 435	HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
 436		RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
 437	HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
 438		RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
 439	HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
 440		RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
 441
 442	/* IPSR5 */
 443	SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
 444	SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
 445	SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
 446	SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
 447	SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
 448	SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
 449	SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
 450	SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
 451	REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
 452	REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
 453
 454	/* IPSR6 */
 455	DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
 456		TCLKA_A_MARK, HIFD00_MARK,
 457	DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
 458		TCLKB_A_MARK, HIFD01_MARK,
 459	DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
 460	DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
 461	DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
 462	DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
 463	DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
 464	DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
 465	DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
 466		TIOC1A_A_MARK, HIFD08_MARK,
 467	DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
 468		HIFD09_MARK,
 469
 470	/* IPSR7 */
 471	DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
 472		HIFD10_MARK,
 473	DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
 474		HIFD11_MARK,
 475	DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
 476		HIFD12_MARK,
 477	DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
 478		HIFD13_MARK,
 479	DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
 480		HIFD14_MARK,
 481	DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
 482		HIFD15_MARK,
 483	DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
 484		HIFCS_MARK,
 485	DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
 486		HIFRS_MARK,
 487	DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
 488		HIFWR_MARK,
 489	DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
 490	DU0_DB4_MARK, HIFINT_MARK,
 491
 492	/* IPSR8 */
 493	DU0_DB5_MARK, HIFDREQ_MARK,
 494	DU0_DB6_MARK, HIFRDY_MARK,
 495	DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
 496	DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
 497	DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
 498	DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
 499	DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
 500	DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
 501		SSI_SDATA1_B_MARK,
 502	DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
 503	DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
 504	IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
 505	IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
 506	IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
 507	IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
 508
 509	/* IPSR9 */
 510	VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
 511	VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
 512	VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
 513	VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
 514	VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
 515	VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
 516	VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
 517	VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
 518	VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
 519	SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
 520	SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
 521	SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
 522	SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
 523	SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
 524	SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
 525
 526	/* IPSR10 */
 527	SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
 528		LCD_DATA15_B_MARK,
 529	SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
 530		FALE_B_MARK, LCD_DON_B_MARK,
 531	SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
 532		LCD_CL1_B_MARK,
 533	SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
 534		LCD_CL2_B_MARK,
 535	AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
 536		LCD_FLM_B_MARK,
 537	AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
 538	AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
 539		LCD_VEPWC_B_MARK,
 540	AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
 541		LCD_M_DISP_B_MARK,
 542	CAN_CLK_A_MARK, RX4_D_MARK,
 543	CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
 544	CAN1_RX_A_MARK, IRQ1_B_MARK,
 545	CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
 546	CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
 547
 548	/* IPSR11 */
 549	SCL1_MARK, SCIF_CLK_C_MARK,
 550	SDA1_MARK, RX1_E_MARK,
 551	SDA0_MARK, HIFEBL_A_MARK,
 552	SDSELF_MARK, RTS1_E_MARK,
 553	SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
 554		ET0_ERXD4_MARK,
 555	SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
 556		ET0_ERXD5_MARK,
 557	RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
 558	TX0_A_MARK, HSPI_TX_A_MARK,
 559	PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
 560		IETX_B_MARK,
 561	USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
 562		IERX_B_MARK,
 563	DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
 564	DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
 565	DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
 566		ET0_TX_CLK_A_MARK,
 567	DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
 568	PRESETOUT_MARK, ST_CLKOUT_MARK,
 569
 570	PINMUX_MARK_END,
 571};
 572
 573static const u16 pinmux_data[] = {
 574	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 575
 576	PINMUX_SINGLE(CLKOUT),
 577	PINMUX_SINGLE(BS),
 578	PINMUX_SINGLE(CS0),
 579	PINMUX_SINGLE(EX_CS0),
 580	PINMUX_SINGLE(RD),
 581	PINMUX_SINGLE(WE0),
 582	PINMUX_SINGLE(WE1),
 583	PINMUX_SINGLE(SCL0),
 584	PINMUX_SINGLE(PENC0),
 585	PINMUX_SINGLE(USB_OVC0),
 586	PINMUX_SINGLE(IRQ2_B),
 587	PINMUX_SINGLE(IRQ3_B),
 588
 589	/* IPSR0 */
 590	PINMUX_IPSR_GPSR(IP0_1_0, A0),
 591	PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
 592	PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
 593	PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
 594
 595	PINMUX_IPSR_GPSR(IP0_3_2, A1),
 596	PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
 597	PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
 598	PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
 599
 600	PINMUX_IPSR_GPSR(IP0_5_4, A2),
 601	PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
 602	PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
 603	PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
 604
 605	PINMUX_IPSR_GPSR(IP0_7_6, A3),
 606	PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
 607	PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
 608	PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
 609
 610	PINMUX_IPSR_GPSR(IP0_9_8, A4),
 611	PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
 612	PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
 613	PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
 614
 615	PINMUX_IPSR_GPSR(IP0_11_10, A5),
 616	PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
 617	PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
 618	PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
 619
 620	PINMUX_IPSR_GPSR(IP0_13_12, A6),
 621	PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
 622	PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
 623	PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
 624
 625	PINMUX_IPSR_GPSR(IP0_15_14, A7),
 626	PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
 627	PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
 628	PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
 629
 630	PINMUX_IPSR_GPSR(IP0_17_16, A8),
 631	PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
 632	PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
 633	PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
 634
 635	PINMUX_IPSR_GPSR(IP0_19_18, A9),
 636	PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
 637	PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
 638	PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
 639
 640	PINMUX_IPSR_GPSR(IP0_21_20, A10),
 641	PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
 642	PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
 643	PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
 644
 645	PINMUX_IPSR_GPSR(IP0_23_22, A11),
 646	PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
 647	PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
 648	PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
 649
 650	PINMUX_IPSR_GPSR(IP0_25_24, A12),
 651	PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
 652	PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
 653
 654	PINMUX_IPSR_GPSR(IP0_27_26, A13),
 655	PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
 656	PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
 657
 658	PINMUX_IPSR_GPSR(IP0_29_28, A14),
 659	PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
 660	PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
 661
 662	PINMUX_IPSR_GPSR(IP0_31_30, A15),
 663	PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
 664	PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
 665	PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
 666
 667	/* IPSR1 */
 668	PINMUX_IPSR_GPSR(IP1_1_0, A16),
 669	PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
 670	PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
 671	PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
 672
 673	PINMUX_IPSR_GPSR(IP1_3_2, A17),
 674	PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
 675	PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
 676	PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
 677
 678	PINMUX_IPSR_GPSR(IP1_5_4, A18),
 679	PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
 680	PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
 681	PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
 682
 683	PINMUX_IPSR_GPSR(IP1_7_6, A19),
 684	PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
 685	PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
 686	PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
 687
 688	PINMUX_IPSR_GPSR(IP1_9_8, A20),
 689	PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
 690	PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
 691
 692	PINMUX_IPSR_GPSR(IP1_11_10, A21),
 693	PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
 694	PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
 695
 696	PINMUX_IPSR_GPSR(IP1_13_12, A22),
 697	PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
 698	PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
 699
 700	PINMUX_IPSR_GPSR(IP1_15_14, A23),
 701	PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
 702	PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
 703
 704	PINMUX_IPSR_GPSR(IP1_17_16, A24),
 705	PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
 706	PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
 707
 708	PINMUX_IPSR_GPSR(IP1_19_18, A25),
 709	PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
 710	PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
 711
 712	PINMUX_IPSR_GPSR(IP1_22_20, D0),
 713	PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
 714	PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
 715	PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
 716	PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
 717
 718	PINMUX_IPSR_GPSR(IP1_25_23, D1),
 719	PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
 720	PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
 721	PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
 722	PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
 723
 724	PINMUX_IPSR_GPSR(IP1_28_26, D2),
 725	PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
 726	PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
 727	PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
 728	PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
 729
 730	PINMUX_IPSR_GPSR(IP1_31_29, D3),
 731	PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
 732	PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
 733	PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
 734	PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
 735
 736	/* IPSR2 */
 737	PINMUX_IPSR_GPSR(IP2_2_0, D4),
 738	PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
 739	PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
 740	PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
 741	PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
 742
 743	PINMUX_IPSR_GPSR(IP2_4_3, D5),
 744	PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
 745	PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
 746	PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
 747
 748	PINMUX_IPSR_GPSR(IP2_7_5, D6),
 749	PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
 750	PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
 751	PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
 752	PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
 753
 754	PINMUX_IPSR_GPSR(IP2_10_8, D7),
 755	PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
 756	PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
 757	PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
 758	PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
 759
 760	PINMUX_IPSR_GPSR(IP2_13_11, D8),
 761	PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
 762	PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
 763	PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
 764	PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
 765	PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
 766
 767	PINMUX_IPSR_GPSR(IP2_16_14, D9),
 768	PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
 769	PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
 770	PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
 771	PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
 772	PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
 773
 774	PINMUX_IPSR_GPSR(IP2_19_17, D10),
 775	PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
 776	PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
 777	PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
 778	PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
 779
 780	PINMUX_IPSR_GPSR(IP2_22_20, D11),
 781	PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
 782	PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
 783	PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
 784
 785	PINMUX_IPSR_GPSR(IP2_24_23, D12),
 786	PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
 787	PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
 788
 789	PINMUX_IPSR_GPSR(IP2_27_25, D13),
 790	PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
 791	PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
 792	PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
 793
 794	PINMUX_IPSR_GPSR(IP2_30_28, D14),
 795	PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
 796	PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
 797	PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
 798
 799	/* IPSR3 */
 800	PINMUX_IPSR_GPSR(IP3_1_0, D15),
 801	PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
 802
 803	PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
 804	PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
 805
 806	PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
 807	PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
 808	PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
 809	PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
 810	PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
 811
 812	PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
 813	PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
 814	PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
 815	PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
 816	PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
 817
 818	PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
 819	PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
 820	PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
 821	PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
 822	PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
 823
 824	PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
 825	PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
 826	PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
 827	PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
 828	PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
 829
 830	PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
 831	PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
 832	PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
 833	PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
 834	PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
 835
 836	PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
 837	PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
 838	PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
 839	PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
 840
 841	PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
 842	PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
 843
 844	PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
 845	PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
 846	PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
 847	PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
 848	PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
 849	PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
 850
 851	PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
 852	PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
 853	PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
 854	PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
 855	PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
 856	PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
 857
 858	PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 859	PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
 860	PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
 861	PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
 862	PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
 863
 864	/* IPSR4 */
 865	PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
 866	PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
 867	PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
 868	PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
 869	PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
 870
 871	PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
 872	PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
 873	PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
 874	PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
 875	PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
 876
 877	PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
 878	PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
 879	PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
 880	PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
 881	PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
 882
 883	PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
 884	PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
 885	PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
 886	PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
 887	PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
 888
 889	PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
 890	PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
 891	PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
 892	PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
 893	PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
 894
 895	PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
 896	PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
 897	PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
 898	PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
 899
 900	PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
 901	PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
 902	PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
 903
 904	PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
 905	PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
 906	PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
 907
 908	PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
 909	PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
 910	PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
 911
 912	PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
 913	PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
 914	PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
 915
 916	PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
 917	PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
 918
 919	PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
 920	PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
 921
 922	PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
 923	PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
 924
 925	/* IPSR5 */
 926	PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
 927	PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
 928	PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
 929	PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
 930
 931	PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
 932	PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
 933	PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
 934	PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
 935
 936	PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
 937	PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
 938	PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
 939	PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
 940
 941	PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
 942	PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
 943	PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
 944	PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
 945
 946	PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
 947	PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
 948	PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
 949	PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
 950
 951	PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
 952	PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
 953	PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
 954	PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
 955
 956	PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
 957	PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
 958	PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
 959	PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
 960
 961	PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
 962	PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
 963	PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
 964
 965	PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
 966	PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
 967	PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
 968	PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
 969	PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
 970	PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
 971
 972	/* IPSR6 */
 973	PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
 974	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
 975	PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
 976	PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
 977	PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
 978	PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
 979
 980	PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
 981	PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
 982	PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
 983	PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
 984	PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
 985	PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
 986
 987	PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
 988	PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
 989	PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
 990	PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
 991
 992	PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
 993	PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
 994	PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
 995	PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
 996
 997	PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
 998	PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
 999	PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1000	PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
1001
1002	PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
1003	PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1004	PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1005	PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
1006
1007	PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
1008	PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1009	PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1010	PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
1011
1012	PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
1013	PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
1014	PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1015	PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
1016
1017	PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
1018	PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
1019	PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1020	PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1021	PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1022	PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
1023
1024	PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
1025	PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1026	PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1027	PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1028	PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
1029
1030	/* IPSR7 */
1031	PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
1032	PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1033	PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1034	PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1035	PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
1036
1037	PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
1038	PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1039	PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1040	PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1041	PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
1042
1043	PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
1044	PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
1045	PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1046	PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1047	PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
1048
1049	PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
1050	PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
1051	PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1052	PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1053	PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
1054
1055	PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
1056	PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
1057	PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1058	PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1059	PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
1060
1061	PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
1062	PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
1063	PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1064	PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1065	PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
1066
1067	PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
1068	PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
1069	PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1070	PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1071	PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
1072
1073	PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
1074	PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
1075	PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1076	PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1077	PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
1078
1079	PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
1080	PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
1081	PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1082	PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1083
1084	PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
1085	PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
1086	PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1087	PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
1088
1089	PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
1090	PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
1091
1092	/* IPSR8 */
1093	PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
1094	PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
1095
1096	PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
1097	PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
1098
1099	PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
1100	PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1101	PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1102
1103	PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
1104	PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1105	PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1106
1107	PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
1108	PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1109	PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1110
1111	PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1112	PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1113	PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1114
1115	PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1116	PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1117	PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1118
1119	PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1120	PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1121	PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1122	PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1123
1124	PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
1125	PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1126	PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1127	PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1128
1129	PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
1130	PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1131	PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1132	PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1133
1134	PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
1135	PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1136	PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
1137	PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
1138
1139	PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
1140	PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1141	PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
1142	PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
1143
1144	PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
1145	PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1146	PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1147	PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1148
1149	PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
1150	PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1151	PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1152	PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1153
1154	/* IPSR9 */
1155	PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1156	PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
1157	PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1158
1159	PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1160	PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
1161	PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1162
1163	PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1164	PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
1165	PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1166
1167	PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1168	PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
1169	PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1170
1171	PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1172	PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
1173	PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1174
1175	PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1176	PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
1177	PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1178
1179	PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1180	PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
1181	PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1182
1183	PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1184	PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
1185	PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1186
1187	PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1188	PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
1189	PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1190
1191	PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1192	PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1193	PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1194
1195	PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1196	PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1197	PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1198
1199	PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1200	PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1201	PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1202	PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1203
1204	PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1205	PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1206	PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1207	PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1208
1209	PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1210	PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1211	PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1212
1213	PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1214	PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1215	PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1216
1217	/* IPSE10 */
1218	PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
1219	PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1220	PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
1221	PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1222	PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1223
1224	PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
1225	PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1226	PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
1227	PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1228	PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
1229	PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1230
1231	PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
1232	PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1233	PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1234	PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
1235	PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1236
1237	PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
1238	PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1239	PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1240	PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
1241	PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1242
1243	PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1244	PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1245	PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1246	PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1247	PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1248
1249	PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1250	PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1251
1252	PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
1253	PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1254	PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1255	PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
1256	PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1257
1258	PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
1259	PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
1260	PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1261	PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
1262	PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1263
1264	PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1265	PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
1266
1267	PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1268	PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
1269	PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
1270
1271	PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1272	PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
1273
1274	PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1275	PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
1276	PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
1277
1278	PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1279	PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
1280	PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
1281
1282	/* IPSR11 */
1283	PINMUX_IPSR_GPSR(IP11_0, SCL1),
1284	PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1285
1286	PINMUX_IPSR_GPSR(IP11_1, SDA1),
1287	PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
1288
1289	PINMUX_IPSR_GPSR(IP11_2, SDA0),
1290	PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
1291
1292	PINMUX_IPSR_GPSR(IP11_3, SDSELF),
1293	PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
1294
1295	PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1296	PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1297	PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
1298	PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1299	PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
1300
1301	PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1302	PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1303	PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
1304	PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1305	PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
1306
1307	PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
1308	PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1309	PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1310	PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
1311
1312	PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
1313	PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1314
1315	PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
1316	PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
1317	PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B,  SEL_RCAN1_1),
1318	PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
1319	PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
1320
1321	PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
1322	PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
1323	PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1324	PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
1325	PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
1326
1327	PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
1328	PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1329	PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
1330
1331	PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
1332	PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1333	PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
1334
1335	PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
1336	PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1337	PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
1338	PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1339	PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1340
1341	PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
1342	PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1343	PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
1344	PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1345
1346	PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
1347	PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
1348};
1349
1350static const struct sh_pfc_pin pinmux_pins[] = {
1351	PINMUX_GPIO_GP_ALL(),
1352};
1353
1354#define PINMUX_FN_BASE	ARRAY_SIZE(pinmux_pins)
1355
1356static const struct pinmux_func pinmux_func_gpios[] = {
1357	GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1358	GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1359	GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
1360	GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
1361
1362	/* IPSR0 */
1363	GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
1364	GPIO_FN(TCLKA_C),
1365	GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
1366	GPIO_FN(TCLKB_C),
1367	GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
1368	GPIO_FN(TCLKC_C),
1369	GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
1370	GPIO_FN(TCLKD_C),
1371	GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
1372	GPIO_FN(TIOC0A_C),
1373	GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
1374	GPIO_FN(TIOC0B_C),
1375	GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
1376	GPIO_FN(TIOC0C_C),
1377	GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
1378	GPIO_FN(TIOC0D_C),
1379	GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
1380	GPIO_FN(TIOC1A_C),
1381	GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
1382	GPIO_FN(TIOC1B_C),
1383	GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
1384	GPIO_FN(TIOC2A_C),
1385	GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
1386	GPIO_FN(TIOC2B_C),
1387	GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
1388	GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
1389	GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
1390	GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
1391	GPIO_FN(TIOC3D_C),
1392
1393	/* IPSR1 */
1394	GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
1395	GPIO_FN(TIOC4A_C),
1396	GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
1397	GPIO_FN(TIOC4B_C),
1398	GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
1399	GPIO_FN(TIOC4C_C),
1400	GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
1401	GPIO_FN(TIOC4D_C),
1402	GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
1403	GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
1404	GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
1405	GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
1406	GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
1407	GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
1408	GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
1409	GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
1410	GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
1411	GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
1412	GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
1413	GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
1414	GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
1415	GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
1416
1417	/* IPSR2 */
1418	GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
1419	GPIO_FN(FD4_A),
1420	GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
1421	GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
1422		GPIO_FN(QSPCLK_A),
1423	GPIO_FN(FD6_A),
1424	GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
1425	GPIO_FN(FD7_A),
1426	GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
1427	GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
1428	GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
1429	GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
1430	GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
1431		GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
1432	GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
1433		GPIO_FN(ET0_ETXD3_B),
1434	GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
1435	GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
1436	GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
1437
1438	/* IPSR3 */
1439	GPIO_FN(D15), GPIO_FN(SCK2_B),
1440	GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
1441	GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
1442	GPIO_FN(ET0_ETXD0),
1443	GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
1444	GPIO_FN(ET0_GTX_CLK_A),
1445	GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
1446	GPIO_FN(ET0_ETXD1_A),
1447	GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
1448	GPIO_FN(ET0_ETXD2_A),
1449	GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1450	GPIO_FN(ET0_ETXD3_A),
1451	GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
1452	GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1453	GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1454		GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
1455	GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
1456		GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
1457	GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
1458	GPIO_FN(ET0_ETXD7),
1459
1460	/* IPSR4 */
1461	GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
1462		GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
1463	GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
1464		GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
1465	GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
1466		GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
1467	GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
1468		GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
1469	GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
1470		GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
1471	GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
1472		GPIO_FN(ET0_MDC),
1473	GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
1474	GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
1475	GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
1476	GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
1477	GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
1478	GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
1479	GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
1480
1481	/* IPSR5 */
1482	GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
1483	GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
1484	GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
1485	GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
1486		GPIO_FN(ET0_PHY_INT_B),
1487	GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
1488		GPIO_FN(ET0_MAGIC_B),
1489	GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
1490		GPIO_FN(ET0_LINK_B),
1491	GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
1492		GPIO_FN(ET0_MDIO_B),
1493	GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
1494		GPIO_FN(ET0_ERXD3_B),
1495	GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
1496		GPIO_FN(ET0_ERXD2_B),
1497	GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
1498		GPIO_FN(ET0_RX_CLK_B),
1499
1500	/* IPSR6 */
1501	GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
1502		GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
1503	GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
1504		GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
1505	GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
1506		GPIO_FN(HIFD07),
1507	GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
1508		GPIO_FN(HIFD06),
1509	GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
1510		GPIO_FN(HIFD05),
1511	GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
1512		GPIO_FN(HIFD04),
1513	GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
1514	GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
1515	GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
1516		GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
1517	GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
1518		GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
1519
1520	/* IPSR7 */
1521	GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
1522	GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
1523	GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
1524		GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
1525	GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
1526		GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
1527	GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
1528		GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
1529	GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
1530		GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
1531	GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
1532		GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
1533	GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
1534		GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
1535	GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
1536		GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
1537	GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
1538		GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
1539	GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
1540		GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
1541
1542	/* IPSR8 */
1543	GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
1544		GPIO_FN(ET0_ERXD3_A),
1545	GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
1546		GPIO_FN(ET0_ERXD2_A),
1547	GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
1548		GPIO_FN(ET0_ERXD1),
1549	GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
1550		GPIO_FN(ET0_ERXD0),
1551	GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
1552		GPIO_FN(LCD_VCPWC_B),
1553	GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
1554		GPIO_FN(AUDIO_CLKA_B),
1555	GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
1556		GPIO_FN(SSI_SDATA1_B),
1557	GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
1558		GPIO_FN(SSI_WS1_B),
1559	GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
1560		GPIO_FN(SSI_SCK1_B),
1561	GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
1562		GPIO_FN(SSI_SDATA0_B),
1563	GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
1564		GPIO_FN(SSI_WS0_B),
1565	GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
1566	GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
1567	GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
1568
1569	/* IPSR9 */
1570	GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
1571	GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
1572	GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
1573		GPIO_FN(LCD_DATA12_B),
1574	GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
1575		GPIO_FN(LCD_DATA11_B),
1576	GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
1577	GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
1578	GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
1579	GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
1580	GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
1581	GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
1582	GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
1583	GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
1584	GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
1585	GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
1586	GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
1587
1588	/* IPSR10 */
1589	GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
1590	GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
1591	GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
1592	GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
1593	GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
1594	GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
1595		GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
1596	GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
1597		GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
1598	GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
1599	GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
1600		GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
1601	GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
1602		GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
1603	GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
1604		GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
1605	GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
1606		GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
1607	GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
1608		GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
1609
1610	/* IPSR11 */
1611	GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
1612	GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
1613		GPIO_FN(ET0_RX_CLK_A),
1614	GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
1615		GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
1616	GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
1617	GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
1618	GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
1619		GPIO_FN(RX5_D), GPIO_FN(IERX_B),
1620	GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
1621		GPIO_FN(TX5_D), GPIO_FN(IETX_B),
1622	GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
1623	GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
1624		GPIO_FN(ET0_ERXD6),
1625	GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
1626		GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
1627	GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
1628		GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
1629	GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
1630	GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
1631	GPIO_FN(SDA1), GPIO_FN(RX1_E),
1632	GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1633};
1634
1635static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1636	{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
1637		GP_0_31_FN, FN_IP2_2_0,
1638		GP_0_30_FN, FN_IP1_31_29,
1639		GP_0_29_FN, FN_IP1_28_26,
1640		GP_0_28_FN, FN_IP1_25_23,
1641		GP_0_27_FN, FN_IP1_22_20,
1642		GP_0_26_FN, FN_IP1_19_18,
1643		GP_0_25_FN, FN_IP1_17_16,
1644		GP_0_24_FN, FN_IP0_5_4,
1645		GP_0_23_FN, FN_IP0_3_2,
1646		GP_0_22_FN, FN_IP0_1_0,
1647		GP_0_21_FN, FN_IP11_28,
1648		GP_0_20_FN, FN_IP1_7_6,
1649		GP_0_19_FN, FN_IP1_5_4,
1650		GP_0_18_FN, FN_IP1_3_2,
1651		GP_0_17_FN, FN_IP1_1_0,
1652		GP_0_16_FN, FN_IP0_31_30,
1653		GP_0_15_FN, FN_IP0_29_28,
1654		GP_0_14_FN, FN_IP0_27_26,
1655		GP_0_13_FN, FN_IP0_25_24,
1656		GP_0_12_FN, FN_IP0_23_22,
1657		GP_0_11_FN, FN_IP0_21_20,
1658		GP_0_10_FN, FN_IP0_19_18,
1659		GP_0_9_FN, FN_IP0_17_16,
1660		GP_0_8_FN, FN_IP0_15_14,
1661		GP_0_7_FN, FN_IP0_13_12,
1662		GP_0_6_FN, FN_IP0_11_10,
1663		GP_0_5_FN, FN_IP0_9_8,
1664		GP_0_4_FN, FN_IP0_7_6,
1665		GP_0_3_FN, FN_IP1_15_14,
1666		GP_0_2_FN, FN_IP1_13_12,
1667		GP_0_1_FN, FN_IP1_11_10,
1668		GP_0_0_FN, FN_IP1_9_8 ))
1669	},
1670	{ PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
1671		GP_1_31_FN, FN_IP11_25_23,
1672		GP_1_30_FN, FN_IP2_13_11,
1673		GP_1_29_FN, FN_IP2_10_8,
1674		GP_1_28_FN, FN_IP2_7_5,
1675		GP_1_27_FN, FN_IP3_26_24,
1676		GP_1_26_FN, FN_IP3_23_21,
1677		GP_1_25_FN, FN_IP2_4_3,
1678		GP_1_24_FN, FN_WE1,
1679		GP_1_23_FN, FN_WE0,
1680		GP_1_22_FN, FN_IP3_19_18,
1681		GP_1_21_FN, FN_RD,
1682		GP_1_20_FN, FN_IP3_17_15,
1683		GP_1_19_FN, FN_IP3_14_12,
1684		GP_1_18_FN, FN_IP3_11_9,
1685		GP_1_17_FN, FN_IP3_8_6,
1686		GP_1_16_FN, FN_IP3_5_3,
1687		GP_1_15_FN, FN_EX_CS0,
1688		GP_1_14_FN, FN_IP3_2,
1689		GP_1_13_FN, FN_CS0,
1690		GP_1_12_FN, FN_BS,
1691		GP_1_11_FN, FN_CLKOUT,
1692		GP_1_10_FN, FN_IP3_1_0,
1693		GP_1_9_FN, FN_IP2_30_28,
1694		GP_1_8_FN, FN_IP2_27_25,
1695		GP_1_7_FN, FN_IP2_24_23,
1696		GP_1_6_FN, FN_IP2_22_20,
1697		GP_1_5_FN, FN_IP2_19_17,
1698		GP_1_4_FN, FN_IP2_16_14,
1699		GP_1_3_FN, FN_IP11_22_21,
1700		GP_1_2_FN, FN_IP11_20_19,
1701		GP_1_1_FN, FN_IP3_29_27,
1702		GP_1_0_FN, FN_IP3_20 ))
1703	},
1704	{ PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
1705		GP_2_31_FN, FN_IP4_31_30,
1706		GP_2_30_FN, FN_IP5_2_0,
1707		GP_2_29_FN, FN_IP5_5_3,
1708		GP_2_28_FN, FN_IP5_8_6,
1709		GP_2_27_FN, FN_IP5_11_9,
1710		GP_2_26_FN, FN_IP5_14_12,
1711		GP_2_25_FN, FN_IP5_17_15,
1712		GP_2_24_FN, FN_IP5_20_18,
1713		GP_2_23_FN, FN_IP5_22_21,
1714		GP_2_22_FN, FN_IP5_24_23,
1715		GP_2_21_FN, FN_IP5_26_25,
1716		GP_2_20_FN, FN_IP4_29_28,
1717		GP_2_19_FN, FN_IP4_27_26,
1718		GP_2_18_FN, FN_IP4_25_24,
1719		GP_2_17_FN, FN_IP4_23_22,
1720		GP_2_16_FN, FN_IP4_21_20,
1721		GP_2_15_FN, FN_IP4_19_18,
1722		GP_2_14_FN, FN_IP4_17_15,
1723		GP_2_13_FN, FN_IP4_14_12,
1724		GP_2_12_FN, FN_IP4_11_9,
1725		GP_2_11_FN, FN_IP4_8_6,
1726		GP_2_10_FN, FN_IP4_5_3,
1727		GP_2_9_FN, FN_IP8_27_26,
1728		GP_2_8_FN, FN_IP11_12,
1729		GP_2_7_FN, FN_IP8_25_23,
1730		GP_2_6_FN, FN_IP8_22_20,
1731		GP_2_5_FN, FN_IP11_27_26,
1732		GP_2_4_FN, FN_IP8_29_28,
1733		GP_2_3_FN, FN_IP4_2_0,
1734		GP_2_2_FN, FN_IP11_11_10,
1735		GP_2_1_FN, FN_IP11_9_7,
1736		GP_2_0_FN, FN_IP11_6_4 ))
1737	},
1738	{ PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
1739		GP_3_31_FN, FN_IP9_1_0,
1740		GP_3_30_FN, FN_IP8_19_18,
1741		GP_3_29_FN, FN_IP8_17_16,
1742		GP_3_28_FN, FN_IP8_15_14,
1743		GP_3_27_FN, FN_IP8_13_12,
1744		GP_3_26_FN, FN_IP8_11_10,
1745		GP_3_25_FN, FN_IP8_9_8,
1746		GP_3_24_FN, FN_IP8_7_6,
1747		GP_3_23_FN, FN_IP8_5_4,
1748		GP_3_22_FN, FN_IP8_3_2,
1749		GP_3_21_FN, FN_IP8_1_0,
1750		GP_3_20_FN, FN_IP7_30_29,
1751		GP_3_19_FN, FN_IP7_28_27,
1752		GP_3_18_FN, FN_IP7_26_24,
1753		GP_3_17_FN, FN_IP7_23_21,
1754		GP_3_16_FN, FN_IP7_20_18,
1755		GP_3_15_FN, FN_IP7_17_15,
1756		GP_3_14_FN, FN_IP7_14_12,
1757		GP_3_13_FN, FN_IP7_11_9,
1758		GP_3_12_FN, FN_IP7_8_6,
1759		GP_3_11_FN, FN_IP7_5_3,
1760		GP_3_10_FN, FN_IP7_2_0,
1761		GP_3_9_FN, FN_IP6_23_21,
1762		GP_3_8_FN, FN_IP6_20_18,
1763		GP_3_7_FN, FN_IP6_17_16,
1764		GP_3_6_FN, FN_IP6_15_14,
1765		GP_3_5_FN, FN_IP6_13_12,
1766		GP_3_4_FN, FN_IP6_11_10,
1767		GP_3_3_FN, FN_IP6_9_8,
1768		GP_3_2_FN, FN_IP6_7_6,
1769		GP_3_1_FN, FN_IP6_5_3,
1770		GP_3_0_FN, FN_IP6_2_0 ))
1771	},
1772
1773	{ PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
1774		GP_4_31_FN, FN_IP10_24_23,
1775		GP_4_30_FN, FN_IP10_22,
1776		GP_4_29_FN, FN_IP11_18_16,
1777		GP_4_28_FN, FN_USB_OVC0,
1778		GP_4_27_FN, FN_IP11_15_13,
1779		GP_4_26_FN, FN_PENC0,
1780		GP_4_25_FN, FN_IP11_2,
1781		GP_4_24_FN, FN_SCL0,
1782		GP_4_23_FN, FN_IP11_1,
1783		GP_4_22_FN, FN_IP11_0,
1784		GP_4_21_FN, FN_IP10_21_19,
1785		GP_4_20_FN, FN_IP10_18_16,
1786		GP_4_19_FN, FN_IP10_15,
1787		GP_4_18_FN, FN_IP10_14_12,
1788		GP_4_17_FN, FN_IP10_11_9,
1789		GP_4_16_FN, FN_IP10_8_6,
1790		GP_4_15_FN, FN_IP10_5_3,
1791		GP_4_14_FN, FN_IP10_2_0,
1792		GP_4_13_FN, FN_IP9_29_28,
1793		GP_4_12_FN, FN_IP9_27_26,
1794		GP_4_11_FN, FN_IP9_9_8,
1795		GP_4_10_FN, FN_IP9_7_6,
1796		GP_4_9_FN, FN_IP9_5_4,
1797		GP_4_8_FN, FN_IP9_3_2,
1798		GP_4_7_FN, FN_IP9_17_16,
1799		GP_4_6_FN, FN_IP9_15_14,
1800		GP_4_5_FN, FN_IP9_13_12,
1801		GP_4_4_FN, FN_IP9_11_10,
1802		GP_4_3_FN, FN_IP9_25_24,
1803		GP_4_2_FN, FN_IP9_23_22,
1804		GP_4_1_FN, FN_IP9_21_20,
1805		GP_4_0_FN, FN_IP9_19_18 ))
1806	},
1807	{ PINMUX_CFG_REG_VAR("GPSR5", 0xFFFC0018, 32,
1808			     GROUP(-20, 1, 1, -6, 1, 1, 1, 1),
1809			     GROUP(
1810		/* GP5_31_12 RESERVED */
1811		GP_5_11_FN, FN_IP10_29_28,
1812		GP_5_10_FN, FN_IP10_27_26,
1813		/* GP5_9_4 RESERVED */
1814		GP_5_3_FN, FN_IRQ3_B,
1815		GP_5_2_FN, FN_IRQ2_B,
1816		GP_5_1_FN, FN_IP11_3,
1817		GP_5_0_FN, FN_IP10_25 ))
1818	},
1819
1820	{ PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1821			GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1822			GROUP(
1823		/* IP0_31_30 [2] */
1824		FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1825			FN_TIOC3D_C,
1826		/* IP0_29_28 [2] */
1827		FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
1828		/* IP0_27_26 [2] */
1829		FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
1830		/* IP0_25_24 [2] */
1831		FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
1832		/* IP0_23_22 [2] */
1833		FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
1834		/* IP0_21_20 [2] */
1835		FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
1836		/* IP0_19_18 [2] */
1837		FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
1838		/* IP0_17_16 [2] */
1839		FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
1840		/* IP0_15_14 [2] */
1841		FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
1842		/* IP0_13_12 [2] */
1843		FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
1844		/* IP0_11_10 [2] */
1845		FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
1846		/* IP0_9_8 [2] */
1847		FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
1848		/* IP0_7_6 [2] */
1849		FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
1850		/* IP0_5_4 [2] */
1851		FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
1852		/* IP0_3_2 [2] */
1853		FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1854		/* IP0_1_0 [2] */
1855		FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
1856	},
1857	{ PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1858			GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1859			GROUP(
1860		/* IP1_31_29 [3] */
1861		FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1862			FN_FD3_A, 0, 0, 0,
1863		/* IP1_28_26 [3] */
1864		FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
1865			FN_FD2_A, 0, 0, 0,
1866		/* IP1_25_23 [3] */
1867		FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
1868			FN_FD1_A, 0, 0, 0,
1869		/* IP1_22_20 [3] */
1870		FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
1871			FN_FD0_A, 0, 0, 0,
1872		/* IP1_19_18 [2] */
1873		FN_A25, FN_TX2_D, FN_ST1_D2, 0,
1874		/* IP1_17_16 [2] */
1875		FN_A24, FN_RX2_D, FN_ST1_D1, 0,
1876		/* IP1_15_14 [2] */
1877		FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
1878		/* IP1_13_12 [2] */
1879		FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
1880		/* IP1_11_10 [2] */
1881		FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
1882		/* IP1_9_8 [2] */
1883		FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
1884		/* IP1_7_6 [2] */
1885		FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,	FN_TIOC4D_C,
1886		/* IP1_5_4 [2] */
1887		FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
1888		/* IP1_3_2 [2] */
1889		FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A,	FN_TIOC4B_C,
1890		/* IP1_1_0 [2] */
1891		FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
1892	},
1893	{ PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1894			     GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
1895			     GROUP(
1896		/* IP2_31 [1] RESERVED */
1897		/* IP2_30_28 [3] */
1898		FN_D14, FN_TX2_B, 0, FN_FSE_A,
1899			FN_ET0_TX_CLK_B, 0, 0, 0,
1900		/* IP2_27_25 [3] */
1901		FN_D13, FN_RX2_B, 0, FN_FRB_A,
1902			FN_ET0_ETXD6_B, 0, 0, 0,
1903		/* IP2_24_23 [2] */
1904		FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
1905		/* IP2_22_20 [3] */
1906		FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
1907			FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
1908		/* IP2_19_17 [3] */
1909		FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
1910			FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
1911		/* IP2_16_14 [3] */
1912		FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
1913			FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
1914		/* IP2_13_11 [3] */
1915		FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
1916			FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
1917		/* IP2_10_8 [3] */
1918		FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
1919			FN_FD7_A, 0, 0, 0,
1920		/* IP2_7_5 [3] */
1921		FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
1922			FN_FD6_A, 0, 0, 0,
1923		/* IP2_4_3 [2] */
1924		FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1925		/* IP2_2_0 [3] */
1926		FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1927			FN_FD4_A, 0, 0, 0 ))
1928	},
1929	{ PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1930			     GROUP(-2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
1931			     GROUP(
1932	    /* IP3_31_30 [2] RESERVED */
1933	    /* IP3_29_27 [3] */
1934		FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
1935		FN_ET0_ETXD7, 0, 0, 0,
1936	    /* IP3_26_24 [3] */
1937		FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
1938		FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
1939	    /* IP3_23_21 [3] */
1940		FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
1941		FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
1942	    /* IP3_20 [1] */
1943		FN_EX_WAIT0, FN_TCLK1_B,
1944	    /* IP3_19_18 [2] */
1945		FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
1946	    /* IP3_17_15 [3] */
1947		FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1948		FN_ET0_ETXD3_A, 0, 0, 0,
1949	    /* IP3_14_12 [3] */
1950		FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
1951		FN_ET0_ETXD2_A, 0, 0, 0,
1952	    /* IP3_11_9 [3] */
1953		FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
1954		FN_ET0_ETXD1_A, 0, 0, 0,
1955	    /* IP3_8_6 [3] */
1956		FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
1957		FN_ET0_GTX_CLK_A, 0, 0, 0,
1958	    /* IP3_5_3 [3] */
1959		FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
1960		FN_ET0_ETXD0, 0, 0, 0,
1961	    /* IP3_2 [1] */
1962		FN_CS1_A26, FN_QIO3_B,
1963	    /* IP3_1_0 [2] */
1964		FN_D15, FN_SCK2_B, 0, 0 ))
1965	},
1966	{ PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
1967			     GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
1968			     GROUP(
1969	    /* IP4_31_30 [2] */
1970		0, FN_SCK2_A, FN_VI0_G3, 0,
1971	    /* IP4_29_28 [2] */
1972		0, FN_RTS1_B, FN_VI0_G2, 0,
1973	    /* IP4_27_26 [2] */
1974		0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
1975	    /* IP4_25_24 [2] */
1976		0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
1977	    /* IP4_23_22 [2] */
1978		0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
1979	    /* IP4_21_20 [2] */
1980		0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
1981	    /* IP4_19_18 [2] */
1982		0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
1983	    /* IP4_17_15 [3] */
1984		0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
1985			FN_ET0_MDC, 0, 0, 0,
1986	    /* IP4_14_12 [3] */
1987		FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
1988			FN_ET0_COL, 0, 0, 0,
1989	    /* IP4_11_9 [3] */
1990		FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
1991			FN_ET0_CRS, 0, 0, 0,
1992	    /* IP4_8_6 [3] */
1993		FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
1994			FN_ET0_RX_ER, 0, 0, 0,
1995	    /* IP4_5_3 [3] */
1996		FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
1997			FN_ET0_RX_DV, 0, 0, 0,
1998	    /* IP4_2_0 [3] */
1999		FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2000			FN_ET0_ERXD7, 0, 0, 0 ))
2001	},
2002	{ PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2003			     GROUP(-5, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3),
2004			     GROUP(
2005	    /* IP5_31_27 [5] RESERVED */
2006	    /* IP5_26_25 [2] */
2007		FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
2008	    /* IP5_24_23 [2] */
2009		FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
2010	    /* IP5_22_21 [2] */
2011		FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
2012	    /* IP5_20_18 [3] */
2013		FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
2014		0, 0, 0, FN_ET0_PHY_INT_B,
2015	    /* IP5_17_15 [3] */
2016		FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
2017		0, 0, 0, FN_ET0_MAGIC_B,
2018	    /* IP5_14_12 [3] */
2019		FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
2020		0, 0, 0, FN_ET0_LINK_B,
2021	    /* IP5_11_9 [3] */
2022		FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
2023		0, 0, 0, FN_ET0_MDIO_B,
2024	    /* IP5_8_6 [3] */
2025		FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
2026		0, 0, 0, FN_ET0_ERXD3_B,
2027	    /* IP5_5_3 [3] */
2028		FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
2029		0, 0, 0, FN_ET0_ERXD2_B,
2030	    /* IP5_2_0 [3] */
2031		FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2032		FN_ET0_RX_CLK_B, 0, 0, 0 ))
2033	},
2034	{ PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2035			     GROUP(-8, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3),
2036			     GROUP(
2037	    /* IP5_31_24 [8] RESERVED */
2038	    /* IP6_23_21 [3] */
2039		FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
2040		FN_HIFD09, 0, 0, 0,
2041	    /* IP6_20_18 [3] */
2042		FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
2043		FN_TIOC1A_A, FN_HIFD08, 0, 0,
2044	    /* IP6_17_16 [2] */
2045		FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
2046	    /* IP6_15_14 [2] */
2047		FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
2048	    /* IP6_13_12 [2] */
2049		FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
2050	    /* IP6_11_10 [2] */
2051		FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
2052	    /* IP6_9_8 [2] */
2053		FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
2054	    /* IP6_7_6 [2] */
2055		FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
2056	    /* IP6_5_3 [3] */
2057		FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
2058		FN_TCLKB_A, FN_HIFD01, 0, 0,
2059	    /* IP6_2_0 [3] */
2060		FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2061		FN_TCLKA_A, FN_HIFD00, 0, 0 ))
2062	},
2063	{ PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2064			     GROUP(-1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2065			     GROUP(
2066	    /* IP7_31 [1] RESERVED */
2067	    /* IP7_30_29 [2] */
2068		FN_DU0_DB4, 0, FN_HIFINT, 0,
2069	    /* IP7_28_27 [2] */
2070		FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
2071	    /* IP7_26_24 [3] */
2072		FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
2073		FN_HIFWR, 0, 0, 0,
2074	    /* IP7_23_21 [3] */
2075		FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
2076		FN_HIFRS, 0, 0, 0,
2077	    /* IP7_20_18 [3] */
2078		FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
2079		FN_HIFCS, 0, 0, 0,
2080	    /* IP7_17_15 [3] */
2081		FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
2082		FN_HIFD15, 0, 0, 0,
2083	    /* IP7_14_12 [3] */
2084		FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
2085		FN_HIFD14, 0, 0, 0,
2086	    /* IP7_11_9 [3] */
2087		FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
2088		FN_HIFD13, 0, 0, 0,
2089	    /* IP7_8_6 [3] */
2090		FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
2091		FN_HIFD12, 0, 0, 0,
2092	    /* IP7_5_3 [3] */
2093		FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
2094		FN_HIFD11, 0, 0, 0,
2095	    /* IP7_2_0 [3] */
2096		FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2097		FN_HIFD10, 0, 0, 0 ))
2098	},
2099	{ PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2100			     GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2101				   2, 2, 2),
2102			     GROUP(
2103	    /* IP9_31_30 [2] RESERVED */
2104	    /* IP8_29_28 [2] */
2105		FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
2106	    /* IP8_27_26 [2] */
2107		FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
2108	    /* IP8_25_23 [3] */
2109		FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
2110			FN_ET0_ERXD1, 0, 0, 0,
2111	    /* IP8_22_20 [3] */
2112		FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
2113			FN_ET0_ERXD0, 0, 0, 0,
2114	    /* IP8_19_18 [2] */
2115		FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
2116	    /* IP8_17_16 [2] */
2117		FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
2118	    /* IP8_15_14 [2] */
2119		FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
2120			FN_SSI_SDATA1_B,
2121	    /* IP8_13_12 [2] */
2122		FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
2123	    /* IP8_11_10 [2] */
2124		FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
2125	    /* IP8_9_8 [2] */
2126		FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
2127	    /* IP8_7_6 [2] */
2128		FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
2129	    /* IP8_5_4 [2] */
2130		FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
2131	    /* IP8_3_2 [2] */
2132		FN_DU0_DB6, 0, FN_HIFRDY, 0,
2133	    /* IP8_1_0 [2] */
2134		FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
2135	},
2136	{ PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2137			     GROUP(-2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2138				   2, 2, 2, 2),
2139			     GROUP(
2140	    /* IP9_31_30 [2] RESERVED */
2141	    /* IP9_29_28 [2] */
2142		FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
2143	    /* IP9_27_26 [2] */
2144		FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
2145	    /* IP9_25_24 [2] */
2146		FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
2147	    /* IP9_23_22 [2] */
2148		FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
2149	    /* IP9_21_20 [2] */
2150		FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
2151	    /* IP9_19_18 [2] */
2152		FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
2153	    /* IP9_17_16 [2] */
2154		FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
2155	    /* IP9_15_14 [2] */
2156		FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
2157	    /* IP9_13_12 [2] */
2158		FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
2159	    /* IP9_11_10 [2] */
2160		FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
2161	    /* IP9_9_8 [2] */
2162		FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
2163	    /* IP9_7_6 [2] */
2164		FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
2165	    /* IP9_5_4 [2] */
2166		FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
2167	    /* IP9_3_2 [2] */
2168		FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2169	    /* IP9_1_0 [2] */
2170		FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
2171	},
2172	{ PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2173			     GROUP(-2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
2174			     GROUP(
2175	    /* IP9_31_30 [2] RESERVED */
2176	    /* IP10_29_28 [2] */
2177		FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
2178	    /* IP10_27_26 [2] */
2179		FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
2180	    /* IP10_25 [1] */
2181		FN_CAN1_RX_A, FN_IRQ1_B,
2182	    /* IP10_24_23 [2] */
2183		FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
2184	    /* IP10_22 [1] */
2185		FN_CAN_CLK_A, FN_RX4_D,
2186	    /* IP10_21_19 [3] */
2187		FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
2188		FN_LCD_M_DISP_B, 0, 0,
2189	    /* IP10_18_16 [3] */
2190		FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
2191		FN_LCD_VEPWC_B, 0, 0,
2192	    /* IP10_15 [1] */
2193		FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
2194	    /* IP10_14_12 [3] */
2195		FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
2196		FN_LCD_FLM_B, 0, 0, 0,
2197	    /* IP10_11_9 [3] */
2198		FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
2199		FN_LCD_CL2_B, 0, 0,
2200	    /* IP10_8_6 [3] */
2201		FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
2202		FN_LCD_CL1_B, 0, 0,
2203	    /* IP10_5_3 [3] */
2204		FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
2205		FN_LCD_DON_B, 0, 0,
2206	    /* IP10_2_0 [3] */
2207		FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2208		FN_LCD_DATA15_B, 0, 0, 0 ))
2209	},
2210	{ PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2211			     GROUP(-3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
2212				   1, 1, 1, 1),
2213			     GROUP(
2214	    /* IP11_31_29 [3] RESERVED */
2215	    /* IP11_28 [1] */
2216		FN_PRESETOUT, FN_ST_CLKOUT,
2217	    /* IP11_27_26 [2] */
2218		FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
2219	    /* IP11_25_23 [3] */
2220		FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
2221		FN_ET0_TX_CLK_A, 0, 0, 0,
2222	    /* IP11_22_21 [2] */
2223		FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
2224	    /* IP11_20_19 [2] */
2225		FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
2226	    /* IP11_18_16 [3] */
2227		FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
2228		FN_IERX_B, 0, 0, 0,
2229	    /* IP11_15_13 [3] */
2230		FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
2231		FN_IETX_B, 0, 0, 0,
2232	    /* IP11_12 [1] */
2233		FN_TX0_A, FN_HSPI_TX_A,
2234	    /* IP11_11_10 [2] */
2235		FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
2236	    /* IP11_9_7 [3] */
2237		FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
2238		FN_ET0_ERXD5, 0, 0, 0,
2239	    /* IP11_6_4 [3] */
2240		FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
2241		FN_ET0_ERXD4, 0, 0, 0,
2242	    /* IP11_3 [1] */
2243		FN_SDSELF, FN_RTS1_E,
2244	    /* IP11_2 [1] */
2245		FN_SDA0, FN_HIFEBL_A,
2246	    /* IP11_1 [1] */
2247		FN_SDA1, FN_RX1_E,
2248	    /* IP11_0 [1] */
2249		FN_SCL1, FN_SCIF_CLK_C ))
2250	},
2251	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2252			     GROUP(-3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2253				   2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2254			     GROUP(
2255		/* SEL1_31_29 [3] RESERVED */
2256		/* SEL1_28 [1] */
2257		FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
2258		/* SEL1_27 [1] */
2259		FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
2260		/* SEL1_26 [1] */
2261		FN_SEL_VIN1_0, FN_SEL_VIN1_1,
2262		/* SEL1_25 [1] */
2263		FN_SEL_HIF_0, FN_SEL_HIF_1,
2264		/* SEL1_24 [1] */
2265		FN_SEL_RSPI_0, FN_SEL_RSPI_1,
2266		/* SEL1_23 [1] */
2267		FN_SEL_LCDC_0, FN_SEL_LCDC_1,
2268		/* SEL1_22_21 [2] */
2269		FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
2270		/* SEL1_20 [1] */
2271		FN_SEL_ET0_0, FN_SEL_ET0_1,
2272		/* SEL1_19 [1] */
2273		FN_SEL_RMII_0, FN_SEL_RMII_1,
2274		/* SEL1_18 [1] */
2275		FN_SEL_TMU_0, FN_SEL_TMU_1,
2276		/* SEL1_17_16 [2] */
2277		FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
2278		/* SEL1_15_14 [2] */
2279		FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
2280		/* SEL1_13 [1] */
2281		FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
2282		/* SEL1_12_11 [2] */
2283		FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
2284		/* SEL1_10 [1] */
2285		FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
2286		/* SEL1_9 [1] */
2287		FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
2288		/* SEL1_8 [1] */
2289		FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
2290		/* SEL1_7 [1] */
2291		FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
2292		/* SEL1_6 [1] */
2293		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
2294		/* SEL1_5 [1] */
2295		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
2296		/* SEL1_4 [1] */
2297		FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
2298		/* SEL1_3 [1] */
2299		FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
2300		/* SEL1_2 [1] */
2301		FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
2302		/* SEL1_1 [1] */
2303		FN_SEL_MMC_0, FN_SEL_MMC_1,
2304		/* SEL1_0 [1] */
2305		FN_SEL_INTC_0, FN_SEL_INTC_1 ))
2306	},
2307	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2308			     GROUP(-8, 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2),
2309			     GROUP(
2310		/* SEL2_31_24 [8] RESERVED */
2311		/* SEL2_23 [1] */
2312		FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
2313		/* SEL2_22 [1] */
2314		FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
2315		/* SEL2_21 [1] */
2316		FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
2317		/* SEL2_20_19 [2] */
2318		FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
2319		/* SEL2_18_17 [2] */
2320		FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
2321		/* SEL2_16 [1] */
2322		FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
2323		/* SEL2_15_14 [2] */
2324		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2325		/* SEL2_13_12 [2] */
2326		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2327		/* SEL2_11_9 [3] */
2328		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2329		FN_SEL_SCIF3_4, 0, 0, 0,
2330		/* SEL2_8_7 [2] */
2331		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2332		/* SEL2_6_4 [3] */
2333		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
2334			FN_SEL_SCIF1_4, 0, 0, 0,
2335		/* SEL2_3_2 [2] */
2336		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2337		/* SEL2_1_0 [2] */
2338		FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0  ))
2339	},
2340	/* GPIO 0 - 5*/
2341	{ PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
2342	},
2343	{ PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
2344	},
2345	{ PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
2346	},
2347	{ PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
2348	},
2349	{ PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
2350	},
2351	{ PINMUX_CFG_REG_VAR("INOUTSEL5", 0xffc45004, 32,
2352			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2353			     GROUP(
2354		/* GP5_31_12 RESERVED */
2355		GP_5_11_IN, GP_5_11_OUT,
2356		GP_5_10_IN, GP_5_10_OUT,
2357		GP_5_9_IN, GP_5_9_OUT,
2358		GP_5_8_IN, GP_5_8_OUT,
2359		GP_5_7_IN, GP_5_7_OUT,
2360		GP_5_6_IN, GP_5_6_OUT,
2361		GP_5_5_IN, GP_5_5_OUT,
2362		GP_5_4_IN, GP_5_4_OUT,
2363		GP_5_3_IN, GP_5_3_OUT,
2364		GP_5_2_IN, GP_5_2_OUT,
2365		GP_5_1_IN, GP_5_1_OUT,
2366		GP_5_0_IN, GP_5_0_OUT ))
2367	},
2368	{ /* sentinel */ }
2369};
2370
2371static const struct pinmux_data_reg pinmux_data_regs[] = {
2372	/* GPIO 0 - 5*/
2373	{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
2374	{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
2375	{ PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
2376	{ PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
2377	{ PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
2378	{ PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
2379		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2380		0, 0, 0, 0,
2381		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2382		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2383		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
2384	},
2385	{ /* sentinel */ }
2386};
2387
2388const struct sh_pfc_soc_info sh7734_pinmux_info = {
2389	.name = "sh7734_pfc",
2390
2391	.unlock_reg = 0xFFFC0000,
2392
2393	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2394	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2395	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2396
2397	.pins = pinmux_pins,
2398	.nr_pins = ARRAY_SIZE(pinmux_pins),
2399	.func_gpios = pinmux_func_gpios,
2400	.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2401
2402	.cfg_regs = pinmux_config_regs,
2403	.data_regs = pinmux_data_regs,
2404
2405	.pinmux_data = pinmux_data,
2406	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
2407};