pfc-r8a779g0.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A779G0 processor support - PFC hardware block.
   4 *
   5 * Copyright (C) 2021 Renesas Electronics Corp.
   6 *
   7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
   8 */
   9
  10#include <linux/errno.h>
  11#include <linux/io.h>
  12#include <linux/kernel.h>
  13
  14#include "sh_pfc.h"
  15
  16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  17
  18#define CPU_ALL_GP(fn, sfx)								\
  19	PORT_GP_CFG_19(0,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  20	PORT_GP_CFG_23(1,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  21	PORT_GP_CFG_1(1, 23,	fn, sfx, CFG_FLAGS),					\
  22	PORT_GP_CFG_1(1, 24,	fn, sfx, CFG_FLAGS),					\
  23	PORT_GP_CFG_1(1, 25,	fn, sfx, CFG_FLAGS),					\
  24	PORT_GP_CFG_1(1, 26,	fn, sfx, CFG_FLAGS),					\
  25	PORT_GP_CFG_1(1, 27,	fn, sfx, CFG_FLAGS),					\
  26	PORT_GP_CFG_1(1, 28,	fn, sfx, CFG_FLAGS),					\
  27	PORT_GP_CFG_20(2,	fn, sfx, CFG_FLAGS),					\
  28	PORT_GP_CFG_13(3,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  29	PORT_GP_CFG_1(3, 13,	fn, sfx, CFG_FLAGS),					\
  30	PORT_GP_CFG_1(3, 14,	fn, sfx, CFG_FLAGS),					\
  31	PORT_GP_CFG_1(3, 15,	fn, sfx, CFG_FLAGS),					\
  32	PORT_GP_CFG_1(3, 16,	fn, sfx, CFG_FLAGS),					\
  33	PORT_GP_CFG_1(3, 17,	fn, sfx, CFG_FLAGS),					\
  34	PORT_GP_CFG_1(3, 18,	fn, sfx, CFG_FLAGS),					\
  35	PORT_GP_CFG_1(3, 19,	fn, sfx, CFG_FLAGS),					\
  36	PORT_GP_CFG_1(3, 20,	fn, sfx, CFG_FLAGS),					\
  37	PORT_GP_CFG_1(3, 21,	fn, sfx, CFG_FLAGS),					\
  38	PORT_GP_CFG_1(3, 22,	fn, sfx, CFG_FLAGS),					\
  39	PORT_GP_CFG_1(3, 23,	fn, sfx, CFG_FLAGS),					\
  40	PORT_GP_CFG_1(3, 24,	fn, sfx, CFG_FLAGS),					\
  41	PORT_GP_CFG_1(3, 25,	fn, sfx, CFG_FLAGS),					\
  42	PORT_GP_CFG_1(3, 26,	fn, sfx, CFG_FLAGS),					\
  43	PORT_GP_CFG_1(3, 27,	fn, sfx, CFG_FLAGS),					\
  44	PORT_GP_CFG_1(3, 28,	fn, sfx, CFG_FLAGS),					\
  45	PORT_GP_CFG_1(3, 29,	fn, sfx, CFG_FLAGS),					\
  46	PORT_GP_CFG_25(4,	fn, sfx, CFG_FLAGS),					\
  47	PORT_GP_CFG_21(5,	fn, sfx, CFG_FLAGS),					\
  48	PORT_GP_CFG_21(6,	fn, sfx, CFG_FLAGS),					\
  49	PORT_GP_CFG_21(7,	fn, sfx, CFG_FLAGS),					\
  50	PORT_GP_CFG_14(8,	fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
  51
  52#define CPU_ALL_NOGP(fn)								\
  53	PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
  54	PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
  55	PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25),	\
  56	PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
  57
  58/* GPSR0 */
  59#define GPSR0_18	F_(MSIOF2_RXD,		IP2SR0_11_8)
  60#define GPSR0_17	F_(MSIOF2_SCK,		IP2SR0_7_4)
  61#define GPSR0_16	F_(MSIOF2_TXD,		IP2SR0_3_0)
  62#define GPSR0_15	F_(MSIOF2_SYNC,		IP1SR0_31_28)
  63#define GPSR0_14	F_(MSIOF2_SS1,		IP1SR0_27_24)
  64#define GPSR0_13	F_(MSIOF2_SS2,		IP1SR0_23_20)
  65#define GPSR0_12	F_(MSIOF5_RXD,		IP1SR0_19_16)
  66#define GPSR0_11	F_(MSIOF5_SCK,		IP1SR0_15_12)
  67#define GPSR0_10	F_(MSIOF5_TXD,		IP1SR0_11_8)
  68#define GPSR0_9		F_(MSIOF5_SYNC,		IP1SR0_7_4)
  69#define GPSR0_8		F_(MSIOF5_SS1,		IP1SR0_3_0)
  70#define GPSR0_7		F_(MSIOF5_SS2,		IP0SR0_31_28)
  71#define GPSR0_6		F_(IRQ0_A,		IP0SR0_27_24)
  72#define GPSR0_5		F_(IRQ1_A,		IP0SR0_23_20)
  73#define GPSR0_4		F_(IRQ2_A,		IP0SR0_19_16)
  74#define GPSR0_3		F_(IRQ3_A,		IP0SR0_15_12)
  75#define GPSR0_2		F_(GP0_02,		IP0SR0_11_8)
  76#define GPSR0_1		F_(GP0_01,		IP0SR0_7_4)
  77#define GPSR0_0		F_(GP0_00,		IP0SR0_3_0)
  78
  79/* GPSR1 */
  80#define GPSR1_28	F_(HTX3_A,		IP3SR1_19_16)
  81#define GPSR1_27	F_(HCTS3_N_A,		IP3SR1_15_12)
  82#define GPSR1_26	F_(HRTS3_N_A,		IP3SR1_11_8)
  83#define GPSR1_25	F_(HSCK3_A,		IP3SR1_7_4)
  84#define GPSR1_24	F_(HRX3_A,		IP3SR1_3_0)
  85#define GPSR1_23	F_(GP1_23,		IP2SR1_31_28)
  86#define GPSR1_22	F_(AUDIO_CLKIN,		IP2SR1_27_24)
  87#define GPSR1_21	F_(AUDIO_CLKOUT,	IP2SR1_23_20)
  88#define GPSR1_20	F_(SSI_SD,		IP2SR1_19_16)
  89#define GPSR1_19	F_(SSI_WS,		IP2SR1_15_12)
  90#define GPSR1_18	F_(SSI_SCK,		IP2SR1_11_8)
  91#define GPSR1_17	F_(SCIF_CLK,		IP2SR1_7_4)
  92#define GPSR1_16	F_(HRX0,		IP2SR1_3_0)
  93#define GPSR1_15	F_(HSCK0,		IP1SR1_31_28)
  94#define GPSR1_14	F_(HRTS0_N,		IP1SR1_27_24)
  95#define GPSR1_13	F_(HCTS0_N,		IP1SR1_23_20)
  96#define GPSR1_12	F_(HTX0,		IP1SR1_19_16)
  97#define GPSR1_11	F_(MSIOF0_RXD,		IP1SR1_15_12)
  98#define GPSR1_10	F_(MSIOF0_SCK,		IP1SR1_11_8)
  99#define GPSR1_9		F_(MSIOF0_TXD,		IP1SR1_7_4)
 100#define GPSR1_8		F_(MSIOF0_SYNC,		IP1SR1_3_0)
 101#define GPSR1_7		F_(MSIOF0_SS1,		IP0SR1_31_28)
 102#define GPSR1_6		F_(MSIOF0_SS2,		IP0SR1_27_24)
 103#define GPSR1_5		F_(MSIOF1_RXD,		IP0SR1_23_20)
 104#define GPSR1_4		F_(MSIOF1_TXD,		IP0SR1_19_16)
 105#define GPSR1_3		F_(MSIOF1_SCK,		IP0SR1_15_12)
 106#define GPSR1_2		F_(MSIOF1_SYNC,		IP0SR1_11_8)
 107#define GPSR1_1		F_(MSIOF1_SS1,		IP0SR1_7_4)
 108#define GPSR1_0		F_(MSIOF1_SS2,		IP0SR1_3_0)
 109
 110/* GPSR2 */
 111#define GPSR2_19	F_(CANFD7_RX,		IP2SR2_15_12)
 112#define GPSR2_18	F_(CANFD7_TX,		IP2SR2_11_8)
 113#define GPSR2_17	F_(CANFD4_RX,		IP2SR2_7_4)
 114#define GPSR2_16	F_(CANFD4_TX,		IP2SR2_3_0)
 115#define GPSR2_15	F_(CANFD3_RX,		IP1SR2_31_28)
 116#define GPSR2_14	F_(CANFD3_TX,		IP1SR2_27_24)
 117#define GPSR2_13	F_(CANFD2_RX,		IP1SR2_23_20)
 118#define GPSR2_12	F_(CANFD2_TX,		IP1SR2_19_16)
 119#define GPSR2_11	F_(CANFD0_RX,		IP1SR2_15_12)
 120#define GPSR2_10	F_(CANFD0_TX,		IP1SR2_11_8)
 121#define GPSR2_9		F_(CAN_CLK,		IP1SR2_7_4)
 122#define GPSR2_8		F_(TPU0TO0_A,		IP1SR2_3_0)
 123#define GPSR2_7		F_(TPU0TO1_A,		IP0SR2_31_28)
 124#define GPSR2_6		F_(FXR_TXDB,		IP0SR2_27_24)
 125#define GPSR2_5		F_(FXR_TXENB_N_A,	IP0SR2_23_20)
 126#define GPSR2_4		F_(RXDB_EXTFXR,		IP0SR2_19_16)
 127#define GPSR2_3		F_(CLK_EXTFXR,		IP0SR2_15_12)
 128#define GPSR2_2		F_(RXDA_EXTFXR,		IP0SR2_11_8)
 129#define GPSR2_1		F_(FXR_TXENA_N_A,	IP0SR2_7_4)
 130#define GPSR2_0		F_(FXR_TXDA,		IP0SR2_3_0)
 131
 132/* GPSR3 */
 133#define GPSR3_29	F_(RPC_INT_N,		IP3SR3_23_20)
 134#define GPSR3_28	F_(RPC_WP_N,		IP3SR3_19_16)
 135#define GPSR3_27	F_(RPC_RESET_N,		IP3SR3_15_12)
 136#define GPSR3_26	F_(QSPI1_IO3,		IP3SR3_11_8)
 137#define GPSR3_25	F_(QSPI1_SSL,		IP3SR3_7_4)
 138#define GPSR3_24	F_(QSPI1_IO2,		IP3SR3_3_0)
 139#define GPSR3_23	F_(QSPI1_MISO_IO1,	IP2SR3_31_28)
 140#define GPSR3_22	F_(QSPI1_SPCLK,		IP2SR3_27_24)
 141#define GPSR3_21	F_(QSPI1_MOSI_IO0,	IP2SR3_23_20)
 142#define GPSR3_20	F_(QSPI0_SPCLK,		IP2SR3_19_16)
 143#define GPSR3_19	F_(QSPI0_MOSI_IO0,	IP2SR3_15_12)
 144#define GPSR3_18	F_(QSPI0_MISO_IO1,	IP2SR3_11_8)
 145#define GPSR3_17	F_(QSPI0_IO2,		IP2SR3_7_4)
 146#define GPSR3_16	F_(QSPI0_IO3,		IP2SR3_3_0)
 147#define GPSR3_15	F_(QSPI0_SSL,		IP1SR3_31_28)
 148#define GPSR3_14	F_(IPC_CLKOUT,		IP1SR3_27_24)
 149#define GPSR3_13	F_(IPC_CLKIN,		IP1SR3_23_20)
 150#define GPSR3_12	F_(SD_WP,		IP1SR3_19_16)
 151#define GPSR3_11	F_(SD_CD,		IP1SR3_15_12)
 152#define GPSR3_10	F_(MMC_SD_CMD,		IP1SR3_11_8)
 153#define GPSR3_9		F_(MMC_D6,		IP1SR3_7_4)
 154#define GPSR3_8		F_(MMC_D7,		IP1SR3_3_0)
 155#define GPSR3_7		F_(MMC_D4,		IP0SR3_31_28)
 156#define GPSR3_6		F_(MMC_D5,		IP0SR3_27_24)
 157#define GPSR3_5		F_(MMC_SD_D3,		IP0SR3_23_20)
 158#define GPSR3_4		F_(MMC_DS,		IP0SR3_19_16)
 159#define GPSR3_3		F_(MMC_SD_CLK,		IP0SR3_15_12)
 160#define GPSR3_2		F_(MMC_SD_D2,		IP0SR3_11_8)
 161#define GPSR3_1		F_(MMC_SD_D0,		IP0SR3_7_4)
 162#define GPSR3_0		F_(MMC_SD_D1,		IP0SR3_3_0)
 163
 164/* GPSR4 */
 165#define GPSR4_24	F_(AVS1,		IP3SR4_3_0)
 166#define GPSR4_23	F_(AVS0,		IP2SR4_31_28)
 167#define GPSR4_22	F_(PCIE1_CLKREQ_N,	IP2SR4_27_24)
 168#define GPSR4_21	F_(PCIE0_CLKREQ_N,	IP2SR4_23_20)
 169#define GPSR4_20	F_(TSN0_TXCREFCLK,	IP2SR4_19_16)
 170#define GPSR4_19	F_(TSN0_TD2,		IP2SR4_15_12)
 171#define GPSR4_18	F_(TSN0_TD3,		IP2SR4_11_8)
 172#define GPSR4_17	F_(TSN0_RD2,		IP2SR4_7_4)
 173#define GPSR4_16	F_(TSN0_RD3,		IP2SR4_3_0)
 174#define GPSR4_15	F_(TSN0_TD0,		IP1SR4_31_28)
 175#define GPSR4_14	F_(TSN0_TD1,		IP1SR4_27_24)
 176#define GPSR4_13	F_(TSN0_RD1,		IP1SR4_23_20)
 177#define GPSR4_12	F_(TSN0_TXC,		IP1SR4_19_16)
 178#define GPSR4_11	F_(TSN0_RXC,		IP1SR4_15_12)
 179#define GPSR4_10	F_(TSN0_RD0,		IP1SR4_11_8)
 180#define GPSR4_9		F_(TSN0_TX_CTL,		IP1SR4_7_4)
 181#define GPSR4_8		F_(TSN0_AVTP_PPS0,	IP1SR4_3_0)
 182#define GPSR4_7		F_(TSN0_RX_CTL,		IP0SR4_31_28)
 183#define GPSR4_6		F_(TSN0_AVTP_CAPTURE,	IP0SR4_27_24)
 184#define GPSR4_5		F_(TSN0_AVTP_MATCH,	IP0SR4_23_20)
 185#define GPSR4_4		F_(TSN0_LINK,		IP0SR4_19_16)
 186#define GPSR4_3		F_(TSN0_PHY_INT,	IP0SR4_15_12)
 187#define GPSR4_2		F_(TSN0_AVTP_PPS1,	IP0SR4_11_8)
 188#define GPSR4_1		F_(TSN0_MDC,		IP0SR4_7_4)
 189#define GPSR4_0		F_(TSN0_MDIO,		IP0SR4_3_0)
 190
 191/* GPSR 5 */
 192#define GPSR5_20	F_(AVB2_RX_CTL,		IP2SR5_19_16)
 193#define GPSR5_19	F_(AVB2_TX_CTL,		IP2SR5_15_12)
 194#define GPSR5_18	F_(AVB2_RXC,		IP2SR5_11_8)
 195#define GPSR5_17	F_(AVB2_RD0,		IP2SR5_7_4)
 196#define GPSR5_16	F_(AVB2_TXC,		IP2SR5_3_0)
 197#define GPSR5_15	F_(AVB2_TD0,		IP1SR5_31_28)
 198#define GPSR5_14	F_(AVB2_RD1,		IP1SR5_27_24)
 199#define GPSR5_13	F_(AVB2_RD2,		IP1SR5_23_20)
 200#define GPSR5_12	F_(AVB2_TD1,		IP1SR5_19_16)
 201#define GPSR5_11	F_(AVB2_TD2,		IP1SR5_15_12)
 202#define GPSR5_10	F_(AVB2_MDIO,		IP1SR5_11_8)
 203#define GPSR5_9		F_(AVB2_RD3,		IP1SR5_7_4)
 204#define GPSR5_8		F_(AVB2_TD3,		IP1SR5_3_0)
 205#define GPSR5_7		F_(AVB2_TXCREFCLK,	IP0SR5_31_28)
 206#define GPSR5_6		F_(AVB2_MDC,		IP0SR5_27_24)
 207#define GPSR5_5		F_(AVB2_MAGIC,		IP0SR5_23_20)
 208#define GPSR5_4		F_(AVB2_PHY_INT,	IP0SR5_19_16)
 209#define GPSR5_3		F_(AVB2_LINK,		IP0SR5_15_12)
 210#define GPSR5_2		F_(AVB2_AVTP_MATCH,	IP0SR5_11_8)
 211#define GPSR5_1		F_(AVB2_AVTP_CAPTURE,	IP0SR5_7_4)
 212#define GPSR5_0		F_(AVB2_AVTP_PPS,	IP0SR5_3_0)
 213
 214/* GPSR 6 */
 215#define GPSR6_20	F_(AVB1_TXCREFCLK,	IP2SR6_19_16)
 216#define GPSR6_19	F_(AVB1_RD3,		IP2SR6_15_12)
 217#define GPSR6_18	F_(AVB1_TD3,		IP2SR6_11_8)
 218#define GPSR6_17	F_(AVB1_RD2,		IP2SR6_7_4)
 219#define GPSR6_16	F_(AVB1_TD2,		IP2SR6_3_0)
 220#define GPSR6_15	F_(AVB1_RD0,		IP1SR6_31_28)
 221#define GPSR6_14	F_(AVB1_RD1,		IP1SR6_27_24)
 222#define GPSR6_13	F_(AVB1_TD0,		IP1SR6_23_20)
 223#define GPSR6_12	F_(AVB1_TD1,		IP1SR6_19_16)
 224#define GPSR6_11	F_(AVB1_AVTP_CAPTURE,	IP1SR6_15_12)
 225#define GPSR6_10	F_(AVB1_AVTP_PPS,	IP1SR6_11_8)
 226#define GPSR6_9		F_(AVB1_RX_CTL,		IP1SR6_7_4)
 227#define GPSR6_8		F_(AVB1_RXC,		IP1SR6_3_0)
 228#define GPSR6_7		F_(AVB1_TX_CTL,		IP0SR6_31_28)
 229#define GPSR6_6		F_(AVB1_TXC,		IP0SR6_27_24)
 230#define GPSR6_5		F_(AVB1_AVTP_MATCH,	IP0SR6_23_20)
 231#define GPSR6_4		F_(AVB1_LINK,		IP0SR6_19_16)
 232#define GPSR6_3		F_(AVB1_PHY_INT,	IP0SR6_15_12)
 233#define GPSR6_2		F_(AVB1_MDC,		IP0SR6_11_8)
 234#define GPSR6_1		F_(AVB1_MAGIC,		IP0SR6_7_4)
 235#define GPSR6_0		F_(AVB1_MDIO,		IP0SR6_3_0)
 236
 237/* GPSR7 */
 238#define GPSR7_20	F_(AVB0_RX_CTL,		IP2SR7_19_16)
 239#define GPSR7_19	F_(AVB0_RXC,		IP2SR7_15_12)
 240#define GPSR7_18	F_(AVB0_RD0,		IP2SR7_11_8)
 241#define GPSR7_17	F_(AVB0_RD1,		IP2SR7_7_4)
 242#define GPSR7_16	F_(AVB0_TX_CTL,		IP2SR7_3_0)
 243#define GPSR7_15	F_(AVB0_TXC,		IP1SR7_31_28)
 244#define GPSR7_14	F_(AVB0_MDIO,		IP1SR7_27_24)
 245#define GPSR7_13	F_(AVB0_MDC,		IP1SR7_23_20)
 246#define GPSR7_12	F_(AVB0_RD2,		IP1SR7_19_16)
 247#define GPSR7_11	F_(AVB0_TD0,		IP1SR7_15_12)
 248#define GPSR7_10	F_(AVB0_MAGIC,		IP1SR7_11_8)
 249#define GPSR7_9		F_(AVB0_TXCREFCLK,	IP1SR7_7_4)
 250#define GPSR7_8		F_(AVB0_RD3,		IP1SR7_3_0)
 251#define GPSR7_7		F_(AVB0_TD1,		IP0SR7_31_28)
 252#define GPSR7_6		F_(AVB0_TD2,		IP0SR7_27_24)
 253#define GPSR7_5		F_(AVB0_PHY_INT,	IP0SR7_23_20)
 254#define GPSR7_4		F_(AVB0_LINK,		IP0SR7_19_16)
 255#define GPSR7_3		F_(AVB0_TD3,		IP0SR7_15_12)
 256#define GPSR7_2		F_(AVB0_AVTP_MATCH,	IP0SR7_11_8)
 257#define GPSR7_1		F_(AVB0_AVTP_CAPTURE,	IP0SR7_7_4)
 258#define GPSR7_0		F_(AVB0_AVTP_PPS,	IP0SR7_3_0)
 259
 260/* GPSR8 */
 261#define GPSR8_13	F_(GP8_13,		IP1SR8_23_20)
 262#define GPSR8_12	F_(GP8_12,		IP1SR8_19_16)
 263#define GPSR8_11	F_(SDA5,		IP1SR8_15_12)
 264#define GPSR8_10	F_(SCL5,		IP1SR8_11_8)
 265#define GPSR8_9		F_(SDA4,		IP1SR8_7_4)
 266#define GPSR8_8		F_(SCL4,		IP1SR8_3_0)
 267#define GPSR8_7		F_(SDA3,		IP0SR8_31_28)
 268#define GPSR8_6		F_(SCL3,		IP0SR8_27_24)
 269#define GPSR8_5		F_(SDA2,		IP0SR8_23_20)
 270#define GPSR8_4		F_(SCL2,		IP0SR8_19_16)
 271#define GPSR8_3		F_(SDA1,		IP0SR8_15_12)
 272#define GPSR8_2		F_(SCL1,		IP0SR8_11_8)
 273#define GPSR8_1		F_(SDA0,		IP0SR8_7_4)
 274#define GPSR8_0		F_(SCL0,		IP0SR8_3_0)
 275
 276/* SR0 */
 277/* IP0SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 278#define IP0SR0_3_0	F_(0, 0)		FM(ERROROUTC_N_B)	FM(TCLK2_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279#define IP0SR0_7_4	F_(0, 0)		FM(MSIOF3_SS1)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280#define IP0SR0_11_8	F_(0, 0)		FM(MSIOF3_SS2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281#define IP0SR0_15_12	FM(IRQ3_A)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282#define IP0SR0_19_16	FM(IRQ2_A)		FM(MSIOF3_TXD)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283#define IP0SR0_23_20	FM(IRQ1_A)		FM(MSIOF3_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284#define IP0SR0_27_24	FM(IRQ0_A)		FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285#define IP0SR0_31_28	FM(MSIOF5_SS2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 286
 287/* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 288#define IP1SR0_3_0	FM(MSIOF5_SS1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289#define IP1SR0_7_4	FM(MSIOF5_SYNC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290#define IP1SR0_11_8	FM(MSIOF5_TXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291#define IP1SR0_15_12	FM(MSIOF5_SCK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292#define IP1SR0_19_16	FM(MSIOF5_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293#define IP1SR0_23_20	FM(MSIOF2_SS2)		FM(TCLK1_A)		FM(IRQ2_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294#define IP1SR0_27_24	FM(MSIOF2_SS1)		FM(HTX1_A)		FM(TX1_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295#define IP1SR0_31_28	FM(MSIOF2_SYNC)		FM(HRX1_A)		FM(RX1_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296
 297/* IP2SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 298#define IP2SR0_3_0	FM(MSIOF2_TXD)		FM(HCTS1_N_A)		FM(CTS1_N_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299#define IP2SR0_7_4	FM(MSIOF2_SCK)		FM(HRTS1_N_A)		FM(RTS1_N_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300#define IP2SR0_11_8	FM(MSIOF2_RXD)		FM(HSCK1_A)		FM(SCK1_A)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301
 302/* SR1 */
 303/* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 304#define IP0SR1_3_0	FM(MSIOF1_SS2)		FM(HTX3_B)		FM(TX3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305#define IP0SR1_7_4	FM(MSIOF1_SS1)		FM(HCTS3_N_B)		FM(RX3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306#define IP0SR1_11_8	FM(MSIOF1_SYNC)		FM(HRTS3_N_B)		FM(RTS3_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307#define IP0SR1_15_12	FM(MSIOF1_SCK)		FM(HSCK3_B)		FM(CTS3_N_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308#define IP0SR1_19_16	FM(MSIOF1_TXD)		FM(HRX3_B)		FM(SCK3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309#define IP0SR1_23_20	FM(MSIOF1_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310#define IP0SR1_27_24	FM(MSIOF0_SS2)		FM(HTX1_B)		FM(TX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311#define IP0SR1_31_28	FM(MSIOF0_SS1)		FM(HRX1_B)		FM(RX1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312
 313/* IP1SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 314#define IP1SR1_3_0	FM(MSIOF0_SYNC)		FM(HCTS1_N_B)		FM(CTS1_N_B)		FM(CANFD5_TX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315#define IP1SR1_7_4	FM(MSIOF0_TXD)		FM(HRTS1_N_B)		FM(RTS1_N_B)		FM(CANFD5_RX_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316#define IP1SR1_11_8	FM(MSIOF0_SCK)		FM(HSCK1_B)		FM(SCK1_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 317#define IP1SR1_15_12	FM(MSIOF0_RXD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 318#define IP1SR1_19_16	FM(HTX0)		FM(TX0)			F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319#define IP1SR1_23_20	FM(HCTS0_N)		FM(CTS0_N)		FM(PWM8)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320#define IP1SR1_27_24	FM(HRTS0_N)		FM(RTS0_N)		FM(PWM9)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321#define IP1SR1_31_28	FM(HSCK0)		FM(SCK0)		FM(PWM0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322
 323/* IP2SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 324#define IP2SR1_3_0	FM(HRX0)		FM(RX0)			F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325#define IP2SR1_7_4	FM(SCIF_CLK)		FM(IRQ4_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326#define IP2SR1_11_8	FM(SSI_SCK)		FM(TCLK3_B)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327#define IP2SR1_15_12	FM(SSI_WS)		FM(TCLK4_B)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328#define IP2SR1_19_16	FM(SSI_SD)		FM(IRQ0_B)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329#define IP2SR1_23_20	FM(AUDIO_CLKOUT)	FM(IRQ1_B)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330#define IP2SR1_27_24	FM(AUDIO_CLKIN)		FM(PWM3_A)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331#define IP2SR1_31_28	F_(0, 0)		FM(TCLK2_A)		FM(MSIOF4_SS1)		FM(IRQ3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332
 333/* IP3SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 334#define IP3SR1_3_0	FM(HRX3_A)		FM(SCK3_A)		FM(MSIOF4_SS2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335#define IP3SR1_7_4	FM(HSCK3_A)		FM(CTS3_N_A)		FM(MSIOF4_SCK)		FM(TPU0TO0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336#define IP3SR1_11_8	FM(HRTS3_N_A)		FM(RTS3_N_A)		FM(MSIOF4_TXD)		FM(TPU0TO1_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337#define IP3SR1_15_12	FM(HCTS3_N_A)		FM(RX3_A)		FM(MSIOF4_RXD)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338#define IP3SR1_19_16	FM(HTX3_A)		FM(TX3_A)		FM(MSIOF4_SYNC)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339
 340/* SR2 */
 341/* IP0SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 342#define IP0SR2_3_0	FM(FXR_TXDA)		FM(CANFD1_TX)		FM(TPU0TO2_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343#define IP0SR2_7_4	FM(FXR_TXENA_N_A)	FM(CANFD1_RX)		FM(TPU0TO3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344#define IP0SR2_11_8	FM(RXDA_EXTFXR)		FM(CANFD5_TX_A)		FM(IRQ5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345#define IP0SR2_15_12	FM(CLK_EXTFXR)		FM(CANFD5_RX_A)		FM(IRQ4_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346#define IP0SR2_19_16	FM(RXDB_EXTFXR)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347#define IP0SR2_23_20	FM(FXR_TXENB_N_A)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348#define IP0SR2_27_24	FM(FXR_TXDB)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349#define IP0SR2_31_28	FM(TPU0TO1_A)		FM(CANFD6_TX)		F_(0, 0)		FM(TCLK2_C)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350
 351/* IP1SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 352#define IP1SR2_3_0	FM(TPU0TO0_A)		FM(CANFD6_RX)		F_(0, 0)		FM(TCLK1_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 353#define IP1SR2_7_4	FM(CAN_CLK)		FM(FXR_TXENA_N_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 354#define IP1SR2_11_8	FM(CANFD0_TX)		FM(FXR_TXENB_N_B)	F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355#define IP1SR2_15_12	FM(CANFD0_RX)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356#define IP1SR2_19_16	FM(CANFD2_TX)		FM(TPU0TO2_A)		F_(0, 0)		FM(TCLK3_C)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357#define IP1SR2_23_20	FM(CANFD2_RX)		FM(TPU0TO3_A)		FM(PWM1_B)		FM(TCLK4_C)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358#define IP1SR2_27_24	FM(CANFD3_TX)		F_(0, 0)		FM(PWM2)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359#define IP1SR2_31_28	FM(CANFD3_RX)		F_(0, 0)		FM(PWM3_B)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360
 361/* IP2SR2 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 362#define IP2SR2_3_0	FM(CANFD4_TX)		F_(0, 0)		FM(PWM4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363#define IP2SR2_7_4	FM(CANFD4_RX)		F_(0, 0)		FM(PWM5)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 364#define IP2SR2_11_8	FM(CANFD7_TX)		F_(0, 0)		FM(PWM6)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 365#define IP2SR2_15_12	FM(CANFD7_RX)		F_(0, 0)		FM(PWM7)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 366
 367/* SR3 */
 368/* IP0SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 369#define IP0SR3_3_0	FM(MMC_SD_D1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 370#define IP0SR3_7_4	FM(MMC_SD_D0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 371#define IP0SR3_11_8	FM(MMC_SD_D2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 372#define IP0SR3_15_12	FM(MMC_SD_CLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 373#define IP0SR3_19_16	FM(MMC_DS)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 374#define IP0SR3_23_20	FM(MMC_SD_D3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 375#define IP0SR3_27_24	FM(MMC_D5)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 376#define IP0SR3_31_28	FM(MMC_D4)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 377
 378/* IP1SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 379#define IP1SR3_3_0	FM(MMC_D7)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 380#define IP1SR3_7_4	FM(MMC_D6)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 381#define IP1SR3_11_8	FM(MMC_SD_CMD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 382#define IP1SR3_15_12	FM(SD_CD)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 383#define IP1SR3_19_16	FM(SD_WP)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 384#define IP1SR3_23_20	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	FM(PWM1_A)		FM(TCLK3_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 385#define IP1SR3_27_24	FM(IPC_CLKOUT)		FM(IPC_CLKEN_OUT)	FM(ERROROUTC_N_A)	FM(TCLK4_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 386#define IP1SR3_31_28	FM(QSPI0_SSL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 387
 388/* IP2SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 389#define IP2SR3_3_0	FM(QSPI0_IO3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 390#define IP2SR3_7_4	FM(QSPI0_IO2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 391#define IP2SR3_11_8	FM(QSPI0_MISO_IO1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 392#define IP2SR3_15_12	FM(QSPI0_MOSI_IO0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 393#define IP2SR3_19_16	FM(QSPI0_SPCLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 394#define IP2SR3_23_20	FM(QSPI1_MOSI_IO0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 395#define IP2SR3_27_24	FM(QSPI1_SPCLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 396#define IP2SR3_31_28	FM(QSPI1_MISO_IO1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 397
 398/* IP3SR3 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 399#define IP3SR3_3_0	FM(QSPI1_IO2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 400#define IP3SR3_7_4	FM(QSPI1_SSL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 401#define IP3SR3_11_8	FM(QSPI1_IO3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 402#define IP3SR3_15_12	FM(RPC_RESET_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 403#define IP3SR3_19_16	FM(RPC_WP_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 404#define IP3SR3_23_20	FM(RPC_INT_N)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 405
 406/* SR4 */
 407/* IP0SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 408#define IP0SR4_3_0	FM(TSN0_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 409#define IP0SR4_7_4	FM(TSN0_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 410#define IP0SR4_11_8	FM(TSN0_AVTP_PPS1)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 411#define IP0SR4_15_12	FM(TSN0_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 412#define IP0SR4_19_16	FM(TSN0_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 413#define IP0SR4_23_20	FM(TSN0_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 414#define IP0SR4_27_24	FM(TSN0_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 415#define IP0SR4_31_28	FM(TSN0_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 416
 417/* IP1SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 418#define IP1SR4_3_0	FM(TSN0_AVTP_PPS0)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 419#define IP1SR4_7_4	FM(TSN0_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 420#define IP1SR4_11_8	FM(TSN0_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 421#define IP1SR4_15_12	FM(TSN0_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 422#define IP1SR4_19_16	FM(TSN0_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 423#define IP1SR4_23_20	FM(TSN0_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 424#define IP1SR4_27_24	FM(TSN0_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 425#define IP1SR4_31_28	FM(TSN0_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 426
 427/* IP2SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 428#define IP2SR4_3_0	FM(TSN0_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 429#define IP2SR4_7_4	FM(TSN0_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 430#define IP2SR4_11_8	FM(TSN0_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 431#define IP2SR4_15_12	FM(TSN0_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 432#define IP2SR4_19_16	FM(TSN0_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 433#define IP2SR4_23_20	FM(PCIE0_CLKREQ_N)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 434#define IP2SR4_27_24	FM(PCIE1_CLKREQ_N)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 435#define IP2SR4_31_28	FM(AVS0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 436
 437/* IP3SR4 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 438#define IP3SR4_3_0	FM(AVS1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 439
 440/* SR5 */
 441/* IP0SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 442#define IP0SR5_3_0	FM(AVB2_AVTP_PPS)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 443#define IP0SR5_7_4	FM(AVB2_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 444#define IP0SR5_11_8	FM(AVB2_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 445#define IP0SR5_15_12	FM(AVB2_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 446#define IP0SR5_19_16	FM(AVB2_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 447#define IP0SR5_23_20	FM(AVB2_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 448#define IP0SR5_27_24	FM(AVB2_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 449#define IP0SR5_31_28	FM(AVB2_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 450
 451/* IP1SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 452#define IP1SR5_3_0	FM(AVB2_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 453#define IP1SR5_7_4	FM(AVB2_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 454#define IP1SR5_11_8	FM(AVB2_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 455#define IP1SR5_15_12	FM(AVB2_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 456#define IP1SR5_19_16	FM(AVB2_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 457#define IP1SR5_23_20	FM(AVB2_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 458#define IP1SR5_27_24	FM(AVB2_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 459#define IP1SR5_31_28	FM(AVB2_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 460
 461/* IP2SR5 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 462#define IP2SR5_3_0	FM(AVB2_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 463#define IP2SR5_7_4	FM(AVB2_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 464#define IP2SR5_11_8	FM(AVB2_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 465#define IP2SR5_15_12	FM(AVB2_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 466#define IP2SR5_19_16	FM(AVB2_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 467
 468/* SR6 */
 469/* IP0SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 470#define IP0SR6_3_0	FM(AVB1_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 471#define IP0SR6_7_4	FM(AVB1_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 472#define IP0SR6_11_8	FM(AVB1_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 473#define IP0SR6_15_12	FM(AVB1_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 474#define IP0SR6_19_16	FM(AVB1_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 475#define IP0SR6_23_20	FM(AVB1_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 476#define IP0SR6_27_24	FM(AVB1_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 477#define IP0SR6_31_28	FM(AVB1_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 478
 479/* IP1SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 480#define IP1SR6_3_0	FM(AVB1_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 481#define IP1SR6_7_4	FM(AVB1_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 482#define IP1SR6_11_8	FM(AVB1_AVTP_PPS)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 483#define IP1SR6_15_12	FM(AVB1_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 484#define IP1SR6_19_16	FM(AVB1_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 485#define IP1SR6_23_20	FM(AVB1_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 486#define IP1SR6_27_24	FM(AVB1_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 487#define IP1SR6_31_28	FM(AVB1_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 488
 489/* IP2SR6 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 490#define IP2SR6_3_0	FM(AVB1_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 491#define IP2SR6_7_4	FM(AVB1_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 492#define IP2SR6_11_8	FM(AVB1_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 493#define IP2SR6_15_12	FM(AVB1_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 494#define IP2SR6_19_16	FM(AVB1_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 495
 496/* SR7 */
 497/* IP0SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 498#define IP0SR7_3_0	FM(AVB0_AVTP_PPS)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 499#define IP0SR7_7_4	FM(AVB0_AVTP_CAPTURE)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 500#define IP0SR7_11_8	FM(AVB0_AVTP_MATCH)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 501#define IP0SR7_15_12	FM(AVB0_TD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 502#define IP0SR7_19_16	FM(AVB0_LINK)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 503#define IP0SR7_23_20	FM(AVB0_PHY_INT)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 504#define IP0SR7_27_24	FM(AVB0_TD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 505#define IP0SR7_31_28	FM(AVB0_TD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 506
 507/* IP1SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 508#define IP1SR7_3_0	FM(AVB0_RD3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 509#define IP1SR7_7_4	FM(AVB0_TXCREFCLK)	F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 510#define IP1SR7_11_8	FM(AVB0_MAGIC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 511#define IP1SR7_15_12	FM(AVB0_TD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 512#define IP1SR7_19_16	FM(AVB0_RD2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 513#define IP1SR7_23_20	FM(AVB0_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 514#define IP1SR7_27_24	FM(AVB0_MDIO)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 515#define IP1SR7_31_28	FM(AVB0_TXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 516
 517/* IP2SR7 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 518#define IP2SR7_3_0	FM(AVB0_TX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 519#define IP2SR7_7_4	FM(AVB0_RD1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 520#define IP2SR7_11_8	FM(AVB0_RD0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 521#define IP2SR7_15_12	FM(AVB0_RXC)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 522#define IP2SR7_19_16	FM(AVB0_RX_CTL)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 523
 524/* SR8 */
 525/* IP0SR8 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 526#define IP0SR8_3_0	FM(SCL0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 527#define IP0SR8_7_4	FM(SDA0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 528#define IP0SR8_11_8	FM(SCL1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 529#define IP0SR8_15_12	FM(SDA1)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 530#define IP0SR8_19_16	FM(SCL2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 531#define IP0SR8_23_20	FM(SDA2)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 532#define IP0SR8_27_24	FM(SCL3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 533#define IP0SR8_31_28	FM(SDA3)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 534
 535/* IP1SR8 */		/* 0 */			/* 1 */			/* 2 */			/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
 536#define IP1SR8_3_0	FM(SCL4)		FM(HRX2)		FM(SCK4)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 537#define IP1SR8_7_4	FM(SDA4)		FM(HTX2)		FM(CTS4_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 538#define IP1SR8_11_8	FM(SCL5)		FM(HRTS2_N)		FM(RTS4_N)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 539#define IP1SR8_15_12	FM(SDA5)		FM(SCIF_CLK2)		F_(0, 0)		F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 540#define IP1SR8_19_16	F_(0, 0)		FM(HCTS2_N)		FM(TX4)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 541#define IP1SR8_23_20	F_(0, 0)		FM(HSCK2)		FM(RX4)			F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 542
 543#define PINMUX_GPSR	\
 544						GPSR3_29											\
 545		GPSR1_28			GPSR3_28											\
 546		GPSR1_27			GPSR3_27											\
 547		GPSR1_26			GPSR3_26											\
 548		GPSR1_25			GPSR3_25											\
 549		GPSR1_24			GPSR3_24	GPSR4_24									\
 550		GPSR1_23			GPSR3_23	GPSR4_23									\
 551		GPSR1_22			GPSR3_22	GPSR4_22									\
 552		GPSR1_21			GPSR3_21	GPSR4_21									\
 553		GPSR1_20			GPSR3_20	GPSR4_20	GPSR5_20	GPSR6_20	GPSR7_20			\
 554		GPSR1_19	GPSR2_19	GPSR3_19	GPSR4_19	GPSR5_19	GPSR6_19	GPSR7_19			\
 555GPSR0_18	GPSR1_18	GPSR2_18	GPSR3_18	GPSR4_18	GPSR5_18	GPSR6_18	GPSR7_18			\
 556GPSR0_17	GPSR1_17	GPSR2_17	GPSR3_17	GPSR4_17	GPSR5_17	GPSR6_17	GPSR7_17			\
 557GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16	GPSR5_16	GPSR6_16	GPSR7_16			\
 558GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15	GPSR7_15			\
 559GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14	GPSR7_14			\
 560GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13	GPSR7_13	GPSR8_13	\
 561GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12	GPSR7_12	GPSR8_12	\
 562GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11	GPSR7_11	GPSR8_11	\
 563GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10	GPSR7_10	GPSR8_10	\
 564GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9		GPSR7_9		GPSR8_9		\
 565GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8		GPSR7_8		GPSR8_8		\
 566GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7		GPSR7_7		GPSR8_7		\
 567GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6		GPSR7_6		GPSR8_6		\
 568GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5		GPSR7_5		GPSR8_5		\
 569GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4		GPSR7_4		GPSR8_4		\
 570GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3		GPSR8_3		\
 571GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2		GPSR8_2		\
 572GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1		GPSR8_1		\
 573GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0		GPSR8_0
 574
 575#define PINMUX_IPSR	\
 576\
 577FM(IP0SR0_3_0)		IP0SR0_3_0	FM(IP1SR0_3_0)		IP1SR0_3_0	FM(IP2SR0_3_0)		IP2SR0_3_0	\
 578FM(IP0SR0_7_4)		IP0SR0_7_4	FM(IP1SR0_7_4)		IP1SR0_7_4	FM(IP2SR0_7_4)		IP2SR0_7_4	\
 579FM(IP0SR0_11_8)		IP0SR0_11_8	FM(IP1SR0_11_8)		IP1SR0_11_8	FM(IP2SR0_11_8)		IP2SR0_11_8	\
 580FM(IP0SR0_15_12)	IP0SR0_15_12	FM(IP1SR0_15_12)	IP1SR0_15_12	\
 581FM(IP0SR0_19_16)	IP0SR0_19_16	FM(IP1SR0_19_16)	IP1SR0_19_16	\
 582FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	\
 583FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	\
 584FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	\
 585\
 586FM(IP0SR1_3_0)		IP0SR1_3_0	FM(IP1SR1_3_0)		IP1SR1_3_0	FM(IP2SR1_3_0)		IP2SR1_3_0	FM(IP3SR1_3_0)		IP3SR1_3_0	\
 587FM(IP0SR1_7_4)		IP0SR1_7_4	FM(IP1SR1_7_4)		IP1SR1_7_4	FM(IP2SR1_7_4)		IP2SR1_7_4	FM(IP3SR1_7_4)		IP3SR1_7_4	\
 588FM(IP0SR1_11_8)		IP0SR1_11_8	FM(IP1SR1_11_8)		IP1SR1_11_8	FM(IP2SR1_11_8)		IP2SR1_11_8	FM(IP3SR1_11_8)		IP3SR1_11_8	\
 589FM(IP0SR1_15_12)	IP0SR1_15_12	FM(IP1SR1_15_12)	IP1SR1_15_12	FM(IP2SR1_15_12)	IP2SR1_15_12	FM(IP3SR1_15_12)	IP3SR1_15_12	\
 590FM(IP0SR1_19_16)	IP0SR1_19_16	FM(IP1SR1_19_16)	IP1SR1_19_16	FM(IP2SR1_19_16)	IP2SR1_19_16	FM(IP3SR1_19_16)	IP3SR1_19_16	\
 591FM(IP0SR1_23_20)	IP0SR1_23_20	FM(IP1SR1_23_20)	IP1SR1_23_20	FM(IP2SR1_23_20)	IP2SR1_23_20	\
 592FM(IP0SR1_27_24)	IP0SR1_27_24	FM(IP1SR1_27_24)	IP1SR1_27_24	FM(IP2SR1_27_24)	IP2SR1_27_24	\
 593FM(IP0SR1_31_28)	IP0SR1_31_28	FM(IP1SR1_31_28)	IP1SR1_31_28	FM(IP2SR1_31_28)	IP2SR1_31_28	\
 594\
 595FM(IP0SR2_3_0)		IP0SR2_3_0	FM(IP1SR2_3_0)		IP1SR2_3_0	FM(IP2SR2_3_0)		IP2SR2_3_0	\
 596FM(IP0SR2_7_4)		IP0SR2_7_4	FM(IP1SR2_7_4)		IP1SR2_7_4	FM(IP2SR2_7_4)		IP2SR2_7_4	\
 597FM(IP0SR2_11_8)		IP0SR2_11_8	FM(IP1SR2_11_8)		IP1SR2_11_8	FM(IP2SR2_11_8)		IP2SR2_11_8	\
 598FM(IP0SR2_15_12)	IP0SR2_15_12	FM(IP1SR2_15_12)	IP1SR2_15_12	FM(IP2SR2_15_12)	IP2SR2_15_12	\
 599FM(IP0SR2_19_16)	IP0SR2_19_16	FM(IP1SR2_19_16)	IP1SR2_19_16	\
 600FM(IP0SR2_23_20)	IP0SR2_23_20	FM(IP1SR2_23_20)	IP1SR2_23_20	\
 601FM(IP0SR2_27_24)	IP0SR2_27_24	FM(IP1SR2_27_24)	IP1SR2_27_24	\
 602FM(IP0SR2_31_28)	IP0SR2_31_28	FM(IP1SR2_31_28)	IP1SR2_31_28	\
 603\
 604FM(IP0SR3_3_0)		IP0SR3_3_0	FM(IP1SR3_3_0)		IP1SR3_3_0	FM(IP2SR3_3_0)		IP2SR3_3_0	FM(IP3SR3_3_0)		IP3SR3_3_0	\
 605FM(IP0SR3_7_4)		IP0SR3_7_4	FM(IP1SR3_7_4)		IP1SR3_7_4	FM(IP2SR3_7_4)		IP2SR3_7_4	FM(IP3SR3_7_4)		IP3SR3_7_4	\
 606FM(IP0SR3_11_8)		IP0SR3_11_8	FM(IP1SR3_11_8)		IP1SR3_11_8	FM(IP2SR3_11_8)		IP2SR3_11_8	FM(IP3SR3_11_8)		IP3SR3_11_8	\
 607FM(IP0SR3_15_12)	IP0SR3_15_12	FM(IP1SR3_15_12)	IP1SR3_15_12	FM(IP2SR3_15_12)	IP2SR3_15_12	FM(IP3SR3_15_12)	IP3SR3_15_12	\
 608FM(IP0SR3_19_16)	IP0SR3_19_16	FM(IP1SR3_19_16)	IP1SR3_19_16	FM(IP2SR3_19_16)	IP2SR3_19_16	FM(IP3SR3_19_16)	IP3SR3_19_16	\
 609FM(IP0SR3_23_20)	IP0SR3_23_20	FM(IP1SR3_23_20)	IP1SR3_23_20	FM(IP2SR3_23_20)	IP2SR3_23_20	FM(IP3SR3_23_20)	IP3SR3_23_20	\
 610FM(IP0SR3_27_24)	IP0SR3_27_24	FM(IP1SR3_27_24)	IP1SR3_27_24	FM(IP2SR3_27_24)	IP2SR3_27_24						\
 611FM(IP0SR3_31_28)	IP0SR3_31_28	FM(IP1SR3_31_28)	IP1SR3_31_28	FM(IP2SR3_31_28)	IP2SR3_31_28						\
 612\
 613FM(IP0SR4_3_0)		IP0SR4_3_0	FM(IP1SR4_3_0)		IP1SR4_3_0	FM(IP2SR4_3_0)		IP2SR4_3_0	FM(IP3SR4_3_0)		IP3SR4_3_0	\
 614FM(IP0SR4_7_4)		IP0SR4_7_4	FM(IP1SR4_7_4)		IP1SR4_7_4	FM(IP2SR4_7_4)		IP2SR4_7_4	\
 615FM(IP0SR4_11_8)		IP0SR4_11_8	FM(IP1SR4_11_8)		IP1SR4_11_8	FM(IP2SR4_11_8)		IP2SR4_11_8	\
 616FM(IP0SR4_15_12)	IP0SR4_15_12	FM(IP1SR4_15_12)	IP1SR4_15_12	FM(IP2SR4_15_12)	IP2SR4_15_12	\
 617FM(IP0SR4_19_16)	IP0SR4_19_16	FM(IP1SR4_19_16)	IP1SR4_19_16	FM(IP2SR4_19_16)	IP2SR4_19_16	\
 618FM(IP0SR4_23_20)	IP0SR4_23_20	FM(IP1SR4_23_20)	IP1SR4_23_20	FM(IP2SR4_23_20)	IP2SR4_23_20	\
 619FM(IP0SR4_27_24)	IP0SR4_27_24	FM(IP1SR4_27_24)	IP1SR4_27_24	FM(IP2SR4_27_24)	IP2SR4_27_24	\
 620FM(IP0SR4_31_28)	IP0SR4_31_28	FM(IP1SR4_31_28)	IP1SR4_31_28	FM(IP2SR4_31_28)	IP2SR4_31_28	\
 621\
 622FM(IP0SR5_3_0)		IP0SR5_3_0	FM(IP1SR5_3_0)		IP1SR5_3_0	FM(IP2SR5_3_0)		IP2SR5_3_0	\
 623FM(IP0SR5_7_4)		IP0SR5_7_4	FM(IP1SR5_7_4)		IP1SR5_7_4	FM(IP2SR5_7_4)		IP2SR5_7_4	\
 624FM(IP0SR5_11_8)		IP0SR5_11_8	FM(IP1SR5_11_8)		IP1SR5_11_8	FM(IP2SR5_11_8)		IP2SR5_11_8	\
 625FM(IP0SR5_15_12)	IP0SR5_15_12	FM(IP1SR5_15_12)	IP1SR5_15_12	FM(IP2SR5_15_12)	IP2SR5_15_12	\
 626FM(IP0SR5_19_16)	IP0SR5_19_16	FM(IP1SR5_19_16)	IP1SR5_19_16	FM(IP2SR5_19_16)	IP2SR5_19_16	\
 627FM(IP0SR5_23_20)	IP0SR5_23_20	FM(IP1SR5_23_20)	IP1SR5_23_20	\
 628FM(IP0SR5_27_24)	IP0SR5_27_24	FM(IP1SR5_27_24)	IP1SR5_27_24	\
 629FM(IP0SR5_31_28)	IP0SR5_31_28	FM(IP1SR5_31_28)	IP1SR5_31_28	\
 630\
 631FM(IP0SR6_3_0)		IP0SR6_3_0	FM(IP1SR6_3_0)		IP1SR6_3_0	FM(IP2SR6_3_0)		IP2SR6_3_0	\
 632FM(IP0SR6_7_4)		IP0SR6_7_4	FM(IP1SR6_7_4)		IP1SR6_7_4	FM(IP2SR6_7_4)		IP2SR6_7_4	\
 633FM(IP0SR6_11_8)		IP0SR6_11_8	FM(IP1SR6_11_8)		IP1SR6_11_8	FM(IP2SR6_11_8)		IP2SR6_11_8	\
 634FM(IP0SR6_15_12)	IP0SR6_15_12	FM(IP1SR6_15_12)	IP1SR6_15_12	FM(IP2SR6_15_12)	IP2SR6_15_12	\
 635FM(IP0SR6_19_16)	IP0SR6_19_16	FM(IP1SR6_19_16)	IP1SR6_19_16	FM(IP2SR6_19_16)	IP2SR6_19_16	\
 636FM(IP0SR6_23_20)	IP0SR6_23_20	FM(IP1SR6_23_20)	IP1SR6_23_20	\
 637FM(IP0SR6_27_24)	IP0SR6_27_24	FM(IP1SR6_27_24)	IP1SR6_27_24	\
 638FM(IP0SR6_31_28)	IP0SR6_31_28	FM(IP1SR6_31_28)	IP1SR6_31_28	\
 639\
 640FM(IP0SR7_3_0)		IP0SR7_3_0	FM(IP1SR7_3_0)		IP1SR7_3_0	FM(IP2SR7_3_0)		IP2SR7_3_0	\
 641FM(IP0SR7_7_4)		IP0SR7_7_4	FM(IP1SR7_7_4)		IP1SR7_7_4	FM(IP2SR7_7_4)		IP2SR7_7_4	\
 642FM(IP0SR7_11_8)		IP0SR7_11_8	FM(IP1SR7_11_8)		IP1SR7_11_8	FM(IP2SR7_11_8)		IP2SR7_11_8	\
 643FM(IP0SR7_15_12)	IP0SR7_15_12	FM(IP1SR7_15_12)	IP1SR7_15_12	FM(IP2SR7_15_12)	IP2SR7_15_12	\
 644FM(IP0SR7_19_16)	IP0SR7_19_16	FM(IP1SR7_19_16)	IP1SR7_19_16	FM(IP2SR7_19_16)	IP2SR7_19_16	\
 645FM(IP0SR7_23_20)	IP0SR7_23_20	FM(IP1SR7_23_20)	IP1SR7_23_20	\
 646FM(IP0SR7_27_24)	IP0SR7_27_24	FM(IP1SR7_27_24)	IP1SR7_27_24	\
 647FM(IP0SR7_31_28)	IP0SR7_31_28	FM(IP1SR7_31_28)	IP1SR7_31_28	\
 648\
 649FM(IP0SR8_3_0)		IP0SR8_3_0	FM(IP1SR8_3_0)		IP1SR8_3_0	\
 650FM(IP0SR8_7_4)		IP0SR8_7_4	FM(IP1SR8_7_4)		IP1SR8_7_4	\
 651FM(IP0SR8_11_8)		IP0SR8_11_8	FM(IP1SR8_11_8)		IP1SR8_11_8	\
 652FM(IP0SR8_15_12)	IP0SR8_15_12	FM(IP1SR8_15_12)	IP1SR8_15_12	\
 653FM(IP0SR8_19_16)	IP0SR8_19_16	FM(IP1SR8_19_16)	IP1SR8_19_16	\
 654FM(IP0SR8_23_20)	IP0SR8_23_20	FM(IP1SR8_23_20)	IP1SR8_23_20	\
 655FM(IP0SR8_27_24)	IP0SR8_27_24	\
 656FM(IP0SR8_31_28)	IP0SR8_31_28
 657
 658/* MOD_SEL8 */			/* 0 */				/* 1 */
 659#define MOD_SEL8_11		FM(SEL_SDA5_0)			FM(SEL_SDA5_1)
 660#define MOD_SEL8_10		FM(SEL_SCL5_0)			FM(SEL_SCL5_1)
 661#define MOD_SEL8_9		FM(SEL_SDA4_0)			FM(SEL_SDA4_1)
 662#define MOD_SEL8_8		FM(SEL_SCL4_0)			FM(SEL_SCL4_1)
 663#define MOD_SEL8_7		FM(SEL_SDA3_0)			FM(SEL_SDA3_1)
 664#define MOD_SEL8_6		FM(SEL_SCL3_0)			FM(SEL_SCL3_1)
 665#define MOD_SEL8_5		FM(SEL_SDA2_0)			FM(SEL_SDA2_1)
 666#define MOD_SEL8_4		FM(SEL_SCL2_0)			FM(SEL_SCL2_1)
 667#define MOD_SEL8_3		FM(SEL_SDA1_0)			FM(SEL_SDA1_1)
 668#define MOD_SEL8_2		FM(SEL_SCL1_0)			FM(SEL_SCL1_1)
 669#define MOD_SEL8_1		FM(SEL_SDA0_0)			FM(SEL_SDA0_1)
 670#define MOD_SEL8_0		FM(SEL_SCL0_0)			FM(SEL_SCL0_1)
 671
 672#define PINMUX_MOD_SELS \
 673\
 674MOD_SEL8_11	\
 675MOD_SEL8_10	\
 676MOD_SEL8_9	\
 677MOD_SEL8_8	\
 678MOD_SEL8_7	\
 679MOD_SEL8_6	\
 680MOD_SEL8_5	\
 681MOD_SEL8_4	\
 682MOD_SEL8_3	\
 683MOD_SEL8_2	\
 684MOD_SEL8_1	\
 685MOD_SEL8_0
 686
 687enum {
 688	PINMUX_RESERVED = 0,
 689
 690	PINMUX_DATA_BEGIN,
 691	GP_ALL(DATA),
 692	PINMUX_DATA_END,
 693
 694#define F_(x, y)
 695#define FM(x)   FN_##x,
 696	PINMUX_FUNCTION_BEGIN,
 697	GP_ALL(FN),
 698	PINMUX_GPSR
 699	PINMUX_IPSR
 700	PINMUX_MOD_SELS
 701	PINMUX_FUNCTION_END,
 702#undef F_
 703#undef FM
 704
 705#define F_(x, y)
 706#define FM(x)	x##_MARK,
 707	PINMUX_MARK_BEGIN,
 708	PINMUX_GPSR
 709	PINMUX_IPSR
 710	PINMUX_MOD_SELS
 711	PINMUX_MARK_END,
 712#undef F_
 713#undef FM
 714};
 715
 716static const u16 pinmux_data[] = {
 717	PINMUX_DATA_GP_ALL(),
 718
 719	/* IP0SR0 */
 720	PINMUX_IPSR_GPSR(IP0SR0_3_0,	ERROROUTC_N_B),
 721	PINMUX_IPSR_GPSR(IP0SR0_3_0,	TCLK2_B),
 722
 723	PINMUX_IPSR_GPSR(IP0SR0_7_4,	MSIOF3_SS1),
 724
 725	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_SS2),
 726
 727	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3_A),
 728	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_SCK),
 729
 730	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2_A),
 731	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_TXD),
 732
 733	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1_A),
 734	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_RXD),
 735
 736	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0_A),
 737	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF3_SYNC),
 738
 739	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF5_SS2),
 740
 741	/* IP1SR0 */
 742	PINMUX_IPSR_GPSR(IP1SR0_3_0,	MSIOF5_SS1),
 743
 744	PINMUX_IPSR_GPSR(IP1SR0_7_4,	MSIOF5_SYNC),
 745
 746	PINMUX_IPSR_GPSR(IP1SR0_11_8,	MSIOF5_TXD),
 747
 748	PINMUX_IPSR_GPSR(IP1SR0_15_12,	MSIOF5_SCK),
 749
 750	PINMUX_IPSR_GPSR(IP1SR0_19_16,	MSIOF5_RXD),
 751
 752	PINMUX_IPSR_GPSR(IP1SR0_23_20,	MSIOF2_SS2),
 753	PINMUX_IPSR_GPSR(IP1SR0_23_20,	TCLK1_A),
 754	PINMUX_IPSR_GPSR(IP1SR0_23_20,	IRQ2_B),
 755
 756	PINMUX_IPSR_GPSR(IP1SR0_27_24,	MSIOF2_SS1),
 757	PINMUX_IPSR_GPSR(IP1SR0_27_24,	HTX1_A),
 758	PINMUX_IPSR_GPSR(IP1SR0_27_24,	TX1_A),
 759
 760	PINMUX_IPSR_GPSR(IP1SR0_31_28,	MSIOF2_SYNC),
 761	PINMUX_IPSR_GPSR(IP1SR0_31_28,	HRX1_A),
 762	PINMUX_IPSR_GPSR(IP1SR0_31_28,	RX1_A),
 763
 764	/* IP2SR0 */
 765	PINMUX_IPSR_GPSR(IP2SR0_3_0,	MSIOF2_TXD),
 766	PINMUX_IPSR_GPSR(IP2SR0_3_0,	HCTS1_N_A),
 767	PINMUX_IPSR_GPSR(IP2SR0_3_0,	CTS1_N_A),
 768
 769	PINMUX_IPSR_GPSR(IP2SR0_7_4,	MSIOF2_SCK),
 770	PINMUX_IPSR_GPSR(IP2SR0_7_4,	HRTS1_N_A),
 771	PINMUX_IPSR_GPSR(IP2SR0_7_4,	RTS1_N_A),
 772
 773	PINMUX_IPSR_GPSR(IP2SR0_11_8,	MSIOF2_RXD),
 774	PINMUX_IPSR_GPSR(IP2SR0_11_8,	HSCK1_A),
 775	PINMUX_IPSR_GPSR(IP2SR0_11_8,	SCK1_A),
 776
 777	/* IP0SR1 */
 778	PINMUX_IPSR_GPSR(IP0SR1_3_0,	MSIOF1_SS2),
 779	PINMUX_IPSR_GPSR(IP0SR1_3_0,	HTX3_B),
 780	PINMUX_IPSR_GPSR(IP0SR1_3_0,	TX3_B),
 781
 782	PINMUX_IPSR_GPSR(IP0SR1_7_4,	MSIOF1_SS1),
 783	PINMUX_IPSR_GPSR(IP0SR1_7_4,	HCTS3_N_B),
 784	PINMUX_IPSR_GPSR(IP0SR1_7_4,	RX3_B),
 785
 786	PINMUX_IPSR_GPSR(IP0SR1_11_8,	MSIOF1_SYNC),
 787	PINMUX_IPSR_GPSR(IP0SR1_11_8,	HRTS3_N_B),
 788	PINMUX_IPSR_GPSR(IP0SR1_11_8,	RTS3_N_B),
 789
 790	PINMUX_IPSR_GPSR(IP0SR1_15_12,	MSIOF1_SCK),
 791	PINMUX_IPSR_GPSR(IP0SR1_15_12,	HSCK3_B),
 792	PINMUX_IPSR_GPSR(IP0SR1_15_12,	CTS3_N_B),
 793
 794	PINMUX_IPSR_GPSR(IP0SR1_19_16,	MSIOF1_TXD),
 795	PINMUX_IPSR_GPSR(IP0SR1_19_16,	HRX3_B),
 796	PINMUX_IPSR_GPSR(IP0SR1_19_16,	SCK3_B),
 797
 798	PINMUX_IPSR_GPSR(IP0SR1_23_20,	MSIOF1_RXD),
 799
 800	PINMUX_IPSR_GPSR(IP0SR1_27_24,	MSIOF0_SS2),
 801	PINMUX_IPSR_GPSR(IP0SR1_27_24,	HTX1_B),
 802	PINMUX_IPSR_GPSR(IP0SR1_27_24,	TX1_B),
 803
 804	PINMUX_IPSR_GPSR(IP0SR1_31_28,	MSIOF0_SS1),
 805	PINMUX_IPSR_GPSR(IP0SR1_31_28,	HRX1_B),
 806	PINMUX_IPSR_GPSR(IP0SR1_31_28,	RX1_B),
 807
 808	/* IP1SR1 */
 809	PINMUX_IPSR_GPSR(IP1SR1_3_0,	MSIOF0_SYNC),
 810	PINMUX_IPSR_GPSR(IP1SR1_3_0,	HCTS1_N_B),
 811	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CTS1_N_B),
 812	PINMUX_IPSR_GPSR(IP1SR1_3_0,	CANFD5_TX_B),
 813
 814	PINMUX_IPSR_GPSR(IP1SR1_7_4,	MSIOF0_TXD),
 815	PINMUX_IPSR_GPSR(IP1SR1_7_4,	HRTS1_N_B),
 816	PINMUX_IPSR_GPSR(IP1SR1_7_4,	RTS1_N_B),
 817	PINMUX_IPSR_GPSR(IP1SR1_7_4,	CANFD5_RX_B),
 818
 819	PINMUX_IPSR_GPSR(IP1SR1_11_8,	MSIOF0_SCK),
 820	PINMUX_IPSR_GPSR(IP1SR1_11_8,	HSCK1_B),
 821	PINMUX_IPSR_GPSR(IP1SR1_11_8,	SCK1_B),
 822
 823	PINMUX_IPSR_GPSR(IP1SR1_15_12,	MSIOF0_RXD),
 824
 825	PINMUX_IPSR_GPSR(IP1SR1_19_16,	HTX0),
 826	PINMUX_IPSR_GPSR(IP1SR1_19_16,	TX0),
 827
 828	PINMUX_IPSR_GPSR(IP1SR1_23_20,	HCTS0_N),
 829	PINMUX_IPSR_GPSR(IP1SR1_23_20,	CTS0_N),
 830	PINMUX_IPSR_GPSR(IP1SR1_23_20,	PWM8),
 831
 832	PINMUX_IPSR_GPSR(IP1SR1_27_24,	HRTS0_N),
 833	PINMUX_IPSR_GPSR(IP1SR1_27_24,	RTS0_N),
 834	PINMUX_IPSR_GPSR(IP1SR1_27_24,	PWM9),
 835
 836	PINMUX_IPSR_GPSR(IP1SR1_31_28,	HSCK0),
 837	PINMUX_IPSR_GPSR(IP1SR1_31_28,	SCK0),
 838	PINMUX_IPSR_GPSR(IP1SR1_31_28,	PWM0),
 839
 840	/* IP2SR1 */
 841	PINMUX_IPSR_GPSR(IP2SR1_3_0,	HRX0),
 842	PINMUX_IPSR_GPSR(IP2SR1_3_0,	RX0),
 843
 844	PINMUX_IPSR_GPSR(IP2SR1_7_4,	SCIF_CLK),
 845	PINMUX_IPSR_GPSR(IP2SR1_7_4,	IRQ4_A),
 846
 847	PINMUX_IPSR_GPSR(IP2SR1_11_8,	SSI_SCK),
 848	PINMUX_IPSR_GPSR(IP2SR1_11_8,	TCLK3_B),
 849
 850	PINMUX_IPSR_GPSR(IP2SR1_15_12,	SSI_WS),
 851	PINMUX_IPSR_GPSR(IP2SR1_15_12,	TCLK4_B),
 852
 853	PINMUX_IPSR_GPSR(IP2SR1_19_16,	SSI_SD),
 854	PINMUX_IPSR_GPSR(IP2SR1_19_16,	IRQ0_B),
 855
 856	PINMUX_IPSR_GPSR(IP2SR1_23_20,	AUDIO_CLKOUT),
 857	PINMUX_IPSR_GPSR(IP2SR1_23_20,	IRQ1_B),
 858
 859	PINMUX_IPSR_GPSR(IP2SR1_27_24,	AUDIO_CLKIN),
 860	PINMUX_IPSR_GPSR(IP2SR1_27_24,	PWM3_A),
 861
 862	PINMUX_IPSR_GPSR(IP2SR1_31_28,	TCLK2_A),
 863	PINMUX_IPSR_GPSR(IP2SR1_31_28,	MSIOF4_SS1),
 864	PINMUX_IPSR_GPSR(IP2SR1_31_28,	IRQ3_B),
 865
 866	/* IP3SR1 */
 867	PINMUX_IPSR_GPSR(IP3SR1_3_0,	HRX3_A),
 868	PINMUX_IPSR_GPSR(IP3SR1_3_0,	SCK3_A),
 869	PINMUX_IPSR_GPSR(IP3SR1_3_0,	MSIOF4_SS2),
 870
 871	PINMUX_IPSR_GPSR(IP3SR1_7_4,	HSCK3_A),
 872	PINMUX_IPSR_GPSR(IP3SR1_7_4,	CTS3_N_A),
 873	PINMUX_IPSR_GPSR(IP3SR1_7_4,	MSIOF4_SCK),
 874	PINMUX_IPSR_GPSR(IP3SR1_7_4,	TPU0TO0_B),
 875
 876	PINMUX_IPSR_GPSR(IP3SR1_11_8,	HRTS3_N_A),
 877	PINMUX_IPSR_GPSR(IP3SR1_11_8,	RTS3_N_A),
 878	PINMUX_IPSR_GPSR(IP3SR1_11_8,	MSIOF4_TXD),
 879	PINMUX_IPSR_GPSR(IP3SR1_11_8,	TPU0TO1_B),
 880
 881	PINMUX_IPSR_GPSR(IP3SR1_15_12,	HCTS3_N_A),
 882	PINMUX_IPSR_GPSR(IP3SR1_15_12,	RX3_A),
 883	PINMUX_IPSR_GPSR(IP3SR1_15_12,	MSIOF4_RXD),
 884
 885	PINMUX_IPSR_GPSR(IP3SR1_19_16,	HTX3_A),
 886	PINMUX_IPSR_GPSR(IP3SR1_19_16,	TX3_A),
 887	PINMUX_IPSR_GPSR(IP3SR1_19_16,	MSIOF4_SYNC),
 888
 889	/* IP0SR2 */
 890	PINMUX_IPSR_GPSR(IP0SR2_3_0,	FXR_TXDA),
 891	PINMUX_IPSR_GPSR(IP0SR2_3_0,	CANFD1_TX),
 892	PINMUX_IPSR_GPSR(IP0SR2_3_0,	TPU0TO2_B),
 893
 894	PINMUX_IPSR_GPSR(IP0SR2_7_4,	FXR_TXENA_N_A),
 895	PINMUX_IPSR_GPSR(IP0SR2_7_4,	CANFD1_RX),
 896	PINMUX_IPSR_GPSR(IP0SR2_7_4,	TPU0TO3_B),
 897
 898	PINMUX_IPSR_GPSR(IP0SR2_11_8,	RXDA_EXTFXR),
 899	PINMUX_IPSR_GPSR(IP0SR2_11_8,	CANFD5_TX_A),
 900	PINMUX_IPSR_GPSR(IP0SR2_11_8,	IRQ5),
 901
 902	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CLK_EXTFXR),
 903	PINMUX_IPSR_GPSR(IP0SR2_15_12,	CANFD5_RX_A),
 904	PINMUX_IPSR_GPSR(IP0SR2_15_12,	IRQ4_B),
 905
 906	PINMUX_IPSR_GPSR(IP0SR2_19_16,	RXDB_EXTFXR),
 907
 908	PINMUX_IPSR_GPSR(IP0SR2_23_20,	FXR_TXENB_N_A),
 909
 910	PINMUX_IPSR_GPSR(IP0SR2_27_24,	FXR_TXDB),
 911
 912	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TPU0TO1_A),
 913	PINMUX_IPSR_GPSR(IP0SR2_31_28,	CANFD6_TX),
 914	PINMUX_IPSR_GPSR(IP0SR2_31_28,	TCLK2_C),
 915
 916	/* IP1SR2 */
 917	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TPU0TO0_A),
 918	PINMUX_IPSR_GPSR(IP1SR2_3_0,	CANFD6_RX),
 919	PINMUX_IPSR_GPSR(IP1SR2_3_0,	TCLK1_B),
 920
 921	PINMUX_IPSR_GPSR(IP1SR2_7_4,	CAN_CLK),
 922	PINMUX_IPSR_GPSR(IP1SR2_7_4,	FXR_TXENA_N_B),
 923
 924	PINMUX_IPSR_GPSR(IP1SR2_11_8,	CANFD0_TX),
 925	PINMUX_IPSR_GPSR(IP1SR2_11_8,	FXR_TXENB_N_B),
 926
 927	PINMUX_IPSR_GPSR(IP1SR2_15_12,	CANFD0_RX),
 928
 929	PINMUX_IPSR_GPSR(IP1SR2_19_16,	CANFD2_TX),
 930	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TPU0TO2_A),
 931	PINMUX_IPSR_GPSR(IP1SR2_19_16,	TCLK3_C),
 932
 933	PINMUX_IPSR_GPSR(IP1SR2_23_20,	CANFD2_RX),
 934	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TPU0TO3_A),
 935	PINMUX_IPSR_GPSR(IP1SR2_23_20,	PWM1_B),
 936	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TCLK4_C),
 937
 938	PINMUX_IPSR_GPSR(IP1SR2_27_24,	CANFD3_TX),
 939	PINMUX_IPSR_GPSR(IP1SR2_27_24,	PWM2),
 940
 941	PINMUX_IPSR_GPSR(IP1SR2_31_28,	CANFD3_RX),
 942	PINMUX_IPSR_GPSR(IP1SR2_31_28,	PWM3_B),
 943
 944	/* IP2SR2 */
 945	PINMUX_IPSR_GPSR(IP2SR2_3_0,	CANFD4_TX),
 946	PINMUX_IPSR_GPSR(IP2SR2_3_0,	PWM4),
 947
 948	PINMUX_IPSR_GPSR(IP2SR2_7_4,	CANFD4_RX),
 949	PINMUX_IPSR_GPSR(IP2SR2_7_4,	PWM5),
 950
 951	PINMUX_IPSR_GPSR(IP2SR2_11_8,	CANFD7_TX),
 952	PINMUX_IPSR_GPSR(IP2SR2_11_8,	PWM6),
 953
 954	PINMUX_IPSR_GPSR(IP2SR2_15_12,	CANFD7_RX),
 955	PINMUX_IPSR_GPSR(IP2SR2_15_12,	PWM7),
 956
 957	/* IP0SR3 */
 958	PINMUX_IPSR_GPSR(IP0SR3_3_0,	MMC_SD_D1),
 959	PINMUX_IPSR_GPSR(IP0SR3_7_4,	MMC_SD_D0),
 960	PINMUX_IPSR_GPSR(IP0SR3_11_8,	MMC_SD_D2),
 961	PINMUX_IPSR_GPSR(IP0SR3_15_12,	MMC_SD_CLK),
 962	PINMUX_IPSR_GPSR(IP0SR3_19_16,	MMC_DS),
 963	PINMUX_IPSR_GPSR(IP0SR3_23_20,	MMC_SD_D3),
 964	PINMUX_IPSR_GPSR(IP0SR3_27_24,	MMC_D5),
 965	PINMUX_IPSR_GPSR(IP0SR3_31_28,	MMC_D4),
 966
 967	/* IP1SR3 */
 968	PINMUX_IPSR_GPSR(IP1SR3_3_0,	MMC_D7),
 969
 970	PINMUX_IPSR_GPSR(IP1SR3_7_4,	MMC_D6),
 971
 972	PINMUX_IPSR_GPSR(IP1SR3_11_8,	MMC_SD_CMD),
 973
 974	PINMUX_IPSR_GPSR(IP1SR3_15_12,	SD_CD),
 975
 976	PINMUX_IPSR_GPSR(IP1SR3_19_16,	SD_WP),
 977
 978	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKIN),
 979	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKEN_IN),
 980	PINMUX_IPSR_GPSR(IP1SR3_23_20,	PWM1_A),
 981	PINMUX_IPSR_GPSR(IP1SR3_23_20,	TCLK3_A),
 982
 983	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKOUT),
 984	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKEN_OUT),
 985	PINMUX_IPSR_GPSR(IP1SR3_27_24,	ERROROUTC_N_A),
 986	PINMUX_IPSR_GPSR(IP1SR3_27_24,	TCLK4_A),
 987
 988	PINMUX_IPSR_GPSR(IP1SR3_31_28,	QSPI0_SSL),
 989
 990	/* IP2SR3 */
 991	PINMUX_IPSR_GPSR(IP2SR3_3_0,	QSPI0_IO3),
 992	PINMUX_IPSR_GPSR(IP2SR3_7_4,	QSPI0_IO2),
 993	PINMUX_IPSR_GPSR(IP2SR3_11_8,	QSPI0_MISO_IO1),
 994	PINMUX_IPSR_GPSR(IP2SR3_15_12,	QSPI0_MOSI_IO0),
 995	PINMUX_IPSR_GPSR(IP2SR3_19_16,	QSPI0_SPCLK),
 996	PINMUX_IPSR_GPSR(IP2SR3_23_20,	QSPI1_MOSI_IO0),
 997	PINMUX_IPSR_GPSR(IP2SR3_27_24,	QSPI1_SPCLK),
 998	PINMUX_IPSR_GPSR(IP2SR3_31_28,	QSPI1_MISO_IO1),
 999
1000	/* IP3SR3 */
1001	PINMUX_IPSR_GPSR(IP3SR3_3_0,	QSPI1_IO2),
1002	PINMUX_IPSR_GPSR(IP3SR3_7_4,	QSPI1_SSL),
1003	PINMUX_IPSR_GPSR(IP3SR3_11_8,	QSPI1_IO3),
1004	PINMUX_IPSR_GPSR(IP3SR3_15_12,	RPC_RESET_N),
1005	PINMUX_IPSR_GPSR(IP3SR3_19_16,	RPC_WP_N),
1006	PINMUX_IPSR_GPSR(IP3SR3_23_20,	RPC_INT_N),
1007
1008	/* IP0SR4 */
1009	PINMUX_IPSR_GPSR(IP0SR4_3_0,	TSN0_MDIO),
1010	PINMUX_IPSR_GPSR(IP0SR4_7_4,	TSN0_MDC),
1011	PINMUX_IPSR_GPSR(IP0SR4_11_8,	TSN0_AVTP_PPS1),
1012	PINMUX_IPSR_GPSR(IP0SR4_15_12,	TSN0_PHY_INT),
1013	PINMUX_IPSR_GPSR(IP0SR4_19_16,	TSN0_LINK),
1014	PINMUX_IPSR_GPSR(IP0SR4_23_20,	TSN0_AVTP_MATCH),
1015	PINMUX_IPSR_GPSR(IP0SR4_27_24,	TSN0_AVTP_CAPTURE),
1016	PINMUX_IPSR_GPSR(IP0SR4_31_28,	TSN0_RX_CTL),
1017
1018	/* IP1SR4 */
1019	PINMUX_IPSR_GPSR(IP1SR4_3_0,	TSN0_AVTP_PPS0),
1020	PINMUX_IPSR_GPSR(IP1SR4_7_4,	TSN0_TX_CTL),
1021	PINMUX_IPSR_GPSR(IP1SR4_11_8,	TSN0_RD0),
1022	PINMUX_IPSR_GPSR(IP1SR4_15_12,	TSN0_RXC),
1023	PINMUX_IPSR_GPSR(IP1SR4_19_16,	TSN0_TXC),
1024	PINMUX_IPSR_GPSR(IP1SR4_23_20,	TSN0_RD1),
1025	PINMUX_IPSR_GPSR(IP1SR4_27_24,	TSN0_TD1),
1026	PINMUX_IPSR_GPSR(IP1SR4_31_28,	TSN0_TD0),
1027
1028	/* IP2SR4 */
1029	PINMUX_IPSR_GPSR(IP2SR4_3_0,	TSN0_RD3),
1030	PINMUX_IPSR_GPSR(IP2SR4_7_4,	TSN0_RD2),
1031	PINMUX_IPSR_GPSR(IP2SR4_11_8,	TSN0_TD3),
1032	PINMUX_IPSR_GPSR(IP2SR4_15_12,	TSN0_TD2),
1033	PINMUX_IPSR_GPSR(IP2SR4_19_16,	TSN0_TXCREFCLK),
1034	PINMUX_IPSR_GPSR(IP2SR4_23_20,	PCIE0_CLKREQ_N),
1035	PINMUX_IPSR_GPSR(IP2SR4_27_24,	PCIE1_CLKREQ_N),
1036	PINMUX_IPSR_GPSR(IP2SR4_31_28,	AVS0),
1037
1038	/* IP3SR4 */
1039	PINMUX_IPSR_GPSR(IP3SR4_3_0,	AVS1),
1040
1041	/* IP0SR5 */
1042	PINMUX_IPSR_GPSR(IP0SR5_3_0,	AVB2_AVTP_PPS),
1043	PINMUX_IPSR_GPSR(IP0SR5_7_4,	AVB2_AVTP_CAPTURE),
1044	PINMUX_IPSR_GPSR(IP0SR5_11_8,	AVB2_AVTP_MATCH),
1045	PINMUX_IPSR_GPSR(IP0SR5_15_12,	AVB2_LINK),
1046	PINMUX_IPSR_GPSR(IP0SR5_19_16,	AVB2_PHY_INT),
1047	PINMUX_IPSR_GPSR(IP0SR5_23_20,	AVB2_MAGIC),
1048	PINMUX_IPSR_GPSR(IP0SR5_27_24,	AVB2_MDC),
1049	PINMUX_IPSR_GPSR(IP0SR5_31_28,	AVB2_TXCREFCLK),
1050
1051	/* IP1SR5 */
1052	PINMUX_IPSR_GPSR(IP1SR5_3_0,	AVB2_TD3),
1053	PINMUX_IPSR_GPSR(IP1SR5_7_4,	AVB2_RD3),
1054	PINMUX_IPSR_GPSR(IP1SR5_11_8,	AVB2_MDIO),
1055	PINMUX_IPSR_GPSR(IP1SR5_15_12,	AVB2_TD2),
1056	PINMUX_IPSR_GPSR(IP1SR5_19_16,	AVB2_TD1),
1057	PINMUX_IPSR_GPSR(IP1SR5_23_20,	AVB2_RD2),
1058	PINMUX_IPSR_GPSR(IP1SR5_27_24,	AVB2_RD1),
1059	PINMUX_IPSR_GPSR(IP1SR5_31_28,	AVB2_TD0),
1060
1061	/* IP2SR5 */
1062	PINMUX_IPSR_GPSR(IP2SR5_3_0,	AVB2_TXC),
1063	PINMUX_IPSR_GPSR(IP2SR5_7_4,	AVB2_RD0),
1064	PINMUX_IPSR_GPSR(IP2SR5_11_8,	AVB2_RXC),
1065	PINMUX_IPSR_GPSR(IP2SR5_15_12,	AVB2_TX_CTL),
1066	PINMUX_IPSR_GPSR(IP2SR5_19_16,	AVB2_RX_CTL),
1067
1068	/* IP0SR6 */
1069	PINMUX_IPSR_GPSR(IP0SR6_3_0,	AVB1_MDIO),
1070
1071	PINMUX_IPSR_GPSR(IP0SR6_7_4,	AVB1_MAGIC),
1072
1073	PINMUX_IPSR_GPSR(IP0SR6_11_8,	AVB1_MDC),
1074
1075	PINMUX_IPSR_GPSR(IP0SR6_15_12,	AVB1_PHY_INT),
1076
1077	PINMUX_IPSR_GPSR(IP0SR6_19_16,	AVB1_LINK),
1078
1079	PINMUX_IPSR_GPSR(IP0SR6_23_20,	AVB1_AVTP_MATCH),
1080
1081	PINMUX_IPSR_GPSR(IP0SR6_27_24,	AVB1_TXC),
1082
1083	PINMUX_IPSR_GPSR(IP0SR6_31_28,	AVB1_TX_CTL),
1084
1085	/* IP1SR6 */
1086	PINMUX_IPSR_GPSR(IP1SR6_3_0,	AVB1_RXC),
1087
1088	PINMUX_IPSR_GPSR(IP1SR6_7_4,	AVB1_RX_CTL),
1089
1090	PINMUX_IPSR_GPSR(IP1SR6_11_8,	AVB1_AVTP_PPS),
1091
1092	PINMUX_IPSR_GPSR(IP1SR6_15_12,	AVB1_AVTP_CAPTURE),
1093
1094	PINMUX_IPSR_GPSR(IP1SR6_19_16,	AVB1_TD1),
1095
1096	PINMUX_IPSR_GPSR(IP1SR6_23_20,	AVB1_TD0),
1097
1098	PINMUX_IPSR_GPSR(IP1SR6_27_24,	AVB1_RD1),
1099
1100	PINMUX_IPSR_GPSR(IP1SR6_31_28,	AVB1_RD0),
1101
1102	/* IP2SR6 */
1103	PINMUX_IPSR_GPSR(IP2SR6_3_0,	AVB1_TD2),
1104
1105	PINMUX_IPSR_GPSR(IP2SR6_7_4,	AVB1_RD2),
1106
1107	PINMUX_IPSR_GPSR(IP2SR6_11_8,	AVB1_TD3),
1108
1109	PINMUX_IPSR_GPSR(IP2SR6_15_12,	AVB1_RD3),
1110
1111	PINMUX_IPSR_GPSR(IP2SR6_19_16,	AVB1_TXCREFCLK),
1112
1113	/* IP0SR7 */
1114	PINMUX_IPSR_GPSR(IP0SR7_3_0,	AVB0_AVTP_PPS),
1115
1116	PINMUX_IPSR_GPSR(IP0SR7_7_4,	AVB0_AVTP_CAPTURE),
1117
1118	PINMUX_IPSR_GPSR(IP0SR7_11_8,	AVB0_AVTP_MATCH),
1119
1120	PINMUX_IPSR_GPSR(IP0SR7_15_12,	AVB0_TD3),
1121
1122	PINMUX_IPSR_GPSR(IP0SR7_19_16,	AVB0_LINK),
1123
1124	PINMUX_IPSR_GPSR(IP0SR7_23_20,	AVB0_PHY_INT),
1125
1126	PINMUX_IPSR_GPSR(IP0SR7_27_24,	AVB0_TD2),
1127
1128	PINMUX_IPSR_GPSR(IP0SR7_31_28,	AVB0_TD1),
1129
1130	/* IP1SR7 */
1131	PINMUX_IPSR_GPSR(IP1SR7_3_0,	AVB0_RD3),
1132
1133	PINMUX_IPSR_GPSR(IP1SR7_7_4,	AVB0_TXCREFCLK),
1134
1135	PINMUX_IPSR_GPSR(IP1SR7_11_8,	AVB0_MAGIC),
1136
1137	PINMUX_IPSR_GPSR(IP1SR7_15_12,	AVB0_TD0),
1138
1139	PINMUX_IPSR_GPSR(IP1SR7_19_16,	AVB0_RD2),
1140
1141	PINMUX_IPSR_GPSR(IP1SR7_23_20,	AVB0_MDC),
1142
1143	PINMUX_IPSR_GPSR(IP1SR7_27_24,	AVB0_MDIO),
1144
1145	PINMUX_IPSR_GPSR(IP1SR7_31_28,	AVB0_TXC),
1146
1147	/* IP2SR7 */
1148	PINMUX_IPSR_GPSR(IP2SR7_3_0,	AVB0_TX_CTL),
1149
1150	PINMUX_IPSR_GPSR(IP2SR7_7_4,	AVB0_RD1),
1151
1152	PINMUX_IPSR_GPSR(IP2SR7_11_8,	AVB0_RD0),
1153
1154	PINMUX_IPSR_GPSR(IP2SR7_15_12,	AVB0_RXC),
1155
1156	PINMUX_IPSR_GPSR(IP2SR7_19_16,	AVB0_RX_CTL),
1157
1158	/* IP0SR8 */
1159	PINMUX_IPSR_MSEL(IP0SR8_3_0,	SCL0,			SEL_SCL0_0),
1160	PINMUX_IPSR_MSEL(IP0SR8_7_4,	SDA0,			SEL_SDA0_0),
1161	PINMUX_IPSR_MSEL(IP0SR8_11_8,	SCL1,			SEL_SCL1_0),
1162	PINMUX_IPSR_MSEL(IP0SR8_15_12,	SDA1,			SEL_SDA1_0),
1163	PINMUX_IPSR_MSEL(IP0SR8_19_16,	SCL2,			SEL_SCL2_0),
1164	PINMUX_IPSR_MSEL(IP0SR8_23_20,	SDA2,			SEL_SDA2_0),
1165	PINMUX_IPSR_MSEL(IP0SR8_27_24,	SCL3,			SEL_SCL3_0),
1166	PINMUX_IPSR_MSEL(IP0SR8_31_28,	SDA3,			SEL_SDA3_0),
1167
1168	/* IP1SR8 */
1169	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCL4,			SEL_SCL4_0),
1170	PINMUX_IPSR_MSEL(IP1SR8_3_0,	HRX2,			SEL_SCL4_0),
1171	PINMUX_IPSR_MSEL(IP1SR8_3_0,	SCK4,			SEL_SCL4_0),
1172
1173	PINMUX_IPSR_MSEL(IP1SR8_7_4,	SDA4,			SEL_SDA4_0),
1174	PINMUX_IPSR_MSEL(IP1SR8_7_4,	HTX2,			SEL_SDA4_0),
1175	PINMUX_IPSR_MSEL(IP1SR8_7_4,	CTS4_N,			SEL_SDA4_0),
1176
1177	PINMUX_IPSR_MSEL(IP1SR8_11_8,	SCL5,			SEL_SCL5_0),
1178	PINMUX_IPSR_MSEL(IP1SR8_11_8,	HRTS2_N,		SEL_SCL5_0),
1179	PINMUX_IPSR_MSEL(IP1SR8_11_8,	RTS4_N,			SEL_SCL5_0),
1180
1181	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SDA5,			SEL_SDA5_0),
1182	PINMUX_IPSR_MSEL(IP1SR8_15_12,	SCIF_CLK2,		SEL_SDA5_0),
1183
1184	PINMUX_IPSR_GPSR(IP1SR8_19_16,	HCTS2_N),
1185	PINMUX_IPSR_GPSR(IP1SR8_19_16,	TX4),
1186
1187	PINMUX_IPSR_GPSR(IP1SR8_23_20,	HSCK2),
1188	PINMUX_IPSR_GPSR(IP1SR8_23_20,	RX4),
1189};
1190
1191/*
1192 * Pins not associated with a GPIO port.
1193 */
1194enum {
1195	GP_ASSIGN_LAST(),
1196	NOGP_ALL(),
1197};
1198
1199static const struct sh_pfc_pin pinmux_pins[] = {
1200	PINMUX_GPIO_GP_ALL(),
1201	PINMUX_NOGP_ALL(),
1202};
1203
1204/* - AUDIO CLOCK ----------------------------------------- */
1205static const unsigned int audio_clkin_pins[] = {
1206	/* CLK IN */
1207	RCAR_GP_PIN(1, 22),
1208};
1209static const unsigned int audio_clkin_mux[] = {
1210	AUDIO_CLKIN_MARK,
1211};
1212static const unsigned int audio_clkout_pins[] = {
1213	/* CLK OUT */
1214	RCAR_GP_PIN(1, 21),
1215};
1216static const unsigned int audio_clkout_mux[] = {
1217	AUDIO_CLKOUT_MARK,
1218};
1219
1220/* - AVB0 ------------------------------------------------ */
1221static const unsigned int avb0_link_pins[] = {
1222	/* AVB0_LINK */
1223	RCAR_GP_PIN(7, 4),
1224};
1225static const unsigned int avb0_link_mux[] = {
1226	AVB0_LINK_MARK,
1227};
1228static const unsigned int avb0_magic_pins[] = {
1229	/* AVB0_MAGIC */
1230	RCAR_GP_PIN(7, 10),
1231};
1232static const unsigned int avb0_magic_mux[] = {
1233	AVB0_MAGIC_MARK,
1234};
1235static const unsigned int avb0_phy_int_pins[] = {
1236	/* AVB0_PHY_INT */
1237	RCAR_GP_PIN(7, 5),
1238};
1239static const unsigned int avb0_phy_int_mux[] = {
1240	AVB0_PHY_INT_MARK,
1241};
1242static const unsigned int avb0_mdio_pins[] = {
1243	/* AVB0_MDC, AVB0_MDIO */
1244	RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1245};
1246static const unsigned int avb0_mdio_mux[] = {
1247	AVB0_MDC_MARK, AVB0_MDIO_MARK,
1248};
1249static const unsigned int avb0_rgmii_pins[] = {
1250	/*
1251	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1252	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1253	 */
1254	RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1255	RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7,  7),
1256	RCAR_GP_PIN(7,  6), RCAR_GP_PIN(7,  3),
1257	RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1258	RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1259	RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7,  8),
1260};
1261static const unsigned int avb0_rgmii_mux[] = {
1262	AVB0_TX_CTL_MARK,	AVB0_TXC_MARK,
1263	AVB0_TD0_MARK,		AVB0_TD1_MARK,
1264	AVB0_TD2_MARK,		AVB0_TD3_MARK,
1265	AVB0_RX_CTL_MARK,	AVB0_RXC_MARK,
1266	AVB0_RD0_MARK,		AVB0_RD1_MARK,
1267	AVB0_RD2_MARK,		AVB0_RD3_MARK,
1268};
1269static const unsigned int avb0_txcrefclk_pins[] = {
1270	/* AVB0_TXCREFCLK */
1271	RCAR_GP_PIN(7, 9),
1272};
1273static const unsigned int avb0_txcrefclk_mux[] = {
1274	AVB0_TXCREFCLK_MARK,
1275};
1276static const unsigned int avb0_avtp_pps_pins[] = {
1277	/* AVB0_AVTP_PPS */
1278	RCAR_GP_PIN(7, 0),
1279};
1280static const unsigned int avb0_avtp_pps_mux[] = {
1281	AVB0_AVTP_PPS_MARK,
1282};
1283static const unsigned int avb0_avtp_capture_pins[] = {
1284	/* AVB0_AVTP_CAPTURE */
1285	RCAR_GP_PIN(7, 1),
1286};
1287static const unsigned int avb0_avtp_capture_mux[] = {
1288	AVB0_AVTP_CAPTURE_MARK,
1289};
1290static const unsigned int avb0_avtp_match_pins[] = {
1291	/* AVB0_AVTP_MATCH */
1292	RCAR_GP_PIN(7, 2),
1293};
1294static const unsigned int avb0_avtp_match_mux[] = {
1295	AVB0_AVTP_MATCH_MARK,
1296};
1297
1298/* - AVB1 ------------------------------------------------ */
1299static const unsigned int avb1_link_pins[] = {
1300	/* AVB1_LINK */
1301	RCAR_GP_PIN(6, 4),
1302};
1303static const unsigned int avb1_link_mux[] = {
1304	AVB1_LINK_MARK,
1305};
1306static const unsigned int avb1_magic_pins[] = {
1307	/* AVB1_MAGIC */
1308	RCAR_GP_PIN(6, 1),
1309};
1310static const unsigned int avb1_magic_mux[] = {
1311	AVB1_MAGIC_MARK,
1312};
1313static const unsigned int avb1_phy_int_pins[] = {
1314	/* AVB1_PHY_INT */
1315	RCAR_GP_PIN(6, 3),
1316};
1317static const unsigned int avb1_phy_int_mux[] = {
1318	AVB1_PHY_INT_MARK,
1319};
1320static const unsigned int avb1_mdio_pins[] = {
1321	/* AVB1_MDC, AVB1_MDIO */
1322	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1323};
1324static const unsigned int avb1_mdio_mux[] = {
1325	AVB1_MDC_MARK, AVB1_MDIO_MARK,
1326};
1327static const unsigned int avb1_rgmii_pins[] = {
1328	/*
1329	 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1330	 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1331	 */
1332	RCAR_GP_PIN(6,  7), RCAR_GP_PIN(6,  6),
1333	RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1334	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1335	RCAR_GP_PIN(6,  9), RCAR_GP_PIN(6,  8),
1336	RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1337	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1338};
1339static const unsigned int avb1_rgmii_mux[] = {
1340	AVB1_TX_CTL_MARK,	AVB1_TXC_MARK,
1341	AVB1_TD0_MARK,		AVB1_TD1_MARK,
1342	AVB1_TD2_MARK,		AVB1_TD3_MARK,
1343	AVB1_RX_CTL_MARK,	AVB1_RXC_MARK,
1344	AVB1_RD0_MARK,		AVB1_RD1_MARK,
1345	AVB1_RD2_MARK,		AVB1_RD3_MARK,
1346};
1347static const unsigned int avb1_txcrefclk_pins[] = {
1348	/* AVB1_TXCREFCLK */
1349	RCAR_GP_PIN(6, 20),
1350};
1351static const unsigned int avb1_txcrefclk_mux[] = {
1352	AVB1_TXCREFCLK_MARK,
1353};
1354static const unsigned int avb1_avtp_pps_pins[] = {
1355	/* AVB1_AVTP_PPS */
1356	RCAR_GP_PIN(6, 10),
1357};
1358static const unsigned int avb1_avtp_pps_mux[] = {
1359	AVB1_AVTP_PPS_MARK,
1360};
1361static const unsigned int avb1_avtp_capture_pins[] = {
1362	/* AVB1_AVTP_CAPTURE */
1363	RCAR_GP_PIN(6, 11),
1364};
1365static const unsigned int avb1_avtp_capture_mux[] = {
1366	AVB1_AVTP_CAPTURE_MARK,
1367};
1368static const unsigned int avb1_avtp_match_pins[] = {
1369	/* AVB1_AVTP_MATCH */
1370	RCAR_GP_PIN(6, 5),
1371};
1372static const unsigned int avb1_avtp_match_mux[] = {
1373	AVB1_AVTP_MATCH_MARK,
1374};
1375
1376/* - AVB2 ------------------------------------------------ */
1377static const unsigned int avb2_link_pins[] = {
1378	/* AVB2_LINK */
1379	RCAR_GP_PIN(5, 3),
1380};
1381static const unsigned int avb2_link_mux[] = {
1382	AVB2_LINK_MARK,
1383};
1384static const unsigned int avb2_magic_pins[] = {
1385	/* AVB2_MAGIC */
1386	RCAR_GP_PIN(5, 5),
1387};
1388static const unsigned int avb2_magic_mux[] = {
1389	AVB2_MAGIC_MARK,
1390};
1391static const unsigned int avb2_phy_int_pins[] = {
1392	/* AVB2_PHY_INT */
1393	RCAR_GP_PIN(5, 4),
1394};
1395static const unsigned int avb2_phy_int_mux[] = {
1396	AVB2_PHY_INT_MARK,
1397};
1398static const unsigned int avb2_mdio_pins[] = {
1399	/* AVB2_MDC, AVB2_MDIO */
1400	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1401};
1402static const unsigned int avb2_mdio_mux[] = {
1403	AVB2_MDC_MARK, AVB2_MDIO_MARK,
1404};
1405static const unsigned int avb2_rgmii_pins[] = {
1406	/*
1407	 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1408	 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1409	 */
1410	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1411	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1412	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5,  8),
1413	RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1414	RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1415	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5,  9),
1416};
1417static const unsigned int avb2_rgmii_mux[] = {
1418	AVB2_TX_CTL_MARK,	AVB2_TXC_MARK,
1419	AVB2_TD0_MARK,		AVB2_TD1_MARK,
1420	AVB2_TD2_MARK,		AVB2_TD3_MARK,
1421	AVB2_RX_CTL_MARK,	AVB2_RXC_MARK,
1422	AVB2_RD0_MARK,		AVB2_RD1_MARK,
1423	AVB2_RD2_MARK,		AVB2_RD3_MARK,
1424};
1425static const unsigned int avb2_txcrefclk_pins[] = {
1426	/* AVB2_TXCREFCLK */
1427	RCAR_GP_PIN(5, 7),
1428};
1429static const unsigned int avb2_txcrefclk_mux[] = {
1430	AVB2_TXCREFCLK_MARK,
1431};
1432static const unsigned int avb2_avtp_pps_pins[] = {
1433	/* AVB2_AVTP_PPS */
1434	RCAR_GP_PIN(5, 0),
1435};
1436static const unsigned int avb2_avtp_pps_mux[] = {
1437	AVB2_AVTP_PPS_MARK,
1438};
1439static const unsigned int avb2_avtp_capture_pins[] = {
1440	/* AVB2_AVTP_CAPTURE */
1441	RCAR_GP_PIN(5, 1),
1442};
1443static const unsigned int avb2_avtp_capture_mux[] = {
1444	AVB2_AVTP_CAPTURE_MARK,
1445};
1446static const unsigned int avb2_avtp_match_pins[] = {
1447	/* AVB2_AVTP_MATCH */
1448	RCAR_GP_PIN(5, 2),
1449};
1450static const unsigned int avb2_avtp_match_mux[] = {
1451	AVB2_AVTP_MATCH_MARK,
1452};
1453
1454/* - CANFD0 ----------------------------------------------------------------- */
1455static const unsigned int canfd0_data_pins[] = {
1456	/* CANFD0_TX, CANFD0_RX */
1457	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1458};
1459static const unsigned int canfd0_data_mux[] = {
1460	CANFD0_TX_MARK, CANFD0_RX_MARK,
1461};
1462
1463/* - CANFD1 ----------------------------------------------------------------- */
1464static const unsigned int canfd1_data_pins[] = {
1465	/* CANFD1_TX, CANFD1_RX */
1466	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1467};
1468static const unsigned int canfd1_data_mux[] = {
1469	CANFD1_TX_MARK, CANFD1_RX_MARK,
1470};
1471
1472/* - CANFD2 ----------------------------------------------------------------- */
1473static const unsigned int canfd2_data_pins[] = {
1474	/* CANFD2_TX, CANFD2_RX */
1475	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1476};
1477static const unsigned int canfd2_data_mux[] = {
1478	CANFD2_TX_MARK, CANFD2_RX_MARK,
1479};
1480
1481/* - CANFD3 ----------------------------------------------------------------- */
1482static const unsigned int canfd3_data_pins[] = {
1483	/* CANFD3_TX, CANFD3_RX */
1484	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1485};
1486static const unsigned int canfd3_data_mux[] = {
1487	CANFD3_TX_MARK, CANFD3_RX_MARK,
1488};
1489
1490/* - CANFD4 ----------------------------------------------------------------- */
1491static const unsigned int canfd4_data_pins[] = {
1492	/* CANFD4_TX, CANFD4_RX */
1493	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1494};
1495static const unsigned int canfd4_data_mux[] = {
1496	CANFD4_TX_MARK, CANFD4_RX_MARK,
1497};
1498
1499/* - CANFD5 ----------------------------------------------------------------- */
1500static const unsigned int canfd5_data_a_pins[] = {
1501	/* CANFD5_TX_A, CANFD5_RX_A */
1502	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1503};
1504static const unsigned int canfd5_data_a_mux[] = {
1505	CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
1506};
1507
1508static const unsigned int canfd5_data_b_pins[] = {
1509	/* CANFD5_TX_B, CANFD5_RX_B */
1510	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1511};
1512static const unsigned int canfd5_data_b_mux[] = {
1513	CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1514};
1515
1516/* - CANFD6 ----------------------------------------------------------------- */
1517static const unsigned int canfd6_data_pins[] = {
1518	/* CANFD6_TX, CANFD6_RX */
1519	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1520};
1521static const unsigned int canfd6_data_mux[] = {
1522	CANFD6_TX_MARK, CANFD6_RX_MARK,
1523};
1524
1525/* - CANFD7 ----------------------------------------------------------------- */
1526static const unsigned int canfd7_data_pins[] = {
1527	/* CANFD7_TX, CANFD7_RX */
1528	RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1529};
1530static const unsigned int canfd7_data_mux[] = {
1531	CANFD7_TX_MARK, CANFD7_RX_MARK,
1532};
1533
1534/* - CANFD Clock ------------------------------------------------------------ */
1535static const unsigned int can_clk_pins[] = {
1536	/* CAN_CLK */
1537	RCAR_GP_PIN(2, 9),
1538};
1539static const unsigned int can_clk_mux[] = {
1540	CAN_CLK_MARK,
1541};
1542
1543/* - HSCIF0 ----------------------------------------------------------------- */
1544static const unsigned int hscif0_data_pins[] = {
1545	/* HRX0, HTX0 */
1546	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1547};
1548static const unsigned int hscif0_data_mux[] = {
1549	HRX0_MARK, HTX0_MARK,
1550};
1551static const unsigned int hscif0_clk_pins[] = {
1552	/* HSCK0 */
1553	RCAR_GP_PIN(1, 15),
1554};
1555static const unsigned int hscif0_clk_mux[] = {
1556	HSCK0_MARK,
1557};
1558static const unsigned int hscif0_ctrl_pins[] = {
1559	/* HRTS0_N, HCTS0_N */
1560	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1561};
1562static const unsigned int hscif0_ctrl_mux[] = {
1563	HRTS0_N_MARK, HCTS0_N_MARK,
1564};
1565
1566/* - HSCIF1 ----------------------------------------------------------------- */
1567static const unsigned int hscif1_data_a_pins[] = {
1568	/* HRX1_A, HTX1_A */
1569	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1570};
1571static const unsigned int hscif1_data_a_mux[] = {
1572	HRX1_A_MARK, HTX1_A_MARK,
1573};
1574static const unsigned int hscif1_clk_a_pins[] = {
1575	/* HSCK1_A */
1576	RCAR_GP_PIN(0, 18),
1577};
1578static const unsigned int hscif1_clk_a_mux[] = {
1579	HSCK1_A_MARK,
1580};
1581static const unsigned int hscif1_ctrl_a_pins[] = {
1582	/* HRTS1_N_A, HCTS1_N_A */
1583	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1584};
1585static const unsigned int hscif1_ctrl_a_mux[] = {
1586	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1587};
1588
1589static const unsigned int hscif1_data_b_pins[] = {
1590	/* HRX1_B, HTX1_B */
1591	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1592};
1593static const unsigned int hscif1_data_b_mux[] = {
1594	HRX1_B_MARK, HTX1_B_MARK,
1595};
1596static const unsigned int hscif1_clk_b_pins[] = {
1597	/* HSCK1_B */
1598	RCAR_GP_PIN(1, 10),
1599};
1600static const unsigned int hscif1_clk_b_mux[] = {
1601	HSCK1_B_MARK,
1602};
1603static const unsigned int hscif1_ctrl_b_pins[] = {
1604	/* HRTS1_N_B, HCTS1_N_B */
1605	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1606};
1607static const unsigned int hscif1_ctrl_b_mux[] = {
1608	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1609};
1610
1611/* - HSCIF2 ----------------------------------------------------------------- */
1612static const unsigned int hscif2_data_pins[] = {
1613	/* HRX2, HTX2 */
1614	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1615};
1616static const unsigned int hscif2_data_mux[] = {
1617	HRX2_MARK, HTX2_MARK,
1618};
1619static const unsigned int hscif2_clk_pins[] = {
1620	/* HSCK2 */
1621	RCAR_GP_PIN(8, 13),
1622};
1623static const unsigned int hscif2_clk_mux[] = {
1624	HSCK2_MARK,
1625};
1626static const unsigned int hscif2_ctrl_pins[] = {
1627	/* HRTS2_N, HCTS2_N */
1628	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1629};
1630static const unsigned int hscif2_ctrl_mux[] = {
1631	HRTS2_N_MARK, HCTS2_N_MARK,
1632};
1633
1634/* - HSCIF3 ----------------------------------------------------------------- */
1635static const unsigned int hscif3_data_a_pins[] = {
1636	/* HRX3_A, HTX3_A */
1637	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1638};
1639static const unsigned int hscif3_data_a_mux[] = {
1640	HRX3_A_MARK, HTX3_A_MARK,
1641};
1642static const unsigned int hscif3_clk_a_pins[] = {
1643	/* HSCK3_A */
1644	RCAR_GP_PIN(1, 25),
1645};
1646static const unsigned int hscif3_clk_a_mux[] = {
1647	HSCK3_A_MARK,
1648};
1649static const unsigned int hscif3_ctrl_a_pins[] = {
1650	/* HRTS3_N_A, HCTS3_N_A */
1651	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1652};
1653static const unsigned int hscif3_ctrl_a_mux[] = {
1654	HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1655};
1656
1657static const unsigned int hscif3_data_b_pins[] = {
1658	/* HRX3_B, HTX3_B */
1659	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1660};
1661static const unsigned int hscif3_data_b_mux[] = {
1662	HRX3_B_MARK, HTX3_B_MARK,
1663};
1664static const unsigned int hscif3_clk_b_pins[] = {
1665	/* HSCK3_B */
1666	RCAR_GP_PIN(1, 3),
1667};
1668static const unsigned int hscif3_clk_b_mux[] = {
1669	HSCK3_B_MARK,
1670};
1671static const unsigned int hscif3_ctrl_b_pins[] = {
1672	/* HRTS3_N_B, HCTS3_N_B */
1673	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1674};
1675static const unsigned int hscif3_ctrl_b_mux[] = {
1676	HRTS3_N_B_MARK, HCTS3_N_B_MARK,
1677};
1678
1679/* - I2C0 ------------------------------------------------------------------- */
1680static const unsigned int i2c0_pins[] = {
1681	/* SDA0, SCL0 */
1682	RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1683};
1684static const unsigned int i2c0_mux[] = {
1685	SDA0_MARK, SCL0_MARK,
1686};
1687
1688/* - I2C1 ------------------------------------------------------------------- */
1689static const unsigned int i2c1_pins[] = {
1690	/* SDA1, SCL1 */
1691	RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1692};
1693static const unsigned int i2c1_mux[] = {
1694	SDA1_MARK, SCL1_MARK,
1695};
1696
1697/* - I2C2 ------------------------------------------------------------------- */
1698static const unsigned int i2c2_pins[] = {
1699	/* SDA2, SCL2 */
1700	RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1701};
1702static const unsigned int i2c2_mux[] = {
1703	SDA2_MARK, SCL2_MARK,
1704};
1705
1706/* - I2C3 ------------------------------------------------------------------- */
1707static const unsigned int i2c3_pins[] = {
1708	/* SDA3, SCL3 */
1709	RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1710};
1711static const unsigned int i2c3_mux[] = {
1712	SDA3_MARK, SCL3_MARK,
1713};
1714
1715/* - I2C4 ------------------------------------------------------------------- */
1716static const unsigned int i2c4_pins[] = {
1717	/* SDA4, SCL4 */
1718	RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1719};
1720static const unsigned int i2c4_mux[] = {
1721	SDA4_MARK, SCL4_MARK,
1722};
1723
1724/* - I2C5 ------------------------------------------------------------------- */
1725static const unsigned int i2c5_pins[] = {
1726	/* SDA5, SCL5 */
1727	RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1728};
1729static const unsigned int i2c5_mux[] = {
1730	SDA5_MARK, SCL5_MARK,
1731};
1732
1733/* - INTC-EX ---------------------------------------------------------------- */
1734static const unsigned int intc_ex_irq0_a_pins[] = {
1735	/* IRQ0_A */
1736	RCAR_GP_PIN(0, 6),
1737};
1738static const unsigned int intc_ex_irq0_a_mux[] = {
1739	IRQ0_A_MARK,
1740};
1741static const unsigned int intc_ex_irq0_b_pins[] = {
1742	/* IRQ0_B */
1743	RCAR_GP_PIN(1, 20),
1744};
1745static const unsigned int intc_ex_irq0_b_mux[] = {
1746	IRQ0_B_MARK,
1747};
1748
1749static const unsigned int intc_ex_irq1_a_pins[] = {
1750	/* IRQ1_A */
1751	RCAR_GP_PIN(0, 5),
1752};
1753static const unsigned int intc_ex_irq1_a_mux[] = {
1754	IRQ1_A_MARK,
1755};
1756static const unsigned int intc_ex_irq1_b_pins[] = {
1757	/* IRQ1_B */
1758	RCAR_GP_PIN(1, 21),
1759};
1760static const unsigned int intc_ex_irq1_b_mux[] = {
1761	IRQ1_B_MARK,
1762};
1763
1764static const unsigned int intc_ex_irq2_a_pins[] = {
1765	/* IRQ2_A */
1766	RCAR_GP_PIN(0, 4),
1767};
1768static const unsigned int intc_ex_irq2_a_mux[] = {
1769	IRQ2_A_MARK,
1770};
1771static const unsigned int intc_ex_irq2_b_pins[] = {
1772	/* IRQ2_B */
1773	RCAR_GP_PIN(0, 13),
1774};
1775static const unsigned int intc_ex_irq2_b_mux[] = {
1776	IRQ2_B_MARK,
1777};
1778
1779static const unsigned int intc_ex_irq3_a_pins[] = {
1780	/* IRQ3_A */
1781	RCAR_GP_PIN(0, 3),
1782};
1783static const unsigned int intc_ex_irq3_a_mux[] = {
1784	IRQ3_A_MARK,
1785};
1786static const unsigned int intc_ex_irq3_b_pins[] = {
1787	/* IRQ3_B */
1788	RCAR_GP_PIN(1, 23),
1789};
1790static const unsigned int intc_ex_irq3_b_mux[] = {
1791	IRQ3_B_MARK,
1792};
1793
1794static const unsigned int intc_ex_irq4_a_pins[] = {
1795	/* IRQ4_A */
1796	RCAR_GP_PIN(1, 17),
1797};
1798static const unsigned int intc_ex_irq4_a_mux[] = {
1799	IRQ4_A_MARK,
1800};
1801static const unsigned int intc_ex_irq4_b_pins[] = {
1802	/* IRQ4_B */
1803	RCAR_GP_PIN(2, 3),
1804};
1805static const unsigned int intc_ex_irq4_b_mux[] = {
1806	IRQ4_B_MARK,
1807};
1808
1809static const unsigned int intc_ex_irq5_pins[] = {
1810	/* IRQ5 */
1811	RCAR_GP_PIN(2, 2),
1812};
1813static const unsigned int intc_ex_irq5_mux[] = {
1814	IRQ5_MARK,
1815};
1816
1817/* - MMC -------------------------------------------------------------------- */
1818static const unsigned int mmc_data_pins[] = {
1819	/* MMC_SD_D[0:3], MMC_D[4:7] */
1820	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1821	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1822	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1823	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1824};
1825static const unsigned int mmc_data_mux[] = {
1826	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1827	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1828	MMC_D4_MARK, MMC_D5_MARK,
1829	MMC_D6_MARK, MMC_D7_MARK,
1830};
1831static const unsigned int mmc_ctrl_pins[] = {
1832	/* MMC_SD_CLK, MMC_SD_CMD */
1833	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1834};
1835static const unsigned int mmc_ctrl_mux[] = {
1836	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1837};
1838static const unsigned int mmc_cd_pins[] = {
1839	/* SD_CD */
1840	RCAR_GP_PIN(3, 11),
1841};
1842static const unsigned int mmc_cd_mux[] = {
1843	SD_CD_MARK,
1844};
1845static const unsigned int mmc_wp_pins[] = {
1846	/* SD_WP */
1847	RCAR_GP_PIN(3, 12),
1848};
1849static const unsigned int mmc_wp_mux[] = {
1850	SD_WP_MARK,
1851};
1852static const unsigned int mmc_ds_pins[] = {
1853	/* MMC_DS */
1854	RCAR_GP_PIN(3, 4),
1855};
1856static const unsigned int mmc_ds_mux[] = {
1857	MMC_DS_MARK,
1858};
1859
1860/* - MSIOF0 ----------------------------------------------------------------- */
1861static const unsigned int msiof0_clk_pins[] = {
1862	/* MSIOF0_SCK */
1863	RCAR_GP_PIN(1, 10),
1864};
1865static const unsigned int msiof0_clk_mux[] = {
1866	MSIOF0_SCK_MARK,
1867};
1868static const unsigned int msiof0_sync_pins[] = {
1869	/* MSIOF0_SYNC */
1870	RCAR_GP_PIN(1, 8),
1871};
1872static const unsigned int msiof0_sync_mux[] = {
1873	MSIOF0_SYNC_MARK,
1874};
1875static const unsigned int msiof0_ss1_pins[] = {
1876	/* MSIOF0_SS1 */
1877	RCAR_GP_PIN(1, 7),
1878};
1879static const unsigned int msiof0_ss1_mux[] = {
1880	MSIOF0_SS1_MARK,
1881};
1882static const unsigned int msiof0_ss2_pins[] = {
1883	/* MSIOF0_SS2 */
1884	RCAR_GP_PIN(1, 6),
1885};
1886static const unsigned int msiof0_ss2_mux[] = {
1887	MSIOF0_SS2_MARK,
1888};
1889static const unsigned int msiof0_txd_pins[] = {
1890	/* MSIOF0_TXD */
1891	RCAR_GP_PIN(1, 9),
1892};
1893static const unsigned int msiof0_txd_mux[] = {
1894	MSIOF0_TXD_MARK,
1895};
1896static const unsigned int msiof0_rxd_pins[] = {
1897	/* MSIOF0_RXD */
1898	RCAR_GP_PIN(1, 11),
1899};
1900static const unsigned int msiof0_rxd_mux[] = {
1901	MSIOF0_RXD_MARK,
1902};
1903
1904/* - MSIOF1 ----------------------------------------------------------------- */
1905static const unsigned int msiof1_clk_pins[] = {
1906	/* MSIOF1_SCK */
1907	RCAR_GP_PIN(1, 3),
1908};
1909static const unsigned int msiof1_clk_mux[] = {
1910	MSIOF1_SCK_MARK,
1911};
1912static const unsigned int msiof1_sync_pins[] = {
1913	/* MSIOF1_SYNC */
1914	RCAR_GP_PIN(1, 2),
1915};
1916static const unsigned int msiof1_sync_mux[] = {
1917	MSIOF1_SYNC_MARK,
1918};
1919static const unsigned int msiof1_ss1_pins[] = {
1920	/* MSIOF1_SS1 */
1921	RCAR_GP_PIN(1, 1),
1922};
1923static const unsigned int msiof1_ss1_mux[] = {
1924	MSIOF1_SS1_MARK,
1925};
1926static const unsigned int msiof1_ss2_pins[] = {
1927	/* MSIOF1_SS2 */
1928	RCAR_GP_PIN(1, 0),
1929};
1930static const unsigned int msiof1_ss2_mux[] = {
1931	MSIOF1_SS2_MARK,
1932};
1933static const unsigned int msiof1_txd_pins[] = {
1934	/* MSIOF1_TXD */
1935	RCAR_GP_PIN(1, 4),
1936};
1937static const unsigned int msiof1_txd_mux[] = {
1938	MSIOF1_TXD_MARK,
1939};
1940static const unsigned int msiof1_rxd_pins[] = {
1941	/* MSIOF1_RXD */
1942	RCAR_GP_PIN(1, 5),
1943};
1944static const unsigned int msiof1_rxd_mux[] = {
1945	MSIOF1_RXD_MARK,
1946};
1947
1948/* - MSIOF2 ----------------------------------------------------------------- */
1949static const unsigned int msiof2_clk_pins[] = {
1950	/* MSIOF2_SCK */
1951	RCAR_GP_PIN(0, 17),
1952};
1953static const unsigned int msiof2_clk_mux[] = {
1954	MSIOF2_SCK_MARK,
1955};
1956static const unsigned int msiof2_sync_pins[] = {
1957	/* MSIOF2_SYNC */
1958	RCAR_GP_PIN(0, 15),
1959};
1960static const unsigned int msiof2_sync_mux[] = {
1961	MSIOF2_SYNC_MARK,
1962};
1963static const unsigned int msiof2_ss1_pins[] = {
1964	/* MSIOF2_SS1 */
1965	RCAR_GP_PIN(0, 14),
1966};
1967static const unsigned int msiof2_ss1_mux[] = {
1968	MSIOF2_SS1_MARK,
1969};
1970static const unsigned int msiof2_ss2_pins[] = {
1971	/* MSIOF2_SS2 */
1972	RCAR_GP_PIN(0, 13),
1973};
1974static const unsigned int msiof2_ss2_mux[] = {
1975	MSIOF2_SS2_MARK,
1976};
1977static const unsigned int msiof2_txd_pins[] = {
1978	/* MSIOF2_TXD */
1979	RCAR_GP_PIN(0, 16),
1980};
1981static const unsigned int msiof2_txd_mux[] = {
1982	MSIOF2_TXD_MARK,
1983};
1984static const unsigned int msiof2_rxd_pins[] = {
1985	/* MSIOF2_RXD */
1986	RCAR_GP_PIN(0, 18),
1987};
1988static const unsigned int msiof2_rxd_mux[] = {
1989	MSIOF2_RXD_MARK,
1990};
1991
1992/* - MSIOF3 ----------------------------------------------------------------- */
1993static const unsigned int msiof3_clk_pins[] = {
1994	/* MSIOF3_SCK */
1995	RCAR_GP_PIN(0, 3),
1996};
1997static const unsigned int msiof3_clk_mux[] = {
1998	MSIOF3_SCK_MARK,
1999};
2000static const unsigned int msiof3_sync_pins[] = {
2001	/* MSIOF3_SYNC */
2002	RCAR_GP_PIN(0, 6),
2003};
2004static const unsigned int msiof3_sync_mux[] = {
2005	MSIOF3_SYNC_MARK,
2006};
2007static const unsigned int msiof3_ss1_pins[] = {
2008	/* MSIOF3_SS1 */
2009	RCAR_GP_PIN(0, 1),
2010};
2011static const unsigned int msiof3_ss1_mux[] = {
2012	MSIOF3_SS1_MARK,
2013};
2014static const unsigned int msiof3_ss2_pins[] = {
2015	/* MSIOF3_SS2 */
2016	RCAR_GP_PIN(0, 2),
2017};
2018static const unsigned int msiof3_ss2_mux[] = {
2019	MSIOF3_SS2_MARK,
2020};
2021static const unsigned int msiof3_txd_pins[] = {
2022	/* MSIOF3_TXD */
2023	RCAR_GP_PIN(0, 4),
2024};
2025static const unsigned int msiof3_txd_mux[] = {
2026	MSIOF3_TXD_MARK,
2027};
2028static const unsigned int msiof3_rxd_pins[] = {
2029	/* MSIOF3_RXD */
2030	RCAR_GP_PIN(0, 5),
2031};
2032static const unsigned int msiof3_rxd_mux[] = {
2033	MSIOF3_RXD_MARK,
2034};
2035
2036/* - MSIOF4 ----------------------------------------------------------------- */
2037static const unsigned int msiof4_clk_pins[] = {
2038	/* MSIOF4_SCK */
2039	RCAR_GP_PIN(1, 25),
2040};
2041static const unsigned int msiof4_clk_mux[] = {
2042	MSIOF4_SCK_MARK,
2043};
2044static const unsigned int msiof4_sync_pins[] = {
2045	/* MSIOF4_SYNC */
2046	RCAR_GP_PIN(1, 28),
2047};
2048static const unsigned int msiof4_sync_mux[] = {
2049	MSIOF4_SYNC_MARK,
2050};
2051static const unsigned int msiof4_ss1_pins[] = {
2052	/* MSIOF4_SS1 */
2053	RCAR_GP_PIN(1, 23),
2054};
2055static const unsigned int msiof4_ss1_mux[] = {
2056	MSIOF4_SS1_MARK,
2057};
2058static const unsigned int msiof4_ss2_pins[] = {
2059	/* MSIOF4_SS2 */
2060	RCAR_GP_PIN(1, 24),
2061};
2062static const unsigned int msiof4_ss2_mux[] = {
2063	MSIOF4_SS2_MARK,
2064};
2065static const unsigned int msiof4_txd_pins[] = {
2066	/* MSIOF4_TXD */
2067	RCAR_GP_PIN(1, 26),
2068};
2069static const unsigned int msiof4_txd_mux[] = {
2070	MSIOF4_TXD_MARK,
2071};
2072static const unsigned int msiof4_rxd_pins[] = {
2073	/* MSIOF4_RXD */
2074	RCAR_GP_PIN(1, 27),
2075};
2076static const unsigned int msiof4_rxd_mux[] = {
2077	MSIOF4_RXD_MARK,
2078};
2079
2080/* - MSIOF5 ----------------------------------------------------------------- */
2081static const unsigned int msiof5_clk_pins[] = {
2082	/* MSIOF5_SCK */
2083	RCAR_GP_PIN(0, 11),
2084};
2085static const unsigned int msiof5_clk_mux[] = {
2086	MSIOF5_SCK_MARK,
2087};
2088static const unsigned int msiof5_sync_pins[] = {
2089	/* MSIOF5_SYNC */
2090	RCAR_GP_PIN(0, 9),
2091};
2092static const unsigned int msiof5_sync_mux[] = {
2093	MSIOF5_SYNC_MARK,
2094};
2095static const unsigned int msiof5_ss1_pins[] = {
2096	/* MSIOF5_SS1 */
2097	RCAR_GP_PIN(0, 8),
2098};
2099static const unsigned int msiof5_ss1_mux[] = {
2100	MSIOF5_SS1_MARK,
2101};
2102static const unsigned int msiof5_ss2_pins[] = {
2103	/* MSIOF5_SS2 */
2104	RCAR_GP_PIN(0, 7),
2105};
2106static const unsigned int msiof5_ss2_mux[] = {
2107	MSIOF5_SS2_MARK,
2108};
2109static const unsigned int msiof5_txd_pins[] = {
2110	/* MSIOF5_TXD */
2111	RCAR_GP_PIN(0, 10),
2112};
2113static const unsigned int msiof5_txd_mux[] = {
2114	MSIOF5_TXD_MARK,
2115};
2116static const unsigned int msiof5_rxd_pins[] = {
2117	/* MSIOF5_RXD */
2118	RCAR_GP_PIN(0, 12),
2119};
2120static const unsigned int msiof5_rxd_mux[] = {
2121	MSIOF5_RXD_MARK,
2122};
2123
2124/* - PCIE ------------------------------------------------------------------- */
2125static const unsigned int pcie0_clkreq_n_pins[] = {
2126	/* PCIE0_CLKREQ_N */
2127	RCAR_GP_PIN(4, 21),
2128};
2129
2130static const unsigned int pcie0_clkreq_n_mux[] = {
2131	PCIE0_CLKREQ_N_MARK,
2132};
2133
2134static const unsigned int pcie1_clkreq_n_pins[] = {
2135	/* PCIE1_CLKREQ_N */
2136	RCAR_GP_PIN(4, 22),
2137};
2138
2139static const unsigned int pcie1_clkreq_n_mux[] = {
2140	PCIE1_CLKREQ_N_MARK,
2141};
2142
2143/* - PWM0 ------------------------------------------------------------------- */
2144static const unsigned int pwm0_pins[] = {
2145	/* PWM0 */
2146	RCAR_GP_PIN(1, 15),
2147};
2148static const unsigned int pwm0_mux[] = {
2149	PWM0_MARK,
2150};
2151
2152/* - PWM1 ------------------------------------------------------------------- */
2153static const unsigned int pwm1_a_pins[] = {
2154	/* PWM1_A */
2155	RCAR_GP_PIN(3, 13),
2156};
2157static const unsigned int pwm1_a_mux[] = {
2158	PWM1_A_MARK,
2159};
2160
2161static const unsigned int pwm1_b_pins[] = {
2162	/* PWM1_B */
2163	RCAR_GP_PIN(2, 13),
2164};
2165static const unsigned int pwm1_b_mux[] = {
2166	PWM1_B_MARK,
2167};
2168
2169/* - PWM2 ------------------------------------------------------------------- */
2170static const unsigned int pwm2_pins[] = {
2171	/* PWM2 */
2172	RCAR_GP_PIN(2, 14),
2173};
2174static const unsigned int pwm2_mux[] = {
2175	PWM2_MARK,
2176};
2177
2178/* - PWM3 ------------------------------------------------------------------- */
2179static const unsigned int pwm3_a_pins[] = {
2180	/* PWM3_A */
2181	RCAR_GP_PIN(1, 22),
2182};
2183static const unsigned int pwm3_a_mux[] = {
2184	PWM3_A_MARK,
2185};
2186
2187static const unsigned int pwm3_b_pins[] = {
2188	/* PWM3_B */
2189	RCAR_GP_PIN(2, 15),
2190};
2191static const unsigned int pwm3_b_mux[] = {
2192	PWM3_B_MARK,
2193};
2194
2195/* - PWM4 ------------------------------------------------------------------- */
2196static const unsigned int pwm4_pins[] = {
2197	/* PWM4 */
2198	RCAR_GP_PIN(2, 16),
2199};
2200static const unsigned int pwm4_mux[] = {
2201	PWM4_MARK,
2202};
2203
2204/* - PWM5 ------------------------------------------------------------------- */
2205static const unsigned int pwm5_pins[] = {
2206	/* PWM5 */
2207	RCAR_GP_PIN(2, 17),
2208};
2209static const unsigned int pwm5_mux[] = {
2210	PWM5_MARK,
2211};
2212
2213/* - PWM6 ------------------------------------------------------------------- */
2214static const unsigned int pwm6_pins[] = {
2215	/* PWM6 */
2216	RCAR_GP_PIN(2, 18),
2217};
2218static const unsigned int pwm6_mux[] = {
2219	PWM6_MARK,
2220};
2221
2222/* - PWM7 ------------------------------------------------------------------- */
2223static const unsigned int pwm7_pins[] = {
2224	/* PWM7 */
2225	RCAR_GP_PIN(2, 19),
2226};
2227static const unsigned int pwm7_mux[] = {
2228	PWM7_MARK,
2229};
2230
2231/* - PWM8 ------------------------------------------------------------------- */
2232static const unsigned int pwm8_pins[] = {
2233	/* PWM8 */
2234	RCAR_GP_PIN(1, 13),
2235};
2236static const unsigned int pwm8_mux[] = {
2237	PWM8_MARK,
2238};
2239
2240/* - PWM9 ------------------------------------------------------------------- */
2241static const unsigned int pwm9_pins[] = {
2242	/* PWM9 */
2243	RCAR_GP_PIN(1, 14),
2244};
2245static const unsigned int pwm9_mux[] = {
2246	PWM9_MARK,
2247};
2248
2249/* - QSPI0 ------------------------------------------------------------------ */
2250static const unsigned int qspi0_ctrl_pins[] = {
2251	/* SPCLK, SSL */
2252	RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2253};
2254static const unsigned int qspi0_ctrl_mux[] = {
2255	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2256};
2257static const unsigned int qspi0_data_pins[] = {
2258	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2259	RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2260	RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2261};
2262static const unsigned int qspi0_data_mux[] = {
2263	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2264	QSPI0_IO2_MARK, QSPI0_IO3_MARK
2265};
2266
2267/* - QSPI1 ------------------------------------------------------------------ */
2268static const unsigned int qspi1_ctrl_pins[] = {
2269	/* SPCLK, SSL */
2270	RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2271};
2272static const unsigned int qspi1_ctrl_mux[] = {
2273	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2274};
2275static const unsigned int qspi1_data_pins[] = {
2276	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2277	RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2278	RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2279};
2280static const unsigned int qspi1_data_mux[] = {
2281	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2282	QSPI1_IO2_MARK, QSPI1_IO3_MARK
2283};
2284
2285/* - SCIF0 ------------------------------------------------------------------ */
2286static const unsigned int scif0_data_pins[] = {
2287	/* RX0, TX0 */
2288	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2289};
2290static const unsigned int scif0_data_mux[] = {
2291	RX0_MARK, TX0_MARK,
2292};
2293static const unsigned int scif0_clk_pins[] = {
2294	/* SCK0 */
2295	RCAR_GP_PIN(1, 15),
2296};
2297static const unsigned int scif0_clk_mux[] = {
2298	SCK0_MARK,
2299};
2300static const unsigned int scif0_ctrl_pins[] = {
2301	/* RTS0_N, CTS0_N */
2302	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2303};
2304static const unsigned int scif0_ctrl_mux[] = {
2305	RTS0_N_MARK, CTS0_N_MARK,
2306};
2307
2308/* - SCIF1 ------------------------------------------------------------------ */
2309static const unsigned int scif1_data_a_pins[] = {
2310	/* RX1_A, TX1_A */
2311	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2312};
2313static const unsigned int scif1_data_a_mux[] = {
2314	RX1_A_MARK, TX1_A_MARK,
2315};
2316static const unsigned int scif1_clk_a_pins[] = {
2317	/* SCK1_A */
2318	RCAR_GP_PIN(0, 18),
2319};
2320static const unsigned int scif1_clk_a_mux[] = {
2321	SCK1_A_MARK,
2322};
2323static const unsigned int scif1_ctrl_a_pins[] = {
2324	/* RTS1_N_A, CTS1_N_A */
2325	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2326};
2327static const unsigned int scif1_ctrl_a_mux[] = {
2328	RTS1_N_A_MARK, CTS1_N_A_MARK,
2329};
2330
2331static const unsigned int scif1_data_b_pins[] = {
2332	/* RX1_B, TX1_B */
2333	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2334};
2335static const unsigned int scif1_data_b_mux[] = {
2336	RX1_B_MARK, TX1_B_MARK,
2337};
2338static const unsigned int scif1_clk_b_pins[] = {
2339	/* SCK1_B */
2340	RCAR_GP_PIN(1, 10),
2341};
2342static const unsigned int scif1_clk_b_mux[] = {
2343	SCK1_B_MARK,
2344};
2345static const unsigned int scif1_ctrl_b_pins[] = {
2346	/* RTS1_N_B, CTS1_N_B */
2347	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2348};
2349static const unsigned int scif1_ctrl_b_mux[] = {
2350	RTS1_N_B_MARK, CTS1_N_B_MARK,
2351};
2352
2353/* - SCIF3 ------------------------------------------------------------------ */
2354static const unsigned int scif3_data_a_pins[] = {
2355	/* RX3_A, TX3_A */
2356	RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2357};
2358static const unsigned int scif3_data_a_mux[] = {
2359	RX3_A_MARK, TX3_A_MARK,
2360};
2361static const unsigned int scif3_clk_a_pins[] = {
2362	/* SCK3_A */
2363	RCAR_GP_PIN(1, 24),
2364};
2365static const unsigned int scif3_clk_a_mux[] = {
2366	SCK3_A_MARK,
2367};
2368static const unsigned int scif3_ctrl_a_pins[] = {
2369	/* RTS3_N_A, CTS3_N_A */
2370	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2371};
2372static const unsigned int scif3_ctrl_a_mux[] = {
2373	RTS3_N_A_MARK, CTS3_N_A_MARK,
2374};
2375
2376static const unsigned int scif3_data_b_pins[] = {
2377	/* RX3_B, TX3_B */
2378	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2379};
2380static const unsigned int scif3_data_b_mux[] = {
2381	RX3_B_MARK, TX3_B_MARK,
2382};
2383static const unsigned int scif3_clk_b_pins[] = {
2384	/* SCK3_B */
2385	RCAR_GP_PIN(1, 4),
2386};
2387static const unsigned int scif3_clk_b_mux[] = {
2388	SCK3_B_MARK,
2389};
2390static const unsigned int scif3_ctrl_b_pins[] = {
2391	/* RTS3_N_B, CTS3_N_B */
2392	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2393};
2394static const unsigned int scif3_ctrl_b_mux[] = {
2395	RTS3_N_B_MARK, CTS3_N_B_MARK,
2396};
2397
2398/* - SCIF4 ------------------------------------------------------------------ */
2399static const unsigned int scif4_data_pins[] = {
2400	/* RX4, TX4 */
2401	RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2402};
2403static const unsigned int scif4_data_mux[] = {
2404	RX4_MARK, TX4_MARK,
2405};
2406static const unsigned int scif4_clk_pins[] = {
2407	/* SCK4 */
2408	RCAR_GP_PIN(8, 8),
2409};
2410static const unsigned int scif4_clk_mux[] = {
2411	SCK4_MARK,
2412};
2413static const unsigned int scif4_ctrl_pins[] = {
2414	/* RTS4_N, CTS4_N */
2415	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2416};
2417static const unsigned int scif4_ctrl_mux[] = {
2418	RTS4_N_MARK, CTS4_N_MARK,
2419};
2420
2421/* - SCIF Clock ------------------------------------------------------------- */
2422static const unsigned int scif_clk_pins[] = {
2423	/* SCIF_CLK */
2424	RCAR_GP_PIN(1, 17),
2425};
2426static const unsigned int scif_clk_mux[] = {
2427	SCIF_CLK_MARK,
2428};
2429
2430static const unsigned int scif_clk2_pins[] = {
2431	/* SCIF_CLK2 */
2432	RCAR_GP_PIN(8, 11),
2433};
2434static const unsigned int scif_clk2_mux[] = {
2435	SCIF_CLK2_MARK,
2436};
2437
2438/* - SSI ------------------------------------------------- */
2439static const unsigned int ssi_data_pins[] = {
2440	/* SSI_SD */
2441	RCAR_GP_PIN(1, 20),
2442};
2443static const unsigned int ssi_data_mux[] = {
2444	SSI_SD_MARK,
2445};
2446static const unsigned int ssi_ctrl_pins[] = {
2447	/* SSI_SCK,  SSI_WS */
2448	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2449};
2450static const unsigned int ssi_ctrl_mux[] = {
2451	SSI_SCK_MARK, SSI_WS_MARK,
2452};
2453
2454/* - TPU -------------------------------------------------------------------- */
2455static const unsigned int tpu_to0_a_pins[] = {
2456	/* TPU0TO0_A */
2457	RCAR_GP_PIN(2, 8),
2458};
2459static const unsigned int tpu_to0_a_mux[] = {
2460	TPU0TO0_A_MARK,
2461};
2462static const unsigned int tpu_to1_a_pins[] = {
2463	/* TPU0TO1_A */
2464	RCAR_GP_PIN(2, 7),
2465};
2466static const unsigned int tpu_to1_a_mux[] = {
2467	TPU0TO1_A_MARK,
2468};
2469static const unsigned int tpu_to2_a_pins[] = {
2470	/* TPU0TO2_A */
2471	RCAR_GP_PIN(2, 12),
2472};
2473static const unsigned int tpu_to2_a_mux[] = {
2474	TPU0TO2_A_MARK,
2475};
2476static const unsigned int tpu_to3_a_pins[] = {
2477	/* TPU0TO3_A */
2478	RCAR_GP_PIN(2, 13),
2479};
2480static const unsigned int tpu_to3_a_mux[] = {
2481	TPU0TO3_A_MARK,
2482};
2483
2484static const unsigned int tpu_to0_b_pins[] = {
2485	/* TPU0TO0_B */
2486	RCAR_GP_PIN(1, 25),
2487};
2488static const unsigned int tpu_to0_b_mux[] = {
2489	TPU0TO0_B_MARK,
2490};
2491static const unsigned int tpu_to1_b_pins[] = {
2492	/* TPU0TO1_B */
2493	RCAR_GP_PIN(1, 26),
2494};
2495static const unsigned int tpu_to1_b_mux[] = {
2496	TPU0TO1_B_MARK,
2497};
2498static const unsigned int tpu_to2_b_pins[] = {
2499	/* TPU0TO2_B */
2500	RCAR_GP_PIN(2, 0),
2501};
2502static const unsigned int tpu_to2_b_mux[] = {
2503	TPU0TO2_B_MARK,
2504};
2505static const unsigned int tpu_to3_b_pins[] = {
2506	/* TPU0TO3_B */
2507	RCAR_GP_PIN(2, 1),
2508};
2509static const unsigned int tpu_to3_b_mux[] = {
2510	TPU0TO3_B_MARK,
2511};
2512
2513/* - TSN0 ------------------------------------------------ */
2514static const unsigned int tsn0_link_pins[] = {
2515	/* TSN0_LINK */
2516	RCAR_GP_PIN(4, 4),
2517};
2518static const unsigned int tsn0_link_mux[] = {
2519	TSN0_LINK_MARK,
2520};
2521static const unsigned int tsn0_phy_int_pins[] = {
2522	/* TSN0_PHY_INT */
2523	RCAR_GP_PIN(4, 3),
2524};
2525static const unsigned int tsn0_phy_int_mux[] = {
2526	TSN0_PHY_INT_MARK,
2527};
2528static const unsigned int tsn0_mdio_pins[] = {
2529	/* TSN0_MDC, TSN0_MDIO */
2530	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2531};
2532static const unsigned int tsn0_mdio_mux[] = {
2533	TSN0_MDC_MARK, TSN0_MDIO_MARK,
2534};
2535static const unsigned int tsn0_rgmii_pins[] = {
2536	/*
2537	 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2538	 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2539	 */
2540	RCAR_GP_PIN(4,  9), RCAR_GP_PIN(4, 12),
2541	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2542	RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2543	RCAR_GP_PIN(4,  7), RCAR_GP_PIN(4, 11),
2544	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2545	RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2546};
2547static const unsigned int tsn0_rgmii_mux[] = {
2548	TSN0_TX_CTL_MARK,	TSN0_TXC_MARK,
2549	TSN0_TD0_MARK,		TSN0_TD1_MARK,
2550	TSN0_TD2_MARK,		TSN0_TD3_MARK,
2551	TSN0_RX_CTL_MARK,	TSN0_RXC_MARK,
2552	TSN0_RD0_MARK,		TSN0_RD1_MARK,
2553	TSN0_RD2_MARK,		TSN0_RD3_MARK,
2554};
2555static const unsigned int tsn0_txcrefclk_pins[] = {
2556	/* TSN0_TXCREFCLK */
2557	RCAR_GP_PIN(4, 20),
2558};
2559static const unsigned int tsn0_txcrefclk_mux[] = {
2560	TSN0_TXCREFCLK_MARK,
2561};
2562static const unsigned int tsn0_avtp_pps_pins[] = {
2563	/* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2564	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2565};
2566static const unsigned int tsn0_avtp_pps_mux[] = {
2567	TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2568};
2569static const unsigned int tsn0_avtp_capture_pins[] = {
2570	/* TSN0_AVTP_CAPTURE */
2571	RCAR_GP_PIN(4, 6),
2572};
2573static const unsigned int tsn0_avtp_capture_mux[] = {
2574	TSN0_AVTP_CAPTURE_MARK,
2575};
2576static const unsigned int tsn0_avtp_match_pins[] = {
2577	/* TSN0_AVTP_MATCH */
2578	RCAR_GP_PIN(4, 5),
2579};
2580static const unsigned int tsn0_avtp_match_mux[] = {
2581	TSN0_AVTP_MATCH_MARK,
2582};
2583
2584static const struct sh_pfc_pin_group pinmux_groups[] = {
2585	SH_PFC_PIN_GROUP(audio_clkin),
2586	SH_PFC_PIN_GROUP(audio_clkout),
2587
2588	SH_PFC_PIN_GROUP(avb0_link),
2589	SH_PFC_PIN_GROUP(avb0_magic),
2590	SH_PFC_PIN_GROUP(avb0_phy_int),
2591	SH_PFC_PIN_GROUP(avb0_mdio),
2592	SH_PFC_PIN_GROUP(avb0_rgmii),
2593	SH_PFC_PIN_GROUP(avb0_txcrefclk),
2594	SH_PFC_PIN_GROUP(avb0_avtp_pps),
2595	SH_PFC_PIN_GROUP(avb0_avtp_capture),
2596	SH_PFC_PIN_GROUP(avb0_avtp_match),
2597
2598	SH_PFC_PIN_GROUP(avb1_link),
2599	SH_PFC_PIN_GROUP(avb1_magic),
2600	SH_PFC_PIN_GROUP(avb1_phy_int),
2601	SH_PFC_PIN_GROUP(avb1_mdio),
2602	SH_PFC_PIN_GROUP(avb1_rgmii),
2603	SH_PFC_PIN_GROUP(avb1_txcrefclk),
2604	SH_PFC_PIN_GROUP(avb1_avtp_pps),
2605	SH_PFC_PIN_GROUP(avb1_avtp_capture),
2606	SH_PFC_PIN_GROUP(avb1_avtp_match),
2607
2608	SH_PFC_PIN_GROUP(avb2_link),
2609	SH_PFC_PIN_GROUP(avb2_magic),
2610	SH_PFC_PIN_GROUP(avb2_phy_int),
2611	SH_PFC_PIN_GROUP(avb2_mdio),
2612	SH_PFC_PIN_GROUP(avb2_rgmii),
2613	SH_PFC_PIN_GROUP(avb2_txcrefclk),
2614	SH_PFC_PIN_GROUP(avb2_avtp_pps),
2615	SH_PFC_PIN_GROUP(avb2_avtp_capture),
2616	SH_PFC_PIN_GROUP(avb2_avtp_match),
2617
2618	SH_PFC_PIN_GROUP(canfd0_data),
2619	SH_PFC_PIN_GROUP(canfd1_data),
2620	SH_PFC_PIN_GROUP(canfd2_data),
2621	SH_PFC_PIN_GROUP(canfd3_data),
2622	SH_PFC_PIN_GROUP(canfd4_data),
2623	SH_PFC_PIN_GROUP(canfd5_data_a),
2624	SH_PFC_PIN_GROUP(canfd5_data_b),
2625	SH_PFC_PIN_GROUP(canfd6_data),
2626	SH_PFC_PIN_GROUP(canfd7_data),
2627	SH_PFC_PIN_GROUP(can_clk),
2628
2629	SH_PFC_PIN_GROUP(hscif0_data),
2630	SH_PFC_PIN_GROUP(hscif0_clk),
2631	SH_PFC_PIN_GROUP(hscif0_ctrl),
2632	SH_PFC_PIN_GROUP(hscif1_data_a),
2633	SH_PFC_PIN_GROUP(hscif1_clk_a),
2634	SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2635	SH_PFC_PIN_GROUP(hscif1_data_b),
2636	SH_PFC_PIN_GROUP(hscif1_clk_b),
2637	SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2638	SH_PFC_PIN_GROUP(hscif2_data),
2639	SH_PFC_PIN_GROUP(hscif2_clk),
2640	SH_PFC_PIN_GROUP(hscif2_ctrl),
2641	SH_PFC_PIN_GROUP(hscif3_data_a),
2642	SH_PFC_PIN_GROUP(hscif3_clk_a),
2643	SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2644	SH_PFC_PIN_GROUP(hscif3_data_b),
2645	SH_PFC_PIN_GROUP(hscif3_clk_b),
2646	SH_PFC_PIN_GROUP(hscif3_ctrl_b),
2647
2648	SH_PFC_PIN_GROUP(i2c0),
2649	SH_PFC_PIN_GROUP(i2c1),
2650	SH_PFC_PIN_GROUP(i2c2),
2651	SH_PFC_PIN_GROUP(i2c3),
2652	SH_PFC_PIN_GROUP(i2c4),
2653	SH_PFC_PIN_GROUP(i2c5),
2654
2655	SH_PFC_PIN_GROUP(intc_ex_irq0_a),
2656	SH_PFC_PIN_GROUP(intc_ex_irq0_b),
2657	SH_PFC_PIN_GROUP(intc_ex_irq1_a),
2658	SH_PFC_PIN_GROUP(intc_ex_irq1_b),
2659	SH_PFC_PIN_GROUP(intc_ex_irq2_a),
2660	SH_PFC_PIN_GROUP(intc_ex_irq2_b),
2661	SH_PFC_PIN_GROUP(intc_ex_irq3_a),
2662	SH_PFC_PIN_GROUP(intc_ex_irq3_b),
2663	SH_PFC_PIN_GROUP(intc_ex_irq4_a),
2664	SH_PFC_PIN_GROUP(intc_ex_irq4_b),
2665	SH_PFC_PIN_GROUP(intc_ex_irq5),
2666
2667	BUS_DATA_PIN_GROUP(mmc_data, 1),
2668	BUS_DATA_PIN_GROUP(mmc_data, 4),
2669	BUS_DATA_PIN_GROUP(mmc_data, 8),
2670	SH_PFC_PIN_GROUP(mmc_ctrl),
2671	SH_PFC_PIN_GROUP(mmc_cd),
2672	SH_PFC_PIN_GROUP(mmc_wp),
2673	SH_PFC_PIN_GROUP(mmc_ds),
2674
2675	SH_PFC_PIN_GROUP(msiof0_clk),
2676	SH_PFC_PIN_GROUP(msiof0_sync),
2677	SH_PFC_PIN_GROUP(msiof0_ss1),
2678	SH_PFC_PIN_GROUP(msiof0_ss2),
2679	SH_PFC_PIN_GROUP(msiof0_txd),
2680	SH_PFC_PIN_GROUP(msiof0_rxd),
2681
2682	SH_PFC_PIN_GROUP(msiof1_clk),
2683	SH_PFC_PIN_GROUP(msiof1_sync),
2684	SH_PFC_PIN_GROUP(msiof1_ss1),
2685	SH_PFC_PIN_GROUP(msiof1_ss2),
2686	SH_PFC_PIN_GROUP(msiof1_txd),
2687	SH_PFC_PIN_GROUP(msiof1_rxd),
2688
2689	SH_PFC_PIN_GROUP(msiof2_clk),
2690	SH_PFC_PIN_GROUP(msiof2_sync),
2691	SH_PFC_PIN_GROUP(msiof2_ss1),
2692	SH_PFC_PIN_GROUP(msiof2_ss2),
2693	SH_PFC_PIN_GROUP(msiof2_txd),
2694	SH_PFC_PIN_GROUP(msiof2_rxd),
2695
2696	SH_PFC_PIN_GROUP(msiof3_clk),
2697	SH_PFC_PIN_GROUP(msiof3_sync),
2698	SH_PFC_PIN_GROUP(msiof3_ss1),
2699	SH_PFC_PIN_GROUP(msiof3_ss2),
2700	SH_PFC_PIN_GROUP(msiof3_txd),
2701	SH_PFC_PIN_GROUP(msiof3_rxd),
2702
2703	SH_PFC_PIN_GROUP(msiof4_clk),
2704	SH_PFC_PIN_GROUP(msiof4_sync),
2705	SH_PFC_PIN_GROUP(msiof4_ss1),
2706	SH_PFC_PIN_GROUP(msiof4_ss2),
2707	SH_PFC_PIN_GROUP(msiof4_txd),
2708	SH_PFC_PIN_GROUP(msiof4_rxd),
2709
2710	SH_PFC_PIN_GROUP(msiof5_clk),
2711	SH_PFC_PIN_GROUP(msiof5_sync),
2712	SH_PFC_PIN_GROUP(msiof5_ss1),
2713	SH_PFC_PIN_GROUP(msiof5_ss2),
2714	SH_PFC_PIN_GROUP(msiof5_txd),
2715	SH_PFC_PIN_GROUP(msiof5_rxd),
2716
2717	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2718	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2719
2720	SH_PFC_PIN_GROUP(pwm0),
2721	SH_PFC_PIN_GROUP(pwm1_a),
2722	SH_PFC_PIN_GROUP(pwm1_b),
2723	SH_PFC_PIN_GROUP(pwm2),
2724	SH_PFC_PIN_GROUP(pwm3_a),
2725	SH_PFC_PIN_GROUP(pwm3_b),
2726	SH_PFC_PIN_GROUP(pwm4),
2727	SH_PFC_PIN_GROUP(pwm5),
2728	SH_PFC_PIN_GROUP(pwm6),
2729	SH_PFC_PIN_GROUP(pwm7),
2730	SH_PFC_PIN_GROUP(pwm8),
2731	SH_PFC_PIN_GROUP(pwm9),
2732
2733	SH_PFC_PIN_GROUP(qspi0_ctrl),
2734	BUS_DATA_PIN_GROUP(qspi0_data, 2),
2735	BUS_DATA_PIN_GROUP(qspi0_data, 4),
2736	SH_PFC_PIN_GROUP(qspi1_ctrl),
2737	BUS_DATA_PIN_GROUP(qspi1_data, 2),
2738	BUS_DATA_PIN_GROUP(qspi1_data, 4),
2739
2740	SH_PFC_PIN_GROUP(scif0_data),
2741	SH_PFC_PIN_GROUP(scif0_clk),
2742	SH_PFC_PIN_GROUP(scif0_ctrl),
2743	SH_PFC_PIN_GROUP(scif1_data_a),
2744	SH_PFC_PIN_GROUP(scif1_clk_a),
2745	SH_PFC_PIN_GROUP(scif1_ctrl_a),
2746	SH_PFC_PIN_GROUP(scif1_data_b),
2747	SH_PFC_PIN_GROUP(scif1_clk_b),
2748	SH_PFC_PIN_GROUP(scif1_ctrl_b),
2749	SH_PFC_PIN_GROUP(scif3_data_a),
2750	SH_PFC_PIN_GROUP(scif3_clk_a),
2751	SH_PFC_PIN_GROUP(scif3_ctrl_a),
2752	SH_PFC_PIN_GROUP(scif3_data_b),
2753	SH_PFC_PIN_GROUP(scif3_clk_b),
2754	SH_PFC_PIN_GROUP(scif3_ctrl_b),
2755	SH_PFC_PIN_GROUP(scif4_data),
2756	SH_PFC_PIN_GROUP(scif4_clk),
2757	SH_PFC_PIN_GROUP(scif4_ctrl),
2758	SH_PFC_PIN_GROUP(scif_clk),
2759	SH_PFC_PIN_GROUP(scif_clk2),
2760
2761	SH_PFC_PIN_GROUP(ssi_data),
2762	SH_PFC_PIN_GROUP(ssi_ctrl),
2763
2764	SH_PFC_PIN_GROUP(tpu_to0_a),
2765	SH_PFC_PIN_GROUP(tpu_to0_b),
2766	SH_PFC_PIN_GROUP(tpu_to1_a),
2767	SH_PFC_PIN_GROUP(tpu_to1_b),
2768	SH_PFC_PIN_GROUP(tpu_to2_a),
2769	SH_PFC_PIN_GROUP(tpu_to2_b),
2770	SH_PFC_PIN_GROUP(tpu_to3_a),
2771	SH_PFC_PIN_GROUP(tpu_to3_b),
2772
2773	SH_PFC_PIN_GROUP(tsn0_link),
2774	SH_PFC_PIN_GROUP(tsn0_phy_int),
2775	SH_PFC_PIN_GROUP(tsn0_mdio),
2776	SH_PFC_PIN_GROUP(tsn0_rgmii),
2777	SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2778	SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2779	SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2780	SH_PFC_PIN_GROUP(tsn0_avtp_match),
2781};
2782
2783static const char * const audio_clk_groups[] = {
2784	"audio_clkin",
2785	"audio_clkout",
2786};
2787
2788static const char * const avb0_groups[] = {
2789	"avb0_link",
2790	"avb0_magic",
2791	"avb0_phy_int",
2792	"avb0_mdio",
2793	"avb0_rgmii",
2794	"avb0_txcrefclk",
2795	"avb0_avtp_pps",
2796	"avb0_avtp_capture",
2797	"avb0_avtp_match",
2798};
2799
2800static const char * const avb1_groups[] = {
2801	"avb1_link",
2802	"avb1_magic",
2803	"avb1_phy_int",
2804	"avb1_mdio",
2805	"avb1_rgmii",
2806	"avb1_txcrefclk",
2807	"avb1_avtp_pps",
2808	"avb1_avtp_capture",
2809	"avb1_avtp_match",
2810};
2811
2812static const char * const avb2_groups[] = {
2813	"avb2_link",
2814	"avb2_magic",
2815	"avb2_phy_int",
2816	"avb2_mdio",
2817	"avb2_rgmii",
2818	"avb2_txcrefclk",
2819	"avb2_avtp_pps",
2820	"avb2_avtp_capture",
2821	"avb2_avtp_match",
2822};
2823
2824static const char * const canfd0_groups[] = {
2825	"canfd0_data",
2826};
2827
2828static const char * const canfd1_groups[] = {
2829	"canfd1_data",
2830};
2831
2832static const char * const canfd2_groups[] = {
2833	"canfd2_data",
2834};
2835
2836static const char * const canfd3_groups[] = {
2837	"canfd3_data",
2838};
2839
2840static const char * const canfd4_groups[] = {
2841	"canfd4_data",
2842};
2843
2844static const char * const canfd5_groups[] = {
2845	"canfd5_data_a",
2846	"canfd5_data_b",
2847};
2848
2849static const char * const canfd6_groups[] = {
2850	"canfd6_data",
2851};
2852
2853static const char * const canfd7_groups[] = {
2854	"canfd7_data",
2855};
2856
2857static const char * const can_clk_groups[] = {
2858	"can_clk",
2859};
2860
2861static const char * const hscif0_groups[] = {
2862	"hscif0_data",
2863	"hscif0_clk",
2864	"hscif0_ctrl",
2865};
2866
2867static const char * const hscif1_groups[] = {
2868	"hscif1_data_a",
2869	"hscif1_clk_a",
2870	"hscif1_ctrl_a",
2871	"hscif1_data_b",
2872	"hscif1_clk_b",
2873	"hscif1_ctrl_b",
2874};
2875
2876static const char * const hscif2_groups[] = {
2877	"hscif2_data",
2878	"hscif2_clk",
2879	"hscif2_ctrl",
2880};
2881
2882static const char * const hscif3_groups[] = {
2883	"hscif3_data_a",
2884	"hscif3_clk_a",
2885	"hscif3_ctrl_a",
2886	"hscif3_data_b",
2887	"hscif3_clk_b",
2888	"hscif3_ctrl_b",
2889};
2890
2891static const char * const i2c0_groups[] = {
2892	"i2c0",
2893};
2894
2895static const char * const i2c1_groups[] = {
2896	"i2c1",
2897};
2898
2899static const char * const i2c2_groups[] = {
2900	"i2c2",
2901};
2902
2903static const char * const i2c3_groups[] = {
2904	"i2c3",
2905};
2906
2907static const char * const i2c4_groups[] = {
2908	"i2c4",
2909};
2910
2911static const char * const i2c5_groups[] = {
2912	"i2c5",
2913};
2914
2915static const char * const intc_ex_groups[] = {
2916	"intc_ex_irq0_a",
2917	"intc_ex_irq0_b",
2918	"intc_ex_irq1_a",
2919	"intc_ex_irq1_b",
2920	"intc_ex_irq2_a",
2921	"intc_ex_irq2_b",
2922	"intc_ex_irq3_a",
2923	"intc_ex_irq3_b",
2924	"intc_ex_irq4_a",
2925	"intc_ex_irq4_b",
2926	"intc_ex_irq5",
2927};
2928
2929static const char * const mmc_groups[] = {
2930	"mmc_data1",
2931	"mmc_data4",
2932	"mmc_data8",
2933	"mmc_ctrl",
2934	"mmc_cd",
2935	"mmc_wp",
2936	"mmc_ds",
2937};
2938
2939static const char * const msiof0_groups[] = {
2940	"msiof0_clk",
2941	"msiof0_sync",
2942	"msiof0_ss1",
2943	"msiof0_ss2",
2944	"msiof0_txd",
2945	"msiof0_rxd",
2946};
2947
2948static const char * const msiof1_groups[] = {
2949	"msiof1_clk",
2950	"msiof1_sync",
2951	"msiof1_ss1",
2952	"msiof1_ss2",
2953	"msiof1_txd",
2954	"msiof1_rxd",
2955};
2956
2957static const char * const msiof2_groups[] = {
2958	"msiof2_clk",
2959	"msiof2_sync",
2960	"msiof2_ss1",
2961	"msiof2_ss2",
2962	"msiof2_txd",
2963	"msiof2_rxd",
2964};
2965
2966static const char * const msiof3_groups[] = {
2967	"msiof3_clk",
2968	"msiof3_sync",
2969	"msiof3_ss1",
2970	"msiof3_ss2",
2971	"msiof3_txd",
2972	"msiof3_rxd",
2973};
2974
2975static const char * const msiof4_groups[] = {
2976	"msiof4_clk",
2977	"msiof4_sync",
2978	"msiof4_ss1",
2979	"msiof4_ss2",
2980	"msiof4_txd",
2981	"msiof4_rxd",
2982};
2983
2984static const char * const msiof5_groups[] = {
2985	"msiof5_clk",
2986	"msiof5_sync",
2987	"msiof5_ss1",
2988	"msiof5_ss2",
2989	"msiof5_txd",
2990	"msiof5_rxd",
2991};
2992
2993static const char * const pcie_groups[] = {
2994	"pcie0_clkreq_n",
2995	"pcie1_clkreq_n",
2996};
2997
2998static const char * const pwm0_groups[] = {
2999	"pwm0",
3000};
3001
3002static const char * const pwm1_groups[] = {
3003	"pwm1_a",
3004	"pwm1_b",
3005};
3006
3007static const char * const pwm2_groups[] = {
3008	"pwm2",
3009};
3010
3011static const char * const pwm3_groups[] = {
3012	"pwm3_a",
3013	"pwm3_b",
3014};
3015
3016static const char * const pwm4_groups[] = {
3017	"pwm4",
3018};
3019
3020static const char * const pwm5_groups[] = {
3021	"pwm5",
3022};
3023
3024static const char * const pwm6_groups[] = {
3025	"pwm6",
3026};
3027
3028static const char * const pwm7_groups[] = {
3029	"pwm7",
3030};
3031
3032static const char * const pwm8_groups[] = {
3033	"pwm8",
3034};
3035
3036static const char * const pwm9_groups[] = {
3037	"pwm9",
3038};
3039
3040static const char * const qspi0_groups[] = {
3041	"qspi0_ctrl",
3042	"qspi0_data2",
3043	"qspi0_data4",
3044};
3045
3046static const char * const qspi1_groups[] = {
3047	"qspi1_ctrl",
3048	"qspi1_data2",
3049	"qspi1_data4",
3050};
3051
3052static const char * const scif0_groups[] = {
3053	"scif0_data",
3054	"scif0_clk",
3055	"scif0_ctrl",
3056};
3057
3058static const char * const scif1_groups[] = {
3059	"scif1_data_a",
3060	"scif1_clk_a",
3061	"scif1_ctrl_a",
3062	"scif1_data_b",
3063	"scif1_clk_b",
3064	"scif1_ctrl_b",
3065};
3066
3067static const char * const scif3_groups[] = {
3068	"scif3_data_a",
3069	"scif3_clk_a",
3070	"scif3_ctrl_a",
3071	"scif3_data_b",
3072	"scif3_clk_b",
3073	"scif3_ctrl_b",
3074};
3075
3076static const char * const scif4_groups[] = {
3077	"scif4_data",
3078	"scif4_clk",
3079	"scif4_ctrl",
3080};
3081
3082static const char * const scif_clk_groups[] = {
3083	"scif_clk",
3084};
3085
3086static const char * const scif_clk2_groups[] = {
3087	"scif_clk2",
3088};
3089
3090static const char * const ssi_groups[] = {
3091	"ssi_data",
3092	"ssi_ctrl",
3093};
3094
3095static const char * const tpu_groups[] = {
3096	"tpu_to0_a",
3097	"tpu_to0_b",
3098	"tpu_to1_a",
3099	"tpu_to1_b",
3100	"tpu_to2_a",
3101	"tpu_to2_b",
3102	"tpu_to3_a",
3103	"tpu_to3_b",
3104};
3105
3106static const char * const tsn0_groups[] = {
3107	"tsn0_link",
3108	"tsn0_phy_int",
3109	"tsn0_mdio",
3110	"tsn0_rgmii",
3111	"tsn0_txcrefclk",
3112	"tsn0_avtp_pps",
3113	"tsn0_avtp_capture",
3114	"tsn0_avtp_match",
3115};
3116
3117static const struct sh_pfc_function pinmux_functions[] = {
3118	SH_PFC_FUNCTION(audio_clk),
3119
3120	SH_PFC_FUNCTION(avb0),
3121	SH_PFC_FUNCTION(avb1),
3122	SH_PFC_FUNCTION(avb2),
3123
3124	SH_PFC_FUNCTION(canfd0),
3125	SH_PFC_FUNCTION(canfd1),
3126	SH_PFC_FUNCTION(canfd2),
3127	SH_PFC_FUNCTION(canfd3),
3128	SH_PFC_FUNCTION(canfd4),
3129	SH_PFC_FUNCTION(canfd5),
3130	SH_PFC_FUNCTION(canfd6),
3131	SH_PFC_FUNCTION(canfd7),
3132	SH_PFC_FUNCTION(can_clk),
3133
3134	SH_PFC_FUNCTION(hscif0),
3135	SH_PFC_FUNCTION(hscif1),
3136	SH_PFC_FUNCTION(hscif2),
3137	SH_PFC_FUNCTION(hscif3),
3138
3139	SH_PFC_FUNCTION(i2c0),
3140	SH_PFC_FUNCTION(i2c1),
3141	SH_PFC_FUNCTION(i2c2),
3142	SH_PFC_FUNCTION(i2c3),
3143	SH_PFC_FUNCTION(i2c4),
3144	SH_PFC_FUNCTION(i2c5),
3145
3146	SH_PFC_FUNCTION(intc_ex),
3147
3148	SH_PFC_FUNCTION(mmc),
3149
3150	SH_PFC_FUNCTION(msiof0),
3151	SH_PFC_FUNCTION(msiof1),
3152	SH_PFC_FUNCTION(msiof2),
3153	SH_PFC_FUNCTION(msiof3),
3154	SH_PFC_FUNCTION(msiof4),
3155	SH_PFC_FUNCTION(msiof5),
3156
3157	SH_PFC_FUNCTION(pcie),
3158
3159	SH_PFC_FUNCTION(pwm0),
3160	SH_PFC_FUNCTION(pwm1),
3161	SH_PFC_FUNCTION(pwm2),
3162	SH_PFC_FUNCTION(pwm3),
3163	SH_PFC_FUNCTION(pwm4),
3164	SH_PFC_FUNCTION(pwm5),
3165	SH_PFC_FUNCTION(pwm6),
3166	SH_PFC_FUNCTION(pwm7),
3167	SH_PFC_FUNCTION(pwm8),
3168	SH_PFC_FUNCTION(pwm9),
3169
3170	SH_PFC_FUNCTION(qspi0),
3171	SH_PFC_FUNCTION(qspi1),
3172
3173	SH_PFC_FUNCTION(scif0),
3174	SH_PFC_FUNCTION(scif1),
3175	SH_PFC_FUNCTION(scif3),
3176	SH_PFC_FUNCTION(scif4),
3177	SH_PFC_FUNCTION(scif_clk),
3178	SH_PFC_FUNCTION(scif_clk2),
3179
3180	SH_PFC_FUNCTION(ssi),
3181
3182	SH_PFC_FUNCTION(tpu),
3183
3184	SH_PFC_FUNCTION(tsn0),
3185};
3186
3187static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3188#define F_(x, y)	FN_##y
3189#define FM(x)		FN_##x
3190	{ PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3191			     GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3192				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3193			     GROUP(
3194		/* GP0_31_19 RESERVED */
3195		GP_0_18_FN,	GPSR0_18,
3196		GP_0_17_FN,	GPSR0_17,
3197		GP_0_16_FN,	GPSR0_16,
3198		GP_0_15_FN,	GPSR0_15,
3199		GP_0_14_FN,	GPSR0_14,
3200		GP_0_13_FN,	GPSR0_13,
3201		GP_0_12_FN,	GPSR0_12,
3202		GP_0_11_FN,	GPSR0_11,
3203		GP_0_10_FN,	GPSR0_10,
3204		GP_0_9_FN,	GPSR0_9,
3205		GP_0_8_FN,	GPSR0_8,
3206		GP_0_7_FN,	GPSR0_7,
3207		GP_0_6_FN,	GPSR0_6,
3208		GP_0_5_FN,	GPSR0_5,
3209		GP_0_4_FN,	GPSR0_4,
3210		GP_0_3_FN,	GPSR0_3,
3211		GP_0_2_FN,	GPSR0_2,
3212		GP_0_1_FN,	GPSR0_1,
3213		GP_0_0_FN,	GPSR0_0, ))
3214	},
3215	{ PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3216		0, 0,
3217		0, 0,
3218		0, 0,
3219		GP_1_28_FN,	GPSR1_28,
3220		GP_1_27_FN,	GPSR1_27,
3221		GP_1_26_FN,	GPSR1_26,
3222		GP_1_25_FN,	GPSR1_25,
3223		GP_1_24_FN,	GPSR1_24,
3224		GP_1_23_FN,	GPSR1_23,
3225		GP_1_22_FN,	GPSR1_22,
3226		GP_1_21_FN,	GPSR1_21,
3227		GP_1_20_FN,	GPSR1_20,
3228		GP_1_19_FN,	GPSR1_19,
3229		GP_1_18_FN,	GPSR1_18,
3230		GP_1_17_FN,	GPSR1_17,
3231		GP_1_16_FN,	GPSR1_16,
3232		GP_1_15_FN,	GPSR1_15,
3233		GP_1_14_FN,	GPSR1_14,
3234		GP_1_13_FN,	GPSR1_13,
3235		GP_1_12_FN,	GPSR1_12,
3236		GP_1_11_FN,	GPSR1_11,
3237		GP_1_10_FN,	GPSR1_10,
3238		GP_1_9_FN,	GPSR1_9,
3239		GP_1_8_FN,	GPSR1_8,
3240		GP_1_7_FN,	GPSR1_7,
3241		GP_1_6_FN,	GPSR1_6,
3242		GP_1_5_FN,	GPSR1_5,
3243		GP_1_4_FN,	GPSR1_4,
3244		GP_1_3_FN,	GPSR1_3,
3245		GP_1_2_FN,	GPSR1_2,
3246		GP_1_1_FN,	GPSR1_1,
3247		GP_1_0_FN,	GPSR1_0, ))
3248	},
3249	{ PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3250			     GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3251				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3252			     GROUP(
3253		/* GP2_31_20 RESERVED */
3254		GP_2_19_FN,	GPSR2_19,
3255		GP_2_18_FN,	GPSR2_18,
3256		GP_2_17_FN,	GPSR2_17,
3257		GP_2_16_FN,	GPSR2_16,
3258		GP_2_15_FN,	GPSR2_15,
3259		GP_2_14_FN,	GPSR2_14,
3260		GP_2_13_FN,	GPSR2_13,
3261		GP_2_12_FN,	GPSR2_12,
3262		GP_2_11_FN,	GPSR2_11,
3263		GP_2_10_FN,	GPSR2_10,
3264		GP_2_9_FN,	GPSR2_9,
3265		GP_2_8_FN,	GPSR2_8,
3266		GP_2_7_FN,	GPSR2_7,
3267		GP_2_6_FN,	GPSR2_6,
3268		GP_2_5_FN,	GPSR2_5,
3269		GP_2_4_FN,	GPSR2_4,
3270		GP_2_3_FN,	GPSR2_3,
3271		GP_2_2_FN,	GPSR2_2,
3272		GP_2_1_FN,	GPSR2_1,
3273		GP_2_0_FN,	GPSR2_0, ))
3274	},
3275	{ PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3276		0, 0,
3277		0, 0,
3278		GP_3_29_FN,	GPSR3_29,
3279		GP_3_28_FN,	GPSR3_28,
3280		GP_3_27_FN,	GPSR3_27,
3281		GP_3_26_FN,	GPSR3_26,
3282		GP_3_25_FN,	GPSR3_25,
3283		GP_3_24_FN,	GPSR3_24,
3284		GP_3_23_FN,	GPSR3_23,
3285		GP_3_22_FN,	GPSR3_22,
3286		GP_3_21_FN,	GPSR3_21,
3287		GP_3_20_FN,	GPSR3_20,
3288		GP_3_19_FN,	GPSR3_19,
3289		GP_3_18_FN,	GPSR3_18,
3290		GP_3_17_FN,	GPSR3_17,
3291		GP_3_16_FN,	GPSR3_16,
3292		GP_3_15_FN,	GPSR3_15,
3293		GP_3_14_FN,	GPSR3_14,
3294		GP_3_13_FN,	GPSR3_13,
3295		GP_3_12_FN,	GPSR3_12,
3296		GP_3_11_FN,	GPSR3_11,
3297		GP_3_10_FN,	GPSR3_10,
3298		GP_3_9_FN,	GPSR3_9,
3299		GP_3_8_FN,	GPSR3_8,
3300		GP_3_7_FN,	GPSR3_7,
3301		GP_3_6_FN,	GPSR3_6,
3302		GP_3_5_FN,	GPSR3_5,
3303		GP_3_4_FN,	GPSR3_4,
3304		GP_3_3_FN,	GPSR3_3,
3305		GP_3_2_FN,	GPSR3_2,
3306		GP_3_1_FN,	GPSR3_1,
3307		GP_3_0_FN,	GPSR3_0, ))
3308	},
3309	{ PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3310		0, 0,
3311		0, 0,
3312		0, 0,
3313		0, 0,
3314		0, 0,
3315		0, 0,
3316		0, 0,
3317		GP_4_24_FN,	GPSR4_24,
3318		GP_4_23_FN,	GPSR4_23,
3319		GP_4_22_FN,	GPSR4_22,
3320		GP_4_21_FN,	GPSR4_21,
3321		GP_4_20_FN,	GPSR4_20,
3322		GP_4_19_FN,	GPSR4_19,
3323		GP_4_18_FN,	GPSR4_18,
3324		GP_4_17_FN,	GPSR4_17,
3325		GP_4_16_FN,	GPSR4_16,
3326		GP_4_15_FN,	GPSR4_15,
3327		GP_4_14_FN,	GPSR4_14,
3328		GP_4_13_FN,	GPSR4_13,
3329		GP_4_12_FN,	GPSR4_12,
3330		GP_4_11_FN,	GPSR4_11,
3331		GP_4_10_FN,	GPSR4_10,
3332		GP_4_9_FN,	GPSR4_9,
3333		GP_4_8_FN,	GPSR4_8,
3334		GP_4_7_FN,	GPSR4_7,
3335		GP_4_6_FN,	GPSR4_6,
3336		GP_4_5_FN,	GPSR4_5,
3337		GP_4_4_FN,	GPSR4_4,
3338		GP_4_3_FN,	GPSR4_3,
3339		GP_4_2_FN,	GPSR4_2,
3340		GP_4_1_FN,	GPSR4_1,
3341		GP_4_0_FN,	GPSR4_0, ))
3342	},
3343	{ PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3344			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3345				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3346			     GROUP(
3347		/* GP5_31_21 RESERVED */
3348		GP_5_20_FN,	GPSR5_20,
3349		GP_5_19_FN,	GPSR5_19,
3350		GP_5_18_FN,	GPSR5_18,
3351		GP_5_17_FN,	GPSR5_17,
3352		GP_5_16_FN,	GPSR5_16,
3353		GP_5_15_FN,	GPSR5_15,
3354		GP_5_14_FN,	GPSR5_14,
3355		GP_5_13_FN,	GPSR5_13,
3356		GP_5_12_FN,	GPSR5_12,
3357		GP_5_11_FN,	GPSR5_11,
3358		GP_5_10_FN,	GPSR5_10,
3359		GP_5_9_FN,	GPSR5_9,
3360		GP_5_8_FN,	GPSR5_8,
3361		GP_5_7_FN,	GPSR5_7,
3362		GP_5_6_FN,	GPSR5_6,
3363		GP_5_5_FN,	GPSR5_5,
3364		GP_5_4_FN,	GPSR5_4,
3365		GP_5_3_FN,	GPSR5_3,
3366		GP_5_2_FN,	GPSR5_2,
3367		GP_5_1_FN,	GPSR5_1,
3368		GP_5_0_FN,	GPSR5_0, ))
3369	},
3370	{ PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3371			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3372				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3373			     GROUP(
3374		/* GP6_31_21 RESERVED */
3375		GP_6_20_FN,	GPSR6_20,
3376		GP_6_19_FN,	GPSR6_19,
3377		GP_6_18_FN,	GPSR6_18,
3378		GP_6_17_FN,	GPSR6_17,
3379		GP_6_16_FN,	GPSR6_16,
3380		GP_6_15_FN,	GPSR6_15,
3381		GP_6_14_FN,	GPSR6_14,
3382		GP_6_13_FN,	GPSR6_13,
3383		GP_6_12_FN,	GPSR6_12,
3384		GP_6_11_FN,	GPSR6_11,
3385		GP_6_10_FN,	GPSR6_10,
3386		GP_6_9_FN,	GPSR6_9,
3387		GP_6_8_FN,	GPSR6_8,
3388		GP_6_7_FN,	GPSR6_7,
3389		GP_6_6_FN,	GPSR6_6,
3390		GP_6_5_FN,	GPSR6_5,
3391		GP_6_4_FN,	GPSR6_4,
3392		GP_6_3_FN,	GPSR6_3,
3393		GP_6_2_FN,	GPSR6_2,
3394		GP_6_1_FN,	GPSR6_1,
3395		GP_6_0_FN,	GPSR6_0, ))
3396	},
3397	{ PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3398			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3399				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3400			     GROUP(
3401		/* GP7_31_21 RESERVED */
3402		GP_7_20_FN,	GPSR7_20,
3403		GP_7_19_FN,	GPSR7_19,
3404		GP_7_18_FN,	GPSR7_18,
3405		GP_7_17_FN,	GPSR7_17,
3406		GP_7_16_FN,	GPSR7_16,
3407		GP_7_15_FN,	GPSR7_15,
3408		GP_7_14_FN,	GPSR7_14,
3409		GP_7_13_FN,	GPSR7_13,
3410		GP_7_12_FN,	GPSR7_12,
3411		GP_7_11_FN,	GPSR7_11,
3412		GP_7_10_FN,	GPSR7_10,
3413		GP_7_9_FN,	GPSR7_9,
3414		GP_7_8_FN,	GPSR7_8,
3415		GP_7_7_FN,	GPSR7_7,
3416		GP_7_6_FN,	GPSR7_6,
3417		GP_7_5_FN,	GPSR7_5,
3418		GP_7_4_FN,	GPSR7_4,
3419		GP_7_3_FN,	GPSR7_3,
3420		GP_7_2_FN,	GPSR7_2,
3421		GP_7_1_FN,	GPSR7_1,
3422		GP_7_0_FN,	GPSR7_0, ))
3423	},
3424	{ PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3425			     GROUP(-18, 1, 1, 1, 1,
3426				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3427			     GROUP(
3428		/* GP8_31_14 RESERVED */
3429		GP_8_13_FN,	GPSR8_13,
3430		GP_8_12_FN,	GPSR8_12,
3431		GP_8_11_FN,	GPSR8_11,
3432		GP_8_10_FN,	GPSR8_10,
3433		GP_8_9_FN,	GPSR8_9,
3434		GP_8_8_FN,	GPSR8_8,
3435		GP_8_7_FN,	GPSR8_7,
3436		GP_8_6_FN,	GPSR8_6,
3437		GP_8_5_FN,	GPSR8_5,
3438		GP_8_4_FN,	GPSR8_4,
3439		GP_8_3_FN,	GPSR8_3,
3440		GP_8_2_FN,	GPSR8_2,
3441		GP_8_1_FN,	GPSR8_1,
3442		GP_8_0_FN,	GPSR8_0, ))
3443	},
3444#undef F_
3445#undef FM
3446
3447#define F_(x, y)	x,
3448#define FM(x)		FN_##x,
3449	{ PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3450		IP0SR0_31_28
3451		IP0SR0_27_24
3452		IP0SR0_23_20
3453		IP0SR0_19_16
3454		IP0SR0_15_12
3455		IP0SR0_11_8
3456		IP0SR0_7_4
3457		IP0SR0_3_0))
3458	},
3459	{ PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3460		IP1SR0_31_28
3461		IP1SR0_27_24
3462		IP1SR0_23_20
3463		IP1SR0_19_16
3464		IP1SR0_15_12
3465		IP1SR0_11_8
3466		IP1SR0_7_4
3467		IP1SR0_3_0))
3468	},
3469	{ PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3470			     GROUP(-20, 4, 4, 4),
3471			     GROUP(
3472		/* IP2SR0_31_12 RESERVED */
3473		IP2SR0_11_8
3474		IP2SR0_7_4
3475		IP2SR0_3_0))
3476	},
3477	{ PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3478		IP0SR1_31_28
3479		IP0SR1_27_24
3480		IP0SR1_23_20
3481		IP0SR1_19_16
3482		IP0SR1_15_12
3483		IP0SR1_11_8
3484		IP0SR1_7_4
3485		IP0SR1_3_0))
3486	},
3487	{ PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3488		IP1SR1_31_28
3489		IP1SR1_27_24
3490		IP1SR1_23_20
3491		IP1SR1_19_16
3492		IP1SR1_15_12
3493		IP1SR1_11_8
3494		IP1SR1_7_4
3495		IP1SR1_3_0))
3496	},
3497	{ PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3498		IP2SR1_31_28
3499		IP2SR1_27_24
3500		IP2SR1_23_20
3501		IP2SR1_19_16
3502		IP2SR1_15_12
3503		IP2SR1_11_8
3504		IP2SR1_7_4
3505		IP2SR1_3_0))
3506	},
3507	{ PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3508			     GROUP(-12, 4, 4, 4, 4, 4),
3509			     GROUP(
3510		/* IP3SR1_31_20 RESERVED */
3511		IP3SR1_19_16
3512		IP3SR1_15_12
3513		IP3SR1_11_8
3514		IP3SR1_7_4
3515		IP3SR1_3_0))
3516	},
3517	{ PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3518		IP0SR2_31_28
3519		IP0SR2_27_24
3520		IP0SR2_23_20
3521		IP0SR2_19_16
3522		IP0SR2_15_12
3523		IP0SR2_11_8
3524		IP0SR2_7_4
3525		IP0SR2_3_0))
3526	},
3527	{ PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3528		IP1SR2_31_28
3529		IP1SR2_27_24
3530		IP1SR2_23_20
3531		IP1SR2_19_16
3532		IP1SR2_15_12
3533		IP1SR2_11_8
3534		IP1SR2_7_4
3535		IP1SR2_3_0))
3536	},
3537	{ PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3538			     GROUP(-16, 4, 4, 4, 4),
3539			     GROUP(
3540		/* IP2SR2_31_16 RESERVED */
3541		IP2SR2_15_12
3542		IP2SR2_11_8
3543		IP2SR2_7_4
3544		IP2SR2_3_0))
3545	},
3546	{ PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3547		IP0SR3_31_28
3548		IP0SR3_27_24
3549		IP0SR3_23_20
3550		IP0SR3_19_16
3551		IP0SR3_15_12
3552		IP0SR3_11_8
3553		IP0SR3_7_4
3554		IP0SR3_3_0))
3555	},
3556	{ PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3557		IP1SR3_31_28
3558		IP1SR3_27_24
3559		IP1SR3_23_20
3560		IP1SR3_19_16
3561		IP1SR3_15_12
3562		IP1SR3_11_8
3563		IP1SR3_7_4
3564		IP1SR3_3_0))
3565	},
3566	{ PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3567		IP2SR3_31_28
3568		IP2SR3_27_24
3569		IP2SR3_23_20
3570		IP2SR3_19_16
3571		IP2SR3_15_12
3572		IP2SR3_11_8
3573		IP2SR3_7_4
3574		IP2SR3_3_0))
3575	},
3576	{ PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3577			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3578			     GROUP(
3579		/* IP3SR3_31_24 RESERVED */
3580		IP3SR3_23_20
3581		IP3SR3_19_16
3582		IP3SR3_15_12
3583		IP3SR3_11_8
3584		IP3SR3_7_4
3585		IP3SR3_3_0))
3586	},
3587	{ PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
3588			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3589			     GROUP(
3590		IP0SR4_31_28
3591		IP0SR4_27_24
3592		IP0SR4_23_20
3593		IP0SR4_19_16
3594		IP0SR4_15_12
3595		IP0SR4_11_8
3596		IP0SR4_7_4
3597		IP0SR4_3_0))
3598	},
3599	{ PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
3600			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3601			     GROUP(
3602		IP1SR4_31_28
3603		IP1SR4_27_24
3604		IP1SR4_23_20
3605		IP1SR4_19_16
3606		IP1SR4_15_12
3607		IP1SR4_11_8
3608		IP1SR4_7_4
3609		IP1SR4_3_0))
3610	},
3611	{ PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3612			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3613			     GROUP(
3614		IP2SR4_31_28
3615		IP2SR4_27_24
3616		IP2SR4_23_20
3617		IP2SR4_19_16
3618		IP2SR4_15_12
3619		IP2SR4_11_8
3620		IP2SR4_7_4
3621		IP2SR4_3_0))
3622	},
3623	{ PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3624			     GROUP(-28, 4),
3625			     GROUP(
3626		/* IP3SR4_31_4 RESERVED */
3627		IP3SR4_3_0))
3628	},
3629	{ PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
3630			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3631			     GROUP(
3632		IP0SR5_31_28
3633		IP0SR5_27_24
3634		IP0SR5_23_20
3635		IP0SR5_19_16
3636		IP0SR5_15_12
3637		IP0SR5_11_8
3638		IP0SR5_7_4
3639		IP0SR5_3_0))
3640	},
3641	{ PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
3642			     GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3643			     GROUP(
3644		IP1SR5_31_28
3645		IP1SR5_27_24
3646		IP1SR5_23_20
3647		IP1SR5_19_16
3648		IP1SR5_15_12
3649		IP1SR5_11_8
3650		IP1SR5_7_4
3651		IP1SR5_3_0))
3652	},
3653	{ PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3654			     GROUP(-12, 4, 4, 4, 4, 4),
3655			     GROUP(
3656		/* IP2SR5_31_20 RESERVED */
3657		IP2SR5_19_16
3658		IP2SR5_15_12
3659		IP2SR5_11_8
3660		IP2SR5_7_4
3661		IP2SR5_3_0))
3662	},
3663	{ PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3664		IP0SR6_31_28
3665		IP0SR6_27_24
3666		IP0SR6_23_20
3667		IP0SR6_19_16
3668		IP0SR6_15_12
3669		IP0SR6_11_8
3670		IP0SR6_7_4
3671		IP0SR6_3_0))
3672	},
3673	{ PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3674		IP1SR6_31_28
3675		IP1SR6_27_24
3676		IP1SR6_23_20
3677		IP1SR6_19_16
3678		IP1SR6_15_12
3679		IP1SR6_11_8
3680		IP1SR6_7_4
3681		IP1SR6_3_0))
3682	},
3683	{ PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3684			     GROUP(-12, 4, 4, 4, 4, 4),
3685			     GROUP(
3686		/* IP2SR6_31_20 RESERVED */
3687		IP2SR6_19_16
3688		IP2SR6_15_12
3689		IP2SR6_11_8
3690		IP2SR6_7_4
3691		IP2SR6_3_0))
3692	},
3693	{ PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3694		IP0SR7_31_28
3695		IP0SR7_27_24
3696		IP0SR7_23_20
3697		IP0SR7_19_16
3698		IP0SR7_15_12
3699		IP0SR7_11_8
3700		IP0SR7_7_4
3701		IP0SR7_3_0))
3702	},
3703	{ PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3704		IP1SR7_31_28
3705		IP1SR7_27_24
3706		IP1SR7_23_20
3707		IP1SR7_19_16
3708		IP1SR7_15_12
3709		IP1SR7_11_8
3710		IP1SR7_7_4
3711		IP1SR7_3_0))
3712	},
3713	{ PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3714			     GROUP(-12, 4, 4, 4, 4, 4),
3715			     GROUP(
3716		/* IP2SR7_31_20 RESERVED */
3717		IP2SR7_19_16
3718		IP2SR7_15_12
3719		IP2SR7_11_8
3720		IP2SR7_7_4
3721		IP2SR7_3_0))
3722	},
3723	{ PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3724		IP0SR8_31_28
3725		IP0SR8_27_24
3726		IP0SR8_23_20
3727		IP0SR8_19_16
3728		IP0SR8_15_12
3729		IP0SR8_11_8
3730		IP0SR8_7_4
3731		IP0SR8_3_0))
3732	},
3733	{ PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3734			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3735			     GROUP(
3736		/* IP1SR8_31_24 RESERVED */
3737		IP1SR8_23_20
3738		IP1SR8_19_16
3739		IP1SR8_15_12
3740		IP1SR8_11_8
3741		IP1SR8_7_4
3742		IP1SR8_3_0))
3743	},
3744#undef F_
3745#undef FM
3746
3747#define F_(x, y)	x,
3748#define FM(x)		FN_##x,
3749	{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3750			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3751			     GROUP(
3752		/* RESERVED 31-12 */
3753		MOD_SEL8_11
3754		MOD_SEL8_10
3755		MOD_SEL8_9
3756		MOD_SEL8_8
3757		MOD_SEL8_7
3758		MOD_SEL8_6
3759		MOD_SEL8_5
3760		MOD_SEL8_4
3761		MOD_SEL8_3
3762		MOD_SEL8_2
3763		MOD_SEL8_1
3764		MOD_SEL8_0))
3765	},
3766	{ /* sentinel */ }
3767};
3768
3769static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3770	{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3771		{ RCAR_GP_PIN(0,  7), 28, 3 },	/* MSIOF5_SS2 */
3772		{ RCAR_GP_PIN(0,  6), 24, 3 },	/* IRQ0 */
3773		{ RCAR_GP_PIN(0,  5), 20, 3 },	/* IRQ1 */
3774		{ RCAR_GP_PIN(0,  4), 16, 3 },	/* IRQ2 */
3775		{ RCAR_GP_PIN(0,  3), 12, 3 },	/* IRQ3 */
3776		{ RCAR_GP_PIN(0,  2),  8, 3 },	/* GP0_02 */
3777		{ RCAR_GP_PIN(0,  1),  4, 3 },	/* GP0_01 */
3778		{ RCAR_GP_PIN(0,  0),  0, 3 },	/* GP0_00 */
3779	} },
3780	{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3781		{ RCAR_GP_PIN(0, 15), 28, 3 },	/* MSIOF2_SYNC */
3782		{ RCAR_GP_PIN(0, 14), 24, 3 },	/* MSIOF2_SS1 */
3783		{ RCAR_GP_PIN(0, 13), 20, 3 },	/* MSIOF2_SS2 */
3784		{ RCAR_GP_PIN(0, 12), 16, 3 },	/* MSIOF5_RXD */
3785		{ RCAR_GP_PIN(0, 11), 12, 3 },	/* MSIOF5_SCK */
3786		{ RCAR_GP_PIN(0, 10),  8, 3 },	/* MSIOF5_TXD */
3787		{ RCAR_GP_PIN(0,  9),  4, 3 },	/* MSIOF5_SYNC */
3788		{ RCAR_GP_PIN(0,  8),  0, 3 },	/* MSIOF5_SS1 */
3789	} },
3790	{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3791		{ RCAR_GP_PIN(0, 18),  8, 3 },	/* MSIOF2_RXD */
3792		{ RCAR_GP_PIN(0, 17),  4, 3 },	/* MSIOF2_SCK */
3793		{ RCAR_GP_PIN(0, 16),  0, 3 },	/* MSIOF2_TXD */
3794	} },
3795	{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3796		{ RCAR_GP_PIN(1,  7), 28, 3 },	/* MSIOF0_SS1 */
3797		{ RCAR_GP_PIN(1,  6), 24, 3 },	/* MSIOF0_SS2 */
3798		{ RCAR_GP_PIN(1,  5), 20, 3 },	/* MSIOF1_RXD */
3799		{ RCAR_GP_PIN(1,  4), 16, 3 },	/* MSIOF1_TXD */
3800		{ RCAR_GP_PIN(1,  3), 12, 3 },	/* MSIOF1_SCK */
3801		{ RCAR_GP_PIN(1,  2),  8, 3 },	/* MSIOF1_SYNC */
3802		{ RCAR_GP_PIN(1,  1),  4, 3 },	/* MSIOF1_SS1 */
3803		{ RCAR_GP_PIN(1,  0),  0, 3 },	/* MSIOF1_SS2 */
3804	} },
3805	{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3806		{ RCAR_GP_PIN(1, 15), 28, 3 },	/* HSCK0 */
3807		{ RCAR_GP_PIN(1, 14), 24, 3 },	/* HRTS0_N */
3808		{ RCAR_GP_PIN(1, 13), 20, 3 },	/* HCTS0_N */
3809		{ RCAR_GP_PIN(1, 12), 16, 3 },	/* HTX0 */
3810		{ RCAR_GP_PIN(1, 11), 12, 3 },	/* MSIOF0_RXD */
3811		{ RCAR_GP_PIN(1, 10),  8, 3 },	/* MSIOF0_SCK */
3812		{ RCAR_GP_PIN(1,  9),  4, 3 },	/* MSIOF0_TXD */
3813		{ RCAR_GP_PIN(1,  8),  0, 3 },	/* MSIOF0_SYNC */
3814	} },
3815	{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3816		{ RCAR_GP_PIN(1, 23), 28, 3 },	/* GP1_23 */
3817		{ RCAR_GP_PIN(1, 22), 24, 3 },	/* AUDIO_CLKIN */
3818		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* AUDIO_CLKOUT */
3819		{ RCAR_GP_PIN(1, 20), 16, 3 },	/* SSI_SD */
3820		{ RCAR_GP_PIN(1, 19), 12, 3 },	/* SSI_WS */
3821		{ RCAR_GP_PIN(1, 18),  8, 3 },	/* SSI_SCK */
3822		{ RCAR_GP_PIN(1, 17),  4, 3 },	/* SCIF_CLK */
3823		{ RCAR_GP_PIN(1, 16),  0, 3 },	/* HRX0 */
3824	} },
3825	{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3826		{ RCAR_GP_PIN(1, 28), 16, 3 },	/* HTX3 */
3827		{ RCAR_GP_PIN(1, 27), 12, 3 },	/* HCTS3_N */
3828		{ RCAR_GP_PIN(1, 26),  8, 3 },	/* HRTS3_N */
3829		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* HSCK3 */
3830		{ RCAR_GP_PIN(1, 24),  0, 3 },	/* HRX3 */
3831	} },
3832	{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3833		{ RCAR_GP_PIN(2,  7), 28, 3 },	/* TPU0TO1 */
3834		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* FXR_TXDB */
3835		{ RCAR_GP_PIN(2,  5), 20, 3 },	/* FXR_TXENB_N */
3836		{ RCAR_GP_PIN(2,  4), 16, 3 },	/* RXDB_EXTFXR */
3837		{ RCAR_GP_PIN(2,  3), 12, 3 },	/* CLK_EXTFXR */
3838		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* RXDA_EXTFXR */
3839		{ RCAR_GP_PIN(2,  1),  4, 3 },	/* FXR_TXENA_N */
3840		{ RCAR_GP_PIN(2,  0),  0, 3 },	/* FXR_TXDA */
3841	} },
3842	{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3843		{ RCAR_GP_PIN(2, 15), 28, 3 },	/* CANFD3_RX */
3844		{ RCAR_GP_PIN(2, 14), 24, 3 },	/* CANFD3_TX */
3845		{ RCAR_GP_PIN(2, 13), 20, 3 },	/* CANFD2_RX */
3846		{ RCAR_GP_PIN(2, 12), 16, 3 },	/* CANFD2_TX */
3847		{ RCAR_GP_PIN(2, 11), 12, 3 },	/* CANFD0_RX */
3848		{ RCAR_GP_PIN(2, 10),  8, 3 },	/* CANFD0_TX */
3849		{ RCAR_GP_PIN(2,  9),  4, 3 },	/* CAN_CLK */
3850		{ RCAR_GP_PIN(2,  8),  0, 3 },	/* TPU0TO0 */
3851	} },
3852	{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3853		{ RCAR_GP_PIN(2, 19), 12, 3 },	/* CANFD7_RX */
3854		{ RCAR_GP_PIN(2, 18),  8, 3 },	/* CANFD7_TX */
3855		{ RCAR_GP_PIN(2, 17),  4, 3 },	/* CANFD4_RX */
3856		{ RCAR_GP_PIN(2, 16),  0, 3 },	/* CANFD4_TX */
3857	} },
3858	{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3859		{ RCAR_GP_PIN(3,  7), 28, 3 },	/* MMC_D4 */
3860		{ RCAR_GP_PIN(3,  6), 24, 3 },	/* MMC_D5 */
3861		{ RCAR_GP_PIN(3,  5), 20, 3 },	/* MMC_SD_D3 */
3862		{ RCAR_GP_PIN(3,  4), 16, 3 },	/* MMC_DS */
3863		{ RCAR_GP_PIN(3,  3), 12, 3 },	/* MMC_SD_CLK */
3864		{ RCAR_GP_PIN(3,  2),  8, 3 },	/* MMC_SD_D2 */
3865		{ RCAR_GP_PIN(3,  1),  4, 3 },	/* MMC_SD_D0 */
3866		{ RCAR_GP_PIN(3,  0),  0, 3 },	/* MMC_SD_D1 */
3867	} },
3868	{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3869		{ RCAR_GP_PIN(3, 15), 28, 2 },	/* QSPI0_SSL */
3870		{ RCAR_GP_PIN(3, 14), 24, 2 },	/* IPC_CLKOUT */
3871		{ RCAR_GP_PIN(3, 13), 20, 2 },	/* IPC_CLKIN */
3872		{ RCAR_GP_PIN(3, 12), 16, 3 },	/* SD_WP */
3873		{ RCAR_GP_PIN(3, 11), 12, 3 },	/* SD_CD */
3874		{ RCAR_GP_PIN(3, 10),  8, 3 },	/* MMC_SD_CMD */
3875		{ RCAR_GP_PIN(3,  9),  4, 3 },	/* MMC_D6*/
3876		{ RCAR_GP_PIN(3,  8),  0, 3 },	/* MMC_D7 */
3877	} },
3878	{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3879		{ RCAR_GP_PIN(3, 23), 28, 2 },	/* QSPI1_MISO_IO1 */
3880		{ RCAR_GP_PIN(3, 22), 24, 2 },	/* QSPI1_SPCLK */
3881		{ RCAR_GP_PIN(3, 21), 20, 2 },	/* QSPI1_MOSI_IO0 */
3882		{ RCAR_GP_PIN(3, 20), 16, 2 },	/* QSPI0_SPCLK */
3883		{ RCAR_GP_PIN(3, 19), 12, 2 },	/* QSPI0_MOSI_IO0 */
3884		{ RCAR_GP_PIN(3, 18),  8, 2 },	/* QSPI0_MISO_IO1 */
3885		{ RCAR_GP_PIN(3, 17),  4, 2 },	/* QSPI0_IO2 */
3886		{ RCAR_GP_PIN(3, 16),  0, 2 },	/* QSPI0_IO3 */
3887	} },
3888	{ PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3889		{ RCAR_GP_PIN(3, 29), 20, 2 },	/* RPC_INT_N */
3890		{ RCAR_GP_PIN(3, 28), 16, 2 },	/* RPC_WP_N */
3891		{ RCAR_GP_PIN(3, 27), 12, 2 },	/* RPC_RESET_N */
3892		{ RCAR_GP_PIN(3, 26),  8, 2 },	/* QSPI1_IO3 */
3893		{ RCAR_GP_PIN(3, 25),  4, 2 },	/* QSPI1_SSL */
3894		{ RCAR_GP_PIN(3, 24),  0, 2 },	/* QSPI1_IO2 */
3895	} },
3896	{ PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3897		{ RCAR_GP_PIN(4,  7), 28, 3 },	/* TSN0_RX_CTL */
3898		{ RCAR_GP_PIN(4,  6), 24, 3 },	/* TSN0_AVTP_CAPTURE */
3899		{ RCAR_GP_PIN(4,  5), 20, 3 },	/* TSN0_AVTP_MATCH */
3900		{ RCAR_GP_PIN(4,  4), 16, 3 },	/* TSN0_LINK */
3901		{ RCAR_GP_PIN(4,  3), 12, 3 },	/* TSN0_PHY_INT */
3902		{ RCAR_GP_PIN(4,  2),  8, 3 },	/* TSN0_AVTP_PPS1 */
3903		{ RCAR_GP_PIN(4,  1),  4, 3 },	/* TSN0_MDC */
3904		{ RCAR_GP_PIN(4,  0),  0, 3 },	/* TSN0_MDIO */
3905	} },
3906	{ PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3907		{ RCAR_GP_PIN(4, 15), 28, 3 },	/* TSN0_TD0 */
3908		{ RCAR_GP_PIN(4, 14), 24, 3 },	/* TSN0_TD1 */
3909		{ RCAR_GP_PIN(4, 13), 20, 3 },	/* TSN0_RD1 */
3910		{ RCAR_GP_PIN(4, 12), 16, 3 },	/* TSN0_TXC */
3911		{ RCAR_GP_PIN(4, 11), 12, 3 },	/* TSN0_RXC */
3912		{ RCAR_GP_PIN(4, 10),  8, 3 },	/* TSN0_RD0 */
3913		{ RCAR_GP_PIN(4,  9),  4, 3 },	/* TSN0_TX_CTL */
3914		{ RCAR_GP_PIN(4,  8),  0, 3 },	/* TSN0_AVTP_PPS0 */
3915	} },
3916	{ PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3917		{ RCAR_GP_PIN(4, 23), 28, 3 },	/* AVS0 */
3918		{ RCAR_GP_PIN(4, 22), 24, 3 },	/* PCIE1_CLKREQ_N */
3919		{ RCAR_GP_PIN(4, 21), 20, 3 },	/* PCIE0_CLKREQ_N */
3920		{ RCAR_GP_PIN(4, 20), 16, 3 },	/* TSN0_TXCREFCLK */
3921		{ RCAR_GP_PIN(4, 19), 12, 3 },	/* TSN0_TD2 */
3922		{ RCAR_GP_PIN(4, 18),  8, 3 },	/* TSN0_TD3 */
3923		{ RCAR_GP_PIN(4, 17),  4, 3 },	/* TSN0_RD2 */
3924		{ RCAR_GP_PIN(4, 16),  0, 3 },	/* TSN0_RD3 */
3925	} },
3926	{ PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3927		{ RCAR_GP_PIN(4, 24),  0, 3 },	/* AVS1 */
3928	} },
3929	{ PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3930		{ RCAR_GP_PIN(5,  7), 28, 3 },	/* AVB2_TXCREFCLK */
3931		{ RCAR_GP_PIN(5,  6), 24, 3 },	/* AVB2_MDC */
3932		{ RCAR_GP_PIN(5,  5), 20, 3 },	/* AVB2_MAGIC */
3933		{ RCAR_GP_PIN(5,  4), 16, 3 },	/* AVB2_PHY_INT */
3934		{ RCAR_GP_PIN(5,  3), 12, 3 },	/* AVB2_LINK */
3935		{ RCAR_GP_PIN(5,  2),  8, 3 },	/* AVB2_AVTP_MATCH */
3936		{ RCAR_GP_PIN(5,  1),  4, 3 },	/* AVB2_AVTP_CAPTURE */
3937		{ RCAR_GP_PIN(5,  0),  0, 3 },	/* AVB2_AVTP_PPS */
3938	} },
3939	{ PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3940		{ RCAR_GP_PIN(5, 15), 28, 3 },	/* AVB2_TD0 */
3941		{ RCAR_GP_PIN(5, 14), 24, 3 },	/* AVB2_RD1 */
3942		{ RCAR_GP_PIN(5, 13), 20, 3 },	/* AVB2_RD2 */
3943		{ RCAR_GP_PIN(5, 12), 16, 3 },	/* AVB2_TD1 */
3944		{ RCAR_GP_PIN(5, 11), 12, 3 },	/* AVB2_TD2 */
3945		{ RCAR_GP_PIN(5, 10),  8, 3 },	/* AVB2_MDIO */
3946		{ RCAR_GP_PIN(5,  9),  4, 3 },	/* AVB2_RD3 */
3947		{ RCAR_GP_PIN(5,  8),  0, 3 },	/* AVB2_TD3 */
3948	} },
3949	{ PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3950		{ RCAR_GP_PIN(5, 20), 16, 3 },	/* AVB2_RX_CTL */
3951		{ RCAR_GP_PIN(5, 19), 12, 3 },	/* AVB2_TX_CTL */
3952		{ RCAR_GP_PIN(5, 18),  8, 3 },	/* AVB2_RXC */
3953		{ RCAR_GP_PIN(5, 17),  4, 3 },	/* AVB2_RD0 */
3954		{ RCAR_GP_PIN(5, 16),  0, 3 },	/* AVB2_TXC */
3955	} },
3956	{ PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3957		{ RCAR_GP_PIN(6,  7), 28, 3 },	/* AVB1_TX_CTL */
3958		{ RCAR_GP_PIN(6,  6), 24, 3 },	/* AVB1_TXC */
3959		{ RCAR_GP_PIN(6,  5), 20, 3 },	/* AVB1_AVTP_MATCH */
3960		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* AVB1_LINK */
3961		{ RCAR_GP_PIN(6,  3), 12, 3 },	/* AVB1_PHY_INT */
3962		{ RCAR_GP_PIN(6,  2),  8, 3 },	/* AVB1_MDC */
3963		{ RCAR_GP_PIN(6,  1),  4, 3 },	/* AVB1_MAGIC */
3964		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* AVB1_MDIO */
3965	} },
3966	{ PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3967		{ RCAR_GP_PIN(6, 15), 28, 3 },	/* AVB1_RD0 */
3968		{ RCAR_GP_PIN(6, 14), 24, 3 },	/* AVB1_RD1 */
3969		{ RCAR_GP_PIN(6, 13), 20, 3 },	/* AVB1_TD0 */
3970		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* AVB1_TD1 */
3971		{ RCAR_GP_PIN(6, 11), 12, 3 },	/* AVB1_AVTP_CAPTURE */
3972		{ RCAR_GP_PIN(6, 10),  8, 3 },	/* AVB1_AVTP_PPS */
3973		{ RCAR_GP_PIN(6,  9),  4, 3 },	/* AVB1_RX_CTL */
3974		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* AVB1_RXC */
3975	} },
3976	{ PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3977		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* AVB1_TXCREFCLK */
3978		{ RCAR_GP_PIN(6, 19), 12, 3 },	/* AVB1_RD3 */
3979		{ RCAR_GP_PIN(6, 18),  8, 3 },	/* AVB1_TD3 */
3980		{ RCAR_GP_PIN(6, 17),  4, 3 },	/* AVB1_RD2 */
3981		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* AVB1_TD2 */
3982	} },
3983	{ PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3984		{ RCAR_GP_PIN(7,  7), 28, 3 },	/* AVB0_TD1 */
3985		{ RCAR_GP_PIN(7,  6), 24, 3 },	/* AVB0_TD2 */
3986		{ RCAR_GP_PIN(7,  5), 20, 3 },	/* AVB0_PHY_INT */
3987		{ RCAR_GP_PIN(7,  4), 16, 3 },	/* AVB0_LINK */
3988		{ RCAR_GP_PIN(7,  3), 12, 3 },	/* AVB0_TD3 */
3989		{ RCAR_GP_PIN(7,  2),  8, 3 },	/* AVB0_AVTP_MATCH */
3990		{ RCAR_GP_PIN(7,  1),  4, 3 },	/* AVB0_AVTP_CAPTURE */
3991		{ RCAR_GP_PIN(7,  0),  0, 3 },	/* AVB0_AVTP_PPS */
3992	} },
3993	{ PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3994		{ RCAR_GP_PIN(7, 15), 28, 3 },	/* AVB0_TXC */
3995		{ RCAR_GP_PIN(7, 14), 24, 3 },	/* AVB0_MDIO */
3996		{ RCAR_GP_PIN(7, 13), 20, 3 },	/* AVB0_MDC */
3997		{ RCAR_GP_PIN(7, 12), 16, 3 },	/* AVB0_RD2 */
3998		{ RCAR_GP_PIN(7, 11), 12, 3 },	/* AVB0_TD0 */
3999		{ RCAR_GP_PIN(7, 10),  8, 3 },	/* AVB0_MAGIC */
4000		{ RCAR_GP_PIN(7,  9),  4, 3 },	/* AVB0_TXCREFCLK */
4001		{ RCAR_GP_PIN(7,  8),  0, 3 },	/* AVB0_RD3 */
4002	} },
4003	{ PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
4004		{ RCAR_GP_PIN(7, 20), 16, 3 },	/* AVB0_RX_CTL */
4005		{ RCAR_GP_PIN(7, 19), 12, 3 },	/* AVB0_RXC */
4006		{ RCAR_GP_PIN(7, 18),  8, 3 },	/* AVB0_RD0 */
4007		{ RCAR_GP_PIN(7, 17),  4, 3 },	/* AVB0_RD1 */
4008		{ RCAR_GP_PIN(7, 16),  0, 3 },	/* AVB0_TX_CTL */
4009	} },
4010	{ PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
4011		{ RCAR_GP_PIN(8,  7), 28, 3 },	/* SDA3 */
4012		{ RCAR_GP_PIN(8,  6), 24, 3 },	/* SCL3 */
4013		{ RCAR_GP_PIN(8,  5), 20, 3 },	/* SDA2 */
4014		{ RCAR_GP_PIN(8,  4), 16, 3 },	/* SCL2 */
4015		{ RCAR_GP_PIN(8,  3), 12, 3 },	/* SDA1 */
4016		{ RCAR_GP_PIN(8,  2),  8, 3 },	/* SCL1 */
4017		{ RCAR_GP_PIN(8,  1),  4, 3 },	/* SDA0 */
4018		{ RCAR_GP_PIN(8,  0),  0, 3 },	/* SCL0 */
4019	} },
4020	{ PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
4021		{ RCAR_GP_PIN(8, 13), 20, 3 },	/* GP8_13 */
4022		{ RCAR_GP_PIN(8, 12), 16, 3 },	/* GP8_12 */
4023		{ RCAR_GP_PIN(8, 11), 12, 3 },	/* SDA5 */
4024		{ RCAR_GP_PIN(8, 10),  8, 3 },	/* SCL5 */
4025		{ RCAR_GP_PIN(8,  9),  4, 3 },	/* SDA4 */
4026		{ RCAR_GP_PIN(8,  8),  0, 3 },	/* SCL4 */
4027	} },
4028	{ /* sentinel */ }
4029};
4030
4031enum ioctrl_regs {
4032	POC0,
4033	POC1,
4034	POC3,
4035	POC4,
4036	POC5,
4037	POC6,
4038	POC7,
4039	POC8,
4040};
4041
4042static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4043	[POC0]		= { 0xE60500A0, },
4044	[POC1]		= { 0xE60508A0, },
4045	[POC3]		= { 0xE60588A0, },
4046	[POC4]		= { 0xE60600A0, },
4047	[POC5]		= { 0xE60608A0, },
4048	[POC6]		= { 0xE60610A0, },
4049	[POC7]		= { 0xE60618A0, },
4050	[POC8]		= { 0xE60680A0, },
4051	{ /* sentinel */ }
4052};
4053
4054static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
4055{
4056	int bit = pin & 0x1f;
4057
4058	switch (pin) {
4059	case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
4060		*pocctrl = pinmux_ioctrl_regs[POC0].reg;
4061		return bit;
4062
4063	case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
4064		*pocctrl = pinmux_ioctrl_regs[POC1].reg;
4065		return bit;
4066
4067	case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
4068		*pocctrl = pinmux_ioctrl_regs[POC3].reg;
4069		return bit;
4070
4071	case PIN_VDDQ_TSN0:
4072		*pocctrl = pinmux_ioctrl_regs[POC4].reg;
4073		return 0;
4074
4075	case PIN_VDDQ_AVB2:
4076		*pocctrl = pinmux_ioctrl_regs[POC5].reg;
4077		return 0;
4078
4079	case PIN_VDDQ_AVB1:
4080		*pocctrl = pinmux_ioctrl_regs[POC6].reg;
4081		return 0;
4082
4083	case PIN_VDDQ_AVB0:
4084		*pocctrl = pinmux_ioctrl_regs[POC7].reg;
4085		return 0;
4086
4087	case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
4088		*pocctrl = pinmux_ioctrl_regs[POC8].reg;
4089		return bit;
4090
4091	default:
4092		return -EINVAL;
4093	}
4094}
4095
4096static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4097	{ PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
4098		[ 0] = RCAR_GP_PIN(0,  0),	/* GP0_00 */
4099		[ 1] = RCAR_GP_PIN(0,  1),	/* GP0_01 */
4100		[ 2] = RCAR_GP_PIN(0,  2),	/* GP0_02 */
4101		[ 3] = RCAR_GP_PIN(0,  3),	/* IRQ3 */
4102		[ 4] = RCAR_GP_PIN(0,  4),	/* IRQ2 */
4103		[ 5] = RCAR_GP_PIN(0,  5),	/* IRQ1 */
4104		[ 6] = RCAR_GP_PIN(0,  6),	/* IRQ0 */
4105		[ 7] = RCAR_GP_PIN(0,  7),	/* MSIOF5_SS2 */
4106		[ 8] = RCAR_GP_PIN(0,  8),	/* MSIOF5_SS1 */
4107		[ 9] = RCAR_GP_PIN(0,  9),	/* MSIOF5_SYNC */
4108		[10] = RCAR_GP_PIN(0, 10),	/* MSIOF5_TXD */
4109		[11] = RCAR_GP_PIN(0, 11),	/* MSIOF5_SCK */
4110		[12] = RCAR_GP_PIN(0, 12),	/* MSIOF5_RXD */
4111		[13] = RCAR_GP_PIN(0, 13),	/* MSIOF2_SS2 */
4112		[14] = RCAR_GP_PIN(0, 14),	/* MSIOF2_SS1 */
4113		[15] = RCAR_GP_PIN(0, 15),	/* MSIOF2_SYNC */
4114		[16] = RCAR_GP_PIN(0, 16),	/* MSIOF2_TXD */
4115		[17] = RCAR_GP_PIN(0, 17),	/* MSIOF2_SCK */
4116		[18] = RCAR_GP_PIN(0, 18),	/* MSIOF2_RXD */
4117		[19] = SH_PFC_PIN_NONE,
4118		[20] = SH_PFC_PIN_NONE,
4119		[21] = SH_PFC_PIN_NONE,
4120		[22] = SH_PFC_PIN_NONE,
4121		[23] = SH_PFC_PIN_NONE,
4122		[24] = SH_PFC_PIN_NONE,
4123		[25] = SH_PFC_PIN_NONE,
4124		[26] = SH_PFC_PIN_NONE,
4125		[27] = SH_PFC_PIN_NONE,
4126		[28] = SH_PFC_PIN_NONE,
4127		[29] = SH_PFC_PIN_NONE,
4128		[30] = SH_PFC_PIN_NONE,
4129		[31] = SH_PFC_PIN_NONE,
4130	} },
4131	{ PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
4132		[ 0] = RCAR_GP_PIN(1,  0),	/* MSIOF1_SS2 */
4133		[ 1] = RCAR_GP_PIN(1,  1),	/* MSIOF1_SS1 */
4134		[ 2] = RCAR_GP_PIN(1,  2),	/* MSIOF1_SYNC */
4135		[ 3] = RCAR_GP_PIN(1,  3),	/* MSIOF1_SCK */
4136		[ 4] = RCAR_GP_PIN(1,  4),	/* MSIOF1_TXD */
4137		[ 5] = RCAR_GP_PIN(1,  5),	/* MSIOF1_RXD */
4138		[ 6] = RCAR_GP_PIN(1,  6),	/* MSIOF0_SS2 */
4139		[ 7] = RCAR_GP_PIN(1,  7),	/* MSIOF0_SS1 */
4140		[ 8] = RCAR_GP_PIN(1,  8),	/* MSIOF0_SYNC */
4141		[ 9] = RCAR_GP_PIN(1,  9),	/* MSIOF0_TXD */
4142		[10] = RCAR_GP_PIN(1, 10),	/* MSIOF0_SCK */
4143		[11] = RCAR_GP_PIN(1, 11),	/* MSIOF0_RXD */
4144		[12] = RCAR_GP_PIN(1, 12),	/* HTX0 */
4145		[13] = RCAR_GP_PIN(1, 13),	/* HCTS0_N */
4146		[14] = RCAR_GP_PIN(1, 14),	/* HRTS0_N */
4147		[15] = RCAR_GP_PIN(1, 15),	/* HSCK0 */
4148		[16] = RCAR_GP_PIN(1, 16),	/* HRX0 */
4149		[17] = RCAR_GP_PIN(1, 17),	/* SCIF_CLK */
4150		[18] = RCAR_GP_PIN(1, 18),	/* SSI_SCK */
4151		[19] = RCAR_GP_PIN(1, 19),	/* SSI_WS */
4152		[20] = RCAR_GP_PIN(1, 20),	/* SSI_SD */
4153		[21] = RCAR_GP_PIN(1, 21),	/* AUDIO_CLKOUT */
4154		[22] = RCAR_GP_PIN(1, 22),	/* AUDIO_CLKIN */
4155		[23] = RCAR_GP_PIN(1, 23),	/* GP1_23 */
4156		[24] = RCAR_GP_PIN(1, 24),	/* HRX3 */
4157		[25] = RCAR_GP_PIN(1, 25),	/* HSCK3 */
4158		[26] = RCAR_GP_PIN(1, 26),	/* HRTS3_N */
4159		[27] = RCAR_GP_PIN(1, 27),	/* HCTS3_N */
4160		[28] = RCAR_GP_PIN(1, 28),	/* HTX3 */
4161		[29] = SH_PFC_PIN_NONE,
4162		[30] = SH_PFC_PIN_NONE,
4163		[31] = SH_PFC_PIN_NONE,
4164	} },
4165	{ PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
4166		[ 0] = RCAR_GP_PIN(2,  0),	/* FXR_TXDA */
4167		[ 1] = RCAR_GP_PIN(2,  1),	/* FXR_TXENA_N */
4168		[ 2] = RCAR_GP_PIN(2,  2),	/* RXDA_EXTFXR */
4169		[ 3] = RCAR_GP_PIN(2,  3),	/* CLK_EXTFXR */
4170		[ 4] = RCAR_GP_PIN(2,  4),	/* RXDB_EXTFXR */
4171		[ 5] = RCAR_GP_PIN(2,  5),	/* FXR_TXENB_N */
4172		[ 6] = RCAR_GP_PIN(2,  6),	/* FXR_TXDB */
4173		[ 7] = RCAR_GP_PIN(2,  7),	/* TPU0TO1 */
4174		[ 8] = RCAR_GP_PIN(2,  8),	/* TPU0TO0 */
4175		[ 9] = RCAR_GP_PIN(2,  9),	/* CAN_CLK */
4176		[10] = RCAR_GP_PIN(2, 10),	/* CANFD0_TX */
4177		[11] = RCAR_GP_PIN(2, 11),	/* CANFD0_RX */
4178		[12] = RCAR_GP_PIN(2, 12),	/* CANFD2_TX */
4179		[13] = RCAR_GP_PIN(2, 13),	/* CANFD2_RX */
4180		[14] = RCAR_GP_PIN(2, 14),	/* CANFD3_TX */
4181		[15] = RCAR_GP_PIN(2, 15),	/* CANFD3_RX */
4182		[16] = RCAR_GP_PIN(2, 16),	/* CANFD4_TX */
4183		[17] = RCAR_GP_PIN(2, 17),	/* CANFD4_RX */
4184		[18] = RCAR_GP_PIN(2, 18),	/* CANFD7_TX */
4185		[19] = RCAR_GP_PIN(2, 19),	/* CANFD7_RX */
4186		[20] = SH_PFC_PIN_NONE,
4187		[21] = SH_PFC_PIN_NONE,
4188		[22] = SH_PFC_PIN_NONE,
4189		[23] = SH_PFC_PIN_NONE,
4190		[24] = SH_PFC_PIN_NONE,
4191		[25] = SH_PFC_PIN_NONE,
4192		[26] = SH_PFC_PIN_NONE,
4193		[27] = SH_PFC_PIN_NONE,
4194		[28] = SH_PFC_PIN_NONE,
4195		[29] = SH_PFC_PIN_NONE,
4196		[30] = SH_PFC_PIN_NONE,
4197		[31] = SH_PFC_PIN_NONE,
4198	} },
4199	{ PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4200		[ 0] = RCAR_GP_PIN(3,  0),	/* MMC_SD_D1 */
4201		[ 1] = RCAR_GP_PIN(3,  1),	/* MMC_SD_D0 */
4202		[ 2] = RCAR_GP_PIN(3,  2),	/* MMC_SD_D2 */
4203		[ 3] = RCAR_GP_PIN(3,  3),	/* MMC_SD_CLK */
4204		[ 4] = RCAR_GP_PIN(3,  4),	/* MMC_DS */
4205		[ 5] = RCAR_GP_PIN(3,  5),	/* MMC_SD_D3 */
4206		[ 6] = RCAR_GP_PIN(3,  6),	/* MMC_D5 */
4207		[ 7] = RCAR_GP_PIN(3,  7),	/* MMC_D4 */
4208		[ 8] = RCAR_GP_PIN(3,  8),	/* MMC_D7 */
4209		[ 9] = RCAR_GP_PIN(3,  9),	/* MMC_D6 */
4210		[10] = RCAR_GP_PIN(3, 10),	/* MMC_SD_CMD */
4211		[11] = RCAR_GP_PIN(3, 11),	/* SD_CD */
4212		[12] = RCAR_GP_PIN(3, 12),	/* SD_WP */
4213		[13] = RCAR_GP_PIN(3, 13),	/* IPC_CLKIN */
4214		[14] = RCAR_GP_PIN(3, 14),	/* IPC_CLKOUT */
4215		[15] = RCAR_GP_PIN(3, 15),	/* QSPI0_SSL */
4216		[16] = RCAR_GP_PIN(3, 16),	/* QSPI0_IO3 */
4217		[17] = RCAR_GP_PIN(3, 17),	/* QSPI0_IO2 */
4218		[18] = RCAR_GP_PIN(3, 18),	/* QSPI0_MISO_IO1 */
4219		[19] = RCAR_GP_PIN(3, 19),	/* QSPI0_MOSI_IO0 */
4220		[20] = RCAR_GP_PIN(3, 20),	/* QSPI0_SPCLK */
4221		[21] = RCAR_GP_PIN(3, 21),	/* QSPI1_MOSI_IO0 */
4222		[22] = RCAR_GP_PIN(3, 22),	/* QSPI1_SPCLK */
4223		[23] = RCAR_GP_PIN(3, 23),	/* QSPI1_MISO_IO1 */
4224		[24] = RCAR_GP_PIN(3, 24),	/* QSPI1_IO2 */
4225		[25] = RCAR_GP_PIN(3, 25),	/* QSPI1_SSL */
4226		[26] = RCAR_GP_PIN(3, 26),	/* QSPI1_IO3 */
4227		[27] = RCAR_GP_PIN(3, 27),	/* RPC_RESET_N */
4228		[28] = RCAR_GP_PIN(3, 28),	/* RPC_WP_N */
4229		[29] = RCAR_GP_PIN(3, 29),	/* RPC_INT_N */
4230		[30] = SH_PFC_PIN_NONE,
4231		[31] = SH_PFC_PIN_NONE,
4232	} },
4233	{ PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4234		[ 0] = RCAR_GP_PIN(4,  0),	/* TSN0_MDIO */
4235		[ 1] = RCAR_GP_PIN(4,  1),	/* TSN0_MDC */
4236		[ 2] = RCAR_GP_PIN(4,  2),	/* TSN0_AVTP_PPS1 */
4237		[ 3] = RCAR_GP_PIN(4,  3),	/* TSN0_PHY_INT */
4238		[ 4] = RCAR_GP_PIN(4,  4),	/* TSN0_LINK */
4239		[ 5] = RCAR_GP_PIN(4,  5),	/* TSN0_AVTP_MATCH */
4240		[ 6] = RCAR_GP_PIN(4,  6),	/* TSN0_AVTP_CAPTURE */
4241		[ 7] = RCAR_GP_PIN(4,  7),	/* TSN0_RX_CTL */
4242		[ 8] = RCAR_GP_PIN(4,  8),	/* TSN0_AVTP_PPS0 */
4243		[ 9] = RCAR_GP_PIN(4,  9),	/* TSN0_TX_CTL */
4244		[10] = RCAR_GP_PIN(4, 10),	/* TSN0_RD0 */
4245		[11] = RCAR_GP_PIN(4, 11),	/* TSN0_RXC */
4246		[12] = RCAR_GP_PIN(4, 12),	/* TSN0_TXC */
4247		[13] = RCAR_GP_PIN(4, 13),	/* TSN0_RD1 */
4248		[14] = RCAR_GP_PIN(4, 14),	/* TSN0_TD1 */
4249		[15] = RCAR_GP_PIN(4, 15),	/* TSN0_TD0 */
4250		[16] = RCAR_GP_PIN(4, 16),	/* TSN0_RD3 */
4251		[17] = RCAR_GP_PIN(4, 17),	/* TSN0_RD2 */
4252		[18] = RCAR_GP_PIN(4, 18),	/* TSN0_TD3 */
4253		[19] = RCAR_GP_PIN(4, 19),	/* TSN0_TD2 */
4254		[20] = RCAR_GP_PIN(4, 20),	/* TSN0_TXCREFCLK */
4255		[21] = RCAR_GP_PIN(4, 21),	/* PCIE0_CLKREQ_N */
4256		[22] = RCAR_GP_PIN(4, 22),	/* PCIE1_CLKREQ_N */
4257		[23] = RCAR_GP_PIN(4, 23),	/* AVS0 */
4258		[24] = RCAR_GP_PIN(4, 24),	/* AVS1 */
4259		[25] = SH_PFC_PIN_NONE,
4260		[26] = SH_PFC_PIN_NONE,
4261		[27] = SH_PFC_PIN_NONE,
4262		[28] = SH_PFC_PIN_NONE,
4263		[29] = SH_PFC_PIN_NONE,
4264		[30] = SH_PFC_PIN_NONE,
4265		[31] = SH_PFC_PIN_NONE,
4266	} },
4267	{ PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4268		[ 0] = RCAR_GP_PIN(5,  0),	/* AVB2_AVTP_PPS */
4269		[ 1] = RCAR_GP_PIN(5,  1),	/* AVB0_AVTP_CAPTURE */
4270		[ 2] = RCAR_GP_PIN(5,  2),	/* AVB2_AVTP_MATCH */
4271		[ 3] = RCAR_GP_PIN(5,  3),	/* AVB2_LINK */
4272		[ 4] = RCAR_GP_PIN(5,  4),	/* AVB2_PHY_INT */
4273		[ 5] = RCAR_GP_PIN(5,  5),	/* AVB2_MAGIC */
4274		[ 6] = RCAR_GP_PIN(5,  6),	/* AVB2_MDC */
4275		[ 7] = RCAR_GP_PIN(5,  7),	/* AVB2_TXCREFCLK */
4276		[ 8] = RCAR_GP_PIN(5,  8),	/* AVB2_TD3 */
4277		[ 9] = RCAR_GP_PIN(5,  9),	/* AVB2_RD3 */
4278		[10] = RCAR_GP_PIN(5, 10),	/* AVB2_MDIO */
4279		[11] = RCAR_GP_PIN(5, 11),	/* AVB2_TD2 */
4280		[12] = RCAR_GP_PIN(5, 12),	/* AVB2_TD1 */
4281		[13] = RCAR_GP_PIN(5, 13),	/* AVB2_RD2 */
4282		[14] = RCAR_GP_PIN(5, 14),	/* AVB2_RD1 */
4283		[15] = RCAR_GP_PIN(5, 15),	/* AVB2_TD0 */
4284		[16] = RCAR_GP_PIN(5, 16),	/* AVB2_TXC */
4285		[17] = RCAR_GP_PIN(5, 17),	/* AVB2_RD0 */
4286		[18] = RCAR_GP_PIN(5, 18),	/* AVB2_RXC */
4287		[19] = RCAR_GP_PIN(5, 19),	/* AVB2_TX_CTL */
4288		[20] = RCAR_GP_PIN(5, 20),	/* AVB2_RX_CTL */
4289		[21] = SH_PFC_PIN_NONE,
4290		[22] = SH_PFC_PIN_NONE,
4291		[23] = SH_PFC_PIN_NONE,
4292		[24] = SH_PFC_PIN_NONE,
4293		[25] = SH_PFC_PIN_NONE,
4294		[26] = SH_PFC_PIN_NONE,
4295		[27] = SH_PFC_PIN_NONE,
4296		[28] = SH_PFC_PIN_NONE,
4297		[29] = SH_PFC_PIN_NONE,
4298		[30] = SH_PFC_PIN_NONE,
4299		[31] = SH_PFC_PIN_NONE,
4300	} },
4301	{ PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4302		[ 0] = RCAR_GP_PIN(6,  0),	/* AVB1_MDIO */
4303		[ 1] = RCAR_GP_PIN(6,  1),	/* AVB1_MAGIC */
4304		[ 2] = RCAR_GP_PIN(6,  2),	/* AVB1_MDC */
4305		[ 3] = RCAR_GP_PIN(6,  3),	/* AVB1_PHY_INT */
4306		[ 4] = RCAR_GP_PIN(6,  4),	/* AVB1_LINK */
4307		[ 5] = RCAR_GP_PIN(6,  5),	/* AVB1_AVTP_MATCH */
4308		[ 6] = RCAR_GP_PIN(6,  6),	/* AVB1_TXC */
4309		[ 7] = RCAR_GP_PIN(6,  7),	/* AVB1_TX_CTL */
4310		[ 8] = RCAR_GP_PIN(6,  8),	/* AVB1_RXC */
4311		[ 9] = RCAR_GP_PIN(6,  9),	/* AVB1_RX_CTL */
4312		[10] = RCAR_GP_PIN(6, 10),	/* AVB1_AVTP_PPS */
4313		[11] = RCAR_GP_PIN(6, 11),	/* AVB1_AVTP_CAPTURE */
4314		[12] = RCAR_GP_PIN(6, 12),	/* AVB1_TD1 */
4315		[13] = RCAR_GP_PIN(6, 13),	/* AVB1_TD0 */
4316		[14] = RCAR_GP_PIN(6, 14),	/* AVB1_RD1*/
4317		[15] = RCAR_GP_PIN(6, 15),	/* AVB1_RD0 */
4318		[16] = RCAR_GP_PIN(6, 16),	/* AVB1_TD2 */
4319		[17] = RCAR_GP_PIN(6, 17),	/* AVB1_RD2 */
4320		[18] = RCAR_GP_PIN(6, 18),	/* AVB1_TD3 */
4321		[19] = RCAR_GP_PIN(6, 19),	/* AVB1_RD3 */
4322		[20] = RCAR_GP_PIN(6, 20),	/* AVB1_TXCREFCLK */
4323		[21] = SH_PFC_PIN_NONE,
4324		[22] = SH_PFC_PIN_NONE,
4325		[23] = SH_PFC_PIN_NONE,
4326		[24] = SH_PFC_PIN_NONE,
4327		[25] = SH_PFC_PIN_NONE,
4328		[26] = SH_PFC_PIN_NONE,
4329		[27] = SH_PFC_PIN_NONE,
4330		[28] = SH_PFC_PIN_NONE,
4331		[29] = SH_PFC_PIN_NONE,
4332		[30] = SH_PFC_PIN_NONE,
4333		[31] = SH_PFC_PIN_NONE,
4334	} },
4335	{ PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4336		[ 0] = RCAR_GP_PIN(7,  0),	/* AVB0_AVTP_PPS */
4337		[ 1] = RCAR_GP_PIN(7,  1),	/* AVB0_AVTP_CAPTURE */
4338		[ 2] = RCAR_GP_PIN(7,  2),	/* AVB0_AVTP_MATCH */
4339		[ 3] = RCAR_GP_PIN(7,  3),	/* AVB0_TD3 */
4340		[ 4] = RCAR_GP_PIN(7,  4),	/* AVB0_LINK */
4341		[ 5] = RCAR_GP_PIN(7,  5),	/* AVB0_PHY_INT */
4342		[ 6] = RCAR_GP_PIN(7,  6),	/* AVB0_TD2 */
4343		[ 7] = RCAR_GP_PIN(7,  7),	/* AVB0_TD1 */
4344		[ 8] = RCAR_GP_PIN(7,  8),	/* AVB0_RD3 */
4345		[ 9] = RCAR_GP_PIN(7,  9),	/* AVB0_TXCREFCLK */
4346		[10] = RCAR_GP_PIN(7, 10),	/* AVB0_MAGIC */
4347		[11] = RCAR_GP_PIN(7, 11),	/* AVB0_TD0 */
4348		[12] = RCAR_GP_PIN(7, 12),	/* AVB0_RD2 */
4349		[13] = RCAR_GP_PIN(7, 13),	/* AVB0_MDC */
4350		[14] = RCAR_GP_PIN(7, 14),	/* AVB0_MDIO */
4351		[15] = RCAR_GP_PIN(7, 15),	/* AVB0_TXC */
4352		[16] = RCAR_GP_PIN(7, 16),	/* AVB0_TX_CTL */
4353		[17] = RCAR_GP_PIN(7, 17),	/* AVB0_RD1 */
4354		[18] = RCAR_GP_PIN(7, 18),	/* AVB0_RD0 */
4355		[19] = RCAR_GP_PIN(7, 19),	/* AVB0_RXC */
4356		[20] = RCAR_GP_PIN(7, 20),	/* AVB0_RX_CTL */
4357		[21] = SH_PFC_PIN_NONE,
4358		[22] = SH_PFC_PIN_NONE,
4359		[23] = SH_PFC_PIN_NONE,
4360		[24] = SH_PFC_PIN_NONE,
4361		[25] = SH_PFC_PIN_NONE,
4362		[26] = SH_PFC_PIN_NONE,
4363		[27] = SH_PFC_PIN_NONE,
4364		[28] = SH_PFC_PIN_NONE,
4365		[29] = SH_PFC_PIN_NONE,
4366		[30] = SH_PFC_PIN_NONE,
4367		[31] = SH_PFC_PIN_NONE,
4368	} },
4369	{ PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4370		[ 0] = RCAR_GP_PIN(8,  0),	/* SCL0 */
4371		[ 1] = RCAR_GP_PIN(8,  1),	/* SDA0 */
4372		[ 2] = RCAR_GP_PIN(8,  2),	/* SCL1 */
4373		[ 3] = RCAR_GP_PIN(8,  3),	/* SDA1 */
4374		[ 4] = RCAR_GP_PIN(8,  4),	/* SCL2 */
4375		[ 5] = RCAR_GP_PIN(8,  5),	/* SDA2 */
4376		[ 6] = RCAR_GP_PIN(8,  6),	/* SCL3 */
4377		[ 7] = RCAR_GP_PIN(8,  7),	/* SDA3 */
4378		[ 8] = RCAR_GP_PIN(8,  8),	/* SCL4 */
4379		[ 9] = RCAR_GP_PIN(8,  9),	/* SDA4 */
4380		[10] = RCAR_GP_PIN(8, 10),	/* SCL5 */
4381		[11] = RCAR_GP_PIN(8, 11),	/* SDA5 */
4382		[12] = RCAR_GP_PIN(8, 12),	/* GP8_12 */
4383		[13] = RCAR_GP_PIN(8, 13),	/* GP8_13 */
4384		[14] = SH_PFC_PIN_NONE,
4385		[15] = SH_PFC_PIN_NONE,
4386		[16] = SH_PFC_PIN_NONE,
4387		[17] = SH_PFC_PIN_NONE,
4388		[18] = SH_PFC_PIN_NONE,
4389		[19] = SH_PFC_PIN_NONE,
4390		[20] = SH_PFC_PIN_NONE,
4391		[21] = SH_PFC_PIN_NONE,
4392		[22] = SH_PFC_PIN_NONE,
4393		[23] = SH_PFC_PIN_NONE,
4394		[24] = SH_PFC_PIN_NONE,
4395		[25] = SH_PFC_PIN_NONE,
4396		[26] = SH_PFC_PIN_NONE,
4397		[27] = SH_PFC_PIN_NONE,
4398		[28] = SH_PFC_PIN_NONE,
4399		[29] = SH_PFC_PIN_NONE,
4400		[30] = SH_PFC_PIN_NONE,
4401		[31] = SH_PFC_PIN_NONE,
4402	} },
4403	{ /* sentinel */ }
4404};
4405
4406static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4407	.pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4408	.get_bias = rcar_pinmux_get_bias,
4409	.set_bias = rcar_pinmux_set_bias,
4410};
4411
4412const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4413	.name = "r8a779g0_pfc",
4414	.ops = &r8a779g0_pin_ops,
4415	.unlock_reg = 0x1ff,	/* PMMRn mask */
4416
4417	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4418
4419	.pins = pinmux_pins,
4420	.nr_pins = ARRAY_SIZE(pinmux_pins),
4421	.groups = pinmux_groups,
4422	.nr_groups = ARRAY_SIZE(pinmux_groups),
4423	.functions = pinmux_functions,
4424	.nr_functions = ARRAY_SIZE(pinmux_functions),
4425
4426	.cfg_regs = pinmux_config_regs,
4427	.drive_regs = pinmux_drive_regs,
4428	.bias_regs = pinmux_bias_regs,
4429	.ioctrl_regs = pinmux_ioctrl_regs,
4430
4431	.pinmux_data = pinmux_data,
4432	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
4433};