pfc-r8a779f0.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A779F0 processor support - PFC hardware block.
   4 *
   5 * Copyright (C) 2021 Renesas Electronics Corp.
   6 *
   7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
   8 */
   9
  10#include <linux/errno.h>
  11#include <linux/io.h>
  12#include <linux/kernel.h>
  13
  14#include "sh_pfc.h"
  15
  16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  17
  18#define CPU_ALL_GP(fn, sfx)	\
  19	PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  20	PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  21	PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS),	\
  22	PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
  23
  24#define CPU_ALL_NOGP(fn)								\
  25	PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN),	\
  26	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  27
  28/*
  29 * F_() : just information
  30 * FM() : macro for FN_xxx / xxx_MARK
  31 */
  32
  33/* GPSR0 */
  34#define GPSR0_20	F_(IRQ3,	IP2SR0_19_16)
  35#define GPSR0_19	F_(IRQ2,	IP2SR0_15_12)
  36#define GPSR0_18	F_(IRQ1,	IP2SR0_11_8)
  37#define GPSR0_17	F_(IRQ0,	IP2SR0_7_4)
  38#define GPSR0_16	F_(MSIOF0_SS2,	IP2SR0_3_0)
  39#define GPSR0_15	F_(MSIOF0_SS1,	IP1SR0_31_28)
  40#define GPSR0_14	F_(MSIOF0_SCK,	IP1SR0_27_24)
  41#define GPSR0_13	F_(MSIOF0_TXD,	IP1SR0_23_20)
  42#define GPSR0_12	F_(MSIOF0_RXD,	IP1SR0_19_16)
  43#define GPSR0_11	F_(MSIOF0_SYNC,	IP1SR0_15_12)
  44#define GPSR0_10	F_(CTS0_N,	IP1SR0_11_8)
  45#define GPSR0_9		F_(RTS0_N,	IP1SR0_7_4)
  46#define GPSR0_8		F_(SCK0,	IP1SR0_3_0)
  47#define GPSR0_7		F_(TX0,		IP0SR0_31_28)
  48#define GPSR0_6		F_(RX0,		IP0SR0_27_24)
  49#define GPSR0_5		F_(HRTS0_N,	IP0SR0_23_20)
  50#define GPSR0_4		F_(HCTS0_N,	IP0SR0_19_16)
  51#define GPSR0_3		F_(HTX0,	IP0SR0_15_12)
  52#define GPSR0_2		F_(HRX0,	IP0SR0_11_8)
  53#define GPSR0_1		F_(HSCK0,	IP0SR0_7_4)
  54#define GPSR0_0		F_(SCIF_CLK,	IP0SR0_3_0)
  55
  56/* GPSR1 */
  57#define GPSR1_24	FM(SD_WP)
  58#define GPSR1_23	FM(SD_CD)
  59#define GPSR1_22	FM(MMC_SD_CMD)
  60#define GPSR1_21	FM(MMC_D7)
  61#define GPSR1_20	FM(MMC_DS)
  62#define GPSR1_19	FM(MMC_D6)
  63#define GPSR1_18	FM(MMC_D4)
  64#define GPSR1_17	FM(MMC_D5)
  65#define GPSR1_16	FM(MMC_SD_D3)
  66#define GPSR1_15	FM(MMC_SD_D2)
  67#define GPSR1_14	FM(MMC_SD_D1)
  68#define GPSR1_13	FM(MMC_SD_D0)
  69#define GPSR1_12	FM(MMC_SD_CLK)
  70#define GPSR1_11	FM(GP1_11)
  71#define GPSR1_10	FM(GP1_10)
  72#define GPSR1_9		FM(GP1_09)
  73#define GPSR1_8		FM(GP1_08)
  74#define GPSR1_7		F_(GP1_07,	IP0SR1_31_28)
  75#define GPSR1_6		F_(GP1_06,	IP0SR1_27_24)
  76#define GPSR1_5		F_(GP1_05,	IP0SR1_23_20)
  77#define GPSR1_4		F_(GP1_04,	IP0SR1_19_16)
  78#define GPSR1_3		F_(GP1_03,	IP0SR1_15_12)
  79#define GPSR1_2		F_(GP1_02,	IP0SR1_11_8)
  80#define GPSR1_1		F_(GP1_01,	IP0SR1_7_4)
  81#define GPSR1_0		F_(GP1_00,	IP0SR1_3_0)
  82
  83/* GPSR2 */
  84#define GPSR2_16	FM(PCIE1_CLKREQ_N)
  85#define GPSR2_15	FM(PCIE0_CLKREQ_N)
  86#define GPSR2_14	FM(QSPI0_IO3)
  87#define GPSR2_13	FM(QSPI0_SSL)
  88#define GPSR2_12	FM(QSPI0_MISO_IO1)
  89#define GPSR2_11	FM(QSPI0_IO2)
  90#define GPSR2_10	FM(QSPI0_SPCLK)
  91#define GPSR2_9		FM(QSPI0_MOSI_IO0)
  92#define GPSR2_8		FM(QSPI1_SPCLK)
  93#define GPSR2_7		FM(QSPI1_MOSI_IO0)
  94#define GPSR2_6		FM(QSPI1_IO2)
  95#define GPSR2_5		FM(QSPI1_MISO_IO1)
  96#define GPSR2_4		FM(QSPI1_IO3)
  97#define GPSR2_3		FM(QSPI1_SSL)
  98#define GPSR2_2		FM(RPC_RESET_N)
  99#define GPSR2_1		FM(RPC_WP_N)
 100#define GPSR2_0		FM(RPC_INT_N)
 101
 102/* GPSR3 */
 103#define GPSR3_18	FM(TSN0_AVTP_CAPTURE_B)
 104#define GPSR3_17	FM(TSN0_AVTP_MATCH_B)
 105#define GPSR3_16	FM(TSN0_AVTP_PPS)
 106#define GPSR3_15	FM(TSN1_AVTP_CAPTURE_B)
 107#define GPSR3_14	FM(TSN1_AVTP_MATCH_B)
 108#define GPSR3_13	FM(TSN1_AVTP_PPS)
 109#define GPSR3_12	FM(TSN0_MAGIC_B)
 110#define GPSR3_11	FM(TSN1_PHY_INT_B)
 111#define GPSR3_10	FM(TSN0_PHY_INT_B)
 112#define GPSR3_9		FM(TSN2_PHY_INT_B)
 113#define GPSR3_8		FM(TSN0_LINK_B)
 114#define GPSR3_7		FM(TSN2_LINK_B)
 115#define GPSR3_6		FM(TSN1_LINK_B)
 116#define GPSR3_5		FM(TSN1_MDC_B)
 117#define GPSR3_4		FM(TSN0_MDC_B)
 118#define GPSR3_3		FM(TSN2_MDC_B)
 119#define GPSR3_2		FM(TSN0_MDIO_B)
 120#define GPSR3_1		FM(TSN2_MDIO_B)
 121#define GPSR3_0		FM(TSN1_MDIO_B)
 122
 123/* IP0SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */		/* 5 */			/* 6 */			/* 7 - F */
 124#define IP0SR0_3_0	FM(SCIF_CLK)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 125#define IP0SR0_7_4	FM(HSCK0)		FM(SCK3)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(TSN0_AVTP_CAPTURE_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 126#define IP0SR0_11_8	FM(HRX0)		FM(RX3)			FM(MSIOF3_RXD)		F_(0, 0)		F_(0, 0)	FM(TSN0_AVTP_MATCH_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 127#define IP0SR0_15_12	FM(HTX0)		FM(TX3)			FM(MSIOF3_TXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 128#define IP0SR0_19_16	FM(HCTS0_N)		FM(CTS3_N)		FM(MSIOF3_SS1)		F_(0, 0)		F_(0, 0)	FM(TSN0_MDC_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 129#define IP0SR0_23_20	FM(HRTS0_N)		FM(RTS3_N)		FM(MSIOF3_SS2)		F_(0, 0)		F_(0, 0)	FM(TSN0_MDIO_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 130#define IP0SR0_27_24	FM(RX0)			FM(HRX1)		F_(0, 0)		FM(MSIOF1_RXD)		F_(0, 0)	FM(TSN1_AVTP_MATCH_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 131#define IP0SR0_31_28	FM(TX0)			FM(HTX1)		F_(0, 0)		FM(MSIOF1_TXD)		F_(0, 0)	FM(TSN1_AVTP_CAPTURE_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 132/* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */		/* 5 */			/* 6 */			/* 7 - F */
 133#define IP1SR0_3_0	FM(SCK0)		FM(HSCK1)		F_(0, 0)		FM(MSIOF1_SCK)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 134#define IP1SR0_7_4	FM(RTS0_N)		FM(HRTS1_N)		FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	FM(TSN1_MDIO_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 135#define IP1SR0_11_8	FM(CTS0_N)		FM(HCTS1_N)		F_(0, 0)		FM(MSIOF1_SYNC)		F_(0, 0)	FM(TSN1_MDC_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 136#define IP1SR0_15_12	FM(MSIOF0_SYNC)		FM(HCTS3_N)		FM(CTS1_N)		FM(IRQ4)		F_(0, 0)	FM(TSN0_LINK_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 137#define IP1SR0_19_16	FM(MSIOF0_RXD)		FM(HRX3)		FM(RX1)			F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 138#define IP1SR0_23_20	FM(MSIOF0_TXD)		FM(HTX3)		FM(TX1)			F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 139#define IP1SR0_27_24	FM(MSIOF0_SCK)		FM(HSCK3)		FM(SCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 140#define IP1SR0_31_28	FM(MSIOF0_SS1)		FM(HRTS3_N)		FM(RTS1_N)		FM(IRQ5)		F_(0, 0)	FM(TSN1_LINK_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 141/* IP2SR0 */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */		/* 5 */			/* 6 */			/* 7 - F */
 142#define IP2SR0_3_0	FM(MSIOF0_SS2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(TSN2_LINK_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 143#define IP2SR0_7_4	FM(IRQ0)		F_(0, 0)		F_(0, 0)		FM(MSIOF1_SS1)		F_(0, 0)	FM(TSN0_MAGIC_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 144#define IP2SR0_11_8	FM(IRQ1)		F_(0, 0)		F_(0, 0)		FM(MSIOF1_SS2)		F_(0, 0)	FM(TSN0_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 145#define IP2SR0_15_12	FM(IRQ2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(TSN1_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 146#define IP2SR0_19_16	FM(IRQ3)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	FM(TSN2_PHY_INT_A)	F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 147
 148/* IP0SR1 */		/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */		/* 5 */			/* 6 */			/* 7 - F */
 149#define IP0SR1_3_0	FM(GP1_00)		FM(TCLK1)		FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 150#define IP0SR1_7_4	FM(GP1_01)		FM(TCLK4)		FM(HRX2)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 151#define IP0SR1_11_8	FM(GP1_02)		F_(0, 0)		FM(HTX2)		FM(MSIOF2_SS1)		F_(0, 0)	FM(TSN2_MDC_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 152#define IP0SR1_15_12	FM(GP1_03)		FM(TCLK2)		FM(HCTS2_N)		FM(MSIOF2_SS2)		FM(CTS4_N)	FM(TSN2_MDIO_A)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 153#define IP0SR1_19_16	FM(GP1_04)		FM(TCLK3)		FM(HRTS2_N)		FM(MSIOF2_SYNC)		FM(RTS4_N)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 154#define IP0SR1_23_20	FM(GP1_05)		FM(MSIOF2_SCK)		FM(SCK4)		F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 155#define IP0SR1_27_24	FM(GP1_06)		FM(MSIOF2_RXD)		FM(RX4)			F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 156#define IP0SR1_31_28	FM(GP1_07)		FM(MSIOF2_TXD)		FM(TX4)			F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 157
 158#define PINMUX_GPSR	\
 159		GPSR1_24					\
 160		GPSR1_23					\
 161		GPSR1_22					\
 162		GPSR1_21					\
 163GPSR0_20	GPSR1_20					\
 164GPSR0_19	GPSR1_19					\
 165GPSR0_18	GPSR1_18			GPSR3_18	\
 166GPSR0_17	GPSR1_17			GPSR3_17	\
 167GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	\
 168GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	\
 169GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	\
 170GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	\
 171GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	\
 172GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	\
 173GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	\
 174GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		\
 175GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		\
 176GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		\
 177GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		\
 178GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		\
 179GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		\
 180GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		\
 181GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		\
 182GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		\
 183GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0
 184
 185#define PINMUX_IPSR	\
 186\
 187FM(IP0SR0_3_0)		IP0SR0_3_0	FM(IP1SR0_3_0)		IP1SR0_3_0	FM(IP2SR0_3_0)		IP2SR0_3_0	\
 188FM(IP0SR0_7_4)		IP0SR0_7_4	FM(IP1SR0_7_4)		IP1SR0_7_4	FM(IP2SR0_7_4)		IP2SR0_7_4	\
 189FM(IP0SR0_11_8)		IP0SR0_11_8	FM(IP1SR0_11_8)		IP1SR0_11_8	FM(IP2SR0_11_8)		IP2SR0_11_8	\
 190FM(IP0SR0_15_12)	IP0SR0_15_12	FM(IP1SR0_15_12)	IP1SR0_15_12	FM(IP2SR0_15_12)	IP2SR0_15_12	\
 191FM(IP0SR0_19_16)	IP0SR0_19_16	FM(IP1SR0_19_16)	IP1SR0_19_16	FM(IP2SR0_19_16)	IP2SR0_19_16	\
 192FM(IP0SR0_23_20)	IP0SR0_23_20	FM(IP1SR0_23_20)	IP1SR0_23_20	\
 193FM(IP0SR0_27_24)	IP0SR0_27_24	FM(IP1SR0_27_24)	IP1SR0_27_24	\
 194FM(IP0SR0_31_28)	IP0SR0_31_28	FM(IP1SR0_31_28)	IP1SR0_31_28	\
 195\
 196FM(IP0SR1_3_0)		IP0SR1_3_0	\
 197FM(IP0SR1_7_4)		IP0SR1_7_4	\
 198FM(IP0SR1_11_8)		IP0SR1_11_8	\
 199FM(IP0SR1_15_12)	IP0SR1_15_12	\
 200FM(IP0SR1_19_16)	IP0SR1_19_16	\
 201FM(IP0SR1_23_20)	IP0SR1_23_20	\
 202FM(IP0SR1_27_24)	IP0SR1_27_24	\
 203FM(IP0SR1_31_28)	IP0SR1_31_28
 204
 205/* MOD_SEL1 */			/* 0 */		/* 1 */		/* 2 */		/* 3 */
 206#define MOD_SEL1_11_10		FM(SEL_I2C5_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C5_3)
 207#define MOD_SEL1_9_8		FM(SEL_I2C4_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C4_3)
 208#define MOD_SEL1_7_6		FM(SEL_I2C3_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C3_3)
 209#define MOD_SEL1_5_4		FM(SEL_I2C2_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C2_3)
 210#define MOD_SEL1_3_2		FM(SEL_I2C1_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C1_3)
 211#define MOD_SEL1_1_0		FM(SEL_I2C0_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C0_3)
 212
 213#define PINMUX_MOD_SELS \
 214\
 215MOD_SEL1_11_10 \
 216MOD_SEL1_9_8 \
 217MOD_SEL1_7_6 \
 218MOD_SEL1_5_4 \
 219MOD_SEL1_3_2 \
 220MOD_SEL1_1_0
 221
 222#define PINMUX_PHYS \
 223	FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
 224	FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5)
 225
 226enum {
 227	PINMUX_RESERVED = 0,
 228
 229	PINMUX_DATA_BEGIN,
 230	GP_ALL(DATA),
 231	PINMUX_DATA_END,
 232
 233#define F_(x, y)
 234#define FM(x)   FN_##x,
 235	PINMUX_FUNCTION_BEGIN,
 236	GP_ALL(FN),
 237	PINMUX_GPSR
 238	PINMUX_IPSR
 239	PINMUX_MOD_SELS
 240	PINMUX_FUNCTION_END,
 241#undef F_
 242#undef FM
 243
 244#define F_(x, y)
 245#define FM(x)	x##_MARK,
 246	PINMUX_MARK_BEGIN,
 247	PINMUX_GPSR
 248	PINMUX_IPSR
 249	PINMUX_MOD_SELS
 250	PINMUX_PHYS
 251	PINMUX_MARK_END,
 252#undef F_
 253#undef FM
 254};
 255
 256static const u16 pinmux_data[] = {
 257/* Using GP_1_[0-9] requires disabling I2C in MOD_SEL1 */
 258#define GP_1_0_FN	GP_1_0_FN,	FN_SEL_I2C0_0
 259#define GP_1_1_FN	GP_1_1_FN,	FN_SEL_I2C0_0
 260#define GP_1_2_FN	GP_1_2_FN,	FN_SEL_I2C1_0
 261#define GP_1_3_FN	GP_1_3_FN,	FN_SEL_I2C1_0
 262#define GP_1_4_FN	GP_1_4_FN,	FN_SEL_I2C2_0
 263#define GP_1_5_FN	GP_1_5_FN,	FN_SEL_I2C2_0
 264#define GP_1_6_FN	GP_1_6_FN,	FN_SEL_I2C3_0
 265#define GP_1_7_FN	GP_1_7_FN,	FN_SEL_I2C3_0
 266#define GP_1_8_FN	GP_1_8_FN,	FN_SEL_I2C4_0
 267#define GP_1_9_FN	GP_1_9_FN,	FN_SEL_I2C4_0
 268	PINMUX_DATA_GP_ALL(),
 269#undef GP_1_0_FN
 270#undef GP_1_1_FN
 271#undef GP_1_2_FN
 272#undef GP_1_3_FN
 273#undef GP_1_4_FN
 274#undef GP_1_5_FN
 275#undef GP_1_6_FN
 276#undef GP_1_7_FN
 277#undef GP_1_8_FN
 278#undef GP_1_9_FN
 279
 280	PINMUX_SINGLE(SD_WP),
 281	PINMUX_SINGLE(SD_CD),
 282	PINMUX_SINGLE(MMC_SD_CMD),
 283	PINMUX_SINGLE(MMC_D7),
 284	PINMUX_SINGLE(MMC_DS),
 285	PINMUX_SINGLE(MMC_D6),
 286	PINMUX_SINGLE(MMC_D4),
 287	PINMUX_SINGLE(MMC_D5),
 288	PINMUX_SINGLE(MMC_SD_D3),
 289	PINMUX_SINGLE(MMC_SD_D2),
 290	PINMUX_SINGLE(MMC_SD_D1),
 291	PINMUX_SINGLE(MMC_SD_D0),
 292	PINMUX_SINGLE(MMC_SD_CLK),
 293	PINMUX_SINGLE(PCIE1_CLKREQ_N),
 294	PINMUX_SINGLE(PCIE0_CLKREQ_N),
 295	PINMUX_SINGLE(QSPI0_IO3),
 296	PINMUX_SINGLE(QSPI0_SSL),
 297	PINMUX_SINGLE(QSPI0_MISO_IO1),
 298	PINMUX_SINGLE(QSPI0_IO2),
 299	PINMUX_SINGLE(QSPI0_SPCLK),
 300	PINMUX_SINGLE(QSPI0_MOSI_IO0),
 301	PINMUX_SINGLE(QSPI1_SPCLK),
 302	PINMUX_SINGLE(QSPI1_MOSI_IO0),
 303	PINMUX_SINGLE(QSPI1_IO2),
 304	PINMUX_SINGLE(QSPI1_MISO_IO1),
 305	PINMUX_SINGLE(QSPI1_IO3),
 306	PINMUX_SINGLE(QSPI1_SSL),
 307	PINMUX_SINGLE(RPC_RESET_N),
 308	PINMUX_SINGLE(RPC_WP_N),
 309	PINMUX_SINGLE(RPC_INT_N),
 310
 311	PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B),
 312	PINMUX_SINGLE(TSN0_AVTP_MATCH_B),
 313	PINMUX_SINGLE(TSN0_AVTP_PPS),
 314	PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B),
 315	PINMUX_SINGLE(TSN1_AVTP_MATCH_B),
 316	PINMUX_SINGLE(TSN1_AVTP_PPS),
 317	PINMUX_SINGLE(TSN0_MAGIC_B),
 318	PINMUX_SINGLE(TSN1_PHY_INT_B),
 319	PINMUX_SINGLE(TSN0_PHY_INT_B),
 320	PINMUX_SINGLE(TSN2_PHY_INT_B),
 321	PINMUX_SINGLE(TSN0_LINK_B),
 322	PINMUX_SINGLE(TSN2_LINK_B),
 323	PINMUX_SINGLE(TSN1_LINK_B),
 324	PINMUX_SINGLE(TSN1_MDC_B),
 325	PINMUX_SINGLE(TSN0_MDC_B),
 326	PINMUX_SINGLE(TSN2_MDC_B),
 327	PINMUX_SINGLE(TSN0_MDIO_B),
 328	PINMUX_SINGLE(TSN2_MDIO_B),
 329	PINMUX_SINGLE(TSN1_MDIO_B),
 330
 331	/* IP0SR0 */
 332	PINMUX_IPSR_GPSR(IP0SR0_3_0,	SCIF_CLK),
 333
 334	PINMUX_IPSR_GPSR(IP0SR0_7_4,	HSCK0),
 335	PINMUX_IPSR_GPSR(IP0SR0_7_4,	SCK3),
 336	PINMUX_IPSR_GPSR(IP0SR0_7_4,	MSIOF3_SCK),
 337	PINMUX_IPSR_GPSR(IP0SR0_7_4,	TSN0_AVTP_CAPTURE_A),
 338
 339	PINMUX_IPSR_GPSR(IP0SR0_11_8,	HRX0),
 340	PINMUX_IPSR_GPSR(IP0SR0_11_8,	RX3),
 341	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_RXD),
 342	PINMUX_IPSR_GPSR(IP0SR0_11_8,	TSN0_AVTP_MATCH_A),
 343
 344	PINMUX_IPSR_GPSR(IP0SR0_15_12,	HTX0),
 345	PINMUX_IPSR_GPSR(IP0SR0_15_12,	TX3),
 346	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_TXD),
 347
 348	PINMUX_IPSR_GPSR(IP0SR0_19_16,	HCTS0_N),
 349	PINMUX_IPSR_GPSR(IP0SR0_19_16,	CTS3_N),
 350	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_SS1),
 351	PINMUX_IPSR_GPSR(IP0SR0_19_16,	TSN0_MDC_A),
 352
 353	PINMUX_IPSR_GPSR(IP0SR0_23_20,	HRTS0_N),
 354	PINMUX_IPSR_GPSR(IP0SR0_23_20,	RTS3_N),
 355	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_SS2),
 356	PINMUX_IPSR_GPSR(IP0SR0_23_20,	TSN0_MDIO_A),
 357
 358	PINMUX_IPSR_GPSR(IP0SR0_27_24,	RX0),
 359	PINMUX_IPSR_GPSR(IP0SR0_27_24,	HRX1),
 360	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF1_RXD),
 361	PINMUX_IPSR_GPSR(IP0SR0_27_24,	TSN1_AVTP_MATCH_A),
 362
 363	PINMUX_IPSR_GPSR(IP0SR0_31_28,	TX0),
 364	PINMUX_IPSR_GPSR(IP0SR0_31_28,	HTX1),
 365	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF1_TXD),
 366	PINMUX_IPSR_GPSR(IP0SR0_31_28,	TSN1_AVTP_CAPTURE_A),
 367
 368	/* IP1SR0 */
 369	PINMUX_IPSR_GPSR(IP1SR0_3_0,	SCK0),
 370	PINMUX_IPSR_GPSR(IP1SR0_3_0,	HSCK1),
 371	PINMUX_IPSR_GPSR(IP1SR0_3_0,	MSIOF1_SCK),
 372
 373	PINMUX_IPSR_GPSR(IP1SR0_7_4,	RTS0_N),
 374	PINMUX_IPSR_GPSR(IP1SR0_7_4,	HRTS1_N),
 375	PINMUX_IPSR_GPSR(IP1SR0_7_4,	MSIOF3_SYNC),
 376	PINMUX_IPSR_GPSR(IP1SR0_7_4,	TSN1_MDIO_A),
 377
 378	PINMUX_IPSR_GPSR(IP1SR0_11_8,	CTS0_N),
 379	PINMUX_IPSR_GPSR(IP1SR0_11_8,	HCTS1_N),
 380	PINMUX_IPSR_GPSR(IP1SR0_11_8,	MSIOF1_SYNC),
 381	PINMUX_IPSR_GPSR(IP1SR0_11_8,	TSN1_MDC_A),
 382
 383	PINMUX_IPSR_GPSR(IP1SR0_15_12,	MSIOF0_SYNC),
 384	PINMUX_IPSR_GPSR(IP1SR0_15_12,	HCTS3_N),
 385	PINMUX_IPSR_GPSR(IP1SR0_15_12,	CTS1_N),
 386	PINMUX_IPSR_GPSR(IP1SR0_15_12,	IRQ4),
 387	PINMUX_IPSR_GPSR(IP1SR0_15_12,	TSN0_LINK_A),
 388
 389	PINMUX_IPSR_GPSR(IP1SR0_19_16,	MSIOF0_RXD),
 390	PINMUX_IPSR_GPSR(IP1SR0_19_16,	HRX3),
 391	PINMUX_IPSR_GPSR(IP1SR0_19_16,	RX1),
 392
 393	PINMUX_IPSR_GPSR(IP1SR0_23_20,	MSIOF0_TXD),
 394	PINMUX_IPSR_GPSR(IP1SR0_23_20,	HTX3),
 395	PINMUX_IPSR_GPSR(IP1SR0_23_20,	TX1),
 396
 397	PINMUX_IPSR_GPSR(IP1SR0_27_24,	MSIOF0_SCK),
 398	PINMUX_IPSR_GPSR(IP1SR0_27_24,	HSCK3),
 399	PINMUX_IPSR_GPSR(IP1SR0_27_24,	SCK1),
 400
 401	PINMUX_IPSR_GPSR(IP1SR0_31_28,	MSIOF0_SS1),
 402	PINMUX_IPSR_GPSR(IP1SR0_31_28,	HRTS3_N),
 403	PINMUX_IPSR_GPSR(IP1SR0_31_28,	RTS1_N),
 404	PINMUX_IPSR_GPSR(IP1SR0_31_28,	IRQ5),
 405	PINMUX_IPSR_GPSR(IP1SR0_31_28,	TSN1_LINK_A),
 406
 407	/* IP2SR0 */
 408	PINMUX_IPSR_GPSR(IP2SR0_3_0,	MSIOF0_SS2),
 409	PINMUX_IPSR_GPSR(IP2SR0_3_0,	TSN2_LINK_A),
 410
 411	PINMUX_IPSR_GPSR(IP2SR0_7_4,	IRQ0),
 412	PINMUX_IPSR_GPSR(IP2SR0_7_4,	MSIOF1_SS1),
 413	PINMUX_IPSR_GPSR(IP2SR0_7_4,	TSN0_MAGIC_A),
 414
 415	PINMUX_IPSR_GPSR(IP2SR0_11_8,	IRQ1),
 416	PINMUX_IPSR_GPSR(IP2SR0_11_8,	MSIOF1_SS2),
 417	PINMUX_IPSR_GPSR(IP2SR0_11_8,	TSN0_PHY_INT_A),
 418
 419	PINMUX_IPSR_GPSR(IP2SR0_15_12,	IRQ2),
 420	PINMUX_IPSR_GPSR(IP2SR0_15_12,	TSN1_PHY_INT_A),
 421
 422	PINMUX_IPSR_GPSR(IP2SR0_19_16,	IRQ3),
 423	PINMUX_IPSR_GPSR(IP2SR0_19_16,	TSN2_PHY_INT_A),
 424
 425	/* IP0SR1 */
 426	/* GP1_00 = SCL0 */
 427	PINMUX_IPSR_MSEL(IP0SR1_3_0,	GP1_00,		SEL_I2C0_0),
 428	PINMUX_IPSR_MSEL(IP0SR1_3_0,	TCLK1,		SEL_I2C0_0),
 429	PINMUX_IPSR_MSEL(IP0SR1_3_0,	HSCK2,		SEL_I2C0_0),
 430	PINMUX_IPSR_PHYS(IP0SR1_3_0,	SCL0,		SEL_I2C0_3),
 431
 432	/* GP1_01 = SDA0 */
 433	PINMUX_IPSR_MSEL(IP0SR1_7_4,	GP1_01,		SEL_I2C0_0),
 434	PINMUX_IPSR_MSEL(IP0SR1_7_4,	TCLK4,		SEL_I2C0_0),
 435	PINMUX_IPSR_MSEL(IP0SR1_7_4,	HRX2,		SEL_I2C0_0),
 436	PINMUX_IPSR_PHYS(IP0SR1_7_4,	SDA0,		SEL_I2C0_3),
 437
 438	/* GP1_02 = SCL1 */
 439	PINMUX_IPSR_MSEL(IP0SR1_11_8,	GP1_02,		SEL_I2C1_0),
 440	PINMUX_IPSR_MSEL(IP0SR1_11_8,	HTX2,		SEL_I2C1_0),
 441	PINMUX_IPSR_MSEL(IP0SR1_11_8,	MSIOF2_SS1,	SEL_I2C1_0),
 442	PINMUX_IPSR_MSEL(IP0SR1_11_8,	TSN2_MDC_A,	SEL_I2C1_0),
 443	PINMUX_IPSR_PHYS(IP0SR1_11_8,	SCL1,		SEL_I2C1_3),
 444
 445	/* GP1_03 = SDA1 */
 446	PINMUX_IPSR_MSEL(IP0SR1_15_12,	GP1_03,		SEL_I2C1_0),
 447	PINMUX_IPSR_MSEL(IP0SR1_15_12,	TCLK2,		SEL_I2C1_0),
 448	PINMUX_IPSR_MSEL(IP0SR1_15_12,	HCTS2_N,	SEL_I2C1_0),
 449	PINMUX_IPSR_MSEL(IP0SR1_15_12,	MSIOF2_SS2,	SEL_I2C1_0),
 450	PINMUX_IPSR_MSEL(IP0SR1_15_12,	CTS4_N,		SEL_I2C1_0),
 451	PINMUX_IPSR_MSEL(IP0SR1_15_12,	TSN2_MDIO_A,	SEL_I2C1_0),
 452	PINMUX_IPSR_PHYS(IP0SR1_15_12,	SDA1,		SEL_I2C1_3),
 453
 454	/* GP1_04 = SCL2 */
 455	PINMUX_IPSR_MSEL(IP0SR1_19_16,	GP1_04,		SEL_I2C2_0),
 456	PINMUX_IPSR_MSEL(IP0SR1_19_16,	TCLK3,		SEL_I2C2_0),
 457	PINMUX_IPSR_MSEL(IP0SR1_19_16,	HRTS2_N,	SEL_I2C2_0),
 458	PINMUX_IPSR_MSEL(IP0SR1_19_16,	MSIOF2_SYNC,	SEL_I2C2_0),
 459	PINMUX_IPSR_MSEL(IP0SR1_19_16,	RTS4_N,		SEL_I2C2_0),
 460	PINMUX_IPSR_PHYS(IP0SR1_19_16,	SCL2,		SEL_I2C2_3),
 461
 462	/* GP1_05 = SDA2 */
 463	PINMUX_IPSR_MSEL(IP0SR1_23_20,	GP1_05,		SEL_I2C2_0),
 464	PINMUX_IPSR_MSEL(IP0SR1_23_20,	MSIOF2_SCK,	SEL_I2C2_0),
 465	PINMUX_IPSR_MSEL(IP0SR1_23_20,	SCK4,		SEL_I2C2_0),
 466	PINMUX_IPSR_PHYS(IP0SR1_23_20,	SDA2,		SEL_I2C2_3),
 467
 468	/* GP1_06 = SCL3 */
 469	PINMUX_IPSR_MSEL(IP0SR1_27_24,	GP1_06,		SEL_I2C3_0),
 470	PINMUX_IPSR_MSEL(IP0SR1_27_24,	MSIOF2_RXD,	SEL_I2C3_0),
 471	PINMUX_IPSR_MSEL(IP0SR1_27_24,	RX4,		SEL_I2C3_0),
 472	PINMUX_IPSR_PHYS(IP0SR1_27_24,	SCL3,		SEL_I2C3_3),
 473
 474	/* GP1_07 = SDA3 */
 475	PINMUX_IPSR_MSEL(IP0SR1_31_28,	GP1_07,		SEL_I2C3_0),
 476	PINMUX_IPSR_MSEL(IP0SR1_31_28,	MSIOF2_TXD,	SEL_I2C3_0),
 477	PINMUX_IPSR_MSEL(IP0SR1_31_28,	TX4,		SEL_I2C3_0),
 478	PINMUX_IPSR_PHYS(IP0SR1_31_28,	SDA3,		SEL_I2C3_3),
 479
 480	/* GP1_08 = SCL4 */
 481	PINMUX_IPSR_NOGM(0,		GP1_08,		SEL_I2C4_0),
 482	PINMUX_IPSR_NOFN(GP1_08,	SCL4,		SEL_I2C4_3),
 483
 484	/* GP1_09 = SDA4 */
 485	PINMUX_IPSR_NOGM(0,		GP1_09,		SEL_I2C4_0),
 486	PINMUX_IPSR_NOFN(GP1_09,	SDA4,		SEL_I2C4_3),
 487
 488	/* GP1_10 = SCL5 */
 489	PINMUX_IPSR_NOGM(0,		GP1_10,		SEL_I2C5_0),
 490	PINMUX_IPSR_NOFN(GP1_10,	SCL5,		SEL_I2C5_3),
 491
 492	/* GP1_11 = SDA5 */
 493	PINMUX_IPSR_NOGM(0,		GP1_11,		SEL_I2C5_0),
 494	PINMUX_IPSR_NOFN(GP1_11,	SDA5,		SEL_I2C5_3),
 495};
 496
 497/*
 498 * Pins not associated with a GPIO port.
 499 */
 500enum {
 501	GP_ASSIGN_LAST(),
 502	NOGP_ALL(),
 503};
 504
 505static const struct sh_pfc_pin pinmux_pins[] = {
 506	PINMUX_GPIO_GP_ALL(),
 507};
 508
 509/* - HSCIF0 ----------------------------------------------------------------- */
 510static const unsigned int hscif0_data_pins[] = {
 511	/* HRX0, HTX0 */
 512	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
 513};
 514static const unsigned int hscif0_data_mux[] = {
 515	HRX0_MARK, HTX0_MARK,
 516};
 517static const unsigned int hscif0_clk_pins[] = {
 518	/* HSCK0 */
 519	RCAR_GP_PIN(0, 1),
 520};
 521static const unsigned int hscif0_clk_mux[] = {
 522	HSCK0_MARK,
 523};
 524static const unsigned int hscif0_ctrl_pins[] = {
 525	/* HRTS0#, HCTS0# */
 526	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
 527};
 528static const unsigned int hscif0_ctrl_mux[] = {
 529	HRTS0_N_MARK, HCTS0_N_MARK,
 530};
 531
 532/* - HSCIF1 ----------------------------------------------------------------- */
 533static const unsigned int hscif1_data_pins[] = {
 534	/* HRX1, HTX1 */
 535	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 536};
 537static const unsigned int hscif1_data_mux[] = {
 538	HRX1_MARK, HTX1_MARK,
 539};
 540static const unsigned int hscif1_clk_pins[] = {
 541	/* HSCK1 */
 542	RCAR_GP_PIN(0, 8),
 543};
 544static const unsigned int hscif1_clk_mux[] = {
 545	HSCK1_MARK,
 546};
 547static const unsigned int hscif1_ctrl_pins[] = {
 548	/* HRTS1#, HCTS1# */
 549	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
 550};
 551static const unsigned int hscif1_ctrl_mux[] = {
 552	HRTS1_N_MARK, HCTS1_N_MARK,
 553};
 554
 555/* - HSCIF2 ----------------------------------------------------------------- */
 556static const unsigned int hscif2_data_pins[] = {
 557	/* HRX2, HTX2 */
 558	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 559};
 560static const unsigned int hscif2_data_mux[] = {
 561	HRX2_MARK, HTX2_MARK,
 562};
 563static const unsigned int hscif2_clk_pins[] = {
 564	/* HSCK2 */
 565	RCAR_GP_PIN(1, 0),
 566};
 567static const unsigned int hscif2_clk_mux[] = {
 568	HSCK2_MARK,
 569};
 570static const unsigned int hscif2_ctrl_pins[] = {
 571	/* HRTS2#, HCTS2# */
 572	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 573};
 574static const unsigned int hscif2_ctrl_mux[] = {
 575	HRTS2_N_MARK, HCTS2_N_MARK,
 576};
 577
 578/* - HSCIF3 ----------------------------------------------------------------- */
 579static const unsigned int hscif3_data_pins[] = {
 580	/* HRX3, HTX3 */
 581	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
 582};
 583static const unsigned int hscif3_data_mux[] = {
 584	HRX3_MARK, HTX3_MARK,
 585};
 586static const unsigned int hscif3_clk_pins[] = {
 587	/* HSCK3 */
 588	RCAR_GP_PIN(0, 14),
 589};
 590static const unsigned int hscif3_clk_mux[] = {
 591	HSCK3_MARK,
 592};
 593static const unsigned int hscif3_ctrl_pins[] = {
 594	/* HRTS3#, HCTS3# */
 595	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
 596};
 597static const unsigned int hscif3_ctrl_mux[] = {
 598	HRTS3_N_MARK, HCTS3_N_MARK,
 599};
 600
 601/* - I2C0 ------------------------------------------------------------------- */
 602static const unsigned int i2c0_pins[] = {
 603	/* SDA0, SCL0 */
 604	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 605};
 606static const unsigned int i2c0_mux[] = {
 607	SDA0_MARK, SCL0_MARK,
 608};
 609
 610/* - I2C1 ------------------------------------------------------------------- */
 611static const unsigned int i2c1_pins[] = {
 612	/* SDA1, SCL1 */
 613	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 614};
 615static const unsigned int i2c1_mux[] = {
 616	SDA1_MARK, SCL1_MARK,
 617};
 618
 619/* - I2C2 ------------------------------------------------------------------- */
 620static const unsigned int i2c2_pins[] = {
 621	/* SDA2, SCL2 */
 622	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
 623};
 624static const unsigned int i2c2_mux[] = {
 625	SDA2_MARK, SCL2_MARK,
 626};
 627
 628/* - I2C3 ------------------------------------------------------------------- */
 629static const unsigned int i2c3_pins[] = {
 630	/* SDA3, SCL3 */
 631	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 632};
 633static const unsigned int i2c3_mux[] = {
 634	SDA3_MARK, SCL3_MARK,
 635};
 636
 637/* - I2C4 ------------------------------------------------------------------- */
 638static const unsigned int i2c4_pins[] = {
 639	/* SDA4, SCL4 */
 640	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
 641};
 642static const unsigned int i2c4_mux[] = {
 643	SDA4_MARK, SCL4_MARK,
 644};
 645
 646/* - I2C5 ------------------------------------------------------------------- */
 647static const unsigned int i2c5_pins[] = {
 648	/* SDA5, SCL5 */
 649	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 650};
 651static const unsigned int i2c5_mux[] = {
 652	SDA5_MARK, SCL5_MARK,
 653};
 654
 655/* - INTC-EX ---------------------------------------------------------------- */
 656static const unsigned int intc_ex_irq0_pins[] = {
 657	/* IRQ0 */
 658	RCAR_GP_PIN(0, 17),
 659};
 660static const unsigned int intc_ex_irq0_mux[] = {
 661	IRQ0_MARK,
 662};
 663static const unsigned int intc_ex_irq1_pins[] = {
 664	/* IRQ1 */
 665	RCAR_GP_PIN(0, 18),
 666};
 667static const unsigned int intc_ex_irq1_mux[] = {
 668	IRQ1_MARK,
 669};
 670static const unsigned int intc_ex_irq2_pins[] = {
 671	/* IRQ2 */
 672	RCAR_GP_PIN(0, 19),
 673};
 674static const unsigned int intc_ex_irq2_mux[] = {
 675	IRQ2_MARK,
 676};
 677static const unsigned int intc_ex_irq3_pins[] = {
 678	/* IRQ3 */
 679	RCAR_GP_PIN(0, 20),
 680};
 681static const unsigned int intc_ex_irq3_mux[] = {
 682	IRQ3_MARK,
 683};
 684static const unsigned int intc_ex_irq4_pins[] = {
 685	/* IRQ4 */
 686	RCAR_GP_PIN(0, 11),
 687};
 688static const unsigned int intc_ex_irq4_mux[] = {
 689	IRQ4_MARK,
 690};
 691static const unsigned int intc_ex_irq5_pins[] = {
 692	/* IRQ5 */
 693	RCAR_GP_PIN(0, 15),
 694};
 695static const unsigned int intc_ex_irq5_mux[] = {
 696	IRQ5_MARK,
 697};
 698
 699/* - MMC -------------------------------------------------------------------- */
 700static const unsigned int mmc_data_pins[] = {
 701	/* MMC_SD_D[0:3], MMC_D[4:7] */
 702	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
 703	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
 704	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
 705	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
 706};
 707static const unsigned int mmc_data_mux[] = {
 708	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
 709	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
 710	MMC_D4_MARK, MMC_D5_MARK,
 711	MMC_D6_MARK, MMC_D7_MARK,
 712};
 713static const unsigned int mmc_ctrl_pins[] = {
 714	/* MMC_SD_CLK, MMC_SD_CMD */
 715	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
 716};
 717static const unsigned int mmc_ctrl_mux[] = {
 718	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
 719};
 720static const unsigned int mmc_cd_pins[] = {
 721	/* SD_CD */
 722	RCAR_GP_PIN(1, 23),
 723};
 724static const unsigned int mmc_cd_mux[] = {
 725	SD_CD_MARK,
 726};
 727static const unsigned int mmc_wp_pins[] = {
 728	/* SD_WP */
 729	RCAR_GP_PIN(1, 24),
 730};
 731static const unsigned int mmc_wp_mux[] = {
 732	SD_WP_MARK,
 733};
 734static const unsigned int mmc_ds_pins[] = {
 735	/* MMC_DS */
 736	RCAR_GP_PIN(1, 20),
 737};
 738static const unsigned int mmc_ds_mux[] = {
 739	MMC_DS_MARK,
 740};
 741
 742/* - MSIOF0 ----------------------------------------------------------------- */
 743static const unsigned int msiof0_clk_pins[] = {
 744	/* MSIOF0_SCK */
 745	RCAR_GP_PIN(0, 14),
 746};
 747static const unsigned int msiof0_clk_mux[] = {
 748	MSIOF0_SCK_MARK,
 749};
 750static const unsigned int msiof0_sync_pins[] = {
 751	/* MSIOF0_SYNC */
 752	RCAR_GP_PIN(0, 11),
 753};
 754static const unsigned int msiof0_sync_mux[] = {
 755	MSIOF0_SYNC_MARK,
 756};
 757static const unsigned int msiof0_ss1_pins[] = {
 758	/* MSIOF0_SS1 */
 759	RCAR_GP_PIN(0, 15),
 760};
 761static const unsigned int msiof0_ss1_mux[] = {
 762	MSIOF0_SS1_MARK,
 763};
 764static const unsigned int msiof0_ss2_pins[] = {
 765	/* MSIOF0_SS2 */
 766	RCAR_GP_PIN(0, 16),
 767};
 768static const unsigned int msiof0_ss2_mux[] = {
 769	MSIOF0_SS2_MARK,
 770};
 771static const unsigned int msiof0_txd_pins[] = {
 772	/* MSIOF0_TXD */
 773	RCAR_GP_PIN(0, 13),
 774};
 775static const unsigned int msiof0_txd_mux[] = {
 776	MSIOF0_TXD_MARK,
 777};
 778static const unsigned int msiof0_rxd_pins[] = {
 779	/* MSIOF0_RXD */
 780	RCAR_GP_PIN(0, 12),
 781};
 782static const unsigned int msiof0_rxd_mux[] = {
 783	MSIOF0_RXD_MARK,
 784};
 785
 786/* - MSIOF1 ----------------------------------------------------------------- */
 787static const unsigned int msiof1_clk_pins[] = {
 788	/* MSIOF1_SCK */
 789	RCAR_GP_PIN(0, 8),
 790};
 791static const unsigned int msiof1_clk_mux[] = {
 792	MSIOF1_SCK_MARK,
 793};
 794static const unsigned int msiof1_sync_pins[] = {
 795	/* MSIOF1_SYNC */
 796	RCAR_GP_PIN(0, 10),
 797};
 798static const unsigned int msiof1_sync_mux[] = {
 799	MSIOF1_SYNC_MARK,
 800};
 801static const unsigned int msiof1_ss1_pins[] = {
 802	/* MSIOF1_SS1 */
 803	RCAR_GP_PIN(0, 17),
 804};
 805static const unsigned int msiof1_ss1_mux[] = {
 806	MSIOF1_SS1_MARK,
 807};
 808static const unsigned int msiof1_ss2_pins[] = {
 809	/* MSIOF1_SS2 */
 810	RCAR_GP_PIN(0, 18),
 811};
 812static const unsigned int msiof1_ss2_mux[] = {
 813	MSIOF1_SS2_MARK,
 814};
 815static const unsigned int msiof1_txd_pins[] = {
 816	/* MSIOF1_TXD */
 817	RCAR_GP_PIN(0, 7),
 818};
 819static const unsigned int msiof1_txd_mux[] = {
 820	MSIOF1_TXD_MARK,
 821};
 822static const unsigned int msiof1_rxd_pins[] = {
 823	/* MSIOF1_RXD */
 824	RCAR_GP_PIN(0, 6),
 825};
 826static const unsigned int msiof1_rxd_mux[] = {
 827	MSIOF1_RXD_MARK,
 828};
 829
 830/* - MSIOF2 ----------------------------------------------------------------- */
 831static const unsigned int msiof2_clk_pins[] = {
 832	/* MSIOF2_SCK */
 833	RCAR_GP_PIN(1, 5),
 834};
 835static const unsigned int msiof2_clk_mux[] = {
 836	MSIOF2_SCK_MARK,
 837};
 838static const unsigned int msiof2_sync_pins[] = {
 839	/* MSIOF2_SYNC */
 840	RCAR_GP_PIN(1, 4),
 841};
 842static const unsigned int msiof2_sync_mux[] = {
 843	MSIOF2_SYNC_MARK,
 844};
 845static const unsigned int msiof2_ss1_pins[] = {
 846	/* MSIOF2_SS1 */
 847	RCAR_GP_PIN(1, 2),
 848};
 849static const unsigned int msiof2_ss1_mux[] = {
 850	MSIOF2_SS1_MARK,
 851};
 852static const unsigned int msiof2_ss2_pins[] = {
 853	/* MSIOF2_SS2 */
 854	RCAR_GP_PIN(1, 3),
 855};
 856static const unsigned int msiof2_ss2_mux[] = {
 857	MSIOF2_SS2_MARK,
 858};
 859static const unsigned int msiof2_txd_pins[] = {
 860	/* MSIOF2_TXD */
 861	RCAR_GP_PIN(1, 7),
 862};
 863static const unsigned int msiof2_txd_mux[] = {
 864	MSIOF2_TXD_MARK,
 865};
 866static const unsigned int msiof2_rxd_pins[] = {
 867	/* MSIOF2_RXD */
 868	RCAR_GP_PIN(1, 6),
 869};
 870static const unsigned int msiof2_rxd_mux[] = {
 871	MSIOF2_RXD_MARK,
 872};
 873
 874/* - MSIOF3 ----------------------------------------------------------------- */
 875static const unsigned int msiof3_clk_pins[] = {
 876	/* MSIOF3_SCK */
 877	RCAR_GP_PIN(0, 1),
 878};
 879static const unsigned int msiof3_clk_mux[] = {
 880	MSIOF3_SCK_MARK,
 881};
 882static const unsigned int msiof3_sync_pins[] = {
 883	/* MSIOF3_SYNC */
 884	RCAR_GP_PIN(0, 9),
 885};
 886static const unsigned int msiof3_sync_mux[] = {
 887	MSIOF3_SYNC_MARK,
 888};
 889static const unsigned int msiof3_ss1_pins[] = {
 890	/* MSIOF3_SS1 */
 891	RCAR_GP_PIN(0, 4),
 892};
 893static const unsigned int msiof3_ss1_mux[] = {
 894	MSIOF3_SS1_MARK,
 895};
 896static const unsigned int msiof3_ss2_pins[] = {
 897	/* MSIOF3_SS2 */
 898	RCAR_GP_PIN(0, 5),
 899};
 900static const unsigned int msiof3_ss2_mux[] = {
 901	MSIOF3_SS2_MARK,
 902};
 903static const unsigned int msiof3_txd_pins[] = {
 904	/* MSIOF3_TXD */
 905	RCAR_GP_PIN(0, 3),
 906};
 907static const unsigned int msiof3_txd_mux[] = {
 908	MSIOF3_TXD_MARK,
 909};
 910static const unsigned int msiof3_rxd_pins[] = {
 911	/* MSIOF3_RXD */
 912	RCAR_GP_PIN(0, 2),
 913};
 914static const unsigned int msiof3_rxd_mux[] = {
 915	MSIOF3_RXD_MARK,
 916};
 917
 918/* - PCIE ------------------------------------------------------------------- */
 919static const unsigned int pcie0_clkreq_n_pins[] = {
 920	/* PCIE0_CLKREQ# */
 921	RCAR_GP_PIN(2, 15),
 922};
 923
 924static const unsigned int pcie0_clkreq_n_mux[] = {
 925	PCIE0_CLKREQ_N_MARK,
 926};
 927
 928static const unsigned int pcie1_clkreq_n_pins[] = {
 929	/* PCIE1_CLKREQ# */
 930	RCAR_GP_PIN(2, 16),
 931};
 932
 933static const unsigned int pcie1_clkreq_n_mux[] = {
 934	PCIE1_CLKREQ_N_MARK,
 935};
 936
 937/* - QSPI0 ------------------------------------------------------------------ */
 938static const unsigned int qspi0_ctrl_pins[] = {
 939	/* SPCLK, SSL */
 940	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
 941};
 942static const unsigned int qspi0_ctrl_mux[] = {
 943	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
 944};
 945static const unsigned int qspi0_data_pins[] = {
 946	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 947	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
 948	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
 949};
 950static const unsigned int qspi0_data_mux[] = {
 951	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
 952	QSPI0_IO2_MARK, QSPI0_IO3_MARK
 953};
 954
 955/* - QSPI1 ------------------------------------------------------------------ */
 956static const unsigned int qspi1_ctrl_pins[] = {
 957	/* SPCLK, SSL */
 958	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
 959};
 960static const unsigned int qspi1_ctrl_mux[] = {
 961	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
 962};
 963static const unsigned int qspi1_data_pins[] = {
 964	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
 965	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
 966	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
 967};
 968static const unsigned int qspi1_data_mux[] = {
 969	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
 970	QSPI1_IO2_MARK, QSPI1_IO3_MARK
 971};
 972
 973/* - SCIF0 ------------------------------------------------------------------ */
 974static const unsigned int scif0_data_pins[] = {
 975	/* RX0, TX0 */
 976	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
 977};
 978static const unsigned int scif0_data_mux[] = {
 979	RX0_MARK, TX0_MARK,
 980};
 981static const unsigned int scif0_clk_pins[] = {
 982	/* SCK0 */
 983	RCAR_GP_PIN(0, 8),
 984};
 985static const unsigned int scif0_clk_mux[] = {
 986	SCK0_MARK,
 987};
 988static const unsigned int scif0_ctrl_pins[] = {
 989	/* RTS0#, CTS0# */
 990	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
 991};
 992static const unsigned int scif0_ctrl_mux[] = {
 993	RTS0_N_MARK, CTS0_N_MARK,
 994};
 995
 996/* - SCIF1 ------------------------------------------------------------------ */
 997static const unsigned int scif1_data_pins[] = {
 998	/* RX1, TX1 */
 999	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1000};
1001static const unsigned int scif1_data_mux[] = {
1002	RX1_MARK, TX1_MARK,
1003};
1004static const unsigned int scif1_clk_pins[] = {
1005	/* SCK1 */
1006	RCAR_GP_PIN(0, 14),
1007};
1008static const unsigned int scif1_clk_mux[] = {
1009	SCK1_MARK,
1010};
1011static const unsigned int scif1_ctrl_pins[] = {
1012	/* RTS1#, CTS1# */
1013	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1014};
1015static const unsigned int scif1_ctrl_mux[] = {
1016	RTS1_N_MARK, CTS1_N_MARK,
1017};
1018
1019/* - SCIF3 ------------------------------------------------------------------ */
1020static const unsigned int scif3_data_pins[] = {
1021	/* RX3, TX3 */
1022	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1023};
1024static const unsigned int scif3_data_mux[] = {
1025	RX3_MARK, TX3_MARK,
1026};
1027static const unsigned int scif3_clk_pins[] = {
1028	/* SCK3 */
1029	RCAR_GP_PIN(0, 1),
1030};
1031static const unsigned int scif3_clk_mux[] = {
1032	SCK3_MARK,
1033};
1034static const unsigned int scif3_ctrl_pins[] = {
1035	/* RTS3#, CTS3# */
1036	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
1037};
1038static const unsigned int scif3_ctrl_mux[] = {
1039	RTS3_N_MARK, CTS3_N_MARK,
1040};
1041
1042/* - SCIF4 ------------------------------------------------------------------ */
1043static const unsigned int scif4_data_pins[] = {
1044	/* RX4, TX4 */
1045	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1046};
1047static const unsigned int scif4_data_mux[] = {
1048	RX4_MARK, TX4_MARK,
1049};
1050static const unsigned int scif4_clk_pins[] = {
1051	/* SCK4 */
1052	RCAR_GP_PIN(1, 5),
1053};
1054static const unsigned int scif4_clk_mux[] = {
1055	SCK4_MARK,
1056};
1057static const unsigned int scif4_ctrl_pins[] = {
1058	/* RTS4#, CTS4# */
1059	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
1060};
1061static const unsigned int scif4_ctrl_mux[] = {
1062	RTS4_N_MARK, CTS4_N_MARK,
1063};
1064
1065/* - SCIF Clock ------------------------------------------------------------- */
1066static const unsigned int scif_clk_pins[] = {
1067	/* SCIF_CLK */
1068	RCAR_GP_PIN(0, 0),
1069};
1070static const unsigned int scif_clk_mux[] = {
1071	SCIF_CLK_MARK,
1072};
1073
1074/* - TSN0 ------------------------------------------------ */
1075static const unsigned int tsn0_link_a_pins[] = {
1076	/* TSN0_LINK_A */
1077	RCAR_GP_PIN(0, 11),
1078};
1079static const unsigned int tsn0_link_a_mux[] = {
1080	TSN0_LINK_A_MARK,
1081};
1082static const unsigned int tsn0_magic_a_pins[] = {
1083	/* TSN0_MAGIC_A */
1084	RCAR_GP_PIN(0, 17),
1085};
1086static const unsigned int tsn0_magic_a_mux[] = {
1087	TSN0_MAGIC_A_MARK,
1088};
1089static const unsigned int tsn0_phy_int_a_pins[] = {
1090	/* TSN0_PHY_INT_A */
1091	RCAR_GP_PIN(0, 18),
1092};
1093static const unsigned int tsn0_phy_int_a_mux[] = {
1094	TSN0_PHY_INT_A_MARK,
1095};
1096static const unsigned int tsn0_mdio_a_pins[] = {
1097	/* TSN0_MDC_A, TSN0_MDIO_A */
1098	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1099};
1100static const unsigned int tsn0_mdio_a_mux[] = {
1101	TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
1102};
1103static const unsigned int tsn0_link_b_pins[] = {
1104	/* TSN0_LINK_B */
1105	RCAR_GP_PIN(3, 8),
1106};
1107static const unsigned int tsn0_link_b_mux[] = {
1108	TSN0_LINK_B_MARK,
1109};
1110static const unsigned int tsn0_magic_b_pins[] = {
1111	/* TSN0_MAGIC_B */
1112	RCAR_GP_PIN(3, 12),
1113};
1114static const unsigned int tsn0_magic_b_mux[] = {
1115	TSN0_MAGIC_B_MARK,
1116};
1117static const unsigned int tsn0_phy_int_b_pins[] = {
1118	/* TSN0_PHY_INT_B */
1119	RCAR_GP_PIN(3, 10),
1120};
1121static const unsigned int tsn0_phy_int_b_mux[] = {
1122	TSN0_PHY_INT_B_MARK,
1123};
1124static const unsigned int tsn0_mdio_b_pins[] = {
1125	/* TSN0_MDC_B, TSN0_MDIO_B */
1126	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
1127};
1128static const unsigned int tsn0_mdio_b_mux[] = {
1129	TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
1130};
1131static const unsigned int tsn0_avtp_pps_pins[] = {
1132	/* TSN0_AVTP_PPS */
1133	RCAR_GP_PIN(3, 16),
1134};
1135static const unsigned int tsn0_avtp_pps_mux[] = {
1136	TSN0_AVTP_PPS_MARK,
1137};
1138static const unsigned int tsn0_avtp_capture_a_pins[] = {
1139	/* TSN0_AVTP_CAPTURE_A */
1140	RCAR_GP_PIN(0, 1),
1141};
1142static const unsigned int tsn0_avtp_capture_a_mux[] = {
1143	TSN0_AVTP_CAPTURE_A_MARK,
1144};
1145static const unsigned int tsn0_avtp_match_a_pins[] = {
1146	/* TSN0_AVTP_MATCH_A */
1147	RCAR_GP_PIN(0, 2),
1148};
1149static const unsigned int tsn0_avtp_match_a_mux[] = {
1150	TSN0_AVTP_MATCH_A_MARK,
1151};
1152static const unsigned int tsn0_avtp_capture_b_pins[] = {
1153	/* TSN0_AVTP_CAPTURE_B */
1154	RCAR_GP_PIN(3, 18),
1155};
1156static const unsigned int tsn0_avtp_capture_b_mux[] = {
1157	TSN0_AVTP_CAPTURE_B_MARK,
1158};
1159static const unsigned int tsn0_avtp_match_b_pins[] = {
1160	/* TSN0_AVTP_MATCH_B */
1161	RCAR_GP_PIN(3, 17),
1162};
1163static const unsigned int tsn0_avtp_match_b_mux[] = {
1164	TSN0_AVTP_MATCH_B_MARK,
1165};
1166
1167/* - TSN1 ------------------------------------------------ */
1168static const unsigned int tsn1_link_a_pins[] = {
1169	/* TSN1_LINK_A */
1170	RCAR_GP_PIN(0, 15),
1171};
1172static const unsigned int tsn1_link_a_mux[] = {
1173	TSN1_LINK_A_MARK,
1174};
1175static const unsigned int tsn1_phy_int_a_pins[] = {
1176	/* TSN1_PHY_INT_A */
1177	RCAR_GP_PIN(0, 19),
1178};
1179static const unsigned int tsn1_phy_int_a_mux[] = {
1180	TSN1_PHY_INT_A_MARK,
1181};
1182static const unsigned int tsn1_mdio_a_pins[] = {
1183	/* TSN1_MDC_A, TSN1_MDIO_A */
1184	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1185};
1186static const unsigned int tsn1_mdio_a_mux[] = {
1187	TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
1188};
1189static const unsigned int tsn1_link_b_pins[] = {
1190	/* TSN1_LINK_B */
1191	RCAR_GP_PIN(3, 6),
1192};
1193static const unsigned int tsn1_link_b_mux[] = {
1194	TSN1_LINK_B_MARK,
1195};
1196static const unsigned int tsn1_phy_int_b_pins[] = {
1197	/* TSN1_PHY_INT_B */
1198	RCAR_GP_PIN(3, 11),
1199};
1200static const unsigned int tsn1_phy_int_b_mux[] = {
1201	TSN1_PHY_INT_B_MARK,
1202};
1203static const unsigned int tsn1_mdio_b_pins[] = {
1204	/* TSN1_MDC_B, TSN1_MDIO_B */
1205	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
1206};
1207static const unsigned int tsn1_mdio_b_mux[] = {
1208	TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
1209};
1210static const unsigned int tsn1_avtp_pps_pins[] = {
1211	/* TSN1_AVTP_PPS */
1212	RCAR_GP_PIN(3, 13),
1213};
1214static const unsigned int tsn1_avtp_pps_mux[] = {
1215	TSN1_AVTP_PPS_MARK,
1216};
1217static const unsigned int tsn1_avtp_capture_a_pins[] = {
1218	/* TSN1_AVTP_CAPTURE_A */
1219	RCAR_GP_PIN(0, 7),
1220};
1221static const unsigned int tsn1_avtp_capture_a_mux[] = {
1222	TSN1_AVTP_CAPTURE_A_MARK,
1223};
1224static const unsigned int tsn1_avtp_match_a_pins[] = {
1225	/* TSN1_AVTP_MATCH_A */
1226	RCAR_GP_PIN(0, 6),
1227};
1228static const unsigned int tsn1_avtp_match_a_mux[] = {
1229	TSN1_AVTP_MATCH_A_MARK,
1230};
1231static const unsigned int tsn1_avtp_capture_b_pins[] = {
1232	/* TSN1_AVTP_CAPTURE_B */
1233	RCAR_GP_PIN(3, 15),
1234};
1235static const unsigned int tsn1_avtp_capture_b_mux[] = {
1236	TSN1_AVTP_CAPTURE_B_MARK,
1237};
1238static const unsigned int tsn1_avtp_match_b_pins[] = {
1239	/* TSN1_AVTP_MATCH_B */
1240	RCAR_GP_PIN(3, 14),
1241};
1242static const unsigned int tsn1_avtp_match_b_mux[] = {
1243	TSN1_AVTP_MATCH_B_MARK,
1244};
1245
1246/* - TSN2 ------------------------------------------------ */
1247static const unsigned int tsn2_link_a_pins[] = {
1248	/* TSN2_LINK_A */
1249	RCAR_GP_PIN(0, 16),
1250};
1251static const unsigned int tsn2_link_a_mux[] = {
1252	TSN2_LINK_A_MARK,
1253};
1254static const unsigned int tsn2_phy_int_a_pins[] = {
1255	/* TSN2_PHY_INT_A */
1256	RCAR_GP_PIN(0, 20),
1257};
1258static const unsigned int tsn2_phy_int_a_mux[] = {
1259	TSN2_PHY_INT_A_MARK,
1260};
1261static const unsigned int tsn2_mdio_a_pins[] = {
1262	/* TSN2_MDC_A, TSN2_MDIO_A */
1263	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1264};
1265static const unsigned int tsn2_mdio_a_mux[] = {
1266	TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
1267};
1268static const unsigned int tsn2_link_b_pins[] = {
1269	/* TSN2_LINK_B */
1270	RCAR_GP_PIN(3, 7),
1271};
1272static const unsigned int tsn2_link_b_mux[] = {
1273	TSN2_LINK_B_MARK,
1274};
1275static const unsigned int tsn2_phy_int_b_pins[] = {
1276	/* TSN2_PHY_INT_B */
1277	RCAR_GP_PIN(3, 9),
1278};
1279static const unsigned int tsn2_phy_int_b_mux[] = {
1280	TSN2_PHY_INT_B_MARK,
1281};
1282static const unsigned int tsn2_mdio_b_pins[] = {
1283	/* TSN2_MDC_B, TSN2_MDIO_B */
1284	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
1285};
1286static const unsigned int tsn2_mdio_b_mux[] = {
1287	TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
1288};
1289
1290static const struct sh_pfc_pin_group pinmux_groups[] = {
1291	SH_PFC_PIN_GROUP(hscif0_data),
1292	SH_PFC_PIN_GROUP(hscif0_clk),
1293	SH_PFC_PIN_GROUP(hscif0_ctrl),
1294	SH_PFC_PIN_GROUP(hscif1_data),
1295	SH_PFC_PIN_GROUP(hscif1_clk),
1296	SH_PFC_PIN_GROUP(hscif1_ctrl),
1297	SH_PFC_PIN_GROUP(hscif2_data),
1298	SH_PFC_PIN_GROUP(hscif2_clk),
1299	SH_PFC_PIN_GROUP(hscif2_ctrl),
1300	SH_PFC_PIN_GROUP(hscif3_data),
1301	SH_PFC_PIN_GROUP(hscif3_clk),
1302	SH_PFC_PIN_GROUP(hscif3_ctrl),
1303	SH_PFC_PIN_GROUP(i2c0),
1304	SH_PFC_PIN_GROUP(i2c1),
1305	SH_PFC_PIN_GROUP(i2c2),
1306	SH_PFC_PIN_GROUP(i2c3),
1307	SH_PFC_PIN_GROUP(i2c4),
1308	SH_PFC_PIN_GROUP(i2c5),
1309	SH_PFC_PIN_GROUP(intc_ex_irq0),
1310	SH_PFC_PIN_GROUP(intc_ex_irq1),
1311	SH_PFC_PIN_GROUP(intc_ex_irq2),
1312	SH_PFC_PIN_GROUP(intc_ex_irq3),
1313	SH_PFC_PIN_GROUP(intc_ex_irq4),
1314	SH_PFC_PIN_GROUP(intc_ex_irq5),
1315	BUS_DATA_PIN_GROUP(mmc_data, 1),
1316	BUS_DATA_PIN_GROUP(mmc_data, 4),
1317	BUS_DATA_PIN_GROUP(mmc_data, 8),
1318	SH_PFC_PIN_GROUP(mmc_ctrl),
1319	SH_PFC_PIN_GROUP(mmc_cd),
1320	SH_PFC_PIN_GROUP(mmc_wp),
1321	SH_PFC_PIN_GROUP(mmc_ds),
1322	SH_PFC_PIN_GROUP(msiof0_clk),
1323	SH_PFC_PIN_GROUP(msiof0_sync),
1324	SH_PFC_PIN_GROUP(msiof0_ss1),
1325	SH_PFC_PIN_GROUP(msiof0_ss2),
1326	SH_PFC_PIN_GROUP(msiof0_txd),
1327	SH_PFC_PIN_GROUP(msiof0_rxd),
1328	SH_PFC_PIN_GROUP(msiof1_clk),
1329	SH_PFC_PIN_GROUP(msiof1_sync),
1330	SH_PFC_PIN_GROUP(msiof1_ss1),
1331	SH_PFC_PIN_GROUP(msiof1_ss2),
1332	SH_PFC_PIN_GROUP(msiof1_txd),
1333	SH_PFC_PIN_GROUP(msiof1_rxd),
1334	SH_PFC_PIN_GROUP(msiof2_clk),
1335	SH_PFC_PIN_GROUP(msiof2_sync),
1336	SH_PFC_PIN_GROUP(msiof2_ss1),
1337	SH_PFC_PIN_GROUP(msiof2_ss2),
1338	SH_PFC_PIN_GROUP(msiof2_txd),
1339	SH_PFC_PIN_GROUP(msiof2_rxd),
1340	SH_PFC_PIN_GROUP(msiof3_clk),
1341	SH_PFC_PIN_GROUP(msiof3_sync),
1342	SH_PFC_PIN_GROUP(msiof3_ss1),
1343	SH_PFC_PIN_GROUP(msiof3_ss2),
1344	SH_PFC_PIN_GROUP(msiof3_txd),
1345	SH_PFC_PIN_GROUP(msiof3_rxd),
1346	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
1347	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
1348	SH_PFC_PIN_GROUP(qspi0_ctrl),
1349	BUS_DATA_PIN_GROUP(qspi0_data, 2),
1350	BUS_DATA_PIN_GROUP(qspi0_data, 4),
1351	SH_PFC_PIN_GROUP(qspi1_ctrl),
1352	BUS_DATA_PIN_GROUP(qspi1_data, 2),
1353	BUS_DATA_PIN_GROUP(qspi1_data, 4),
1354	SH_PFC_PIN_GROUP(scif0_data),
1355	SH_PFC_PIN_GROUP(scif0_clk),
1356	SH_PFC_PIN_GROUP(scif0_ctrl),
1357	SH_PFC_PIN_GROUP(scif1_data),
1358	SH_PFC_PIN_GROUP(scif1_clk),
1359	SH_PFC_PIN_GROUP(scif1_ctrl),
1360	SH_PFC_PIN_GROUP(scif3_data),
1361	SH_PFC_PIN_GROUP(scif3_clk),
1362	SH_PFC_PIN_GROUP(scif3_ctrl),
1363	SH_PFC_PIN_GROUP(scif4_data),
1364	SH_PFC_PIN_GROUP(scif4_clk),
1365	SH_PFC_PIN_GROUP(scif4_ctrl),
1366	SH_PFC_PIN_GROUP(scif_clk),
1367	SH_PFC_PIN_GROUP(tsn0_link_a),
1368	SH_PFC_PIN_GROUP(tsn0_magic_a),
1369	SH_PFC_PIN_GROUP(tsn0_phy_int_a),
1370	SH_PFC_PIN_GROUP(tsn0_mdio_a),
1371	SH_PFC_PIN_GROUP(tsn0_link_b),
1372	SH_PFC_PIN_GROUP(tsn0_magic_b),
1373	SH_PFC_PIN_GROUP(tsn0_phy_int_b),
1374	SH_PFC_PIN_GROUP(tsn0_mdio_b),
1375	SH_PFC_PIN_GROUP(tsn0_avtp_pps),
1376	SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
1377	SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
1378	SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
1379	SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
1380	SH_PFC_PIN_GROUP(tsn1_link_a),
1381	SH_PFC_PIN_GROUP(tsn1_phy_int_a),
1382	SH_PFC_PIN_GROUP(tsn1_mdio_a),
1383	SH_PFC_PIN_GROUP(tsn1_link_b),
1384	SH_PFC_PIN_GROUP(tsn1_phy_int_b),
1385	SH_PFC_PIN_GROUP(tsn1_mdio_b),
1386	SH_PFC_PIN_GROUP(tsn1_avtp_pps),
1387	SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
1388	SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
1389	SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
1390	SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
1391	SH_PFC_PIN_GROUP(tsn2_link_a),
1392	SH_PFC_PIN_GROUP(tsn2_phy_int_a),
1393	SH_PFC_PIN_GROUP(tsn2_mdio_a),
1394	SH_PFC_PIN_GROUP(tsn2_link_b),
1395	SH_PFC_PIN_GROUP(tsn2_phy_int_b),
1396	SH_PFC_PIN_GROUP(tsn2_mdio_b),
1397};
1398
1399static const char * const hscif0_groups[] = {
1400	"hscif0_data",
1401	"hscif0_clk",
1402	"hscif0_ctrl",
1403};
1404
1405static const char * const hscif1_groups[] = {
1406	"hscif1_data",
1407	"hscif1_clk",
1408	"hscif1_ctrl",
1409};
1410
1411static const char * const hscif2_groups[] = {
1412	"hscif2_data",
1413	"hscif2_clk",
1414	"hscif2_ctrl",
1415};
1416
1417static const char * const hscif3_groups[] = {
1418	"hscif3_data",
1419	"hscif3_clk",
1420	"hscif3_ctrl",
1421};
1422
1423static const char * const i2c0_groups[] = {
1424	"i2c0",
1425};
1426
1427static const char * const i2c1_groups[] = {
1428	"i2c1",
1429};
1430
1431static const char * const i2c2_groups[] = {
1432	"i2c2",
1433};
1434
1435static const char * const i2c3_groups[] = {
1436	"i2c3",
1437};
1438
1439static const char * const i2c4_groups[] = {
1440	"i2c4",
1441};
1442
1443static const char * const i2c5_groups[] = {
1444	"i2c5",
1445};
1446
1447static const char * const intc_ex_groups[] = {
1448	"intc_ex_irq0",
1449	"intc_ex_irq1",
1450	"intc_ex_irq2",
1451	"intc_ex_irq3",
1452	"intc_ex_irq4",
1453	"intc_ex_irq5",
1454};
1455
1456static const char * const mmc_groups[] = {
1457	"mmc_data1",
1458	"mmc_data4",
1459	"mmc_data8",
1460	"mmc_ctrl",
1461	"mmc_cd",
1462	"mmc_wp",
1463	"mmc_ds",
1464};
1465
1466static const char * const msiof0_groups[] = {
1467	"msiof0_clk",
1468	"msiof0_sync",
1469	"msiof0_ss1",
1470	"msiof0_ss2",
1471	"msiof0_txd",
1472	"msiof0_rxd",
1473};
1474
1475static const char * const msiof1_groups[] = {
1476	"msiof1_clk",
1477	"msiof1_sync",
1478	"msiof1_ss1",
1479	"msiof1_ss2",
1480	"msiof1_txd",
1481	"msiof1_rxd",
1482};
1483
1484static const char * const msiof2_groups[] = {
1485	"msiof2_clk",
1486	"msiof2_sync",
1487	"msiof2_ss1",
1488	"msiof2_ss2",
1489	"msiof2_txd",
1490	"msiof2_rxd",
1491};
1492
1493static const char * const msiof3_groups[] = {
1494	"msiof3_clk",
1495	"msiof3_sync",
1496	"msiof3_ss1",
1497	"msiof3_ss2",
1498	"msiof3_txd",
1499	"msiof3_rxd",
1500};
1501
1502static const char * const pcie_groups[] = {
1503	"pcie0_clkreq_n",
1504	"pcie1_clkreq_n",
1505};
1506
1507static const char * const qspi0_groups[] = {
1508	"qspi0_ctrl",
1509	"qspi0_data2",
1510	"qspi0_data4",
1511};
1512
1513static const char * const qspi1_groups[] = {
1514	"qspi1_ctrl",
1515	"qspi1_data2",
1516	"qspi1_data4",
1517};
1518
1519static const char * const scif0_groups[] = {
1520	"scif0_data",
1521	"scif0_clk",
1522	"scif0_ctrl",
1523};
1524
1525static const char * const scif1_groups[] = {
1526	"scif1_data",
1527	"scif1_clk",
1528	"scif1_ctrl",
1529};
1530
1531static const char * const scif3_groups[] = {
1532	"scif3_data",
1533	"scif3_clk",
1534	"scif3_ctrl",
1535};
1536
1537static const char * const scif4_groups[] = {
1538	"scif4_data",
1539	"scif4_clk",
1540	"scif4_ctrl",
1541};
1542
1543static const char * const scif_clk_groups[] = {
1544	"scif_clk",
1545};
1546
1547static const char * const tsn0_groups[] = {
1548	"tsn0_link_a",
1549	"tsn0_magic_a",
1550	"tsn0_phy_int_a",
1551	"tsn0_mdio_a",
1552	"tsn0_link_b",
1553	"tsn0_magic_b",
1554	"tsn0_phy_int_b",
1555	"tsn0_mdio_b",
1556	"tsn0_avtp_pps",
1557	"tsn0_avtp_capture_a",
1558	"tsn0_avtp_match_a",
1559	"tsn0_avtp_capture_b",
1560	"tsn0_avtp_match_b",
1561};
1562
1563static const char * const tsn1_groups[] = {
1564	"tsn1_link_a",
1565	"tsn1_phy_int_a",
1566	"tsn1_mdio_a",
1567	"tsn1_link_b",
1568	"tsn1_phy_int_b",
1569	"tsn1_mdio_b",
1570	"tsn1_avtp_pps",
1571	"tsn1_avtp_capture_a",
1572	"tsn1_avtp_match_a",
1573	"tsn1_avtp_capture_b",
1574	"tsn1_avtp_match_b",
1575};
1576
1577static const char * const tsn2_groups[] = {
1578	"tsn2_link_a",
1579	"tsn2_phy_int_a",
1580	"tsn2_mdio_a",
1581	"tsn2_link_b",
1582	"tsn2_phy_int_b",
1583	"tsn2_mdio_b",
1584};
1585
1586static const struct sh_pfc_function pinmux_functions[] = {
1587	SH_PFC_FUNCTION(hscif0),
1588	SH_PFC_FUNCTION(hscif1),
1589	SH_PFC_FUNCTION(hscif2),
1590	SH_PFC_FUNCTION(hscif3),
1591	SH_PFC_FUNCTION(i2c0),
1592	SH_PFC_FUNCTION(i2c1),
1593	SH_PFC_FUNCTION(i2c2),
1594	SH_PFC_FUNCTION(i2c3),
1595	SH_PFC_FUNCTION(i2c4),
1596	SH_PFC_FUNCTION(i2c5),
1597	SH_PFC_FUNCTION(intc_ex),
1598	SH_PFC_FUNCTION(mmc),
1599	SH_PFC_FUNCTION(msiof0),
1600	SH_PFC_FUNCTION(msiof1),
1601	SH_PFC_FUNCTION(msiof2),
1602	SH_PFC_FUNCTION(msiof3),
1603	SH_PFC_FUNCTION(pcie),
1604	SH_PFC_FUNCTION(qspi0),
1605	SH_PFC_FUNCTION(qspi1),
1606	SH_PFC_FUNCTION(scif0),
1607	SH_PFC_FUNCTION(scif1),
1608	SH_PFC_FUNCTION(scif3),
1609	SH_PFC_FUNCTION(scif4),
1610	SH_PFC_FUNCTION(scif_clk),
1611	SH_PFC_FUNCTION(tsn0),
1612	SH_PFC_FUNCTION(tsn1),
1613	SH_PFC_FUNCTION(tsn2),
1614};
1615
1616static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1617#define F_(x, y)	FN_##y
1618#define FM(x)		FN_##x
1619	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
1620			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1621				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
1622			     GROUP(
1623		/* GP0_31_21 RESERVED */
1624		GP_0_20_FN,	GPSR0_20,
1625		GP_0_19_FN,	GPSR0_19,
1626		GP_0_18_FN,	GPSR0_18,
1627		GP_0_17_FN,	GPSR0_17,
1628		GP_0_16_FN,	GPSR0_16,
1629		GP_0_15_FN,	GPSR0_15,
1630		GP_0_14_FN,	GPSR0_14,
1631		GP_0_13_FN,	GPSR0_13,
1632		GP_0_12_FN,	GPSR0_12,
1633		GP_0_11_FN,	GPSR0_11,
1634		GP_0_10_FN,	GPSR0_10,
1635		GP_0_9_FN,	GPSR0_9,
1636		GP_0_8_FN,	GPSR0_8,
1637		GP_0_7_FN,	GPSR0_7,
1638		GP_0_6_FN,	GPSR0_6,
1639		GP_0_5_FN,	GPSR0_5,
1640		GP_0_4_FN,	GPSR0_4,
1641		GP_0_3_FN,	GPSR0_3,
1642		GP_0_2_FN,	GPSR0_2,
1643		GP_0_1_FN,	GPSR0_1,
1644		GP_0_0_FN,	GPSR0_0, ))
1645	},
1646	{ PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
1647			     GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1648				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
1649			     GROUP(
1650		/* GP1_31_25 RESERVED */
1651		GP_1_24_FN,	GPSR1_24,
1652		GP_1_23_FN,	GPSR1_23,
1653		GP_1_22_FN,	GPSR1_22,
1654		GP_1_21_FN,	GPSR1_21,
1655		GP_1_20_FN,	GPSR1_20,
1656		GP_1_19_FN,	GPSR1_19,
1657		GP_1_18_FN,	GPSR1_18,
1658		GP_1_17_FN,	GPSR1_17,
1659		GP_1_16_FN,	GPSR1_16,
1660		GP_1_15_FN,	GPSR1_15,
1661		GP_1_14_FN,	GPSR1_14,
1662		GP_1_13_FN,	GPSR1_13,
1663		GP_1_12_FN,	GPSR1_12,
1664		GP_1_11_FN,	GPSR1_11,
1665		GP_1_10_FN,	GPSR1_10,
1666		GP_1_9_FN,	GPSR1_9,
1667		GP_1_8_FN,	GPSR1_8,
1668		GP_1_7_FN,	GPSR1_7,
1669		GP_1_6_FN,	GPSR1_6,
1670		GP_1_5_FN,	GPSR1_5,
1671		GP_1_4_FN,	GPSR1_4,
1672		GP_1_3_FN,	GPSR1_3,
1673		GP_1_2_FN,	GPSR1_2,
1674		GP_1_1_FN,	GPSR1_1,
1675		GP_1_0_FN,	GPSR1_0, ))
1676	},
1677	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
1678			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1679				   1, 1, 1, 1, 1, 1),
1680			     GROUP(
1681		/* GP2_31_17 RESERVED */
1682		GP_2_16_FN,	GPSR2_16,
1683		GP_2_15_FN,	GPSR2_15,
1684		GP_2_14_FN,	GPSR2_14,
1685		GP_2_13_FN,	GPSR2_13,
1686		GP_2_12_FN,	GPSR2_12,
1687		GP_2_11_FN,	GPSR2_11,
1688		GP_2_10_FN,	GPSR2_10,
1689		GP_2_9_FN,	GPSR2_9,
1690		GP_2_8_FN,	GPSR2_8,
1691		GP_2_7_FN,	GPSR2_7,
1692		GP_2_6_FN,	GPSR2_6,
1693		GP_2_5_FN,	GPSR2_5,
1694		GP_2_4_FN,	GPSR2_4,
1695		GP_2_3_FN,	GPSR2_3,
1696		GP_2_2_FN,	GPSR2_2,
1697		GP_2_1_FN,	GPSR2_1,
1698		GP_2_0_FN,	GPSR2_0, ))
1699	},
1700	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
1701			     GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1702				   1, 1, 1, 1, 1, 1, 1, 1),
1703			     GROUP(
1704		/* GP3_31_19 RESERVED */
1705		GP_3_18_FN,	GPSR3_18,
1706		GP_3_17_FN,	GPSR3_17,
1707		GP_3_16_FN,	GPSR3_16,
1708		GP_3_15_FN,	GPSR3_15,
1709		GP_3_14_FN,	GPSR3_14,
1710		GP_3_13_FN,	GPSR3_13,
1711		GP_3_12_FN,	GPSR3_12,
1712		GP_3_11_FN,	GPSR3_11,
1713		GP_3_10_FN,	GPSR3_10,
1714		GP_3_9_FN,	GPSR3_9,
1715		GP_3_8_FN,	GPSR3_8,
1716		GP_3_7_FN,	GPSR3_7,
1717		GP_3_6_FN,	GPSR3_6,
1718		GP_3_5_FN,	GPSR3_5,
1719		GP_3_4_FN,	GPSR3_4,
1720		GP_3_3_FN,	GPSR3_3,
1721		GP_3_2_FN,	GPSR3_2,
1722		GP_3_1_FN,	GPSR3_1,
1723		GP_3_0_FN,	GPSR3_0, ))
1724	},
1725#undef F_
1726#undef FM
1727
1728#define F_(x, y)	x,
1729#define FM(x)		FN_##x,
1730	{ PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP(
1731		IP0SR0_31_28
1732		IP0SR0_27_24
1733		IP0SR0_23_20
1734		IP0SR0_19_16
1735		IP0SR0_15_12
1736		IP0SR0_11_8
1737		IP0SR0_7_4
1738		IP0SR0_3_0))
1739	},
1740	{ PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP(
1741		IP1SR0_31_28
1742		IP1SR0_27_24
1743		IP1SR0_23_20
1744		IP1SR0_19_16
1745		IP1SR0_15_12
1746		IP1SR0_11_8
1747		IP1SR0_7_4
1748		IP1SR0_3_0))
1749	},
1750	{ PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
1751			     GROUP(-12, 4, 4, 4, 4, 4),
1752			     GROUP(
1753		/* IP2SR0_31_20 RESERVED */
1754		IP2SR0_19_16
1755		IP2SR0_15_12
1756		IP2SR0_11_8
1757		IP2SR0_7_4
1758		IP2SR0_3_0))
1759	},
1760	{ PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP(
1761		IP0SR1_31_28
1762		IP0SR1_27_24
1763		IP0SR1_23_20
1764		IP0SR1_19_16
1765		IP0SR1_15_12
1766		IP0SR1_11_8
1767		IP0SR1_7_4
1768		IP0SR1_3_0))
1769	},
1770#undef F_
1771#undef FM
1772
1773#define F_(x, y)	x,
1774#define FM(x)		FN_##x,
1775	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
1776			     GROUP(-20, 2, 2, 2, 2, 2, 2),
1777			     GROUP(
1778		/* RESERVED 31-12 */
1779		MOD_SEL1_11_10
1780		MOD_SEL1_9_8
1781		MOD_SEL1_7_6
1782		MOD_SEL1_5_4
1783		MOD_SEL1_3_2
1784		MOD_SEL1_1_0))
1785	},
1786	{ /* sentinel */ }
1787};
1788
1789static const struct pinmux_drive_reg pinmux_drive_regs[] = {
1790	{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) {
1791		{ RCAR_GP_PIN(0,  7), 28, 3 },	/* TX0 */
1792		{ RCAR_GP_PIN(0,  6), 24, 3 },	/* RX0 */
1793		{ RCAR_GP_PIN(0,  5), 20, 3 },	/* HRTS0_N */
1794		{ RCAR_GP_PIN(0,  4), 16, 3 },	/* HCTS0_N */
1795		{ RCAR_GP_PIN(0,  3), 12, 3 },	/* HTX0 */
1796		{ RCAR_GP_PIN(0,  2),  8, 3 },	/* HRX0 */
1797		{ RCAR_GP_PIN(0,  1),  4, 3 },	/* HSCK0 */
1798		{ RCAR_GP_PIN(0,  0),  0, 3 },	/* SCIF_CLK */
1799	} },
1800	{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) {
1801		{ RCAR_GP_PIN(0, 15), 28, 3 },	/* MSIOF0_SS1 */
1802		{ RCAR_GP_PIN(0, 14), 24, 3 },	/* MSIOF0_SCK */
1803		{ RCAR_GP_PIN(0, 13), 20, 3 },	/* MSIOF0_TXD */
1804		{ RCAR_GP_PIN(0, 12), 16, 3 },	/* MSIOF0_RXD */
1805		{ RCAR_GP_PIN(0, 11), 12, 3 },	/* MSIOF0_SYNC */
1806		{ RCAR_GP_PIN(0, 10),  8, 3 },	/* CTS0_N */
1807		{ RCAR_GP_PIN(0,  9),  4, 3 },	/* RTS0_N */
1808		{ RCAR_GP_PIN(0,  8),  0, 3 },	/* SCK0 */
1809	} },
1810	{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) {
1811		{ RCAR_GP_PIN(0, 20), 16, 3 },	/* IRQ3 */
1812		{ RCAR_GP_PIN(0, 19), 12, 3 },	/* IRQ2 */
1813		{ RCAR_GP_PIN(0, 18),  8, 3 },	/* IRQ1 */
1814		{ RCAR_GP_PIN(0, 17),  4, 3 },	/* IRQ0 */
1815		{ RCAR_GP_PIN(0, 16),  0, 3 },	/* MSIOF0_SS2 */
1816	} },
1817	{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) {
1818		{ RCAR_GP_PIN(1,  7), 28, 3 },	/* GP1_07 */
1819		{ RCAR_GP_PIN(1,  6), 24, 3 },	/* GP1_06 */
1820		{ RCAR_GP_PIN(1,  5), 20, 3 },	/* GP1_05 */
1821		{ RCAR_GP_PIN(1,  4), 16, 3 },	/* GP1_04 */
1822		{ RCAR_GP_PIN(1,  3), 12, 3 },	/* GP1_03 */
1823		{ RCAR_GP_PIN(1,  2),  8, 3 },	/* GP1_02 */
1824		{ RCAR_GP_PIN(1,  1),  4, 3 },	/* GP1_01 */
1825		{ RCAR_GP_PIN(1,  0),  0, 3 },	/* GP1_00 */
1826	} },
1827	{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) {
1828		{ RCAR_GP_PIN(1, 15), 28, 3 },	/* MMC_SD_D2 */
1829		{ RCAR_GP_PIN(1, 14), 24, 3 },	/* MMC_SD_D1 */
1830		{ RCAR_GP_PIN(1, 13), 20, 3 },	/* MMC_SD_D0 */
1831		{ RCAR_GP_PIN(1, 12), 16, 3 },	/* MMC_SD_CLK */
1832		{ RCAR_GP_PIN(1, 11), 12, 3 },	/* GP1_11 */
1833		{ RCAR_GP_PIN(1, 10),  8, 3 },	/* GP1_10 */
1834		{ RCAR_GP_PIN(1,  9),  4, 3 },	/* GP1_09 */
1835		{ RCAR_GP_PIN(1,  8),  0, 3 },	/* GP1_08 */
1836	} },
1837	{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) {
1838		{ RCAR_GP_PIN(1, 23), 28, 3 },	/* SD_CD */
1839		{ RCAR_GP_PIN(1, 22), 24, 3 },	/* MMC_SD_CMD */
1840		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* MMC_D7 */
1841		{ RCAR_GP_PIN(1, 20), 16, 3 },	/* MMC_DS */
1842		{ RCAR_GP_PIN(1, 19), 12, 3 },	/* MMC_D6 */
1843		{ RCAR_GP_PIN(1, 18),  8, 3 },	/* MMC_D4 */
1844		{ RCAR_GP_PIN(1, 17),  4, 3 },	/* MMC_D5 */
1845		{ RCAR_GP_PIN(1, 16),  0, 3 },	/* MMC_SD_D3 */
1846	} },
1847	{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) {
1848		{ RCAR_GP_PIN(1, 24),  0, 3 },	/* SD_WP */
1849	} },
1850	{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) {
1851		{ RCAR_GP_PIN(2,  7), 28, 2 },	/* QSPI1_MOSI_IO0 */
1852		{ RCAR_GP_PIN(2,  6), 24, 2 },	/* QSPI1_IO2 */
1853		{ RCAR_GP_PIN(2,  5), 20, 2 },	/* QSPI1_MISO_IO1 */
1854		{ RCAR_GP_PIN(2,  4), 16, 2 },	/* QSPI1_IO3 */
1855		{ RCAR_GP_PIN(2,  3), 12, 2 },	/* QSPI1_SSL */
1856		{ RCAR_GP_PIN(2,  2),  8, 2 },	/* RPC_RESET_N */
1857		{ RCAR_GP_PIN(2,  1),  4, 2 },	/* RPC_WP_N */
1858		{ RCAR_GP_PIN(2,  0),  0, 2 },	/* RPC_INT_N */
1859	} },
1860	{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) {
1861		{ RCAR_GP_PIN(2, 15), 28, 3 },	/* PCIE0_CLKREQ_N */
1862		{ RCAR_GP_PIN(2, 14), 24, 2 },	/* QSPI0_IO3 */
1863		{ RCAR_GP_PIN(2, 13), 20, 2 },	/* QSPI0_SSL */
1864		{ RCAR_GP_PIN(2, 12), 16, 2 },	/* QSPI0_MISO_IO1 */
1865		{ RCAR_GP_PIN(2, 11), 12, 2 },	/* QSPI0_IO2 */
1866		{ RCAR_GP_PIN(2, 10),  8, 2 },	/* QSPI0_SPCLK */
1867		{ RCAR_GP_PIN(2,  9),  4, 2 },	/* QSPI0_MOSI_IO0 */
1868		{ RCAR_GP_PIN(2,  8),  0, 2 },	/* QSPI1_SPCLK */
1869	} },
1870	{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) {
1871		{ RCAR_GP_PIN(2, 16),  0, 3 },	/* PCIE1_CLKREQ_N */
1872	} },
1873	{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) {
1874		{ RCAR_GP_PIN(3,  7), 28, 3 },	/* TSN2_LINK_B */
1875		{ RCAR_GP_PIN(3,  6), 24, 3 },	/* TSN1_LINK_B */
1876		{ RCAR_GP_PIN(3,  5), 20, 3 },	/* TSN1_MDC_B */
1877		{ RCAR_GP_PIN(3,  4), 16, 3 },	/* TSN0_MDC_B */
1878		{ RCAR_GP_PIN(3,  3), 12, 3 },	/* TSN2_MDC_B */
1879		{ RCAR_GP_PIN(3,  2),  8, 3 },	/* TSN0_MDIO_B */
1880		{ RCAR_GP_PIN(3,  1),  4, 3 },	/* TSN2_MDIO_B */
1881		{ RCAR_GP_PIN(3,  0),  0, 3 },	/* TSN1_MDIO_B */
1882	} },
1883	{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) {
1884		{ RCAR_GP_PIN(3, 15), 28, 3 },	/* TSN1_AVTP_CAPTURE_B */
1885		{ RCAR_GP_PIN(3, 14), 24, 3 },	/* TSN1_AVTP_MATCH_B */
1886		{ RCAR_GP_PIN(3, 13), 20, 3 },	/* TSN1_AVTP_PPS */
1887		{ RCAR_GP_PIN(3, 12), 16, 3 },	/* TSN0_MAGIC_B */
1888		{ RCAR_GP_PIN(3, 11), 12, 3 },	/* TSN1_PHY_INT_B */
1889		{ RCAR_GP_PIN(3, 10),  8, 3 },	/* TSN0_PHY_INT_B */
1890		{ RCAR_GP_PIN(3,  9),  4, 3 },	/* TSN2_PHY_INT_B */
1891		{ RCAR_GP_PIN(3,  8),  0, 3 },	/* TSN0_LINK_B */
1892	} },
1893	{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) {
1894		{ RCAR_GP_PIN(3, 18),  8, 3 },	/* TSN0_AVTP_CAPTURE_B */
1895		{ RCAR_GP_PIN(3, 17),  4, 3 },	/* TSN0_AVTP_MATCH_B */
1896		{ RCAR_GP_PIN(3, 16),  0, 3 },	/* TSN0_AVTP_PPS */
1897	} },
1898	{ /* sentinel */ }
1899};
1900
1901enum ioctrl_regs {
1902	POC0,
1903	POC1,
1904	POC3,
1905	TD0SEL1,
1906};
1907
1908static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
1909	[POC0] = { 0xe60500a0, },
1910	[POC1] = { 0xe60508a0, },
1911	[POC3] = { 0xe60518a0, },
1912	[TD0SEL1] = { 0xe6050920, },
1913	{ /* sentinel */ }
1914};
1915
1916static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
1917{
1918	int bit = pin & 0x1f;
1919
1920	*pocctrl = pinmux_ioctrl_regs[POC0].reg;
1921	if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20))
1922		return bit;
1923
1924	*pocctrl = pinmux_ioctrl_regs[POC1].reg;
1925	if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24))
1926		return bit;
1927
1928	*pocctrl = pinmux_ioctrl_regs[POC3].reg;
1929	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18))
1930		return bit;
1931
1932	return -EINVAL;
1933}
1934
1935static const struct pinmux_bias_reg pinmux_bias_regs[] = {
1936	{ PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) {
1937		[ 0] = RCAR_GP_PIN(0,  0),	/* SCIF_CLK */
1938		[ 1] = RCAR_GP_PIN(0,  1),	/* HSCK0 */
1939		[ 2] = RCAR_GP_PIN(0,  2),	/* HRX0 */
1940		[ 3] = RCAR_GP_PIN(0,  3),	/* HTX0 */
1941		[ 4] = RCAR_GP_PIN(0,  4),	/* HCTS0_N */
1942		[ 5] = RCAR_GP_PIN(0,  5),	/* HRTS0_N */
1943		[ 6] = RCAR_GP_PIN(0,  6),	/* RX0 */
1944		[ 7] = RCAR_GP_PIN(0,  7),	/* TX0 */
1945		[ 8] = RCAR_GP_PIN(0,  8),	/* SCK0 */
1946		[ 9] = RCAR_GP_PIN(0,  9),	/* RTS0_N */
1947		[10] = RCAR_GP_PIN(0, 10),	/* CTS0_N */
1948		[11] = RCAR_GP_PIN(0, 11),	/* MSIOF0_SYNC */
1949		[12] = RCAR_GP_PIN(0, 12),	/* MSIOF0_RXD */
1950		[13] = RCAR_GP_PIN(0, 13),	/* MSIOF0_TXD */
1951		[14] = RCAR_GP_PIN(0, 14),	/* MSIOF0_SCK */
1952		[15] = RCAR_GP_PIN(0, 15),	/* MSIOF0_SS1 */
1953		[16] = RCAR_GP_PIN(0, 16),	/* MSIOF0_SS2 */
1954		[17] = RCAR_GP_PIN(0, 17),	/* IRQ0 */
1955		[18] = RCAR_GP_PIN(0, 18),	/* IRQ1 */
1956		[19] = RCAR_GP_PIN(0, 19),	/* IRQ2 */
1957		[20] = RCAR_GP_PIN(0, 20),	/* IRQ3 */
1958		[21] = SH_PFC_PIN_NONE,
1959		[22] = SH_PFC_PIN_NONE,
1960		[23] = SH_PFC_PIN_NONE,
1961		[24] = SH_PFC_PIN_NONE,
1962		[25] = SH_PFC_PIN_NONE,
1963		[26] = SH_PFC_PIN_NONE,
1964		[27] = SH_PFC_PIN_NONE,
1965		[28] = SH_PFC_PIN_NONE,
1966		[29] = SH_PFC_PIN_NONE,
1967		[30] = SH_PFC_PIN_NONE,
1968		[31] = SH_PFC_PIN_NONE,
1969	} },
1970	{ PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) {
1971		[ 0] = RCAR_GP_PIN(1,  0),	/* GP1_00 */
1972		[ 1] = RCAR_GP_PIN(1,  1),	/* GP1_01 */
1973		[ 2] = RCAR_GP_PIN(1,  2),	/* GP1_02 */
1974		[ 3] = RCAR_GP_PIN(1,  3),	/* GP1_03 */
1975		[ 4] = RCAR_GP_PIN(1,  4),	/* GP1_04 */
1976		[ 5] = RCAR_GP_PIN(1,  5),	/* GP1_05 */
1977		[ 6] = RCAR_GP_PIN(1,  6),	/* GP1_06 */
1978		[ 7] = RCAR_GP_PIN(1,  7),	/* GP1_07 */
1979		[ 8] = RCAR_GP_PIN(1,  8),	/* GP1_08 */
1980		[ 9] = RCAR_GP_PIN(1,  9),	/* GP1_09 */
1981		[10] = RCAR_GP_PIN(1, 10),	/* GP1_10 */
1982		[11] = RCAR_GP_PIN(1, 11),	/* GP1_11 */
1983		[12] = RCAR_GP_PIN(1, 12),	/* MMC_SD_CLK */
1984		[13] = RCAR_GP_PIN(1, 13),	/* MMC_SD_D0 */
1985		[14] = RCAR_GP_PIN(1, 14),	/* MMC_SD_D1 */
1986		[15] = RCAR_GP_PIN(1, 15),	/* MMC_SD_D2 */
1987		[16] = RCAR_GP_PIN(1, 16),	/* MMC_SD_D3 */
1988		[17] = RCAR_GP_PIN(1, 17),	/* MMC_D5 */
1989		[18] = RCAR_GP_PIN(1, 18),	/* MMC_D4 */
1990		[19] = RCAR_GP_PIN(1, 19),	/* MMC_D6 */
1991		[20] = RCAR_GP_PIN(1, 20),	/* MMC_DS */
1992		[21] = RCAR_GP_PIN(1, 21),	/* MMC_D7 */
1993		[22] = RCAR_GP_PIN(1, 22),	/* MMC_SD_CMD */
1994		[23] = RCAR_GP_PIN(1, 23),	/* SD_CD */
1995		[24] = RCAR_GP_PIN(1, 24),	/* SD_WP */
1996		[25] = SH_PFC_PIN_NONE,
1997		[26] = SH_PFC_PIN_NONE,
1998		[27] = SH_PFC_PIN_NONE,
1999		[28] = SH_PFC_PIN_NONE,
2000		[29] = SH_PFC_PIN_NONE,
2001		[30] = SH_PFC_PIN_NONE,
2002		[31] = SH_PFC_PIN_NONE,
2003	} },
2004	{ PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) {
2005		[ 0] = RCAR_GP_PIN(2,  0),	/* RPC_INT_N */
2006		[ 1] = RCAR_GP_PIN(2,  1),	/* RPC_WP_N */
2007		[ 2] = RCAR_GP_PIN(2,  2),	/* RPC_RESET_N */
2008		[ 3] = RCAR_GP_PIN(2,  3),	/* QSPI1_SSL */
2009		[ 4] = RCAR_GP_PIN(2,  4),	/* QSPI1_IO3 */
2010		[ 5] = RCAR_GP_PIN(2,  5),	/* QSPI1_MISO_IO1 */
2011		[ 6] = RCAR_GP_PIN(2,  6),	/* QSPI1_IO2 */
2012		[ 7] = RCAR_GP_PIN(2,  7),	/* QSPI1_MOSI_IO0 */
2013		[ 8] = RCAR_GP_PIN(2,  8),	/* QSPI1_SPCLK */
2014		[ 9] = RCAR_GP_PIN(2,  9),	/* QSPI0_MOSI_IO0 */
2015		[10] = RCAR_GP_PIN(2, 10),	/* QSPI0_SPCLK */
2016		[11] = RCAR_GP_PIN(2, 11),	/* QSPI0_IO2 */
2017		[12] = RCAR_GP_PIN(2, 12),	/* QSPI0_MISO_IO1 */
2018		[13] = RCAR_GP_PIN(2, 13),	/* QSPI0_SSL */
2019		[14] = RCAR_GP_PIN(2, 14),	/* QSPI0_IO3 */
2020		[15] = RCAR_GP_PIN(2, 15),	/* PCIE0_CLKREQ_N */
2021		[16] = RCAR_GP_PIN(2, 16),	/* PCIE1_CLKREQ_N */
2022		[17] = SH_PFC_PIN_NONE,
2023		[18] = SH_PFC_PIN_NONE,
2024		[19] = SH_PFC_PIN_NONE,
2025		[20] = SH_PFC_PIN_NONE,
2026		[21] = SH_PFC_PIN_NONE,
2027		[22] = SH_PFC_PIN_NONE,
2028		[23] = SH_PFC_PIN_NONE,
2029		[24] = SH_PFC_PIN_NONE,
2030		[25] = SH_PFC_PIN_NONE,
2031		[26] = SH_PFC_PIN_NONE,
2032		[27] = SH_PFC_PIN_NONE,
2033		[28] = SH_PFC_PIN_NONE,
2034		[29] = SH_PFC_PIN_NONE,
2035		[30] = SH_PFC_PIN_NONE,
2036		[31] = SH_PFC_PIN_NONE,
2037	} },
2038	{ PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) {
2039		[ 0] = RCAR_GP_PIN(3,  0),	/* TSN1_MDIO_B */
2040		[ 1] = RCAR_GP_PIN(3,  1),	/* TSN2_MDIO_B */
2041		[ 2] = RCAR_GP_PIN(3,  2),	/* TSN0_MDIO_B */
2042		[ 3] = RCAR_GP_PIN(3,  3),	/* TSN2_MDC_B */
2043		[ 4] = RCAR_GP_PIN(3,  4),	/* TSN0_MDC_B */
2044		[ 5] = RCAR_GP_PIN(3,  5),	/* TSN1_MDC_B */
2045		[ 6] = RCAR_GP_PIN(3,  6),	/* TSN1_LINK_B */
2046		[ 7] = RCAR_GP_PIN(3,  7),	/* TSN2_LINK_B */
2047		[ 8] = RCAR_GP_PIN(3,  8),	/* TSN0_LINK_B */
2048		[ 9] = RCAR_GP_PIN(3,  9),	/* TSN2_PHY_INT_B */
2049		[10] = RCAR_GP_PIN(3, 10),	/* TSN0_PHY_INT_B */
2050		[11] = RCAR_GP_PIN(3, 11),	/* TSN1_PHY_INT_B */
2051		[12] = RCAR_GP_PIN(3, 12),	/* TSN0_MAGIC_B */
2052		[13] = RCAR_GP_PIN(3, 13),	/* TSN1_AVTP_PPS */
2053		[14] = RCAR_GP_PIN(3, 14),	/* TSN1_AVTP_MATCH_B */
2054		[15] = RCAR_GP_PIN(3, 15),	/* TSN1_AVTP_CAPTURE_B */
2055		[16] = RCAR_GP_PIN(3, 16),	/* TSN0_AVTP_PPS */
2056		[17] = RCAR_GP_PIN(3, 17),	/* TSN0_AVTP_MATCH_B */
2057		[18] = RCAR_GP_PIN(3, 18),	/* TSN0_AVTP_CAPTURE_B */
2058		[19] = SH_PFC_PIN_NONE,
2059		[20] = SH_PFC_PIN_NONE,
2060		[21] = SH_PFC_PIN_NONE,
2061		[22] = SH_PFC_PIN_NONE,
2062		[23] = SH_PFC_PIN_NONE,
2063		[24] = SH_PFC_PIN_NONE,
2064		[25] = SH_PFC_PIN_NONE,
2065		[26] = SH_PFC_PIN_NONE,
2066		[27] = SH_PFC_PIN_NONE,
2067		[28] = SH_PFC_PIN_NONE,
2068		[29] = SH_PFC_PIN_NONE,
2069		[30] = SH_PFC_PIN_NONE,
2070		[31] = SH_PFC_PIN_NONE,
2071	} },
2072	{ /* sentinel */ }
2073};
2074
2075static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
2076	.pin_to_pocctrl = r8a779f0_pin_to_pocctrl,
2077	.get_bias = rcar_pinmux_get_bias,
2078	.set_bias = rcar_pinmux_set_bias,
2079};
2080
2081const struct sh_pfc_soc_info r8a779f0_pinmux_info = {
2082	.name = "r8a779f0_pfc",
2083	.ops = &r8a779f0_pfc_ops,
2084	.unlock_reg = 0x1ff,	/* PMMRn mask */
2085
2086	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2087
2088	.pins = pinmux_pins,
2089	.nr_pins = ARRAY_SIZE(pinmux_pins),
2090	.groups = pinmux_groups,
2091	.nr_groups = ARRAY_SIZE(pinmux_groups),
2092	.functions = pinmux_functions,
2093	.nr_functions = ARRAY_SIZE(pinmux_functions),
2094
2095	.cfg_regs = pinmux_config_regs,
2096	.drive_regs = pinmux_drive_regs,
2097	.bias_regs = pinmux_bias_regs,
2098	.ioctrl_regs = pinmux_ioctrl_regs,
2099
2100	.pinmux_data = pinmux_data,
2101	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
2102};