pfc-r8a77980.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A77980 processor support - PFC hardware block.
   4 *
   5 * Copyright (C) 2018 Renesas Electronics Corp.
   6 * Copyright (C) 2018 Cogent Embedded, Inc.
   7 *
   8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
   9 *
  10 * R-Car Gen3 processor support - PFC hardware block.
  11 *
  12 * Copyright (C) 2015 Renesas Electronics Corporation
  13 */
  14
  15#include <linux/errno.h>
  16#include <linux/io.h>
  17#include <linux/kernel.h>
  18
  19#include "sh_pfc.h"
  20
  21#define CPU_ALL_GP(fn, sfx)	\
  22	PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  23	PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  24	PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  25	PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  26	PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  27	PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  28
  29#define CPU_ALL_NOGP(fn)	\
  30	PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  31	PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  32	PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  33	PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  34	PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  35	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  36	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  37	PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  38	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
  39	PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
  40	PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
  41
  42/*
  43 * F_() : just information
  44 * FM() : macro for FN_xxx / xxx_MARK
  45 */
  46
  47/* GPSR0 */
  48#define GPSR0_21	F_(DU_EXODDF_DU_ODDF_DISP_CDE,	IP2_23_20)
  49#define GPSR0_20	F_(DU_EXVSYNC_DU_VSYNC,		IP2_19_16)
  50#define GPSR0_19	F_(DU_EXHSYNC_DU_HSYNC,		IP2_15_12)
  51#define GPSR0_18	F_(DU_DOTCLKOUT,		IP2_11_8)
  52#define GPSR0_17	F_(DU_DB7,			IP2_7_4)
  53#define GPSR0_16	F_(DU_DB6,			IP2_3_0)
  54#define GPSR0_15	F_(DU_DB5,			IP1_31_28)
  55#define GPSR0_14	F_(DU_DB4,			IP1_27_24)
  56#define GPSR0_13	F_(DU_DB3,			IP1_23_20)
  57#define GPSR0_12	F_(DU_DB2,			IP1_19_16)
  58#define GPSR0_11	F_(DU_DG7,			IP1_15_12)
  59#define GPSR0_10	F_(DU_DG6,			IP1_11_8)
  60#define GPSR0_9		F_(DU_DG5,			IP1_7_4)
  61#define GPSR0_8		F_(DU_DG4,			IP1_3_0)
  62#define GPSR0_7		F_(DU_DG3,			IP0_31_28)
  63#define GPSR0_6		F_(DU_DG2,			IP0_27_24)
  64#define GPSR0_5		F_(DU_DR7,			IP0_23_20)
  65#define GPSR0_4		F_(DU_DR6,			IP0_19_16)
  66#define GPSR0_3		F_(DU_DR5,			IP0_15_12)
  67#define GPSR0_2		F_(DU_DR4,			IP0_11_8)
  68#define GPSR0_1		F_(DU_DR3,			IP0_7_4)
  69#define GPSR0_0		F_(DU_DR2,			IP0_3_0)
  70
  71/* GPSR1 */
  72#define GPSR1_27	F_(DIGRF_CLKOUT,	IP8_31_28)
  73#define GPSR1_26	F_(DIGRF_CLKIN,		IP8_27_24)
  74#define GPSR1_25	F_(CANFD_CLK_A,		IP8_23_20)
  75#define GPSR1_24	F_(CANFD1_RX,		IP8_19_16)
  76#define GPSR1_23	F_(CANFD1_TX,		IP8_15_12)
  77#define GPSR1_22	F_(CANFD0_RX_A,		IP8_11_8)
  78#define GPSR1_21	F_(CANFD0_TX_A,		IP8_7_4)
  79#define GPSR1_20	F_(AVB_AVTP_CAPTURE,	IP8_3_0)
  80#define GPSR1_19	F_(AVB_AVTP_MATCH,	IP7_31_28)
  81#define GPSR1_18	FM(AVB_LINK)
  82#define GPSR1_17	FM(AVB_PHY_INT)
  83#define GPSR1_16	FM(AVB_MAGIC)
  84#define GPSR1_15	FM(AVB_MDC)
  85#define GPSR1_14	FM(AVB_MDIO)
  86#define GPSR1_13	FM(AVB_TXCREFCLK)
  87#define GPSR1_12	FM(AVB_TD3)
  88#define GPSR1_11	FM(AVB_TD2)
  89#define GPSR1_10	FM(AVB_TD1)
  90#define GPSR1_9		FM(AVB_TD0)
  91#define GPSR1_8		FM(AVB_TXC)
  92#define GPSR1_7		FM(AVB_TX_CTL)
  93#define GPSR1_6		FM(AVB_RD3)
  94#define GPSR1_5		FM(AVB_RD2)
  95#define GPSR1_4		FM(AVB_RD1)
  96#define GPSR1_3		FM(AVB_RD0)
  97#define GPSR1_2		FM(AVB_RXC)
  98#define GPSR1_1		FM(AVB_RX_CTL)
  99#define GPSR1_0		F_(IRQ0,		IP2_27_24)
 100
 101/* GPSR2 */
 102#define GPSR2_29	F_(FSO_TOE_N,		IP10_19_16)
 103#define GPSR2_28	F_(FSO_CFE_1_N,		IP10_15_12)
 104#define GPSR2_27	F_(FSO_CFE_0_N,		IP10_11_8)
 105#define GPSR2_26	F_(SDA3,		IP10_7_4)
 106#define GPSR2_25	F_(SCL3,		IP10_3_0)
 107#define GPSR2_24	F_(MSIOF0_SS2,		IP9_31_28)
 108#define GPSR2_23	F_(MSIOF0_SS1,		IP9_27_24)
 109#define GPSR2_22	F_(MSIOF0_SYNC,		IP9_23_20)
 110#define GPSR2_21	F_(MSIOF0_SCK,		IP9_19_16)
 111#define GPSR2_20	F_(MSIOF0_TXD,		IP9_15_12)
 112#define GPSR2_19	F_(MSIOF0_RXD,		IP9_11_8)
 113#define GPSR2_18	F_(IRQ5,		IP9_7_4)
 114#define GPSR2_17	F_(IRQ4,		IP9_3_0)
 115#define GPSR2_16	F_(VI0_FIELD,		IP4_31_28)
 116#define GPSR2_15	F_(VI0_DATA11,		IP4_27_24)
 117#define GPSR2_14	F_(VI0_DATA10,		IP4_23_20)
 118#define GPSR2_13	F_(VI0_DATA9,		IP4_19_16)
 119#define GPSR2_12	F_(VI0_DATA8,		IP4_15_12)
 120#define GPSR2_11	F_(VI0_DATA7,		IP4_11_8)
 121#define GPSR2_10	F_(VI0_DATA6,		IP4_7_4)
 122#define GPSR2_9		F_(VI0_DATA5,		IP4_3_0)
 123#define GPSR2_8		F_(VI0_DATA4,		IP3_31_28)
 124#define GPSR2_7		F_(VI0_DATA3,		IP3_27_24)
 125#define GPSR2_6		F_(VI0_DATA2,		IP3_23_20)
 126#define GPSR2_5		F_(VI0_DATA1,		IP3_19_16)
 127#define GPSR2_4		F_(VI0_DATA0,		IP3_15_12)
 128#define GPSR2_3		F_(VI0_VSYNC_N,		IP3_11_8)
 129#define GPSR2_2		F_(VI0_HSYNC_N,		IP3_7_4)
 130#define GPSR2_1		F_(VI0_CLKENB,		IP3_3_0)
 131#define GPSR2_0		F_(VI0_CLK,		IP2_31_28)
 132
 133/* GPSR3 */
 134#define GPSR3_16	F_(VI1_FIELD,		IP7_3_0)
 135#define GPSR3_15	F_(VI1_DATA11,		IP6_31_28)
 136#define GPSR3_14	F_(VI1_DATA10,		IP6_27_24)
 137#define GPSR3_13	F_(VI1_DATA9,		IP6_23_20)
 138#define GPSR3_12	F_(VI1_DATA8,		IP6_19_16)
 139#define GPSR3_11	F_(VI1_DATA7,		IP6_15_12)
 140#define GPSR3_10	F_(VI1_DATA6,		IP6_11_8)
 141#define GPSR3_9		F_(VI1_DATA5,		IP6_7_4)
 142#define GPSR3_8		F_(VI1_DATA4,		IP6_3_0)
 143#define GPSR3_7		F_(VI1_DATA3,		IP5_31_28)
 144#define GPSR3_6		F_(VI1_DATA2,		IP5_27_24)
 145#define GPSR3_5		F_(VI1_DATA1,		IP5_23_20)
 146#define GPSR3_4		F_(VI1_DATA0,		IP5_19_16)
 147#define GPSR3_3		F_(VI1_VSYNC_N,		IP5_15_12)
 148#define GPSR3_2		F_(VI1_HSYNC_N,		IP5_11_8)
 149#define GPSR3_1		F_(VI1_CLKENB,		IP5_7_4)
 150#define GPSR3_0		F_(VI1_CLK,		IP5_3_0)
 151
 152/* GPSR4 */
 153#define GPSR4_24	FM(GETHER_LINK_A)
 154#define GPSR4_23	FM(GETHER_PHY_INT_A)
 155#define GPSR4_22	FM(GETHER_MAGIC)
 156#define GPSR4_21	FM(GETHER_MDC_A)
 157#define GPSR4_20	FM(GETHER_MDIO_A)
 158#define GPSR4_19	FM(GETHER_TXCREFCLK_MEGA)
 159#define GPSR4_18	FM(GETHER_TXCREFCLK)
 160#define GPSR4_17	FM(GETHER_TD3)
 161#define GPSR4_16	FM(GETHER_TD2)
 162#define GPSR4_15	FM(GETHER_TD1)
 163#define GPSR4_14	FM(GETHER_TD0)
 164#define GPSR4_13	FM(GETHER_TXC)
 165#define GPSR4_12	FM(GETHER_TX_CTL)
 166#define GPSR4_11	FM(GETHER_RD3)
 167#define GPSR4_10	FM(GETHER_RD2)
 168#define GPSR4_9		FM(GETHER_RD1)
 169#define GPSR4_8		FM(GETHER_RD0)
 170#define GPSR4_7		FM(GETHER_RXC)
 171#define GPSR4_6		FM(GETHER_RX_CTL)
 172#define GPSR4_5		F_(SDA2,		IP7_27_24)
 173#define GPSR4_4		F_(SCL2,		IP7_23_20)
 174#define GPSR4_3		F_(SDA1,		IP7_19_16)
 175#define GPSR4_2		F_(SCL1,		IP7_15_12)
 176#define GPSR4_1		F_(SDA0,		IP7_11_8)
 177#define GPSR4_0		F_(SCL0,		IP7_7_4)
 178
 179/* GPSR5 */
 180#define GPSR5_14	FM(RPC_INT_N)
 181#define GPSR5_13	FM(RPC_WP_N)
 182#define GPSR5_12	FM(RPC_RESET_N)
 183#define GPSR5_11	FM(QSPI1_SSL)
 184#define GPSR5_10	FM(QSPI1_IO3)
 185#define GPSR5_9		FM(QSPI1_IO2)
 186#define GPSR5_8		FM(QSPI1_MISO_IO1)
 187#define GPSR5_7		FM(QSPI1_MOSI_IO0)
 188#define GPSR5_6		FM(QSPI1_SPCLK)
 189#define GPSR5_5		FM(QSPI0_SSL)
 190#define GPSR5_4		FM(QSPI0_IO3)
 191#define GPSR5_3		FM(QSPI0_IO2)
 192#define GPSR5_2		FM(QSPI0_MISO_IO1)
 193#define GPSR5_1		FM(QSPI0_MOSI_IO0)
 194#define GPSR5_0		FM(QSPI0_SPCLK)
 195
 196/* IPSRx */		/* 0 */				/* 1 */			/* 2 */			/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
 197#define IP0_3_0		FM(DU_DR2)			FM(SCK4)		FM(GETHER_RMII_CRS_DV)	FM(A0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 198#define IP0_7_4		FM(DU_DR3)			FM(RX4)			FM(GETHER_RMII_RX_ER)	FM(A1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 199#define IP0_11_8	FM(DU_DR4)			FM(TX4)			FM(GETHER_RMII_RXD0)	FM(A2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 200#define IP0_15_12	FM(DU_DR5)			FM(CTS4_N)		FM(GETHER_RMII_RXD1)	FM(A3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 201#define IP0_19_16	FM(DU_DR6)			FM(RTS4_N)		FM(GETHER_RMII_TXD_EN)	FM(A4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 202#define IP0_23_20	FM(DU_DR7)			F_(0, 0)		FM(GETHER_RMII_TXD0)	FM(A5)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 203#define IP0_27_24	FM(DU_DG2)			F_(0, 0)		FM(GETHER_RMII_TXD1)	FM(A6)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 204#define IP0_31_28	FM(DU_DG3)			FM(CPG_CPCKOUT)		FM(GETHER_RMII_REFCLK)	FM(A7)		FM(PWMFSW0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 205#define IP1_3_0		FM(DU_DG4)			FM(SCL5)		F_(0, 0)		FM(A8)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 206#define IP1_7_4		FM(DU_DG5)			FM(SDA5)		FM(GETHER_MDC_B)	FM(A9)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 207#define IP1_11_8	FM(DU_DG6)			FM(SCIF_CLK_A)		FM(GETHER_MDIO_B)	FM(A10)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 208#define IP1_15_12	FM(DU_DG7)			FM(HRX0_A)		F_(0, 0)		FM(A11)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 209#define IP1_19_16	FM(DU_DB2)			FM(HSCK0_A)		F_(0, 0)		FM(A12)		FM(IRQ1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 210#define IP1_23_20	FM(DU_DB3)			FM(HRTS0_N_A)		F_(0, 0)		FM(A13)		FM(IRQ2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 211#define IP1_27_24	FM(DU_DB4)			FM(HCTS0_N_A)		F_(0, 0)		FM(A14)		FM(IRQ3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 212#define IP1_31_28	FM(DU_DB5)			FM(HTX0_A)		FM(PWM0_A)		FM(A15)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 213#define IP2_3_0		FM(DU_DB6)			FM(MSIOF3_RXD)		F_(0, 0)		FM(A16)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 214#define IP2_7_4		FM(DU_DB7)			FM(MSIOF3_TXD)		F_(0, 0)		FM(A17)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 215#define IP2_11_8	FM(DU_DOTCLKOUT)		FM(MSIOF3_SS1)		FM(GETHER_LINK_B)	FM(A18)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 216#define IP2_15_12	FM(DU_EXHSYNC_DU_HSYNC)		FM(MSIOF3_SS2)		FM(GETHER_PHY_INT_B)	FM(A19)		FM(FXR_TXENA_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 217#define IP2_19_16	FM(DU_EXVSYNC_DU_VSYNC)		FM(MSIOF3_SCK)		F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 218#define IP2_23_20	FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(MSIOF3_SYNC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 219#define IP2_27_24	FM(IRQ0)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 220#define IP2_31_28	FM(VI0_CLK)			FM(MSIOF2_SCK)		FM(SCK3)		F_(0, 0)	FM(HSCK3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 221#define IP3_3_0		FM(VI0_CLKENB)			FM(MSIOF2_RXD)		FM(RX3)			FM(RD_WR_N)	FM(HCTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 222#define IP3_7_4		FM(VI0_HSYNC_N)			FM(MSIOF2_TXD)		FM(TX3)			F_(0, 0)	FM(HRTS3_N)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 223#define IP3_11_8	FM(VI0_VSYNC_N)			FM(MSIOF2_SYNC)		FM(CTS3_N)		F_(0, 0)	FM(HTX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 224#define IP3_15_12	FM(VI0_DATA0)			FM(MSIOF2_SS1)		FM(RTS3_N)		F_(0, 0)	FM(HRX3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 225#define IP3_19_16	FM(VI0_DATA1)			FM(MSIOF2_SS2)		FM(SCK1)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 226#define IP3_23_20	FM(VI0_DATA2)			FM(AVB_AVTP_PPS)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 227#define IP3_27_24	FM(VI0_DATA3)			FM(HSCK1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 228#define IP3_31_28	FM(VI0_DATA4)			FM(HRTS1_N)		FM(RX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 229#define IP4_3_0		FM(VI0_DATA5)			FM(HCTS1_N)		FM(TX1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 230#define IP4_7_4		FM(VI0_DATA6)			FM(HTX1)		FM(CTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 231#define IP4_11_8	FM(VI0_DATA7)			FM(HRX1)		FM(RTS1_N)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 232#define IP4_15_12	FM(VI0_DATA8)			FM(HSCK2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 233#define IP4_19_16	FM(VI0_DATA9)			FM(HCTS2_N)		FM(PWM1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 234#define IP4_23_20	FM(VI0_DATA10)			FM(HRTS2_N)		FM(PWM2_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 235#define IP4_27_24	FM(VI0_DATA11)			FM(HTX2)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 236#define IP4_31_28	FM(VI0_FIELD)			FM(HRX2)		FM(PWM4_A)		FM(CS1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 237#define IP5_3_0		FM(VI1_CLK)			FM(MSIOF1_RXD)		F_(0, 0)		FM(CS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 238#define IP5_7_4		FM(VI1_CLKENB)			FM(MSIOF1_TXD)		F_(0, 0)		FM(D0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 239#define IP5_11_8	FM(VI1_HSYNC_N)			FM(MSIOF1_SCK)		F_(0, 0)		FM(D1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 240#define IP5_15_12	FM(VI1_VSYNC_N)			FM(MSIOF1_SYNC)		F_(0, 0)		FM(D2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 241#define IP5_19_16	FM(VI1_DATA0)			FM(MSIOF1_SS1)		F_(0, 0)		FM(D3)		FM(MMC_WP)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 242#define IP5_23_20	FM(VI1_DATA1)			FM(MSIOF1_SS2)		F_(0, 0)		FM(D4)		FM(MMC_CD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 243#define IP5_27_24	FM(VI1_DATA2)			FM(CANFD0_TX_B)		F_(0, 0)		FM(D5)		FM(MMC_DS)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 244#define IP5_31_28	FM(VI1_DATA3)			FM(CANFD0_RX_B)		F_(0, 0)		FM(D6)		FM(MMC_CMD)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 245#define IP6_3_0		FM(VI1_DATA4)			FM(CANFD_CLK_B)		F_(0, 0)		FM(D7)		FM(MMC_D0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 246#define IP6_7_4		FM(VI1_DATA5)			F_(0, 0)		F_(0, 0)		FM(D8)		FM(MMC_D1)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 247#define IP6_11_8	FM(VI1_DATA6)			F_(0, 0)		F_(0, 0)		FM(D9)		FM(MMC_D2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 248#define IP6_15_12	FM(VI1_DATA7)			F_(0, 0)		F_(0, 0)		FM(D10)		FM(MMC_D3)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 249#define IP6_19_16	FM(VI1_DATA8)			F_(0, 0)		F_(0, 0)		FM(D11)		FM(MMC_CLK)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 250#define IP6_23_20	FM(VI1_DATA9)			FM(TCLK1_A)		F_(0, 0)		FM(D12)		FM(MMC_D4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 251#define IP6_27_24	FM(VI1_DATA10)			FM(TCLK2_A)		F_(0, 0)		FM(D13)		FM(MMC_D5)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 252#define IP6_31_28	FM(VI1_DATA11)			FM(SCL4)		F_(0, 0)		FM(D14)		FM(MMC_D6)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 253#define IP7_3_0		FM(VI1_FIELD)			FM(SDA4)		F_(0, 0)		FM(D15)		FM(MMC_D7)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 254#define IP7_7_4		FM(SCL0)			F_(0, 0)		F_(0, 0)		FM(CLKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 255#define IP7_11_8	FM(SDA0)			F_(0, 0)		F_(0, 0)		FM(BS_N)	FM(SCK0)	FM(HSCK0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 256#define IP7_15_12	FM(SCL1)			F_(0, 0)		FM(TPU0TO2)		FM(RD_N)	FM(CTS0_N)	FM(HCTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 257#define IP7_19_16	FM(SDA1)			F_(0, 0)		FM(TPU0TO3)		FM(WE0_N)	FM(RTS0_N)	FM(HRTS0_N_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 258#define IP7_23_20	FM(SCL2)			F_(0, 0)		F_(0, 0)		FM(WE1_N)	FM(RX0)		FM(HRX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259#define IP7_27_24	FM(SDA2)			F_(0, 0)		F_(0, 0)		FM(EX_WAIT0)	FM(TX0)		FM(HTX0_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260#define IP7_31_28	FM(AVB_AVTP_MATCH)		FM(TPU0TO0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261#define IP8_3_0		FM(AVB_AVTP_CAPTURE)		FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262#define IP8_7_4		FM(CANFD0_TX_A)			FM(FXR_TXDA)		FM(PWM0_B)		FM(DU_DISP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263#define IP8_11_8	FM(CANFD0_RX_A)			FM(RXDA_EXTFXR)		FM(PWM1_B)		FM(DU_CDE)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264#define IP8_15_12	FM(CANFD1_TX)			FM(FXR_TXDB)		FM(PWM2_B)		FM(TCLK1_B)	FM(TX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265#define IP8_19_16	FM(CANFD1_RX)			FM(RXDB_EXTFXR)		FM(PWM3_B)		FM(TCLK2_B)	FM(RX1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266#define IP8_23_20	FM(CANFD_CLK_A)			FM(CLK_EXTFXR)		FM(PWM4_B)		FM(SPEEDIN_B)	FM(SCIF_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267#define IP8_27_24	FM(DIGRF_CLKIN)			FM(DIGRF_CLKEN_IN)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268#define IP8_31_28	FM(DIGRF_CLKOUT)		FM(DIGRF_CLKEN_OUT)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269#define IP9_3_0		FM(IRQ4)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA12)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270#define IP9_7_4		FM(IRQ5)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA13)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271#define IP9_11_8	FM(MSIOF0_RXD)			FM(DU_DR0)		F_(0, 0)		FM(VI0_DATA14)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272#define IP9_15_12	FM(MSIOF0_TXD)			FM(DU_DR1)		F_(0, 0)		FM(VI0_DATA15)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273#define IP9_19_16	FM(MSIOF0_SCK)			FM(DU_DG0)		F_(0, 0)		FM(VI0_DATA16)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274#define IP9_23_20	FM(MSIOF0_SYNC)			FM(DU_DG1)		F_(0, 0)		FM(VI0_DATA17)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275#define IP9_27_24	FM(MSIOF0_SS1)			FM(DU_DB0)		FM(TCLK3)		FM(VI0_DATA18)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276#define IP9_31_28	FM(MSIOF0_SS2)			FM(DU_DB1)		FM(TCLK4)		FM(VI0_DATA19)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277#define IP10_3_0	FM(SCL3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA20)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278#define IP10_7_4	FM(SDA3)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA21)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279#define IP10_11_8	FM(FSO_CFE_0_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA22)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280#define IP10_15_12	FM(FSO_CFE_1_N)			F_(0, 0)		F_(0, 0)		FM(VI0_DATA23)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281#define IP10_19_16	FM(FSO_TOE_N)			F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282
 283#define PINMUX_GPSR	\
 284\
 285				GPSR2_29 \
 286				GPSR2_28 \
 287		GPSR1_27	GPSR2_27 \
 288		GPSR1_26	GPSR2_26 \
 289		GPSR1_25	GPSR2_25 \
 290		GPSR1_24	GPSR2_24			GPSR4_24 \
 291		GPSR1_23	GPSR2_23			GPSR4_23 \
 292		GPSR1_22	GPSR2_22			GPSR4_22 \
 293GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
 294GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20 \
 295GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19 \
 296GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18 \
 297GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17 \
 298GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16 \
 299GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15 \
 300GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14 \
 301GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13 \
 302GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12 \
 303GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11 \
 304GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10 \
 305GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9 \
 306GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8 \
 307GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7 \
 308GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6 \
 309GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5 \
 310GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4 \
 311GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3 \
 312GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2 \
 313GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1 \
 314GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0
 315
 316#define PINMUX_IPSR	\
 317\
 318FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
 319FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
 320FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
 321FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
 322FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
 323FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
 324FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
 325FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
 326\
 327FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
 328FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
 329FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
 330FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12	FM(IP7_15_12)	IP7_15_12 \
 331FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
 332FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
 333FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
 334FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
 335\
 336FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0 \
 337FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4 \
 338FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8 \
 339FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12 \
 340FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16 \
 341FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20 \
 342FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24 \
 343FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28
 344
 345/* MOD_SEL0 */		/* 0 */			/* 1 */
 346#define MOD_SEL0_11	FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
 347#define MOD_SEL0_10	FM(SEL_GETHER_0)	FM(SEL_GETHER_1)
 348#define MOD_SEL0_9	FM(SEL_HSCIF0_0)	FM(SEL_HSCIF0_1)
 349#define MOD_SEL0_8	FM(SEL_PWM0_0)		FM(SEL_PWM0_1)
 350#define MOD_SEL0_7	FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
 351#define MOD_SEL0_6	FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
 352#define MOD_SEL0_5	FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
 353#define MOD_SEL0_4	FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
 354#define MOD_SEL0_2	FM(SEL_RSP_0)		FM(SEL_RSP_1)
 355#define MOD_SEL0_1	FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
 356#define MOD_SEL0_0	FM(SEL_TMU_0)		FM(SEL_TMU_1)
 357
 358#define PINMUX_MOD_SELS \
 359\
 360MOD_SEL0_11 \
 361MOD_SEL0_10 \
 362MOD_SEL0_9 \
 363MOD_SEL0_8 \
 364MOD_SEL0_7 \
 365MOD_SEL0_6 \
 366MOD_SEL0_5 \
 367MOD_SEL0_4 \
 368MOD_SEL0_2 \
 369MOD_SEL0_1 \
 370MOD_SEL0_0
 371
 372enum {
 373	PINMUX_RESERVED = 0,
 374
 375	PINMUX_DATA_BEGIN,
 376	GP_ALL(DATA),
 377	PINMUX_DATA_END,
 378
 379#define F_(x, y)
 380#define FM(x)   FN_##x,
 381	PINMUX_FUNCTION_BEGIN,
 382	GP_ALL(FN),
 383	PINMUX_GPSR
 384	PINMUX_IPSR
 385	PINMUX_MOD_SELS
 386	PINMUX_FUNCTION_END,
 387#undef F_
 388#undef FM
 389
 390#define F_(x, y)
 391#define FM(x)	x##_MARK,
 392	PINMUX_MARK_BEGIN,
 393	PINMUX_GPSR
 394	PINMUX_IPSR
 395	PINMUX_MOD_SELS
 396	PINMUX_MARK_END,
 397#undef F_
 398#undef FM
 399};
 400
 401static const u16 pinmux_data[] = {
 402	PINMUX_DATA_GP_ALL(),
 403
 404	PINMUX_SINGLE(AVB_RX_CTL),
 405	PINMUX_SINGLE(AVB_RXC),
 406	PINMUX_SINGLE(AVB_RD0),
 407	PINMUX_SINGLE(AVB_RD1),
 408	PINMUX_SINGLE(AVB_RD2),
 409	PINMUX_SINGLE(AVB_RD3),
 410	PINMUX_SINGLE(AVB_TX_CTL),
 411	PINMUX_SINGLE(AVB_TXC),
 412	PINMUX_SINGLE(AVB_TD0),
 413	PINMUX_SINGLE(AVB_TD1),
 414	PINMUX_SINGLE(AVB_TD2),
 415	PINMUX_SINGLE(AVB_TD3),
 416	PINMUX_SINGLE(AVB_TXCREFCLK),
 417	PINMUX_SINGLE(AVB_MDIO),
 418	PINMUX_SINGLE(AVB_MDC),
 419	PINMUX_SINGLE(AVB_MAGIC),
 420	PINMUX_SINGLE(AVB_PHY_INT),
 421	PINMUX_SINGLE(AVB_LINK),
 422
 423	PINMUX_SINGLE(GETHER_RX_CTL),
 424	PINMUX_SINGLE(GETHER_RXC),
 425	PINMUX_SINGLE(GETHER_RD0),
 426	PINMUX_SINGLE(GETHER_RD1),
 427	PINMUX_SINGLE(GETHER_RD2),
 428	PINMUX_SINGLE(GETHER_RD3),
 429	PINMUX_SINGLE(GETHER_TX_CTL),
 430	PINMUX_SINGLE(GETHER_TXC),
 431	PINMUX_SINGLE(GETHER_TD0),
 432	PINMUX_SINGLE(GETHER_TD1),
 433	PINMUX_SINGLE(GETHER_TD2),
 434	PINMUX_SINGLE(GETHER_TD3),
 435	PINMUX_SINGLE(GETHER_TXCREFCLK),
 436	PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
 437	PINMUX_SINGLE(GETHER_MDIO_A),
 438	PINMUX_SINGLE(GETHER_MDC_A),
 439	PINMUX_SINGLE(GETHER_MAGIC),
 440	PINMUX_SINGLE(GETHER_PHY_INT_A),
 441	PINMUX_SINGLE(GETHER_LINK_A),
 442
 443	PINMUX_SINGLE(QSPI0_SPCLK),
 444	PINMUX_SINGLE(QSPI0_MOSI_IO0),
 445	PINMUX_SINGLE(QSPI0_MISO_IO1),
 446	PINMUX_SINGLE(QSPI0_IO2),
 447	PINMUX_SINGLE(QSPI0_IO3),
 448	PINMUX_SINGLE(QSPI0_SSL),
 449	PINMUX_SINGLE(QSPI1_SPCLK),
 450	PINMUX_SINGLE(QSPI1_MOSI_IO0),
 451	PINMUX_SINGLE(QSPI1_MISO_IO1),
 452	PINMUX_SINGLE(QSPI1_IO2),
 453	PINMUX_SINGLE(QSPI1_IO3),
 454	PINMUX_SINGLE(QSPI1_SSL),
 455	PINMUX_SINGLE(RPC_RESET_N),
 456	PINMUX_SINGLE(RPC_WP_N),
 457	PINMUX_SINGLE(RPC_INT_N),
 458
 459	/* IPSR0 */
 460	PINMUX_IPSR_GPSR(IP0_3_0,	DU_DR2),
 461	PINMUX_IPSR_GPSR(IP0_3_0,	SCK4),
 462	PINMUX_IPSR_GPSR(IP0_3_0,	GETHER_RMII_CRS_DV),
 463	PINMUX_IPSR_GPSR(IP0_3_0,	A0),
 464
 465	PINMUX_IPSR_GPSR(IP0_7_4,	DU_DR3),
 466	PINMUX_IPSR_GPSR(IP0_7_4,	RX4),
 467	PINMUX_IPSR_GPSR(IP0_7_4,	GETHER_RMII_RX_ER),
 468	PINMUX_IPSR_GPSR(IP0_7_4,	A1),
 469
 470	PINMUX_IPSR_GPSR(IP0_11_8,	DU_DR4),
 471	PINMUX_IPSR_GPSR(IP0_11_8,	TX4),
 472	PINMUX_IPSR_GPSR(IP0_11_8,	GETHER_RMII_RXD0),
 473	PINMUX_IPSR_GPSR(IP0_11_8,	A2),
 474
 475	PINMUX_IPSR_GPSR(IP0_15_12,	DU_DR5),
 476	PINMUX_IPSR_GPSR(IP0_15_12,	CTS4_N),
 477	PINMUX_IPSR_GPSR(IP0_15_12,	GETHER_RMII_RXD1),
 478	PINMUX_IPSR_GPSR(IP0_15_12,	A3),
 479
 480	PINMUX_IPSR_GPSR(IP0_19_16,	DU_DR6),
 481	PINMUX_IPSR_GPSR(IP0_19_16,	RTS4_N),
 482	PINMUX_IPSR_GPSR(IP0_19_16,	GETHER_RMII_TXD_EN),
 483	PINMUX_IPSR_GPSR(IP0_19_16,	A4),
 484
 485	PINMUX_IPSR_GPSR(IP0_23_20,	DU_DR7),
 486	PINMUX_IPSR_GPSR(IP0_23_20,	GETHER_RMII_TXD0),
 487	PINMUX_IPSR_GPSR(IP0_23_20,	A5),
 488
 489	PINMUX_IPSR_GPSR(IP0_27_24,	DU_DG2),
 490	PINMUX_IPSR_GPSR(IP0_27_24,	GETHER_RMII_TXD1),
 491	PINMUX_IPSR_GPSR(IP0_27_24,	A6),
 492
 493	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DG3),
 494	PINMUX_IPSR_GPSR(IP0_31_28,	CPG_CPCKOUT),
 495	PINMUX_IPSR_GPSR(IP0_31_28,	GETHER_RMII_REFCLK),
 496	PINMUX_IPSR_GPSR(IP0_31_28,	A7),
 497	PINMUX_IPSR_GPSR(IP0_31_28,	PWMFSW0),
 498
 499	/* IPSR1 */
 500	PINMUX_IPSR_GPSR(IP1_3_0,	DU_DG4),
 501	PINMUX_IPSR_GPSR(IP1_3_0,	SCL5),
 502	PINMUX_IPSR_GPSR(IP1_3_0,	A8),
 503
 504	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DG5),
 505	PINMUX_IPSR_GPSR(IP1_7_4,	SDA5),
 506	PINMUX_IPSR_MSEL(IP1_7_4,	GETHER_MDC_B, SEL_GETHER_1),
 507	PINMUX_IPSR_GPSR(IP1_7_4,	A9),
 508
 509	PINMUX_IPSR_GPSR(IP1_11_8,	DU_DG6),
 510	PINMUX_IPSR_MSEL(IP1_11_8,	SCIF_CLK_A, SEL_HSCIF0_0),
 511	PINMUX_IPSR_MSEL(IP1_11_8,	GETHER_MDIO_B, SEL_GETHER_1),
 512	PINMUX_IPSR_GPSR(IP1_11_8,	A10),
 513
 514	PINMUX_IPSR_GPSR(IP1_15_12,	DU_DG7),
 515	PINMUX_IPSR_MSEL(IP1_15_12,	HRX0_A, SEL_HSCIF0_0),
 516	PINMUX_IPSR_GPSR(IP1_15_12,	A11),
 517
 518	PINMUX_IPSR_GPSR(IP1_19_16,	DU_DB2),
 519	PINMUX_IPSR_MSEL(IP1_19_16,	HSCK0_A, SEL_HSCIF0_0),
 520	PINMUX_IPSR_GPSR(IP1_19_16,	A12),
 521	PINMUX_IPSR_GPSR(IP1_19_16,	IRQ1),
 522
 523	PINMUX_IPSR_GPSR(IP1_23_20,	DU_DB3),
 524	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_A, SEL_HSCIF0_0),
 525	PINMUX_IPSR_GPSR(IP1_23_20,	A13),
 526	PINMUX_IPSR_GPSR(IP1_23_20,	IRQ2),
 527
 528	PINMUX_IPSR_GPSR(IP1_27_24,	DU_DB4),
 529	PINMUX_IPSR_MSEL(IP1_27_24,	HCTS0_N_A, SEL_HSCIF0_0),
 530	PINMUX_IPSR_GPSR(IP1_27_24,	A14),
 531	PINMUX_IPSR_GPSR(IP1_27_24,	IRQ3),
 532
 533	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB5),
 534	PINMUX_IPSR_MSEL(IP1_31_28,	HTX0_A, SEL_HSCIF0_0),
 535	PINMUX_IPSR_MSEL(IP1_31_28,	PWM0_A, SEL_PWM0_0),
 536	PINMUX_IPSR_GPSR(IP1_31_28,	A15),
 537
 538	/* IPSR2 */
 539	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB6),
 540	PINMUX_IPSR_GPSR(IP2_3_0,	MSIOF3_RXD),
 541	PINMUX_IPSR_GPSR(IP2_3_0,	A16),
 542
 543	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB7),
 544	PINMUX_IPSR_GPSR(IP2_7_4,	MSIOF3_TXD),
 545	PINMUX_IPSR_GPSR(IP2_7_4,	A17),
 546
 547	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DOTCLKOUT),
 548	PINMUX_IPSR_GPSR(IP2_11_8,	MSIOF3_SS1),
 549	PINMUX_IPSR_MSEL(IP2_11_8,	GETHER_LINK_B, SEL_GETHER_1),
 550	PINMUX_IPSR_GPSR(IP2_11_8,	A18),
 551
 552	PINMUX_IPSR_GPSR(IP2_15_12,	DU_EXHSYNC_DU_HSYNC),
 553	PINMUX_IPSR_GPSR(IP2_15_12,	MSIOF3_SS2),
 554	PINMUX_IPSR_MSEL(IP2_15_12,	GETHER_PHY_INT_B, SEL_GETHER_1),
 555	PINMUX_IPSR_GPSR(IP2_15_12,	A19),
 556	PINMUX_IPSR_GPSR(IP2_15_12,	FXR_TXENA_N),
 557
 558	PINMUX_IPSR_GPSR(IP2_19_16,	DU_EXVSYNC_DU_VSYNC),
 559	PINMUX_IPSR_GPSR(IP2_19_16,	MSIOF3_SCK),
 560	PINMUX_IPSR_GPSR(IP2_19_16,	FXR_TXENB_N),
 561
 562	PINMUX_IPSR_GPSR(IP2_23_20,	DU_EXODDF_DU_ODDF_DISP_CDE),
 563	PINMUX_IPSR_GPSR(IP2_23_20,	MSIOF3_SYNC),
 564
 565	PINMUX_IPSR_GPSR(IP2_27_24,	IRQ0),
 566
 567	PINMUX_IPSR_GPSR(IP2_31_28,	VI0_CLK),
 568	PINMUX_IPSR_GPSR(IP2_31_28,	MSIOF2_SCK),
 569	PINMUX_IPSR_GPSR(IP2_31_28,	SCK3),
 570	PINMUX_IPSR_GPSR(IP2_31_28,	HSCK3),
 571
 572	/* IPSR3 */
 573	PINMUX_IPSR_GPSR(IP3_3_0,	VI0_CLKENB),
 574	PINMUX_IPSR_GPSR(IP3_3_0,	MSIOF2_RXD),
 575	PINMUX_IPSR_GPSR(IP3_3_0,	RX3),
 576	PINMUX_IPSR_GPSR(IP3_3_0,	RD_WR_N),
 577	PINMUX_IPSR_GPSR(IP3_3_0,	HCTS3_N),
 578
 579	PINMUX_IPSR_GPSR(IP3_7_4,	VI0_HSYNC_N),
 580	PINMUX_IPSR_GPSR(IP3_7_4,	MSIOF2_TXD),
 581	PINMUX_IPSR_GPSR(IP3_7_4,	TX3),
 582	PINMUX_IPSR_GPSR(IP3_7_4,	HRTS3_N),
 583
 584	PINMUX_IPSR_GPSR(IP3_11_8,	VI0_VSYNC_N),
 585	PINMUX_IPSR_GPSR(IP3_11_8,	MSIOF2_SYNC),
 586	PINMUX_IPSR_GPSR(IP3_11_8,	CTS3_N),
 587	PINMUX_IPSR_GPSR(IP3_11_8,	HTX3),
 588
 589	PINMUX_IPSR_GPSR(IP3_15_12,	VI0_DATA0),
 590	PINMUX_IPSR_GPSR(IP3_15_12,	MSIOF2_SS1),
 591	PINMUX_IPSR_GPSR(IP3_15_12,	RTS3_N),
 592	PINMUX_IPSR_GPSR(IP3_15_12,	HRX3),
 593
 594	PINMUX_IPSR_GPSR(IP3_19_16,	VI0_DATA1),
 595	PINMUX_IPSR_GPSR(IP3_19_16,	MSIOF2_SS2),
 596	PINMUX_IPSR_GPSR(IP3_19_16,	SCK1),
 597	PINMUX_IPSR_MSEL(IP3_19_16,	SPEEDIN_A, SEL_RSP_0),
 598
 599	PINMUX_IPSR_GPSR(IP3_23_20,	VI0_DATA2),
 600	PINMUX_IPSR_GPSR(IP3_23_20,	AVB_AVTP_PPS),
 601
 602	PINMUX_IPSR_GPSR(IP3_27_24,	VI0_DATA3),
 603	PINMUX_IPSR_GPSR(IP3_27_24,	HSCK1),
 604
 605	PINMUX_IPSR_GPSR(IP3_31_28,	VI0_DATA4),
 606	PINMUX_IPSR_GPSR(IP3_31_28,	HRTS1_N),
 607	PINMUX_IPSR_MSEL(IP3_31_28,	RX1_A, SEL_SCIF1_0),
 608
 609	/* IPSR4 */
 610	PINMUX_IPSR_GPSR(IP4_3_0,	VI0_DATA5),
 611	PINMUX_IPSR_GPSR(IP4_3_0,	HCTS1_N),
 612	PINMUX_IPSR_MSEL(IP4_3_0,	TX1_A, SEL_SCIF1_0),
 613
 614	PINMUX_IPSR_GPSR(IP4_7_4,	VI0_DATA6),
 615	PINMUX_IPSR_GPSR(IP4_7_4,	HTX1),
 616	PINMUX_IPSR_GPSR(IP4_7_4,	CTS1_N),
 617
 618	PINMUX_IPSR_GPSR(IP4_11_8,	VI0_DATA7),
 619	PINMUX_IPSR_GPSR(IP4_11_8,	HRX1),
 620	PINMUX_IPSR_GPSR(IP4_11_8,	RTS1_N),
 621
 622	PINMUX_IPSR_GPSR(IP4_15_12,	VI0_DATA8),
 623	PINMUX_IPSR_GPSR(IP4_15_12,	HSCK2),
 624
 625	PINMUX_IPSR_GPSR(IP4_19_16,	VI0_DATA9),
 626	PINMUX_IPSR_GPSR(IP4_19_16,	HCTS2_N),
 627	PINMUX_IPSR_MSEL(IP4_19_16,	PWM1_A, SEL_PWM1_0),
 628
 629	PINMUX_IPSR_GPSR(IP4_23_20,	VI0_DATA10),
 630	PINMUX_IPSR_GPSR(IP4_23_20,	HRTS2_N),
 631	PINMUX_IPSR_MSEL(IP4_23_20,	PWM2_A, SEL_PWM2_0),
 632
 633	PINMUX_IPSR_GPSR(IP4_27_24,	VI0_DATA11),
 634	PINMUX_IPSR_GPSR(IP4_27_24,	HTX2),
 635	PINMUX_IPSR_MSEL(IP4_27_24,	PWM3_A, SEL_PWM3_0),
 636
 637	PINMUX_IPSR_GPSR(IP4_31_28,	VI0_FIELD),
 638	PINMUX_IPSR_GPSR(IP4_31_28,	HRX2),
 639	PINMUX_IPSR_MSEL(IP4_31_28,	PWM4_A, SEL_PWM4_0),
 640	PINMUX_IPSR_GPSR(IP4_31_28,	CS1_N),
 641
 642	/* IPSR5 */
 643	PINMUX_IPSR_GPSR(IP5_3_0,	VI1_CLK),
 644	PINMUX_IPSR_GPSR(IP5_3_0,	MSIOF1_RXD),
 645	PINMUX_IPSR_GPSR(IP5_3_0,	CS0_N),
 646
 647	PINMUX_IPSR_GPSR(IP5_7_4,	VI1_CLKENB),
 648	PINMUX_IPSR_GPSR(IP5_7_4,	MSIOF1_TXD),
 649	PINMUX_IPSR_GPSR(IP5_7_4,	D0),
 650
 651	PINMUX_IPSR_GPSR(IP5_11_8,	VI1_HSYNC_N),
 652	PINMUX_IPSR_GPSR(IP5_11_8,	MSIOF1_SCK),
 653	PINMUX_IPSR_GPSR(IP5_11_8,	D1),
 654
 655	PINMUX_IPSR_GPSR(IP5_15_12,	VI1_VSYNC_N),
 656	PINMUX_IPSR_GPSR(IP5_15_12,	MSIOF1_SYNC),
 657	PINMUX_IPSR_GPSR(IP5_15_12,	D2),
 658
 659	PINMUX_IPSR_GPSR(IP5_19_16,	VI1_DATA0),
 660	PINMUX_IPSR_GPSR(IP5_19_16,	MSIOF1_SS1),
 661	PINMUX_IPSR_GPSR(IP5_19_16,	D3),
 662	PINMUX_IPSR_GPSR(IP5_19_16,	MMC_WP),
 663
 664	PINMUX_IPSR_GPSR(IP5_23_20,	VI1_DATA1),
 665	PINMUX_IPSR_GPSR(IP5_23_20,	MSIOF1_SS2),
 666	PINMUX_IPSR_GPSR(IP5_23_20,	D4),
 667	PINMUX_IPSR_GPSR(IP5_23_20,	MMC_CD),
 668
 669	PINMUX_IPSR_GPSR(IP5_27_24,	VI1_DATA2),
 670	PINMUX_IPSR_MSEL(IP5_27_24,	CANFD0_TX_B, SEL_CANFD0_1),
 671	PINMUX_IPSR_GPSR(IP5_27_24,	D5),
 672	PINMUX_IPSR_GPSR(IP5_27_24,	MMC_DS),
 673
 674	PINMUX_IPSR_GPSR(IP5_31_28,	VI1_DATA3),
 675	PINMUX_IPSR_MSEL(IP5_31_28,	CANFD0_RX_B, SEL_CANFD0_1),
 676	PINMUX_IPSR_GPSR(IP5_31_28,	D6),
 677	PINMUX_IPSR_GPSR(IP5_31_28,	MMC_CMD),
 678
 679	/* IPSR6 */
 680	PINMUX_IPSR_GPSR(IP6_3_0,	VI1_DATA4),
 681	PINMUX_IPSR_MSEL(IP6_3_0,	CANFD_CLK_B, SEL_CANFD0_1),
 682	PINMUX_IPSR_GPSR(IP6_3_0,	D7),
 683	PINMUX_IPSR_GPSR(IP6_3_0,	MMC_D0),
 684
 685	PINMUX_IPSR_GPSR(IP6_7_4,	VI1_DATA5),
 686	PINMUX_IPSR_GPSR(IP6_7_4,	D8),
 687	PINMUX_IPSR_GPSR(IP6_7_4,	MMC_D1),
 688
 689	PINMUX_IPSR_GPSR(IP6_11_8,	VI1_DATA6),
 690	PINMUX_IPSR_GPSR(IP6_11_8,	D9),
 691	PINMUX_IPSR_GPSR(IP6_11_8,	MMC_D2),
 692
 693	PINMUX_IPSR_GPSR(IP6_15_12,	VI1_DATA7),
 694	PINMUX_IPSR_GPSR(IP6_15_12,	D10),
 695	PINMUX_IPSR_GPSR(IP6_15_12,	MMC_D3),
 696
 697	PINMUX_IPSR_GPSR(IP6_19_16,	VI1_DATA8),
 698	PINMUX_IPSR_GPSR(IP6_19_16,	D11),
 699	PINMUX_IPSR_GPSR(IP6_19_16,	MMC_CLK),
 700
 701	PINMUX_IPSR_GPSR(IP6_23_20,	VI1_DATA9),
 702	PINMUX_IPSR_MSEL(IP6_23_20,	TCLK1_A, SEL_TMU_0),
 703	PINMUX_IPSR_GPSR(IP6_23_20,	D12),
 704	PINMUX_IPSR_GPSR(IP6_23_20,	MMC_D4),
 705
 706	PINMUX_IPSR_GPSR(IP6_27_24,	VI1_DATA10),
 707	PINMUX_IPSR_MSEL(IP6_27_24,	TCLK2_A, SEL_TMU_0),
 708	PINMUX_IPSR_GPSR(IP6_27_24,	D13),
 709	PINMUX_IPSR_GPSR(IP6_27_24,	MMC_D5),
 710
 711	PINMUX_IPSR_GPSR(IP6_31_28,	VI1_DATA11),
 712	PINMUX_IPSR_GPSR(IP6_31_28,	SCL4),
 713	PINMUX_IPSR_GPSR(IP6_31_28,	D14),
 714	PINMUX_IPSR_GPSR(IP6_31_28,	MMC_D6),
 715
 716	/* IPSR7 */
 717	PINMUX_IPSR_GPSR(IP7_3_0,	VI1_FIELD),
 718	PINMUX_IPSR_GPSR(IP7_3_0,	SDA4),
 719	PINMUX_IPSR_GPSR(IP7_3_0,	D15),
 720	PINMUX_IPSR_GPSR(IP7_3_0,	MMC_D7),
 721
 722	PINMUX_IPSR_GPSR(IP7_7_4,	SCL0),
 723	PINMUX_IPSR_GPSR(IP7_7_4,	CLKOUT),
 724
 725	PINMUX_IPSR_GPSR(IP7_11_8,	SDA0),
 726	PINMUX_IPSR_GPSR(IP7_11_8,	BS_N),
 727	PINMUX_IPSR_GPSR(IP7_11_8,	SCK0),
 728	PINMUX_IPSR_MSEL(IP7_11_8,	HSCK0_B, SEL_HSCIF0_1),
 729
 730	PINMUX_IPSR_GPSR(IP7_15_12,	SCL1),
 731	PINMUX_IPSR_GPSR(IP7_15_12,	TPU0TO2),
 732	PINMUX_IPSR_GPSR(IP7_15_12,	RD_N),
 733	PINMUX_IPSR_GPSR(IP7_15_12,	CTS0_N),
 734	PINMUX_IPSR_GPSR(IP7_15_12,	HCTS0_N_B),
 735
 736	PINMUX_IPSR_GPSR(IP7_19_16,	SDA1),
 737	PINMUX_IPSR_GPSR(IP7_19_16,	TPU0TO3),
 738	PINMUX_IPSR_GPSR(IP7_19_16,	WE0_N),
 739	PINMUX_IPSR_GPSR(IP7_19_16,	RTS0_N),
 740	PINMUX_IPSR_MSEL(IP1_23_20,	HRTS0_N_B, SEL_HSCIF0_1),
 741
 742	PINMUX_IPSR_GPSR(IP7_23_20,	SCL2),
 743	PINMUX_IPSR_GPSR(IP7_23_20,	WE1_N),
 744	PINMUX_IPSR_GPSR(IP7_23_20,	RX0),
 745	PINMUX_IPSR_MSEL(IP7_23_20,	HRX0_B, SEL_HSCIF0_1),
 746
 747	PINMUX_IPSR_GPSR(IP7_27_24,	SDA2),
 748	PINMUX_IPSR_GPSR(IP7_27_24,	EX_WAIT0),
 749	PINMUX_IPSR_GPSR(IP7_27_24,	TX0),
 750	PINMUX_IPSR_MSEL(IP7_27_24,	HTX0_B, SEL_HSCIF0_1),
 751
 752	PINMUX_IPSR_GPSR(IP7_31_28,	AVB_AVTP_MATCH),
 753	PINMUX_IPSR_GPSR(IP7_31_28,	TPU0TO0),
 754
 755	/* IPSR8 */
 756	PINMUX_IPSR_GPSR(IP8_3_0,	AVB_AVTP_CAPTURE),
 757	PINMUX_IPSR_GPSR(IP8_3_0,	TPU0TO1),
 758
 759	PINMUX_IPSR_MSEL(IP8_7_4,	CANFD0_TX_A, SEL_CANFD0_0),
 760	PINMUX_IPSR_GPSR(IP8_7_4,	FXR_TXDA),
 761	PINMUX_IPSR_MSEL(IP8_7_4,	PWM0_B, SEL_PWM0_1),
 762	PINMUX_IPSR_GPSR(IP8_7_4,	DU_DISP),
 763
 764	PINMUX_IPSR_MSEL(IP8_11_8,	CANFD0_RX_A, SEL_CANFD0_0),
 765	PINMUX_IPSR_GPSR(IP8_11_8,	RXDA_EXTFXR),
 766	PINMUX_IPSR_MSEL(IP8_11_8,	PWM1_B, SEL_PWM1_1),
 767	PINMUX_IPSR_GPSR(IP8_11_8,	DU_CDE),
 768
 769	PINMUX_IPSR_GPSR(IP8_15_12,	CANFD1_TX),
 770	PINMUX_IPSR_GPSR(IP8_15_12,	FXR_TXDB),
 771	PINMUX_IPSR_MSEL(IP8_15_12,	PWM2_B, SEL_PWM2_1),
 772	PINMUX_IPSR_MSEL(IP8_15_12,	TCLK1_B, SEL_TMU_1),
 773	PINMUX_IPSR_MSEL(IP8_15_12,	TX1_B, SEL_SCIF1_1),
 774
 775	PINMUX_IPSR_GPSR(IP8_19_16,	CANFD1_RX),
 776	PINMUX_IPSR_GPSR(IP8_19_16,	RXDB_EXTFXR),
 777	PINMUX_IPSR_MSEL(IP8_19_16,	PWM3_B, SEL_PWM3_1),
 778	PINMUX_IPSR_MSEL(IP8_19_16,	TCLK2_B, SEL_TMU_1),
 779	PINMUX_IPSR_MSEL(IP8_19_16,	RX1_B, SEL_SCIF1_1),
 780
 781	PINMUX_IPSR_MSEL(IP8_23_20,	CANFD_CLK_A, SEL_CANFD0_0),
 782	PINMUX_IPSR_GPSR(IP8_23_20,	CLK_EXTFXR),
 783	PINMUX_IPSR_MSEL(IP8_23_20,	PWM4_B, SEL_PWM4_1),
 784	PINMUX_IPSR_MSEL(IP8_23_20,	SPEEDIN_B, SEL_RSP_1),
 785	PINMUX_IPSR_MSEL(IP8_23_20,	SCIF_CLK_B, SEL_HSCIF0_1),
 786
 787	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKIN),
 788	PINMUX_IPSR_GPSR(IP8_27_24,	DIGRF_CLKEN_IN),
 789
 790	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKOUT),
 791	PINMUX_IPSR_GPSR(IP8_31_28,	DIGRF_CLKEN_OUT),
 792
 793	/* IPSR9 */
 794	PINMUX_IPSR_GPSR(IP9_3_0,	IRQ4),
 795	PINMUX_IPSR_GPSR(IP9_3_0,	VI0_DATA12),
 796
 797	PINMUX_IPSR_GPSR(IP9_7_4,	IRQ5),
 798	PINMUX_IPSR_GPSR(IP9_7_4,	VI0_DATA13),
 799
 800	PINMUX_IPSR_GPSR(IP9_11_8,	MSIOF0_RXD),
 801	PINMUX_IPSR_GPSR(IP9_11_8,	DU_DR0),
 802	PINMUX_IPSR_GPSR(IP9_11_8,	VI0_DATA14),
 803
 804	PINMUX_IPSR_GPSR(IP9_15_12,	MSIOF0_TXD),
 805	PINMUX_IPSR_GPSR(IP9_15_12,	DU_DR1),
 806	PINMUX_IPSR_GPSR(IP9_15_12,	VI0_DATA15),
 807
 808	PINMUX_IPSR_GPSR(IP9_19_16,	MSIOF0_SCK),
 809	PINMUX_IPSR_GPSR(IP9_19_16,	DU_DG0),
 810	PINMUX_IPSR_GPSR(IP9_19_16,	VI0_DATA16),
 811
 812	PINMUX_IPSR_GPSR(IP9_23_20,	MSIOF0_SYNC),
 813	PINMUX_IPSR_GPSR(IP9_23_20,	DU_DG1),
 814	PINMUX_IPSR_GPSR(IP9_23_20,	VI0_DATA17),
 815
 816	PINMUX_IPSR_GPSR(IP9_27_24,	MSIOF0_SS1),
 817	PINMUX_IPSR_GPSR(IP9_27_24,	DU_DB0),
 818	PINMUX_IPSR_GPSR(IP9_27_24,	TCLK3),
 819	PINMUX_IPSR_GPSR(IP9_27_24,	VI0_DATA18),
 820
 821	PINMUX_IPSR_GPSR(IP9_31_28,	MSIOF0_SS2),
 822	PINMUX_IPSR_GPSR(IP9_31_28,	DU_DB1),
 823	PINMUX_IPSR_GPSR(IP9_31_28,	TCLK4),
 824	PINMUX_IPSR_GPSR(IP9_31_28,	VI0_DATA19),
 825
 826	/* IPSR10 */
 827	PINMUX_IPSR_GPSR(IP10_3_0,	SCL3),
 828	PINMUX_IPSR_GPSR(IP10_3_0,	VI0_DATA20),
 829
 830	PINMUX_IPSR_GPSR(IP10_7_4,	SDA3),
 831	PINMUX_IPSR_GPSR(IP10_7_4,	VI0_DATA21),
 832
 833	PINMUX_IPSR_GPSR(IP10_11_8,	FSO_CFE_0_N),
 834	PINMUX_IPSR_GPSR(IP10_11_8,	VI0_DATA22),
 835
 836	PINMUX_IPSR_GPSR(IP10_15_12,	FSO_CFE_1_N),
 837	PINMUX_IPSR_GPSR(IP10_15_12,	VI0_DATA23),
 838
 839	PINMUX_IPSR_GPSR(IP10_19_16,	FSO_TOE_N),
 840};
 841
 842/*
 843 * Pins not associated with a GPIO port.
 844 */
 845enum {
 846	GP_ASSIGN_LAST(),
 847	NOGP_ALL(),
 848};
 849
 850static const struct sh_pfc_pin pinmux_pins[] = {
 851	PINMUX_GPIO_GP_ALL(),
 852	PINMUX_NOGP_ALL(),
 853};
 854
 855/* - AVB -------------------------------------------------------------------- */
 856static const unsigned int avb_link_pins[] = {
 857	/* AVB_LINK */
 858	RCAR_GP_PIN(1, 18),
 859};
 860static const unsigned int avb_link_mux[] = {
 861	AVB_LINK_MARK,
 862};
 863static const unsigned int avb_magic_pins[] = {
 864	/* AVB_MAGIC */
 865	RCAR_GP_PIN(1, 16),
 866};
 867static const unsigned int avb_magic_mux[] = {
 868	AVB_MAGIC_MARK,
 869};
 870static const unsigned int avb_phy_int_pins[] = {
 871	/* AVB_PHY_INT */
 872	RCAR_GP_PIN(1, 17),
 873};
 874static const unsigned int avb_phy_int_mux[] = {
 875	AVB_PHY_INT_MARK,
 876};
 877static const unsigned int avb_mdio_pins[] = {
 878	/* AVB_MDC, AVB_MDIO */
 879	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
 880};
 881static const unsigned int avb_mdio_mux[] = {
 882	AVB_MDC_MARK, AVB_MDIO_MARK,
 883};
 884static const unsigned int avb_rgmii_pins[] = {
 885	/*
 886	 * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
 887	 * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
 888	 */
 889	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
 890	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
 891	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
 892	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
 893	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
 894	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
 895};
 896static const unsigned int avb_rgmii_mux[] = {
 897	AVB_TX_CTL_MARK, AVB_TXC_MARK,
 898	AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
 899	AVB_RX_CTL_MARK, AVB_RXC_MARK,
 900	AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
 901};
 902static const unsigned int avb_txcrefclk_pins[] = {
 903	/* AVB_TXCREFCLK */
 904	RCAR_GP_PIN(1, 13),
 905};
 906static const unsigned int avb_txcrefclk_mux[] = {
 907	AVB_TXCREFCLK_MARK,
 908};
 909static const unsigned int avb_avtp_pps_pins[] = {
 910	/* AVB_AVTP_PPS */
 911	RCAR_GP_PIN(2, 6),
 912};
 913static const unsigned int avb_avtp_pps_mux[] = {
 914	AVB_AVTP_PPS_MARK,
 915};
 916static const unsigned int avb_avtp_capture_pins[] = {
 917	/* AVB_AVTP_CAPTURE */
 918	RCAR_GP_PIN(1, 20),
 919};
 920static const unsigned int avb_avtp_capture_mux[] = {
 921	AVB_AVTP_CAPTURE_MARK,
 922};
 923static const unsigned int avb_avtp_match_pins[] = {
 924	/* AVB_AVTP_MATCH */
 925	RCAR_GP_PIN(1, 19),
 926};
 927static const unsigned int avb_avtp_match_mux[] = {
 928	AVB_AVTP_MATCH_MARK,
 929};
 930
 931/* - CANFD0 ----------------------------------------------------------------- */
 932static const unsigned int canfd0_data_a_pins[] = {
 933	/* CANFD0_TX, CANFD0_RX */
 934	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
 935};
 936static const unsigned int canfd0_data_a_mux[] = {
 937	CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
 938};
 939static const unsigned int canfd0_data_b_pins[] = {
 940	/* CANFD0_TX, CANFD0_RX */
 941	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
 942};
 943static const unsigned int canfd0_data_b_mux[] = {
 944	CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
 945};
 946
 947/* - CANFD1 ----------------------------------------------------------------- */
 948static const unsigned int canfd1_data_pins[] = {
 949	/* CANFD1_TX, CANFD1_RX */
 950	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
 951};
 952static const unsigned int canfd1_data_mux[] = {
 953	CANFD1_TX_MARK, CANFD1_RX_MARK,
 954};
 955
 956/* - CANFD Clock ------------------------------------------------------------ */
 957static const unsigned int canfd_clk_a_pins[] = {
 958	/* CANFD_CLK */
 959	RCAR_GP_PIN(1, 25),
 960};
 961static const unsigned int canfd_clk_a_mux[] = {
 962	CANFD_CLK_A_MARK,
 963};
 964static const unsigned int canfd_clk_b_pins[] = {
 965	/* CANFD_CLK */
 966	RCAR_GP_PIN(3, 8),
 967};
 968static const unsigned int canfd_clk_b_mux[] = {
 969	CANFD_CLK_B_MARK,
 970};
 971
 972/* - DU --------------------------------------------------------------------- */
 973static const unsigned int du_rgb666_pins[] = {
 974	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
 975	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 976	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 977	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
 978	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 979	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
 980	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
 981};
 982static const unsigned int du_rgb666_mux[] = {
 983	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
 984	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
 985	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
 986	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
 987	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
 988	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
 989};
 990static const unsigned int du_rgb888_pins[] = {
 991	/* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
 992	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
 993	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 994	RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
 995	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
 996	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
 997	RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
 998	RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
 999	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
1000	RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1001};
1002static const unsigned int du_rgb888_mux[] = {
1003	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1004	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1005	DU_DR1_MARK, DU_DR0_MARK,
1006	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1007	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1008	DU_DG1_MARK, DU_DG0_MARK,
1009	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1010	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1011	DU_DB1_MARK, DU_DB0_MARK,
1012};
1013static const unsigned int du_clk_out_pins[] = {
1014	/* DU_DOTCLKOUT */
1015	RCAR_GP_PIN(0, 18),
1016};
1017static const unsigned int du_clk_out_mux[] = {
1018	DU_DOTCLKOUT_MARK,
1019};
1020static const unsigned int du_sync_pins[] = {
1021	/* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1022	RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1023};
1024static const unsigned int du_sync_mux[] = {
1025	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1026};
1027static const unsigned int du_oddf_pins[] = {
1028	/* DU_EXODDF/DU_ODDF/DISP/CDE */
1029	RCAR_GP_PIN(0, 21),
1030};
1031static const unsigned int du_oddf_mux[] = {
1032	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1033};
1034static const unsigned int du_cde_pins[] = {
1035	/* DU_CDE */
1036	RCAR_GP_PIN(1, 22),
1037};
1038static const unsigned int du_cde_mux[] = {
1039	DU_CDE_MARK,
1040};
1041static const unsigned int du_disp_pins[] = {
1042	/* DU_DISP */
1043	RCAR_GP_PIN(1, 21),
1044};
1045static const unsigned int du_disp_mux[] = {
1046	DU_DISP_MARK,
1047};
1048
1049/* - GETHER ----------------------------------------------------------------- */
1050static const unsigned int gether_link_a_pins[] = {
1051	/* GETHER_LINK */
1052	RCAR_GP_PIN(4, 24),
1053};
1054static const unsigned int gether_link_a_mux[] = {
1055	GETHER_LINK_A_MARK,
1056};
1057static const unsigned int gether_phy_int_a_pins[] = {
1058	/* GETHER_PHY_INT */
1059	RCAR_GP_PIN(4, 23),
1060};
1061static const unsigned int gether_phy_int_a_mux[] = {
1062	GETHER_PHY_INT_A_MARK,
1063};
1064static const unsigned int gether_mdio_a_pins[] = {
1065	/* GETHER_MDC, GETHER_MDIO */
1066	RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1067};
1068static const unsigned int gether_mdio_a_mux[] = {
1069	GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1070};
1071static const unsigned int gether_link_b_pins[] = {
1072	/* GETHER_LINK */
1073	RCAR_GP_PIN(0, 18),
1074};
1075static const unsigned int gether_link_b_mux[] = {
1076	GETHER_LINK_B_MARK,
1077};
1078static const unsigned int gether_phy_int_b_pins[] = {
1079	/* GETHER_PHY_INT */
1080	RCAR_GP_PIN(0, 19),
1081};
1082static const unsigned int gether_phy_int_b_mux[] = {
1083	GETHER_PHY_INT_B_MARK,
1084};
1085static const unsigned int gether_mdio_b_mux[] = {
1086	GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1087};
1088static const unsigned int gether_mdio_b_pins[] = {
1089	/* GETHER_MDC, GETHER_MDIO */
1090	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1091};
1092static const unsigned int gether_magic_pins[] = {
1093	/* GETHER_MAGIC */
1094	RCAR_GP_PIN(4, 22),
1095};
1096static const unsigned int gether_magic_mux[] = {
1097	GETHER_MAGIC_MARK,
1098};
1099static const unsigned int gether_rgmii_pins[] = {
1100	/*
1101	 * GETHER_TX_CTL, GETHER_TXC,
1102	 * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1103	 * GETHER_RX_CTL, GETHER_RXC,
1104	 * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1105	 */
1106	RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1107	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1108	RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1109	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1110	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1111	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1112};
1113static const unsigned int gether_rgmii_mux[] = {
1114	GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1115	GETHER_TD0_MARK, GETHER_TD1_MARK,
1116	GETHER_TD2_MARK, GETHER_TD3_MARK,
1117	GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1118	GETHER_RD0_MARK, AVB_RD1_MARK,
1119	GETHER_RD2_MARK, AVB_RD3_MARK,
1120};
1121static const unsigned int gether_txcrefclk_pins[] = {
1122	/* GETHER_TXCREFCLK */
1123	RCAR_GP_PIN(4, 18),
1124};
1125static const unsigned int gether_txcrefclk_mux[] = {
1126	GETHER_TXCREFCLK_MARK,
1127};
1128static const unsigned int gether_txcrefclk_mega_pins[] = {
1129	/* GETHER_TXCREFCLK_MEGA */
1130	RCAR_GP_PIN(4, 19),
1131};
1132static const unsigned int gether_txcrefclk_mega_mux[] = {
1133	GETHER_TXCREFCLK_MEGA_MARK,
1134};
1135static const unsigned int gether_rmii_pins[] = {
1136	/*
1137	 * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1138	 * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1139	 * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1140	 * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1141	 */
1142	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1143	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1144	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1145	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1146};
1147static const unsigned int gether_rmii_mux[] = {
1148	GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1149	GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1150	GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1151	GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1152};
1153
1154/* - HSCIF0 ----------------------------------------------------------------- */
1155static const unsigned int hscif0_data_a_pins[] = {
1156	/* HRX0, HTX0 */
1157	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1158};
1159static const unsigned int hscif0_data_a_mux[] = {
1160	HRX0_A_MARK, HTX0_A_MARK,
1161};
1162static const unsigned int hscif0_clk_a_pins[] = {
1163	/* HSCK0 */
1164	RCAR_GP_PIN(0, 12),
1165};
1166static const unsigned int hscif0_clk_a_mux[] = {
1167	HSCK0_A_MARK,
1168};
1169static const unsigned int hscif0_ctrl_a_pins[] = {
1170	/* HRTS0#, HCTS0# */
1171	RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1172};
1173static const unsigned int hscif0_ctrl_a_mux[] = {
1174	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1175};
1176static const unsigned int hscif0_data_b_pins[] = {
1177	/* HRX0, HTX0 */
1178	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1179};
1180static const unsigned int hscif0_data_b_mux[] = {
1181	HRX0_B_MARK, HTX0_B_MARK,
1182};
1183static const unsigned int hscif0_clk_b_pins[] = {
1184	/* HSCK0 */
1185	RCAR_GP_PIN(4, 1),
1186};
1187static const unsigned int hscif0_clk_b_mux[] = {
1188	HSCK0_B_MARK,
1189};
1190static const unsigned int hscif0_ctrl_b_pins[] = {
1191	/* HRTS0#, HCTS0# */
1192	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1193};
1194static const unsigned int hscif0_ctrl_b_mux[] = {
1195	HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1196};
1197
1198/* - HSCIF1 ----------------------------------------------------------------- */
1199static const unsigned int hscif1_data_pins[] = {
1200	/* HRX1, HTX1 */
1201	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1202};
1203static const unsigned int hscif1_data_mux[] = {
1204	HRX1_MARK, HTX1_MARK,
1205};
1206static const unsigned int hscif1_clk_pins[] = {
1207	/* HSCK1 */
1208	RCAR_GP_PIN(2, 7),
1209};
1210static const unsigned int hscif1_clk_mux[] = {
1211	HSCK1_MARK,
1212};
1213static const unsigned int hscif1_ctrl_pins[] = {
1214	/* HRTS1#, HCTS1# */
1215	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1216};
1217static const unsigned int hscif1_ctrl_mux[] = {
1218	HRTS1_N_MARK, HCTS1_N_MARK,
1219};
1220
1221/* - HSCIF2 ----------------------------------------------------------------- */
1222static const unsigned int hscif2_data_pins[] = {
1223	/* HRX2, HTX2 */
1224	RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1225};
1226static const unsigned int hscif2_data_mux[] = {
1227	HRX2_MARK, HTX2_MARK,
1228};
1229static const unsigned int hscif2_clk_pins[] = {
1230	/* HSCK2 */
1231	RCAR_GP_PIN(2, 12),
1232};
1233static const unsigned int hscif2_clk_mux[] = {
1234	HSCK2_MARK,
1235};
1236static const unsigned int hscif2_ctrl_pins[] = {
1237	/* HRTS2#, HCTS2# */
1238	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1239};
1240static const unsigned int hscif2_ctrl_mux[] = {
1241	HRTS2_N_MARK, HCTS2_N_MARK,
1242};
1243
1244/* - HSCIF3 ----------------------------------------------------------------- */
1245static const unsigned int hscif3_data_pins[] = {
1246	/* HRX3, HTX3 */
1247	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1248};
1249static const unsigned int hscif3_data_mux[] = {
1250	HRX3_MARK, HTX3_MARK,
1251};
1252static const unsigned int hscif3_clk_pins[] = {
1253	/* HSCK3 */
1254	RCAR_GP_PIN(2, 0),
1255};
1256static const unsigned int hscif3_clk_mux[] = {
1257	HSCK3_MARK,
1258};
1259static const unsigned int hscif3_ctrl_pins[] = {
1260	/* HRTS3#, HCTS3# */
1261	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1262};
1263static const unsigned int hscif3_ctrl_mux[] = {
1264	HRTS3_N_MARK, HCTS3_N_MARK,
1265};
1266
1267/* - I2C0 ------------------------------------------------------------------- */
1268static const unsigned int i2c0_pins[] = {
1269	/* SDA0, SCL0 */
1270	RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1271};
1272static const unsigned int i2c0_mux[] = {
1273	SDA0_MARK, SCL0_MARK,
1274};
1275
1276/* - I2C1 ------------------------------------------------------------------- */
1277static const unsigned int i2c1_pins[] = {
1278	/* SDA1, SCL1 */
1279	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1280};
1281static const unsigned int i2c1_mux[] = {
1282	SDA1_MARK, SCL1_MARK,
1283};
1284
1285/* - I2C2 ------------------------------------------------------------------- */
1286static const unsigned int i2c2_pins[] = {
1287	/* SDA2, SCL2 */
1288	RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1289};
1290static const unsigned int i2c2_mux[] = {
1291	SDA2_MARK, SCL2_MARK,
1292};
1293
1294/* - I2C3 ------------------------------------------------------------------- */
1295static const unsigned int i2c3_pins[] = {
1296	/* SDA3, SCL3 */
1297	RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1298};
1299static const unsigned int i2c3_mux[] = {
1300	SDA3_MARK, SCL3_MARK,
1301};
1302
1303/* - I2C4 ------------------------------------------------------------------- */
1304static const unsigned int i2c4_pins[] = {
1305	/* SDA4, SCL4 */
1306	RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1307};
1308static const unsigned int i2c4_mux[] = {
1309	SDA4_MARK, SCL4_MARK,
1310};
1311
1312/* - I2C5 ------------------------------------------------------------------- */
1313static const unsigned int i2c5_pins[] = {
1314	/* SDA5, SCL5 */
1315	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1316};
1317static const unsigned int i2c5_mux[] = {
1318	SDA5_MARK, SCL5_MARK,
1319};
1320
1321/* - INTC-EX ---------------------------------------------------------------- */
1322static const unsigned int intc_ex_irq0_pins[] = {
1323	/* IRQ0 */
1324	RCAR_GP_PIN(1, 0),
1325};
1326static const unsigned int intc_ex_irq0_mux[] = {
1327	IRQ0_MARK,
1328};
1329static const unsigned int intc_ex_irq1_pins[] = {
1330	/* IRQ1 */
1331	RCAR_GP_PIN(0, 12),
1332};
1333static const unsigned int intc_ex_irq1_mux[] = {
1334	IRQ1_MARK,
1335};
1336static const unsigned int intc_ex_irq2_pins[] = {
1337	/* IRQ2 */
1338	RCAR_GP_PIN(0, 13),
1339};
1340static const unsigned int intc_ex_irq2_mux[] = {
1341	IRQ2_MARK,
1342};
1343static const unsigned int intc_ex_irq3_pins[] = {
1344	/* IRQ3 */
1345	RCAR_GP_PIN(0, 14),
1346};
1347static const unsigned int intc_ex_irq3_mux[] = {
1348	IRQ3_MARK,
1349};
1350static const unsigned int intc_ex_irq4_pins[] = {
1351	/* IRQ4 */
1352	RCAR_GP_PIN(2, 17),
1353};
1354static const unsigned int intc_ex_irq4_mux[] = {
1355	IRQ4_MARK,
1356};
1357static const unsigned int intc_ex_irq5_pins[] = {
1358	/* IRQ5 */
1359	RCAR_GP_PIN(2, 18),
1360};
1361static const unsigned int intc_ex_irq5_mux[] = {
1362	IRQ5_MARK,
1363};
1364
1365/* - MMC -------------------------------------------------------------------- */
1366static const unsigned int mmc_data_pins[] = {
1367	/* MMC_D[0:7] */
1368	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1369	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1370	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1371	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1372};
1373static const unsigned int mmc_data_mux[] = {
1374	MMC_D0_MARK, MMC_D1_MARK,
1375	MMC_D2_MARK, MMC_D3_MARK,
1376	MMC_D4_MARK, MMC_D5_MARK,
1377	MMC_D6_MARK, MMC_D7_MARK,
1378};
1379static const unsigned int mmc_ctrl_pins[] = {
1380	/* MMC_CLK, MMC_CMD */
1381	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1382};
1383static const unsigned int mmc_ctrl_mux[] = {
1384	MMC_CLK_MARK, MMC_CMD_MARK,
1385};
1386static const unsigned int mmc_cd_pins[] = {
1387	/* MMC_CD */
1388	RCAR_GP_PIN(3, 5),
1389};
1390static const unsigned int mmc_cd_mux[] = {
1391	MMC_CD_MARK,
1392};
1393static const unsigned int mmc_wp_pins[] = {
1394	/* MMC_WP */
1395	RCAR_GP_PIN(3, 4),
1396};
1397static const unsigned int mmc_wp_mux[] = {
1398	MMC_WP_MARK,
1399};
1400static const unsigned int mmc_ds_pins[] = {
1401	/* MMC_DS */
1402	RCAR_GP_PIN(3, 6),
1403};
1404static const unsigned int mmc_ds_mux[] = {
1405	MMC_DS_MARK,
1406};
1407
1408/* - MSIOF0 ----------------------------------------------------------------- */
1409static const unsigned int msiof0_clk_pins[] = {
1410	/* MSIOF0_SCK */
1411	RCAR_GP_PIN(2, 21),
1412};
1413static const unsigned int msiof0_clk_mux[] = {
1414	MSIOF0_SCK_MARK,
1415};
1416static const unsigned int msiof0_sync_pins[] = {
1417	/* MSIOF0_SYNC */
1418	RCAR_GP_PIN(2, 22),
1419};
1420static const unsigned int msiof0_sync_mux[] = {
1421	MSIOF0_SYNC_MARK,
1422};
1423static const unsigned int msiof0_ss1_pins[] = {
1424	/* MSIOF0_SS1 */
1425	RCAR_GP_PIN(2, 23),
1426};
1427static const unsigned int msiof0_ss1_mux[] = {
1428	MSIOF0_SS1_MARK,
1429};
1430static const unsigned int msiof0_ss2_pins[] = {
1431	/* MSIOF0_SS2 */
1432	RCAR_GP_PIN(2, 24),
1433};
1434static const unsigned int msiof0_ss2_mux[] = {
1435	MSIOF0_SS2_MARK,
1436};
1437static const unsigned int msiof0_txd_pins[] = {
1438	/* MSIOF0_TXD */
1439	RCAR_GP_PIN(2, 20),
1440};
1441static const unsigned int msiof0_txd_mux[] = {
1442	MSIOF0_TXD_MARK,
1443};
1444static const unsigned int msiof0_rxd_pins[] = {
1445	/* MSIOF0_RXD */
1446	RCAR_GP_PIN(2, 19),
1447};
1448static const unsigned int msiof0_rxd_mux[] = {
1449	MSIOF0_RXD_MARK,
1450};
1451
1452/* - MSIOF1 ----------------------------------------------------------------- */
1453static const unsigned int msiof1_clk_pins[] = {
1454	/* MSIOF1_SCK */
1455	RCAR_GP_PIN(3, 2),
1456};
1457static const unsigned int msiof1_clk_mux[] = {
1458	MSIOF1_SCK_MARK,
1459};
1460static const unsigned int msiof1_sync_pins[] = {
1461	/* MSIOF1_SYNC */
1462	RCAR_GP_PIN(3, 3),
1463};
1464static const unsigned int msiof1_sync_mux[] = {
1465	MSIOF1_SYNC_MARK,
1466};
1467static const unsigned int msiof1_ss1_pins[] = {
1468	/* MSIOF1_SS1 */
1469	RCAR_GP_PIN(3, 4),
1470};
1471static const unsigned int msiof1_ss1_mux[] = {
1472	MSIOF1_SS1_MARK,
1473};
1474static const unsigned int msiof1_ss2_pins[] = {
1475	/* MSIOF1_SS2 */
1476	RCAR_GP_PIN(3, 5),
1477};
1478static const unsigned int msiof1_ss2_mux[] = {
1479	MSIOF1_SS2_MARK,
1480};
1481static const unsigned int msiof1_txd_pins[] = {
1482	/* MSIOF1_TXD */
1483	RCAR_GP_PIN(3, 1),
1484};
1485static const unsigned int msiof1_txd_mux[] = {
1486	MSIOF1_TXD_MARK,
1487};
1488static const unsigned int msiof1_rxd_pins[] = {
1489	/* MSIOF1_RXD */
1490	RCAR_GP_PIN(3, 0),
1491};
1492static const unsigned int msiof1_rxd_mux[] = {
1493	MSIOF1_RXD_MARK,
1494};
1495
1496/* - MSIOF2 ----------------------------------------------------------------- */
1497static const unsigned int msiof2_clk_pins[] = {
1498	/* MSIOF2_SCK */
1499	RCAR_GP_PIN(2, 0),
1500};
1501static const unsigned int msiof2_clk_mux[] = {
1502	MSIOF2_SCK_MARK,
1503};
1504static const unsigned int msiof2_sync_pins[] = {
1505	/* MSIOF2_SYNC */
1506	RCAR_GP_PIN(2, 3),
1507};
1508static const unsigned int msiof2_sync_mux[] = {
1509	MSIOF2_SYNC_MARK,
1510};
1511static const unsigned int msiof2_ss1_pins[] = {
1512	/* MSIOF2_SS1 */
1513	RCAR_GP_PIN(2, 4),
1514};
1515static const unsigned int msiof2_ss1_mux[] = {
1516	MSIOF2_SS1_MARK,
1517};
1518static const unsigned int msiof2_ss2_pins[] = {
1519	/* MSIOF2_SS2 */
1520	RCAR_GP_PIN(2, 5),
1521};
1522static const unsigned int msiof2_ss2_mux[] = {
1523	MSIOF2_SS2_MARK,
1524};
1525static const unsigned int msiof2_txd_pins[] = {
1526	/* MSIOF2_TXD */
1527	RCAR_GP_PIN(2, 2),
1528};
1529static const unsigned int msiof2_txd_mux[] = {
1530	MSIOF2_TXD_MARK,
1531};
1532static const unsigned int msiof2_rxd_pins[] = {
1533	/* MSIOF2_RXD */
1534	RCAR_GP_PIN(2, 1),
1535};
1536static const unsigned int msiof2_rxd_mux[] = {
1537	MSIOF2_RXD_MARK,
1538};
1539
1540/* - MSIOF3 ----------------------------------------------------------------- */
1541static const unsigned int msiof3_clk_pins[] = {
1542	/* MSIOF3_SCK */
1543	RCAR_GP_PIN(0, 20),
1544};
1545static const unsigned int msiof3_clk_mux[] = {
1546	MSIOF3_SCK_MARK,
1547};
1548static const unsigned int msiof3_sync_pins[] = {
1549	/* MSIOF3_SYNC */
1550	RCAR_GP_PIN(0, 21),
1551};
1552static const unsigned int msiof3_sync_mux[] = {
1553	MSIOF3_SYNC_MARK,
1554};
1555static const unsigned int msiof3_ss1_pins[] = {
1556	/* MSIOF3_SS1 */
1557	RCAR_GP_PIN(0, 18),
1558};
1559static const unsigned int msiof3_ss1_mux[] = {
1560	MSIOF3_SS1_MARK,
1561};
1562static const unsigned int msiof3_ss2_pins[] = {
1563	/* MSIOF3_SS2 */
1564	RCAR_GP_PIN(0, 19),
1565};
1566static const unsigned int msiof3_ss2_mux[] = {
1567	MSIOF3_SS2_MARK,
1568};
1569static const unsigned int msiof3_txd_pins[] = {
1570	/* MSIOF3_TXD */
1571	RCAR_GP_PIN(0, 17),
1572};
1573static const unsigned int msiof3_txd_mux[] = {
1574	MSIOF3_TXD_MARK,
1575};
1576static const unsigned int msiof3_rxd_pins[] = {
1577	/* MSIOF3_RXD */
1578	RCAR_GP_PIN(0, 16),
1579};
1580static const unsigned int msiof3_rxd_mux[] = {
1581	MSIOF3_RXD_MARK,
1582};
1583
1584/* - PWM0 ------------------------------------------------------------------- */
1585static const unsigned int pwm0_a_pins[] = {
1586	/* PWM0 */
1587	RCAR_GP_PIN(0, 15),
1588};
1589static const unsigned int pwm0_a_mux[] = {
1590	PWM0_A_MARK,
1591};
1592static const unsigned int pwm0_b_pins[] = {
1593	/* PWM0 */
1594	RCAR_GP_PIN(1, 21),
1595};
1596static const unsigned int pwm0_b_mux[] = {
1597	PWM0_B_MARK,
1598};
1599
1600/* - PWM1 ------------------------------------------------------------------- */
1601static const unsigned int pwm1_a_pins[] = {
1602	/* PWM1 */
1603	RCAR_GP_PIN(2, 13),
1604};
1605static const unsigned int pwm1_a_mux[] = {
1606	PWM1_A_MARK,
1607};
1608static const unsigned int pwm1_b_pins[] = {
1609	/* PWM1 */
1610	RCAR_GP_PIN(1, 22),
1611};
1612static const unsigned int pwm1_b_mux[] = {
1613	PWM1_B_MARK,
1614};
1615
1616/* - PWM2 ------------------------------------------------------------------- */
1617static const unsigned int pwm2_a_pins[] = {
1618	/* PWM2 */
1619	RCAR_GP_PIN(2, 14),
1620};
1621static const unsigned int pwm2_a_mux[] = {
1622	PWM2_A_MARK,
1623};
1624static const unsigned int pwm2_b_pins[] = {
1625	/* PWM2 */
1626	RCAR_GP_PIN(1, 23),
1627};
1628static const unsigned int pwm2_b_mux[] = {
1629	PWM2_B_MARK,
1630};
1631
1632/* - PWM3 ------------------------------------------------------------------- */
1633static const unsigned int pwm3_a_pins[] = {
1634	/* PWM3 */
1635	RCAR_GP_PIN(2, 15),
1636};
1637static const unsigned int pwm3_a_mux[] = {
1638	PWM3_A_MARK,
1639};
1640static const unsigned int pwm3_b_pins[] = {
1641	/* PWM3 */
1642	RCAR_GP_PIN(1, 24),
1643};
1644static const unsigned int pwm3_b_mux[] = {
1645	PWM3_B_MARK,
1646};
1647
1648/* - PWM4 ------------------------------------------------------------------- */
1649static const unsigned int pwm4_a_pins[] = {
1650	/* PWM4 */
1651	RCAR_GP_PIN(2, 16),
1652};
1653static const unsigned int pwm4_a_mux[] = {
1654	PWM4_A_MARK,
1655};
1656static const unsigned int pwm4_b_pins[] = {
1657	/* PWM4 */
1658	RCAR_GP_PIN(1, 25),
1659};
1660static const unsigned int pwm4_b_mux[] = {
1661	PWM4_B_MARK,
1662};
1663
1664/* - QSPI0 ------------------------------------------------------------------ */
1665static const unsigned int qspi0_ctrl_pins[] = {
1666	/* SPCLK, SSL */
1667	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1668};
1669static const unsigned int qspi0_ctrl_mux[] = {
1670	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1671};
1672
1673/* - QSPI1 ------------------------------------------------------------------ */
1674static const unsigned int qspi1_ctrl_pins[] = {
1675	/* SPCLK, SSL */
1676	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1677};
1678static const unsigned int qspi1_ctrl_mux[] = {
1679	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1680};
1681
1682/* - RPC -------------------------------------------------------------------- */
1683static const unsigned int rpc_clk_pins[] = {
1684	/* Octal-SPI flash: C/SCLK */
1685	/* HyperFlash: CK, CK# */
1686	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1687};
1688static const unsigned int rpc_clk_mux[] = {
1689	QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1690};
1691static const unsigned int rpc_ctrl_pins[] = {
1692	/* Octal-SPI flash: S#/CS, DQS */
1693	/* HyperFlash: CS#, RDS */
1694	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1695};
1696static const unsigned int rpc_ctrl_mux[] = {
1697	QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1698};
1699static const unsigned int rpc_data_pins[] = {
1700	/* DQ[0:7] */
1701	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1702	RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1703	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1704	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1705};
1706static const unsigned int rpc_data_mux[] = {
1707	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1708	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1709	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1710	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1711};
1712static const unsigned int rpc_reset_pins[] = {
1713	/* RPC_RESET# */
1714	RCAR_GP_PIN(5, 12),
1715};
1716static const unsigned int rpc_reset_mux[] = {
1717	RPC_RESET_N_MARK,
1718};
1719static const unsigned int rpc_int_pins[] = {
1720	/* RPC_INT# */
1721	RCAR_GP_PIN(5, 14),
1722};
1723static const unsigned int rpc_int_mux[] = {
1724	RPC_INT_N_MARK,
1725};
1726static const unsigned int rpc_wp_pins[] = {
1727	/* RPC_WP# */
1728	RCAR_GP_PIN(5, 13),
1729};
1730static const unsigned int rpc_wp_mux[] = {
1731	RPC_WP_N_MARK,
1732};
1733
1734/* - SCIF0 ------------------------------------------------------------------ */
1735static const unsigned int scif0_data_pins[] = {
1736	/* RX0, TX0 */
1737	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1738};
1739static const unsigned int scif0_data_mux[] = {
1740	RX0_MARK, TX0_MARK,
1741};
1742static const unsigned int scif0_clk_pins[] = {
1743	/* SCK0 */
1744	RCAR_GP_PIN(4, 1),
1745};
1746static const unsigned int scif0_clk_mux[] = {
1747	SCK0_MARK,
1748};
1749static const unsigned int scif0_ctrl_pins[] = {
1750	/* RTS0#, CTS0# */
1751	RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1752};
1753static const unsigned int scif0_ctrl_mux[] = {
1754	RTS0_N_MARK, CTS0_N_MARK,
1755};
1756
1757/* - SCIF1 ------------------------------------------------------------------ */
1758static const unsigned int scif1_data_a_pins[] = {
1759	/* RX1, TX1 */
1760	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1761};
1762static const unsigned int scif1_data_a_mux[] = {
1763	RX1_A_MARK, TX1_A_MARK,
1764};
1765static const unsigned int scif1_clk_pins[] = {
1766	/* SCK1 */
1767	RCAR_GP_PIN(2, 5),
1768};
1769static const unsigned int scif1_clk_mux[] = {
1770	SCK1_MARK,
1771};
1772static const unsigned int scif1_ctrl_pins[] = {
1773	/* RTS1#, CTS1# */
1774	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1775};
1776static const unsigned int scif1_ctrl_mux[] = {
1777	RTS1_N_MARK, CTS1_N_MARK,
1778};
1779static const unsigned int scif1_data_b_pins[] = {
1780	/* RX1, TX1 */
1781	RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1782};
1783static const unsigned int scif1_data_b_mux[] = {
1784	RX1_B_MARK, TX1_B_MARK,
1785};
1786
1787/* - SCIF3 ------------------------------------------------------------------ */
1788static const unsigned int scif3_data_pins[] = {
1789	/* RX3, TX3 */
1790	RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1791};
1792static const unsigned int scif3_data_mux[] = {
1793	RX3_MARK, TX3_MARK,
1794};
1795static const unsigned int scif3_clk_pins[] = {
1796	/* SCK3 */
1797	RCAR_GP_PIN(2, 0),
1798};
1799static const unsigned int scif3_clk_mux[] = {
1800	SCK3_MARK,
1801};
1802static const unsigned int scif3_ctrl_pins[] = {
1803	/* RTS3#, CTS3# */
1804	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1805};
1806static const unsigned int scif3_ctrl_mux[] = {
1807	RTS3_N_MARK, CTS3_N_MARK,
1808};
1809
1810/* - SCIF4 ------------------------------------------------------------------ */
1811static const unsigned int scif4_data_pins[] = {
1812	/* RX4, TX4 */
1813	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1814};
1815static const unsigned int scif4_data_mux[] = {
1816	RX4_MARK, TX4_MARK,
1817};
1818static const unsigned int scif4_clk_pins[] = {
1819	/* SCK4 */
1820	RCAR_GP_PIN(0, 0),
1821};
1822static const unsigned int scif4_clk_mux[] = {
1823	SCK4_MARK,
1824};
1825static const unsigned int scif4_ctrl_pins[] = {
1826	/* RTS4#, CTS4# */
1827	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1828};
1829static const unsigned int scif4_ctrl_mux[] = {
1830	RTS4_N_MARK, CTS4_N_MARK,
1831};
1832
1833/* - SCIF Clock ------------------------------------------------------------- */
1834static const unsigned int scif_clk_a_pins[] = {
1835	/* SCIF_CLK */
1836	RCAR_GP_PIN(0, 10),
1837};
1838static const unsigned int scif_clk_a_mux[] = {
1839	SCIF_CLK_A_MARK,
1840};
1841static const unsigned int scif_clk_b_pins[] = {
1842	/* SCIF_CLK */
1843	RCAR_GP_PIN(1, 25),
1844};
1845static const unsigned int scif_clk_b_mux[] = {
1846	SCIF_CLK_B_MARK,
1847};
1848
1849/* - TMU -------------------------------------------------------------------- */
1850static const unsigned int tmu_tclk1_a_pins[] = {
1851	/* TCLK1 */
1852	RCAR_GP_PIN(3, 13),
1853};
1854static const unsigned int tmu_tclk1_a_mux[] = {
1855	TCLK1_A_MARK,
1856};
1857static const unsigned int tmu_tclk1_b_pins[] = {
1858	/* TCLK1 */
1859	RCAR_GP_PIN(1, 23),
1860};
1861static const unsigned int tmu_tclk1_b_mux[] = {
1862	TCLK1_B_MARK,
1863};
1864static const unsigned int tmu_tclk2_a_pins[] = {
1865	/* TCLK2 */
1866	RCAR_GP_PIN(3, 14),
1867};
1868static const unsigned int tmu_tclk2_a_mux[] = {
1869	TCLK2_A_MARK,
1870};
1871static const unsigned int tmu_tclk2_b_pins[] = {
1872	/* TCLK2 */
1873	RCAR_GP_PIN(1, 24),
1874};
1875static const unsigned int tmu_tclk2_b_mux[] = {
1876	TCLK2_B_MARK,
1877};
1878
1879/* - TPU ------------------------------------------------------------------- */
1880static const unsigned int tpu_to0_pins[] = {
1881	/* TPU0TO0 */
1882	RCAR_GP_PIN(1, 19),
1883};
1884static const unsigned int tpu_to0_mux[] = {
1885	TPU0TO0_MARK,
1886};
1887static const unsigned int tpu_to1_pins[] = {
1888	/* TPU0TO1 */
1889	RCAR_GP_PIN(1, 20),
1890};
1891static const unsigned int tpu_to1_mux[] = {
1892	TPU0TO1_MARK,
1893};
1894static const unsigned int tpu_to2_pins[] = {
1895	/* TPU0TO2 */
1896	RCAR_GP_PIN(4, 2),
1897};
1898static const unsigned int tpu_to2_mux[] = {
1899	TPU0TO2_MARK,
1900};
1901static const unsigned int tpu_to3_pins[] = {
1902	/* TPU0TO3 */
1903	RCAR_GP_PIN(4, 3),
1904};
1905static const unsigned int tpu_to3_mux[] = {
1906	TPU0TO3_MARK,
1907};
1908
1909/* - VIN0 ------------------------------------------------------------------- */
1910static const unsigned int vin0_data_pins[] = {
1911	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1912	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1913	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1914	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1915	RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1916	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1917	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1918	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1919	RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1920	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1921	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1922	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1923};
1924static const unsigned int vin0_data_mux[] = {
1925	VI0_DATA0_MARK, VI0_DATA1_MARK,
1926	VI0_DATA2_MARK, VI0_DATA3_MARK,
1927	VI0_DATA4_MARK, VI0_DATA5_MARK,
1928	VI0_DATA6_MARK, VI0_DATA7_MARK,
1929	VI0_DATA8_MARK, VI0_DATA9_MARK,
1930	VI0_DATA10_MARK, VI0_DATA11_MARK,
1931	VI0_DATA12_MARK, VI0_DATA13_MARK,
1932	VI0_DATA14_MARK, VI0_DATA15_MARK,
1933	VI0_DATA16_MARK, VI0_DATA17_MARK,
1934	VI0_DATA18_MARK, VI0_DATA19_MARK,
1935	VI0_DATA20_MARK, VI0_DATA21_MARK,
1936	VI0_DATA22_MARK, VI0_DATA23_MARK,
1937};
1938static const unsigned int vin0_data18_pins[] = {
1939	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1940	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1941	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1942	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1943	RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1944	RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1945	RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1946	RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1947	RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1948};
1949static const unsigned int vin0_data18_mux[] = {
1950	VI0_DATA2_MARK, VI0_DATA3_MARK,
1951	VI0_DATA4_MARK, VI0_DATA5_MARK,
1952	VI0_DATA6_MARK, VI0_DATA7_MARK,
1953	VI0_DATA10_MARK, VI0_DATA11_MARK,
1954	VI0_DATA12_MARK, VI0_DATA13_MARK,
1955	VI0_DATA14_MARK, VI0_DATA15_MARK,
1956	VI0_DATA18_MARK, VI0_DATA19_MARK,
1957	VI0_DATA20_MARK, VI0_DATA21_MARK,
1958	VI0_DATA22_MARK, VI0_DATA23_MARK,
1959};
1960static const unsigned int vin0_sync_pins[] = {
1961	/* VI0_VSYNC#, VI0_HSYNC# */
1962	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1963};
1964static const unsigned int vin0_sync_mux[] = {
1965	VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1966};
1967static const unsigned int vin0_field_pins[] = {
1968	/* VI0_FIELD */
1969	RCAR_GP_PIN(2, 16),
1970};
1971static const unsigned int vin0_field_mux[] = {
1972	VI0_FIELD_MARK,
1973};
1974static const unsigned int vin0_clkenb_pins[] = {
1975	/* VI0_CLKENB */
1976	RCAR_GP_PIN(2, 1),
1977};
1978static const unsigned int vin0_clkenb_mux[] = {
1979	VI0_CLKENB_MARK,
1980};
1981static const unsigned int vin0_clk_pins[] = {
1982	/* VI0_CLK */
1983	RCAR_GP_PIN(2, 0),
1984};
1985static const unsigned int vin0_clk_mux[] = {
1986	VI0_CLK_MARK,
1987};
1988
1989/* - VIN1 ------------------------------------------------------------------- */
1990static const unsigned int vin1_data_pins[] = {
1991	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1992	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1993	RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1994	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1995	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1996	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1997};
1998static const unsigned int vin1_data_mux[] = {
1999	VI1_DATA0_MARK, VI1_DATA1_MARK,
2000	VI1_DATA2_MARK, VI1_DATA3_MARK,
2001	VI1_DATA4_MARK, VI1_DATA5_MARK,
2002	VI1_DATA6_MARK, VI1_DATA7_MARK,
2003	VI1_DATA8_MARK,  VI1_DATA9_MARK,
2004	VI1_DATA10_MARK, VI1_DATA11_MARK,
2005};
2006static const unsigned int vin1_sync_pins[] = {
2007	/* VI1_VSYNC#, VI1_HSYNC# */
2008	 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2009};
2010static const unsigned int vin1_sync_mux[] = {
2011	VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2012};
2013static const unsigned int vin1_field_pins[] = {
2014	/* VI1_FIELD */
2015	RCAR_GP_PIN(3, 16),
2016};
2017static const unsigned int vin1_field_mux[] = {
2018	VI1_FIELD_MARK,
2019};
2020static const unsigned int vin1_clkenb_pins[] = {
2021	/* VI1_CLKENB */
2022	RCAR_GP_PIN(3, 1),
2023};
2024static const unsigned int vin1_clkenb_mux[] = {
2025	VI1_CLKENB_MARK,
2026};
2027static const unsigned int vin1_clk_pins[] = {
2028	/* VI1_CLK */
2029	RCAR_GP_PIN(3, 0),
2030};
2031static const unsigned int vin1_clk_mux[] = {
2032	VI1_CLK_MARK,
2033};
2034
2035static const struct sh_pfc_pin_group pinmux_groups[] = {
2036	SH_PFC_PIN_GROUP(avb_link),
2037	SH_PFC_PIN_GROUP(avb_magic),
2038	SH_PFC_PIN_GROUP(avb_phy_int),
2039	SH_PFC_PIN_GROUP(avb_mdio),
2040	SH_PFC_PIN_GROUP(avb_rgmii),
2041	SH_PFC_PIN_GROUP(avb_txcrefclk),
2042	SH_PFC_PIN_GROUP(avb_avtp_pps),
2043	SH_PFC_PIN_GROUP(avb_avtp_capture),
2044	SH_PFC_PIN_GROUP(avb_avtp_match),
2045	SH_PFC_PIN_GROUP(canfd0_data_a),
2046	SH_PFC_PIN_GROUP(canfd0_data_b),
2047	SH_PFC_PIN_GROUP(canfd1_data),
2048	SH_PFC_PIN_GROUP(canfd_clk_a),
2049	SH_PFC_PIN_GROUP(canfd_clk_b),
2050	SH_PFC_PIN_GROUP(du_rgb666),
2051	SH_PFC_PIN_GROUP(du_rgb888),
2052	SH_PFC_PIN_GROUP(du_clk_out),
2053	SH_PFC_PIN_GROUP(du_sync),
2054	SH_PFC_PIN_GROUP(du_oddf),
2055	SH_PFC_PIN_GROUP(du_cde),
2056	SH_PFC_PIN_GROUP(du_disp),
2057	SH_PFC_PIN_GROUP(gether_link_a),
2058	SH_PFC_PIN_GROUP(gether_phy_int_a),
2059	SH_PFC_PIN_GROUP(gether_mdio_a),
2060	SH_PFC_PIN_GROUP(gether_link_b),
2061	SH_PFC_PIN_GROUP(gether_phy_int_b),
2062	SH_PFC_PIN_GROUP(gether_mdio_b),
2063	SH_PFC_PIN_GROUP(gether_magic),
2064	SH_PFC_PIN_GROUP(gether_rgmii),
2065	SH_PFC_PIN_GROUP(gether_txcrefclk),
2066	SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2067	SH_PFC_PIN_GROUP(gether_rmii),
2068	SH_PFC_PIN_GROUP(hscif0_data_a),
2069	SH_PFC_PIN_GROUP(hscif0_clk_a),
2070	SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2071	SH_PFC_PIN_GROUP(hscif0_data_b),
2072	SH_PFC_PIN_GROUP(hscif0_clk_b),
2073	SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2074	SH_PFC_PIN_GROUP(hscif1_data),
2075	SH_PFC_PIN_GROUP(hscif1_clk),
2076	SH_PFC_PIN_GROUP(hscif1_ctrl),
2077	SH_PFC_PIN_GROUP(hscif2_data),
2078	SH_PFC_PIN_GROUP(hscif2_clk),
2079	SH_PFC_PIN_GROUP(hscif2_ctrl),
2080	SH_PFC_PIN_GROUP(hscif3_data),
2081	SH_PFC_PIN_GROUP(hscif3_clk),
2082	SH_PFC_PIN_GROUP(hscif3_ctrl),
2083	SH_PFC_PIN_GROUP(i2c0),
2084	SH_PFC_PIN_GROUP(i2c1),
2085	SH_PFC_PIN_GROUP(i2c2),
2086	SH_PFC_PIN_GROUP(i2c3),
2087	SH_PFC_PIN_GROUP(i2c4),
2088	SH_PFC_PIN_GROUP(i2c5),
2089	SH_PFC_PIN_GROUP(intc_ex_irq0),
2090	SH_PFC_PIN_GROUP(intc_ex_irq1),
2091	SH_PFC_PIN_GROUP(intc_ex_irq2),
2092	SH_PFC_PIN_GROUP(intc_ex_irq3),
2093	SH_PFC_PIN_GROUP(intc_ex_irq4),
2094	SH_PFC_PIN_GROUP(intc_ex_irq5),
2095	BUS_DATA_PIN_GROUP(mmc_data, 1),
2096	BUS_DATA_PIN_GROUP(mmc_data, 4),
2097	BUS_DATA_PIN_GROUP(mmc_data, 8),
2098	SH_PFC_PIN_GROUP(mmc_ctrl),
2099	SH_PFC_PIN_GROUP(mmc_cd),
2100	SH_PFC_PIN_GROUP(mmc_wp),
2101	SH_PFC_PIN_GROUP(mmc_ds),
2102	SH_PFC_PIN_GROUP(msiof0_clk),
2103	SH_PFC_PIN_GROUP(msiof0_sync),
2104	SH_PFC_PIN_GROUP(msiof0_ss1),
2105	SH_PFC_PIN_GROUP(msiof0_ss2),
2106	SH_PFC_PIN_GROUP(msiof0_txd),
2107	SH_PFC_PIN_GROUP(msiof0_rxd),
2108	SH_PFC_PIN_GROUP(msiof1_clk),
2109	SH_PFC_PIN_GROUP(msiof1_sync),
2110	SH_PFC_PIN_GROUP(msiof1_ss1),
2111	SH_PFC_PIN_GROUP(msiof1_ss2),
2112	SH_PFC_PIN_GROUP(msiof1_txd),
2113	SH_PFC_PIN_GROUP(msiof1_rxd),
2114	SH_PFC_PIN_GROUP(msiof2_clk),
2115	SH_PFC_PIN_GROUP(msiof2_sync),
2116	SH_PFC_PIN_GROUP(msiof2_ss1),
2117	SH_PFC_PIN_GROUP(msiof2_ss2),
2118	SH_PFC_PIN_GROUP(msiof2_txd),
2119	SH_PFC_PIN_GROUP(msiof2_rxd),
2120	SH_PFC_PIN_GROUP(msiof3_clk),
2121	SH_PFC_PIN_GROUP(msiof3_sync),
2122	SH_PFC_PIN_GROUP(msiof3_ss1),
2123	SH_PFC_PIN_GROUP(msiof3_ss2),
2124	SH_PFC_PIN_GROUP(msiof3_txd),
2125	SH_PFC_PIN_GROUP(msiof3_rxd),
2126	SH_PFC_PIN_GROUP(pwm0_a),
2127	SH_PFC_PIN_GROUP(pwm0_b),
2128	SH_PFC_PIN_GROUP(pwm1_a),
2129	SH_PFC_PIN_GROUP(pwm1_b),
2130	SH_PFC_PIN_GROUP(pwm2_a),
2131	SH_PFC_PIN_GROUP(pwm2_b),
2132	SH_PFC_PIN_GROUP(pwm3_a),
2133	SH_PFC_PIN_GROUP(pwm3_b),
2134	SH_PFC_PIN_GROUP(pwm4_a),
2135	SH_PFC_PIN_GROUP(pwm4_b),
2136	SH_PFC_PIN_GROUP(qspi0_ctrl),
2137	SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2138	SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2139	SH_PFC_PIN_GROUP(qspi1_ctrl),
2140	SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2141	SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2142	BUS_DATA_PIN_GROUP(rpc_clk, 1),
2143	BUS_DATA_PIN_GROUP(rpc_clk, 2),
2144	SH_PFC_PIN_GROUP(rpc_ctrl),
2145	SH_PFC_PIN_GROUP(rpc_data),
2146	SH_PFC_PIN_GROUP(rpc_reset),
2147	SH_PFC_PIN_GROUP(rpc_int),
2148	SH_PFC_PIN_GROUP(rpc_wp),
2149	SH_PFC_PIN_GROUP(scif0_data),
2150	SH_PFC_PIN_GROUP(scif0_clk),
2151	SH_PFC_PIN_GROUP(scif0_ctrl),
2152	SH_PFC_PIN_GROUP(scif1_data_a),
2153	SH_PFC_PIN_GROUP(scif1_clk),
2154	SH_PFC_PIN_GROUP(scif1_ctrl),
2155	SH_PFC_PIN_GROUP(scif1_data_b),
2156	SH_PFC_PIN_GROUP(scif3_data),
2157	SH_PFC_PIN_GROUP(scif3_clk),
2158	SH_PFC_PIN_GROUP(scif3_ctrl),
2159	SH_PFC_PIN_GROUP(scif4_data),
2160	SH_PFC_PIN_GROUP(scif4_clk),
2161	SH_PFC_PIN_GROUP(scif4_ctrl),
2162	SH_PFC_PIN_GROUP(scif_clk_a),
2163	SH_PFC_PIN_GROUP(scif_clk_b),
2164	SH_PFC_PIN_GROUP(tmu_tclk1_a),
2165	SH_PFC_PIN_GROUP(tmu_tclk1_b),
2166	SH_PFC_PIN_GROUP(tmu_tclk2_a),
2167	SH_PFC_PIN_GROUP(tmu_tclk2_b),
2168	SH_PFC_PIN_GROUP(tpu_to0),
2169	SH_PFC_PIN_GROUP(tpu_to1),
2170	SH_PFC_PIN_GROUP(tpu_to2),
2171	SH_PFC_PIN_GROUP(tpu_to3),
2172	BUS_DATA_PIN_GROUP(vin0_data, 8),
2173	BUS_DATA_PIN_GROUP(vin0_data, 10),
2174	BUS_DATA_PIN_GROUP(vin0_data, 12),
2175	BUS_DATA_PIN_GROUP(vin0_data, 16),
2176	SH_PFC_PIN_GROUP(vin0_data18),
2177	BUS_DATA_PIN_GROUP(vin0_data, 20),
2178	BUS_DATA_PIN_GROUP(vin0_data, 24),
2179	SH_PFC_PIN_GROUP(vin0_sync),
2180	SH_PFC_PIN_GROUP(vin0_field),
2181	SH_PFC_PIN_GROUP(vin0_clkenb),
2182	SH_PFC_PIN_GROUP(vin0_clk),
2183	BUS_DATA_PIN_GROUP(vin1_data, 8),
2184	BUS_DATA_PIN_GROUP(vin1_data, 10),
2185	BUS_DATA_PIN_GROUP(vin1_data, 12),
2186	SH_PFC_PIN_GROUP(vin1_sync),
2187	SH_PFC_PIN_GROUP(vin1_field),
2188	SH_PFC_PIN_GROUP(vin1_clkenb),
2189	SH_PFC_PIN_GROUP(vin1_clk),
2190};
2191
2192static const char * const avb_groups[] = {
2193	"avb_link",
2194	"avb_magic",
2195	"avb_phy_int",
2196	"avb_mdio",
2197	"avb_rgmii",
2198	"avb_txcrefclk",
2199	"avb_avtp_pps",
2200	"avb_avtp_capture",
2201	"avb_avtp_match",
2202};
2203
2204static const char * const canfd0_groups[] = {
2205	"canfd0_data_a",
2206	"canfd0_data_b",
2207};
2208
2209static const char * const canfd1_groups[] = {
2210	"canfd1_data",
2211};
2212
2213static const char * const canfd_clk_groups[] = {
2214	"canfd_clk_a",
2215	"canfd_clk_b",
2216};
2217
2218static const char * const du_groups[] = {
2219	"du_rgb666",
2220	"du_rgb888",
2221	"du_clk_out",
2222	"du_sync",
2223	"du_oddf",
2224	"du_cde",
2225	"du_disp",
2226};
2227
2228static const char * const gether_groups[] = {
2229	"gether_link_a",
2230	"gether_phy_int_a",
2231	"gether_mdio_a",
2232	"gether_link_b",
2233	"gether_phy_int_b",
2234	"gether_mdio_b",
2235	"gether_magic",
2236	"gether_rgmii",
2237	"gether_txcrefclk",
2238	"gether_txcrefclk_mega",
2239	"gether_rmii",
2240};
2241
2242static const char * const hscif0_groups[] = {
2243	"hscif0_data_a",
2244	"hscif0_clk_a",
2245	"hscif0_ctrl_a",
2246	"hscif0_data_b",
2247	"hscif0_clk_b",
2248	"hscif0_ctrl_b",
2249};
2250
2251static const char * const hscif1_groups[] = {
2252	"hscif1_data",
2253	"hscif1_clk",
2254	"hscif1_ctrl",
2255};
2256
2257static const char * const hscif2_groups[] = {
2258	"hscif2_data",
2259	"hscif2_clk",
2260	"hscif2_ctrl",
2261};
2262
2263static const char * const hscif3_groups[] = {
2264	"hscif3_data",
2265	"hscif3_clk",
2266	"hscif3_ctrl",
2267};
2268
2269static const char * const i2c0_groups[] = {
2270	"i2c0",
2271};
2272
2273static const char * const i2c1_groups[] = {
2274	"i2c1",
2275};
2276
2277static const char * const i2c2_groups[] = {
2278	"i2c2",
2279};
2280
2281static const char * const i2c3_groups[] = {
2282	"i2c3",
2283};
2284
2285static const char * const i2c4_groups[] = {
2286	"i2c4",
2287};
2288
2289static const char * const i2c5_groups[] = {
2290	"i2c5",
2291};
2292
2293static const char * const intc_ex_groups[] = {
2294	"intc_ex_irq0",
2295	"intc_ex_irq1",
2296	"intc_ex_irq2",
2297	"intc_ex_irq3",
2298	"intc_ex_irq4",
2299	"intc_ex_irq5",
2300};
2301
2302static const char * const mmc_groups[] = {
2303	"mmc_data1",
2304	"mmc_data4",
2305	"mmc_data8",
2306	"mmc_ctrl",
2307	"mmc_cd",
2308	"mmc_wp",
2309	"mmc_ds",
2310};
2311
2312static const char * const msiof0_groups[] = {
2313	"msiof0_clk",
2314	"msiof0_sync",
2315	"msiof0_ss1",
2316	"msiof0_ss2",
2317	"msiof0_txd",
2318	"msiof0_rxd",
2319};
2320
2321static const char * const msiof1_groups[] = {
2322	"msiof1_clk",
2323	"msiof1_sync",
2324	"msiof1_ss1",
2325	"msiof1_ss2",
2326	"msiof1_txd",
2327	"msiof1_rxd",
2328};
2329
2330static const char * const msiof2_groups[] = {
2331	"msiof2_clk",
2332	"msiof2_sync",
2333	"msiof2_ss1",
2334	"msiof2_ss2",
2335	"msiof2_txd",
2336	"msiof2_rxd",
2337};
2338
2339static const char * const msiof3_groups[] = {
2340	"msiof3_clk",
2341	"msiof3_sync",
2342	"msiof3_ss1",
2343	"msiof3_ss2",
2344	"msiof3_txd",
2345	"msiof3_rxd",
2346};
2347
2348static const char * const pwm0_groups[] = {
2349	"pwm0_a",
2350	"pwm0_b",
2351};
2352
2353static const char * const pwm1_groups[] = {
2354	"pwm1_a",
2355	"pwm1_b",
2356};
2357
2358static const char * const pwm2_groups[] = {
2359	"pwm2_a",
2360	"pwm2_b",
2361};
2362
2363static const char * const pwm3_groups[] = {
2364	"pwm3_a",
2365	"pwm3_b",
2366};
2367
2368static const char * const pwm4_groups[] = {
2369	"pwm4_a",
2370	"pwm4_b",
2371};
2372
2373static const char * const qspi0_groups[] = {
2374	"qspi0_ctrl",
2375	"qspi0_data2",
2376	"qspi0_data4",
2377};
2378
2379static const char * const qspi1_groups[] = {
2380	"qspi1_ctrl",
2381	"qspi1_data2",
2382	"qspi1_data4",
2383};
2384
2385static const char * const rpc_groups[] = {
2386	"rpc_clk1",
2387	"rpc_clk2",
2388	"rpc_ctrl",
2389	"rpc_data",
2390	"rpc_reset",
2391	"rpc_int",
2392	"rpc_wp",
2393};
2394
2395static const char * const scif0_groups[] = {
2396	"scif0_data",
2397	"scif0_clk",
2398	"scif0_ctrl",
2399};
2400
2401static const char * const scif1_groups[] = {
2402	"scif1_data_a",
2403	"scif1_clk",
2404	"scif1_ctrl",
2405	"scif1_data_b",
2406};
2407
2408static const char * const scif3_groups[] = {
2409	"scif3_data",
2410	"scif3_clk",
2411	"scif3_ctrl",
2412};
2413
2414static const char * const scif4_groups[] = {
2415	"scif4_data",
2416	"scif4_clk",
2417	"scif4_ctrl",
2418};
2419
2420static const char * const scif_clk_groups[] = {
2421	"scif_clk_a",
2422	"scif_clk_b",
2423};
2424
2425static const char * const tmu_groups[] = {
2426	"tmu_tclk1_a",
2427	"tmu_tclk1_b",
2428	"tmu_tclk2_a",
2429	"tmu_tclk2_b",
2430};
2431
2432static const char * const tpu_groups[] = {
2433	"tpu_to0",
2434	"tpu_to1",
2435	"tpu_to2",
2436	"tpu_to3",
2437};
2438
2439static const char * const vin0_groups[] = {
2440	"vin0_data8",
2441	"vin0_data10",
2442	"vin0_data12",
2443	"vin0_data16",
2444	"vin0_data18",
2445	"vin0_data20",
2446	"vin0_data24",
2447	"vin0_sync",
2448	"vin0_field",
2449	"vin0_clkenb",
2450	"vin0_clk",
2451};
2452
2453static const char * const vin1_groups[] = {
2454	"vin1_data8",
2455	"vin1_data10",
2456	"vin1_data12",
2457	"vin1_sync",
2458	"vin1_field",
2459	"vin1_clkenb",
2460	"vin1_clk",
2461};
2462
2463static const struct sh_pfc_function pinmux_functions[] = {
2464	SH_PFC_FUNCTION(avb),
2465	SH_PFC_FUNCTION(canfd0),
2466	SH_PFC_FUNCTION(canfd1),
2467	SH_PFC_FUNCTION(canfd_clk),
2468	SH_PFC_FUNCTION(du),
2469	SH_PFC_FUNCTION(gether),
2470	SH_PFC_FUNCTION(hscif0),
2471	SH_PFC_FUNCTION(hscif1),
2472	SH_PFC_FUNCTION(hscif2),
2473	SH_PFC_FUNCTION(hscif3),
2474	SH_PFC_FUNCTION(i2c0),
2475	SH_PFC_FUNCTION(i2c1),
2476	SH_PFC_FUNCTION(i2c2),
2477	SH_PFC_FUNCTION(i2c3),
2478	SH_PFC_FUNCTION(i2c4),
2479	SH_PFC_FUNCTION(i2c5),
2480	SH_PFC_FUNCTION(intc_ex),
2481	SH_PFC_FUNCTION(mmc),
2482	SH_PFC_FUNCTION(msiof0),
2483	SH_PFC_FUNCTION(msiof1),
2484	SH_PFC_FUNCTION(msiof2),
2485	SH_PFC_FUNCTION(msiof3),
2486	SH_PFC_FUNCTION(pwm0),
2487	SH_PFC_FUNCTION(pwm1),
2488	SH_PFC_FUNCTION(pwm2),
2489	SH_PFC_FUNCTION(pwm3),
2490	SH_PFC_FUNCTION(pwm4),
2491	SH_PFC_FUNCTION(qspi0),
2492	SH_PFC_FUNCTION(qspi1),
2493	SH_PFC_FUNCTION(rpc),
2494	SH_PFC_FUNCTION(scif0),
2495	SH_PFC_FUNCTION(scif1),
2496	SH_PFC_FUNCTION(scif3),
2497	SH_PFC_FUNCTION(scif4),
2498	SH_PFC_FUNCTION(scif_clk),
2499	SH_PFC_FUNCTION(tmu),
2500	SH_PFC_FUNCTION(tpu),
2501	SH_PFC_FUNCTION(vin0),
2502	SH_PFC_FUNCTION(vin1),
2503};
2504
2505static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2506#define F_(x, y)	FN_##y
2507#define FM(x)		FN_##x
2508	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2509			     GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2510				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2511			     GROUP(
2512		/* GP0_31_22 RESERVED */
2513		GP_0_21_FN,	GPSR0_21,
2514		GP_0_20_FN,	GPSR0_20,
2515		GP_0_19_FN,	GPSR0_19,
2516		GP_0_18_FN,	GPSR0_18,
2517		GP_0_17_FN,	GPSR0_17,
2518		GP_0_16_FN,	GPSR0_16,
2519		GP_0_15_FN,	GPSR0_15,
2520		GP_0_14_FN,	GPSR0_14,
2521		GP_0_13_FN,	GPSR0_13,
2522		GP_0_12_FN,	GPSR0_12,
2523		GP_0_11_FN,	GPSR0_11,
2524		GP_0_10_FN,	GPSR0_10,
2525		GP_0_9_FN,	GPSR0_9,
2526		GP_0_8_FN,	GPSR0_8,
2527		GP_0_7_FN,	GPSR0_7,
2528		GP_0_6_FN,	GPSR0_6,
2529		GP_0_5_FN,	GPSR0_5,
2530		GP_0_4_FN,	GPSR0_4,
2531		GP_0_3_FN,	GPSR0_3,
2532		GP_0_2_FN,	GPSR0_2,
2533		GP_0_1_FN,	GPSR0_1,
2534		GP_0_0_FN,	GPSR0_0, ))
2535	},
2536	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2537		0, 0,
2538		0, 0,
2539		0, 0,
2540		0, 0,
2541		GP_1_27_FN,	GPSR1_27,
2542		GP_1_26_FN,	GPSR1_26,
2543		GP_1_25_FN,	GPSR1_25,
2544		GP_1_24_FN,	GPSR1_24,
2545		GP_1_23_FN,	GPSR1_23,
2546		GP_1_22_FN,	GPSR1_22,
2547		GP_1_21_FN,	GPSR1_21,
2548		GP_1_20_FN,	GPSR1_20,
2549		GP_1_19_FN,	GPSR1_19,
2550		GP_1_18_FN,	GPSR1_18,
2551		GP_1_17_FN,	GPSR1_17,
2552		GP_1_16_FN,	GPSR1_16,
2553		GP_1_15_FN,	GPSR1_15,
2554		GP_1_14_FN,	GPSR1_14,
2555		GP_1_13_FN,	GPSR1_13,
2556		GP_1_12_FN,	GPSR1_12,
2557		GP_1_11_FN,	GPSR1_11,
2558		GP_1_10_FN,	GPSR1_10,
2559		GP_1_9_FN,	GPSR1_9,
2560		GP_1_8_FN,	GPSR1_8,
2561		GP_1_7_FN,	GPSR1_7,
2562		GP_1_6_FN,	GPSR1_6,
2563		GP_1_5_FN,	GPSR1_5,
2564		GP_1_4_FN,	GPSR1_4,
2565		GP_1_3_FN,	GPSR1_3,
2566		GP_1_2_FN,	GPSR1_2,
2567		GP_1_1_FN,	GPSR1_1,
2568		GP_1_0_FN,	GPSR1_0, ))
2569	},
2570	{ PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2571		0, 0,
2572		0, 0,
2573		GP_2_29_FN,	GPSR2_29,
2574		GP_2_28_FN,	GPSR2_28,
2575		GP_2_27_FN,	GPSR2_27,
2576		GP_2_26_FN,	GPSR2_26,
2577		GP_2_25_FN,	GPSR2_25,
2578		GP_2_24_FN,	GPSR2_24,
2579		GP_2_23_FN,	GPSR2_23,
2580		GP_2_22_FN,	GPSR2_22,
2581		GP_2_21_FN,	GPSR2_21,
2582		GP_2_20_FN,	GPSR2_20,
2583		GP_2_19_FN,	GPSR2_19,
2584		GP_2_18_FN,	GPSR2_18,
2585		GP_2_17_FN,	GPSR2_17,
2586		GP_2_16_FN,	GPSR2_16,
2587		GP_2_15_FN,	GPSR2_15,
2588		GP_2_14_FN,	GPSR2_14,
2589		GP_2_13_FN,	GPSR2_13,
2590		GP_2_12_FN,	GPSR2_12,
2591		GP_2_11_FN,	GPSR2_11,
2592		GP_2_10_FN,	GPSR2_10,
2593		GP_2_9_FN,	GPSR2_9,
2594		GP_2_8_FN,	GPSR2_8,
2595		GP_2_7_FN,	GPSR2_7,
2596		GP_2_6_FN,	GPSR2_6,
2597		GP_2_5_FN,	GPSR2_5,
2598		GP_2_4_FN,	GPSR2_4,
2599		GP_2_3_FN,	GPSR2_3,
2600		GP_2_2_FN,	GPSR2_2,
2601		GP_2_1_FN,	GPSR2_1,
2602		GP_2_0_FN,	GPSR2_0, ))
2603	},
2604	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2605			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2606				   1, 1, 1, 1, 1, 1),
2607			     GROUP(
2608		/* GP3_31_17 RESERVED */
2609		GP_3_16_FN,	GPSR3_16,
2610		GP_3_15_FN,	GPSR3_15,
2611		GP_3_14_FN,	GPSR3_14,
2612		GP_3_13_FN,	GPSR3_13,
2613		GP_3_12_FN,	GPSR3_12,
2614		GP_3_11_FN,	GPSR3_11,
2615		GP_3_10_FN,	GPSR3_10,
2616		GP_3_9_FN,	GPSR3_9,
2617		GP_3_8_FN,	GPSR3_8,
2618		GP_3_7_FN,	GPSR3_7,
2619		GP_3_6_FN,	GPSR3_6,
2620		GP_3_5_FN,	GPSR3_5,
2621		GP_3_4_FN,	GPSR3_4,
2622		GP_3_3_FN,	GPSR3_3,
2623		GP_3_2_FN,	GPSR3_2,
2624		GP_3_1_FN,	GPSR3_1,
2625		GP_3_0_FN,	GPSR3_0, ))
2626	},
2627	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2628			     GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2629				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2630				   1, 1),
2631			     GROUP(
2632		/* GP4_31_25 RESERVED */
2633		GP_4_24_FN,	GPSR4_24,
2634		GP_4_23_FN,	GPSR4_23,
2635		GP_4_22_FN,	GPSR4_22,
2636		GP_4_21_FN,	GPSR4_21,
2637		GP_4_20_FN,	GPSR4_20,
2638		GP_4_19_FN,	GPSR4_19,
2639		GP_4_18_FN,	GPSR4_18,
2640		GP_4_17_FN,	GPSR4_17,
2641		GP_4_16_FN,	GPSR4_16,
2642		GP_4_15_FN,	GPSR4_15,
2643		GP_4_14_FN,	GPSR4_14,
2644		GP_4_13_FN,	GPSR4_13,
2645		GP_4_12_FN,	GPSR4_12,
2646		GP_4_11_FN,	GPSR4_11,
2647		GP_4_10_FN,	GPSR4_10,
2648		GP_4_9_FN,	GPSR4_9,
2649		GP_4_8_FN,	GPSR4_8,
2650		GP_4_7_FN,	GPSR4_7,
2651		GP_4_6_FN,	GPSR4_6,
2652		GP_4_5_FN,	GPSR4_5,
2653		GP_4_4_FN,	GPSR4_4,
2654		GP_4_3_FN,	GPSR4_3,
2655		GP_4_2_FN,	GPSR4_2,
2656		GP_4_1_FN,	GPSR4_1,
2657		GP_4_0_FN,	GPSR4_0, ))
2658	},
2659	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2660			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2661				   1, 1, 1, 1),
2662			     GROUP(
2663		/* GP5_31_15 RESERVED */
2664		GP_5_14_FN,	GPSR5_14,
2665		GP_5_13_FN,	GPSR5_13,
2666		GP_5_12_FN,	GPSR5_12,
2667		GP_5_11_FN,	GPSR5_11,
2668		GP_5_10_FN,	GPSR5_10,
2669		GP_5_9_FN,	GPSR5_9,
2670		GP_5_8_FN,	GPSR5_8,
2671		GP_5_7_FN,	GPSR5_7,
2672		GP_5_6_FN,	GPSR5_6,
2673		GP_5_5_FN,	GPSR5_5,
2674		GP_5_4_FN,	GPSR5_4,
2675		GP_5_3_FN,	GPSR5_3,
2676		GP_5_2_FN,	GPSR5_2,
2677		GP_5_1_FN,	GPSR5_1,
2678		GP_5_0_FN,	GPSR5_0, ))
2679	},
2680#undef F_
2681#undef FM
2682
2683#define F_(x, y)	x,
2684#define FM(x)		FN_##x,
2685	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2686		IP0_31_28
2687		IP0_27_24
2688		IP0_23_20
2689		IP0_19_16
2690		IP0_15_12
2691		IP0_11_8
2692		IP0_7_4
2693		IP0_3_0 ))
2694	},
2695	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2696		IP1_31_28
2697		IP1_27_24
2698		IP1_23_20
2699		IP1_19_16
2700		IP1_15_12
2701		IP1_11_8
2702		IP1_7_4
2703		IP1_3_0 ))
2704	},
2705	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2706		IP2_31_28
2707		IP2_27_24
2708		IP2_23_20
2709		IP2_19_16
2710		IP2_15_12
2711		IP2_11_8
2712		IP2_7_4
2713		IP2_3_0 ))
2714	},
2715	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2716		IP3_31_28
2717		IP3_27_24
2718		IP3_23_20
2719		IP3_19_16
2720		IP3_15_12
2721		IP3_11_8
2722		IP3_7_4
2723		IP3_3_0 ))
2724	},
2725	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2726		IP4_31_28
2727		IP4_27_24
2728		IP4_23_20
2729		IP4_19_16
2730		IP4_15_12
2731		IP4_11_8
2732		IP4_7_4
2733		IP4_3_0 ))
2734	},
2735	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2736		IP5_31_28
2737		IP5_27_24
2738		IP5_23_20
2739		IP5_19_16
2740		IP5_15_12
2741		IP5_11_8
2742		IP5_7_4
2743		IP5_3_0 ))
2744	},
2745	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2746		IP6_31_28
2747		IP6_27_24
2748		IP6_23_20
2749		IP6_19_16
2750		IP6_15_12
2751		IP6_11_8
2752		IP6_7_4
2753		IP6_3_0 ))
2754	},
2755	{ PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2756		IP7_31_28
2757		IP7_27_24
2758		IP7_23_20
2759		IP7_19_16
2760		IP7_15_12
2761		IP7_11_8
2762		IP7_7_4
2763		IP7_3_0 ))
2764	},
2765	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2766		IP8_31_28
2767		IP8_27_24
2768		IP8_23_20
2769		IP8_19_16
2770		IP8_15_12
2771		IP8_11_8
2772		IP8_7_4
2773		IP8_3_0 ))
2774	},
2775	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2776		IP9_31_28
2777		IP9_27_24
2778		IP9_23_20
2779		IP9_19_16
2780		IP9_15_12
2781		IP9_11_8
2782		IP9_7_4
2783		IP9_3_0 ))
2784	},
2785	{ PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2786			     GROUP(-12, 4, 4, 4, 4, 4),
2787			     GROUP(
2788		/* IP10_31_20 RESERVED */
2789		IP10_19_16
2790		IP10_15_12
2791		IP10_11_8
2792		IP10_7_4
2793		IP10_3_0 ))
2794	},
2795#undef F_
2796#undef FM
2797
2798#define F_(x, y)	x,
2799#define FM(x)		FN_##x,
2800	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2801			     GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
2802			     GROUP(
2803		/* RESERVED 31-12 */
2804		MOD_SEL0_11
2805		MOD_SEL0_10
2806		MOD_SEL0_9
2807		MOD_SEL0_8
2808		MOD_SEL0_7
2809		MOD_SEL0_6
2810		MOD_SEL0_5
2811		MOD_SEL0_4
2812		/* RESERVED 3 */
2813		MOD_SEL0_2
2814		MOD_SEL0_1
2815		MOD_SEL0_0 ))
2816	},
2817	{ /* sentinel */ }
2818};
2819
2820enum ioctrl_regs {
2821	POCCTRL0,
2822	POCCTRL1,
2823	POCCTRL2,
2824	POCCTRL3,
2825	TDSELCTRL,
2826};
2827
2828static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2829	[POCCTRL0] = { 0xe6060380, },
2830	[POCCTRL1] = { 0xe6060384, },
2831	[POCCTRL2] = { 0xe6060388, },
2832	[POCCTRL3] = { 0xe606038c, },
2833	[TDSELCTRL] = { 0xe60603c0, },
2834	{ /* sentinel */ }
2835};
2836
2837static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2838{
2839	int bit = pin & 0x1f;
2840
2841	switch (pin) {
2842	case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
2843		*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2844		return bit;
2845
2846	case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
2847		*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2848		return bit + 22;
2849
2850	case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
2851		*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2852		return bit - 10;
2853
2854	case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
2855	case RCAR_GP_PIN(3,  0) ... RCAR_GP_PIN(3, 16):
2856		*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2857		return bit + 7;
2858
2859	case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
2860		*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2861		return pin - 25;
2862
2863	case PIN_VDDQ_AVB:
2864		*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2865		return 0;
2866
2867	case PIN_VDDQ_GE:
2868		*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
2869		return 1;
2870
2871	default:
2872		return -EINVAL;
2873	}
2874}
2875
2876static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2877	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2878		[ 0] = RCAR_GP_PIN(0, 0),	/* DU_DR2 */
2879		[ 1] = RCAR_GP_PIN(0, 1),	/* DU_DR3 */
2880		[ 2] = RCAR_GP_PIN(0, 2),	/* DU_DR4 */
2881		[ 3] = RCAR_GP_PIN(0, 3),	/* DU_DR5 */
2882		[ 4] = RCAR_GP_PIN(0, 4),	/* DU_DR6 */
2883		[ 5] = RCAR_GP_PIN(0, 5),	/* DU_DR7 */
2884		[ 6] = RCAR_GP_PIN(0, 6),	/* DU_DG2 */
2885		[ 7] = RCAR_GP_PIN(0, 7),	/* DU_DG3 */
2886		[ 8] = RCAR_GP_PIN(0, 8),	/* DU_DG4 */
2887		[ 9] = RCAR_GP_PIN(0, 9),	/* DU_DG5 */
2888		[10] = RCAR_GP_PIN(0, 10),	/* DU_DG6 */
2889		[11] = RCAR_GP_PIN(0, 11),	/* DU_DG7 */
2890		[12] = RCAR_GP_PIN(0, 12),	/* DU_DB2 */
2891		[13] = RCAR_GP_PIN(0, 13),	/* DU_DB3 */
2892		[14] = RCAR_GP_PIN(0, 14),	/* DU_DB4 */
2893		[15] = RCAR_GP_PIN(0, 15),	/* DU_DB5 */
2894		[16] = RCAR_GP_PIN(0, 16),	/* DU_DB6 */
2895		[17] = RCAR_GP_PIN(0, 17),	/* DU_DB7 */
2896		[18] = RCAR_GP_PIN(0, 18),	/* DU_DOTCLKOUT */
2897		[19] = RCAR_GP_PIN(0, 19),	/* DU_EXHSYNC/DU_HSYNC */
2898		[20] = RCAR_GP_PIN(0, 20),	/* DU_EXVSYNC/DU_VSYNC */
2899		[21] = RCAR_GP_PIN(0, 21),	/* DU_EXODDF/DU_ODDF/DISP/CDE */
2900		[22] = SH_PFC_PIN_NONE,
2901		[23] = SH_PFC_PIN_NONE,
2902		[24] = PIN_DU_DOTCLKIN,		/* DU_DOTCLKIN */
2903		[25] = SH_PFC_PIN_NONE,
2904		[26] = PIN_PRESETOUT_N,		/* PRESETOUT# */
2905		[27] = SH_PFC_PIN_NONE,
2906		[28] = SH_PFC_PIN_NONE,
2907		[29] = SH_PFC_PIN_NONE,
2908		[30] = PIN_EXTALR,		/* EXTALR */
2909		[31] = PIN_FSCLKST_N,		/* FSCLKST# */
2910	} },
2911	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2912		[ 0] = PIN_FSCLKST,		/* FSCLKST */
2913		[ 1] = SH_PFC_PIN_NONE,
2914		[ 2] = RCAR_GP_PIN(1, 0),	/* IRQ0 */
2915		[ 3] = PIN_DCUTRST_N,		/* DCUTRST# */
2916		[ 4] = PIN_DCUTCK_LPDCLK,	/* DCUTCK_LPDCLK */
2917		[ 5] = PIN_DCUTMS,		/* DCUTMS */
2918		[ 6] = PIN_DCUTDI_LPDI,		/* DCUTDI_LPDI */
2919		[ 7] = SH_PFC_PIN_NONE,
2920		[ 8] = RCAR_GP_PIN(2, 0),	/* VI0_CLK */
2921		[ 9] = RCAR_GP_PIN(2, 1),	/* VI0_CLKENB */
2922		[10] = RCAR_GP_PIN(2, 2),	/* VI0_HSYNC# */
2923		[11] = RCAR_GP_PIN(2, 3),	/* VI0_VSYNC# */
2924		[12] = RCAR_GP_PIN(2, 4),	/* VI0_DATA0 */
2925		[13] = RCAR_GP_PIN(2, 5),	/* VI0_DATA1 */
2926		[14] = RCAR_GP_PIN(2, 6),	/* VI0_DATA2 */
2927		[15] = RCAR_GP_PIN(2, 7),	/* VI0_DATA3 */
2928		[16] = RCAR_GP_PIN(2, 8),	/* VI0_DATA4 */
2929		[17] = RCAR_GP_PIN(2, 9),	/* VI0_DATA5 */
2930		[18] = RCAR_GP_PIN(2, 10),	/* VI0_DATA6 */
2931		[19] = RCAR_GP_PIN(2, 11),	/* VI0_DATA7 */
2932		[20] = RCAR_GP_PIN(2, 12),	/* VI0_DATA8 */
2933		[21] = RCAR_GP_PIN(2, 13),	/* VI0_DATA9 */
2934		[22] = RCAR_GP_PIN(2, 14),	/* VI0_DATA10 */
2935		[23] = RCAR_GP_PIN(2, 15),	/* VI0_DATA11 */
2936		[24] = RCAR_GP_PIN(2, 16),	/* VI0_FIELD */
2937		[25] = RCAR_GP_PIN(3, 0),	/* VI1_CLK */
2938		[26] = RCAR_GP_PIN(3, 1),	/* VI1_CLKENB */
2939		[27] = RCAR_GP_PIN(3, 2),	/* VI1_HSYNC# */
2940		[28] = RCAR_GP_PIN(3, 3),	/* VI1_VSYNC# */
2941		[29] = RCAR_GP_PIN(3, 4),	/* VI1_DATA0 */
2942		[30] = RCAR_GP_PIN(3, 5),	/* VI1_DATA1 */
2943		[31] = RCAR_GP_PIN(3, 6),	/* VI1_DATA2 */
2944	} },
2945	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2946		[ 0] = RCAR_GP_PIN(3, 7),	/* VI1_DATA3 */
2947		[ 1] = RCAR_GP_PIN(3, 8),	/* VI1_DATA4 */
2948		[ 2] = RCAR_GP_PIN(3, 9),	/* VI1_DATA5 */
2949		[ 3] = RCAR_GP_PIN(3, 10),	/* VI1_DATA6 */
2950		[ 4] = RCAR_GP_PIN(3, 11),	/* VI1_DATA7 */
2951		[ 5] = RCAR_GP_PIN(3, 12),	/* VI1_DATA8 */
2952		[ 6] = RCAR_GP_PIN(3, 13),	/* VI1_DATA9 */
2953		[ 7] = RCAR_GP_PIN(3, 14),	/* VI1_DATA10 */
2954		[ 8] = RCAR_GP_PIN(3, 15),	/* VI1_DATA11 */
2955		[ 9] = RCAR_GP_PIN(3, 16),	/* VI1_FIELD */
2956		[10] = RCAR_GP_PIN(4, 0),	/* SCL0 */
2957		[11] = RCAR_GP_PIN(4, 1),	/* SDA0 */
2958		[12] = RCAR_GP_PIN(4, 2),	/* SCL1 */
2959		[13] = RCAR_GP_PIN(4, 3),	/* SDA1 */
2960		[14] = RCAR_GP_PIN(4, 4),	/* SCL2 */
2961		[15] = RCAR_GP_PIN(4, 5),	/* SDA2 */
2962		[16] = RCAR_GP_PIN(1, 1),	/* AVB_RX_CTL */
2963		[17] = RCAR_GP_PIN(1, 2),	/* AVB_RXC */
2964		[18] = RCAR_GP_PIN(1, 3),	/* AVB_RD0 */
2965		[19] = RCAR_GP_PIN(1, 4),	/* AVB_RD1 */
2966		[20] = RCAR_GP_PIN(1, 5),	/* AVB_RD2 */
2967		[21] = RCAR_GP_PIN(1, 6),	/* AVB_RD3 */
2968		[22] = RCAR_GP_PIN(1, 7),	/* AVB_TX_CTL */
2969		[23] = RCAR_GP_PIN(1, 8),	/* AVB_TXC */
2970		[24] = RCAR_GP_PIN(1, 9),	/* AVB_TD0 */
2971		[25] = RCAR_GP_PIN(1, 10),	/* AVB_TD1 */
2972		[26] = RCAR_GP_PIN(1, 11),	/* AVB_TD2 */
2973		[27] = RCAR_GP_PIN(1, 12),	/* AVB_TD3 */
2974		[28] = RCAR_GP_PIN(1, 13),	/* AVB_TXCREFCLK */
2975		[29] = RCAR_GP_PIN(1, 14),	/* AVB_MDIO */
2976		[30] = RCAR_GP_PIN(1, 15),	/* AVB_MDC */
2977		[31] = RCAR_GP_PIN(1, 16),	/* AVB_MAGIC */
2978	} },
2979	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2980		[ 0] = RCAR_GP_PIN(1, 17),	/* AVB_PHY_INT */
2981		[ 1] = RCAR_GP_PIN(1, 18),	/* AVB_LINK */
2982		[ 2] = RCAR_GP_PIN(1, 19),	/* AVB_AVTP_MATCH */
2983		[ 3] = RCAR_GP_PIN(1, 20),	/* AVTP_CAPTURE */
2984		[ 4] = RCAR_GP_PIN(4, 6),	/* GETHER_RX_CTL */
2985		[ 5] = RCAR_GP_PIN(4, 7),	/* GETHER_RXC */
2986		[ 6] = RCAR_GP_PIN(4, 8),	/* GETHER_RD0 */
2987		[ 7] = RCAR_GP_PIN(4, 9),	/* GETHER_RD1 */
2988		[ 8] = RCAR_GP_PIN(4, 10),	/* GETHER_RD2 */
2989		[ 9] = RCAR_GP_PIN(4, 11),	/* GETHER_RD3 */
2990		[10] = RCAR_GP_PIN(4, 12),	/* GETHER_TX_CTL */
2991		[11] = RCAR_GP_PIN(4, 13),	/* GETHER_TXC */
2992		[12] = RCAR_GP_PIN(4, 14),	/* GETHER_TD0 */
2993		[13] = RCAR_GP_PIN(4, 15),	/* GETHER_TD1 */
2994		[14] = RCAR_GP_PIN(4, 16),	/* GETHER_TD2 */
2995		[15] = RCAR_GP_PIN(4, 17),	/* GETHER_TD3 */
2996		[16] = RCAR_GP_PIN(4, 18),	/* GETHER_TXCREFCLK */
2997		[17] = RCAR_GP_PIN(4, 19),	/* GETHER_TXCREFCLK_MEGA */
2998		[18] = RCAR_GP_PIN(4, 20),	/* GETHER_MDIO_A */
2999		[19] = RCAR_GP_PIN(4, 21),	/* GETHER_MDC_A */
3000		[20] = RCAR_GP_PIN(4, 22),	/* GETHER_MAGIC */
3001		[21] = RCAR_GP_PIN(4, 23),	/* GETHER_PHY_INT_A */
3002		[22] = RCAR_GP_PIN(4, 24),	/* GETHER_LINK_A */
3003		[23] = RCAR_GP_PIN(1, 21),	/* CANFD0_TX_A */
3004		[24] = RCAR_GP_PIN(1, 22),	/* CANFD0_RX_A */
3005		[25] = RCAR_GP_PIN(1, 23),	/* CANFD1_TX */
3006		[26] = RCAR_GP_PIN(1, 24),	/* CANFD1_RX */
3007		[27] = RCAR_GP_PIN(1, 25),	/* CAN_CLK_A */
3008		[28] = RCAR_GP_PIN(5, 0),	/* QSPI0_SPCLK */
3009		[29] = RCAR_GP_PIN(5, 1),	/* QSPI0_MOSI_IO0 */
3010		[30] = RCAR_GP_PIN(5, 2),	/* QSPI0_MISO_IO1 */
3011		[31] = RCAR_GP_PIN(5, 3),	/* QSPI0_IO2 */
3012	} },
3013	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3014		[ 0] = RCAR_GP_PIN(5, 4),	/* QSPI0_IO3 */
3015		[ 1] = RCAR_GP_PIN(5, 5),	/* QSPI0_SSL */
3016		[ 2] = RCAR_GP_PIN(5, 6),	/* QSPI1_SPCLK */
3017		[ 3] = RCAR_GP_PIN(5, 7),	/* QSPI1_MOSI_IO0 */
3018		[ 4] = RCAR_GP_PIN(5, 8),	/* QSPI1_MISO_IO1 */
3019		[ 5] = RCAR_GP_PIN(5, 9),	/* QSPI1_IO2 */
3020		[ 6] = RCAR_GP_PIN(5, 10),	/* QSPI1_IO3 */
3021		[ 7] = RCAR_GP_PIN(5, 11),	/* QSPI1_SSL */
3022		[ 8] = RCAR_GP_PIN(5, 12),	/* RPC_RESET# */
3023		[ 9] = RCAR_GP_PIN(5, 13),	/* RPC_WP# */
3024		[10] = RCAR_GP_PIN(5, 14),	/* RPC_INT# */
3025		[11] = RCAR_GP_PIN(1, 26),	/* DIGRF_CLKIN */
3026		[12] = RCAR_GP_PIN(1, 27),	/* DIGRF_CLKOUT */
3027		[13] = RCAR_GP_PIN(2, 17),	/* IRQ4 */
3028		[14] = RCAR_GP_PIN(2, 18),	/* IRQ5 */
3029		[15] = RCAR_GP_PIN(2, 25),	/* SCL3 */
3030		[16] = RCAR_GP_PIN(2, 26),	/* SDA3 */
3031		[17] = RCAR_GP_PIN(2, 19),	/* MSIOF0_RXD */
3032		[18] = RCAR_GP_PIN(2, 20),	/* MSIOF0_TXD */
3033		[19] = RCAR_GP_PIN(2, 21),	/* MSIOF0_SCK */
3034		[20] = RCAR_GP_PIN(2, 22),	/* MSIOF0_SYNC */
3035		[21] = RCAR_GP_PIN(2, 23),	/* MSIOF0_SS1 */
3036		[22] = RCAR_GP_PIN(2, 24),	/* MSIOF0_SS2 */
3037		[23] = RCAR_GP_PIN(2, 27),	/* FSO_CFE_0# */
3038		[24] = RCAR_GP_PIN(2, 28),	/* FSO_CFE_1# */
3039		[25] = RCAR_GP_PIN(2, 29),	/* FSO_TOE# */
3040		[26] = SH_PFC_PIN_NONE,
3041		[27] = SH_PFC_PIN_NONE,
3042		[28] = SH_PFC_PIN_NONE,
3043		[29] = SH_PFC_PIN_NONE,
3044		[30] = SH_PFC_PIN_NONE,
3045		[31] = SH_PFC_PIN_NONE,
3046	} },
3047	{ /* sentinel */ }
3048};
3049
3050static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
3051	.pin_to_pocctrl = r8a77980_pin_to_pocctrl,
3052	.get_bias = rcar_pinmux_get_bias,
3053	.set_bias = rcar_pinmux_set_bias,
3054};
3055
3056const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3057	.name = "r8a77980_pfc",
3058	.ops = &r8a77980_pfc_ops,
3059	.unlock_reg = 0xe6060000, /* PMMR */
3060
3061	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3062
3063	.pins = pinmux_pins,
3064	.nr_pins = ARRAY_SIZE(pinmux_pins),
3065	.groups = pinmux_groups,
3066	.nr_groups = ARRAY_SIZE(pinmux_groups),
3067	.functions = pinmux_functions,
3068	.nr_functions = ARRAY_SIZE(pinmux_functions),
3069
3070	.cfg_regs = pinmux_config_regs,
3071	.bias_regs = pinmux_bias_regs,
3072	.ioctrl_regs = pinmux_ioctrl_regs,
3073
3074	.pinmux_data = pinmux_data,
3075	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
3076};