pfc-r8a77965.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A77965 processor support - PFC hardware block.
   4 *
   5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
   7 *
   8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
   9 *
  10 * R-Car Gen3 processor support - PFC hardware block.
  11 *
  12 * Copyright (C) 2015  Renesas Electronics Corporation
  13 */
  14
  15#include <linux/errno.h>
  16#include <linux/kernel.h>
  17
  18#include "sh_pfc.h"
  19
  20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  21
  22#define CPU_ALL_GP(fn, sfx)						\
  23	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
  24	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
  25	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
  26	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  27	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
  28	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
  29	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
  30	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
  31	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  32	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
  33	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
  34	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  35
  36#define CPU_ALL_NOGP(fn)						\
  37	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
  38	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
  39	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
  40	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
  41	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
  42	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
  43	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
  44	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
  45	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
  46	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
  47	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
  48	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
  49	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
  50	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
  51	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
  52	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
  53	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
  54	PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS),	\
  55	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  56	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
  57	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
  58	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
  59	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
  60	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
  61	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
  62	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
  63	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
  64	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
  65	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
  66	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
  67	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
  68	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
  69	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
  70	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
  71	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
  72	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
  73	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
  74	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  75	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  76	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
  77	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
  78	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  79
  80/*
  81 * F_() : just information
  82 * FM() : macro for FN_xxx / xxx_MARK
  83 */
  84
  85/* GPSR0 */
  86#define GPSR0_15	F_(D15,			IP7_11_8)
  87#define GPSR0_14	F_(D14,			IP7_7_4)
  88#define GPSR0_13	F_(D13,			IP7_3_0)
  89#define GPSR0_12	F_(D12,			IP6_31_28)
  90#define GPSR0_11	F_(D11,			IP6_27_24)
  91#define GPSR0_10	F_(D10,			IP6_23_20)
  92#define GPSR0_9		F_(D9,			IP6_19_16)
  93#define GPSR0_8		F_(D8,			IP6_15_12)
  94#define GPSR0_7		F_(D7,			IP6_11_8)
  95#define GPSR0_6		F_(D6,			IP6_7_4)
  96#define GPSR0_5		F_(D5,			IP6_3_0)
  97#define GPSR0_4		F_(D4,			IP5_31_28)
  98#define GPSR0_3		F_(D3,			IP5_27_24)
  99#define GPSR0_2		F_(D2,			IP5_23_20)
 100#define GPSR0_1		F_(D1,			IP5_19_16)
 101#define GPSR0_0		F_(D0,			IP5_15_12)
 102
 103/* GPSR1 */
 104#define GPSR1_28	FM(CLKOUT)
 105#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
 106#define GPSR1_26	F_(WE1_N,		IP5_7_4)
 107#define GPSR1_25	F_(WE0_N,		IP5_3_0)
 108#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
 109#define GPSR1_23	F_(RD_N,		IP4_27_24)
 110#define GPSR1_22	F_(BS_N,		IP4_23_20)
 111#define GPSR1_21	F_(CS1_N,		IP4_19_16)
 112#define GPSR1_20	F_(CS0_N,		IP4_15_12)
 113#define GPSR1_19	F_(A19,			IP4_11_8)
 114#define GPSR1_18	F_(A18,			IP4_7_4)
 115#define GPSR1_17	F_(A17,			IP4_3_0)
 116#define GPSR1_16	F_(A16,			IP3_31_28)
 117#define GPSR1_15	F_(A15,			IP3_27_24)
 118#define GPSR1_14	F_(A14,			IP3_23_20)
 119#define GPSR1_13	F_(A13,			IP3_19_16)
 120#define GPSR1_12	F_(A12,			IP3_15_12)
 121#define GPSR1_11	F_(A11,			IP3_11_8)
 122#define GPSR1_10	F_(A10,			IP3_7_4)
 123#define GPSR1_9		F_(A9,			IP3_3_0)
 124#define GPSR1_8		F_(A8,			IP2_31_28)
 125#define GPSR1_7		F_(A7,			IP2_27_24)
 126#define GPSR1_6		F_(A6,			IP2_23_20)
 127#define GPSR1_5		F_(A5,			IP2_19_16)
 128#define GPSR1_4		F_(A4,			IP2_15_12)
 129#define GPSR1_3		F_(A3,			IP2_11_8)
 130#define GPSR1_2		F_(A2,			IP2_7_4)
 131#define GPSR1_1		F_(A1,			IP2_3_0)
 132#define GPSR1_0		F_(A0,			IP1_31_28)
 133
 134/* GPSR2 */
 135#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
 136#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
 137#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
 138#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
 139#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
 140#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
 141#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
 142#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
 143#define GPSR2_6		F_(PWM0,		IP1_19_16)
 144#define GPSR2_5		F_(IRQ5,		IP1_15_12)
 145#define GPSR2_4		F_(IRQ4,		IP1_11_8)
 146#define GPSR2_3		F_(IRQ3,		IP1_7_4)
 147#define GPSR2_2		F_(IRQ2,		IP1_3_0)
 148#define GPSR2_1		F_(IRQ1,		IP0_31_28)
 149#define GPSR2_0		F_(IRQ0,		IP0_27_24)
 150
 151/* GPSR3 */
 152#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
 153#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
 154#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
 155#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
 156#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
 157#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
 158#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
 159#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
 160#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
 161#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
 162#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
 163#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
 164#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
 165#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
 166#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
 167#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
 168
 169/* GPSR4 */
 170#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
 171#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
 172#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
 173#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
 174#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
 175#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
 176#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
 177#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
 178#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
 179#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
 180#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
 181#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
 182#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
 183#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
 184#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
 185#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
 186#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
 187#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
 188
 189/* GPSR5 */
 190#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
 191#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
 192#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
 193#define GPSR5_22	FM(MSIOF0_RXD)
 194#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
 195#define GPSR5_20	FM(MSIOF0_TXD)
 196#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
 197#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
 198#define GPSR5_17	FM(MSIOF0_SCK)
 199#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
 200#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
 201#define GPSR5_14	F_(HTX0,		IP13_19_16)
 202#define GPSR5_13	F_(HRX0,		IP13_15_12)
 203#define GPSR5_12	F_(HSCK0,		IP13_11_8)
 204#define GPSR5_11	F_(RX2_A,		IP13_7_4)
 205#define GPSR5_10	F_(TX2_A,		IP13_3_0)
 206#define GPSR5_9		F_(SCK2,		IP12_31_28)
 207#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
 208#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
 209#define GPSR5_6		F_(TX1_A,		IP12_19_16)
 210#define GPSR5_5		F_(RX1_A,		IP12_15_12)
 211#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
 212#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
 213#define GPSR5_2		F_(TX0,			IP12_3_0)
 214#define GPSR5_1		F_(RX0,			IP11_31_28)
 215#define GPSR5_0		F_(SCK0,		IP11_27_24)
 216
 217/* GPSR6 */
 218#define GPSR6_31	F_(GP6_31,		IP18_7_4)
 219#define GPSR6_30	F_(GP6_30,		IP18_3_0)
 220#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
 221#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
 222#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
 223#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
 224#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
 225#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
 226#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
 227#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
 228#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
 229#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
 230#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
 231#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
 232#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
 233#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
 234#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
 235#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
 236#define GPSR6_13	FM(SSI_SDATA5)
 237#define GPSR6_12	FM(SSI_WS5)
 238#define GPSR6_11	FM(SSI_SCK5)
 239#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
 240#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
 241#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
 242#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
 243#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
 244#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
 245#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
 246#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
 247#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
 248#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
 249#define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
 250
 251/* GPSR7 */
 252#define GPSR7_3		FM(GP7_03)
 253#define GPSR7_2		FM(GP7_02)
 254#define GPSR7_1		FM(AVS2)
 255#define GPSR7_0		FM(AVS1)
 256
 257/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 258#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	FM(FSCLKST2_N_A) F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285
 286/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 287#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316
 317/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 318#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_B)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352
 353/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 354#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 364#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 365#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 366#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 367#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 368#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 370#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 371#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 372#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 373#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 374#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 375#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 376#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 377#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 378#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 379#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 380#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 381#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 382
 383/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 384#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 385#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 386#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 387#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 388#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 389#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 390#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 391#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 392#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 393#define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 394#define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 395#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(SATA_DEVSLP_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 396#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 397#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 398#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 399#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 400#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 401#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 402#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 403#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 404#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 405#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 406#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 407#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 408#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 409#define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 410#define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 411
 412#define PINMUX_GPSR	\
 413\
 414												GPSR6_31 \
 415												GPSR6_30 \
 416												GPSR6_29 \
 417		GPSR1_28									GPSR6_28 \
 418		GPSR1_27									GPSR6_27 \
 419		GPSR1_26									GPSR6_26 \
 420		GPSR1_25							GPSR5_25	GPSR6_25 \
 421		GPSR1_24							GPSR5_24	GPSR6_24 \
 422		GPSR1_23							GPSR5_23	GPSR6_23 \
 423		GPSR1_22							GPSR5_22	GPSR6_22 \
 424		GPSR1_21							GPSR5_21	GPSR6_21 \
 425		GPSR1_20							GPSR5_20	GPSR6_20 \
 426		GPSR1_19							GPSR5_19	GPSR6_19 \
 427		GPSR1_18							GPSR5_18	GPSR6_18 \
 428		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
 429		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
 430GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
 431GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
 432GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
 433GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
 434GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
 435GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
 436GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
 437GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
 438GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
 439GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
 440GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
 441GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
 442GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
 443GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
 444GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
 445GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
 446
 447#define PINMUX_IPSR				\
 448\
 449FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
 450FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
 451FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
 452FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
 453FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
 454FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
 455FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
 456FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
 457\
 458FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
 459FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
 460FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
 461FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
 462FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
 463FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
 464FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
 465FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
 466\
 467FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
 468FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
 469FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
 470FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
 471FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
 472FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
 473FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
 474FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
 475\
 476FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
 477FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
 478FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
 479FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
 480FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
 481FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
 482FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
 483FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
 484\
 485FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
 486FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
 487FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
 488FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
 489FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
 490FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
 491FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
 492FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
 493
 494/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 495#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
 496#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
 497#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
 498#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
 499#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
 500#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
 501#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
 502#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
 503#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
 504#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
 505#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
 506#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
 507#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
 508#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
 509#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
 510#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
 511#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
 512#define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
 513
 514/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 515#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
 516#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
 517#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
 518#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
 519#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
 520#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
 521#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
 522#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
 523#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
 524#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
 525#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
 526#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
 527#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
 528#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
 529#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
 530#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
 531#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
 532#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
 533#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
 534#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
 535#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
 536#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
 537
 538/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 539#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
 540#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
 541#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
 542#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
 543#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
 544#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
 545#define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
 546#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
 547#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
 548#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
 549#define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
 550#define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
 551#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
 552
 553#define PINMUX_MOD_SELS	\
 554\
 555MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
 556						MOD_SEL2_30 \
 557			MOD_SEL1_29_28_27	MOD_SEL2_29 \
 558MOD_SEL0_28_27					MOD_SEL2_28_27 \
 559MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
 560			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
 561MOD_SEL0_23		MOD_SEL1_23_22_21 \
 562MOD_SEL0_22					MOD_SEL2_22 \
 563MOD_SEL0_21					MOD_SEL2_21 \
 564MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
 565MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
 566MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
 567						MOD_SEL2_17 \
 568MOD_SEL0_16		MOD_SEL1_16 \
 569			MOD_SEL1_15_14 \
 570MOD_SEL0_14_13 \
 571			MOD_SEL1_13 \
 572MOD_SEL0_12		MOD_SEL1_12 \
 573MOD_SEL0_11		MOD_SEL1_11 \
 574MOD_SEL0_10		MOD_SEL1_10 \
 575MOD_SEL0_9_8		MOD_SEL1_9 \
 576MOD_SEL0_7_6 \
 577			MOD_SEL1_6 \
 578MOD_SEL0_5		MOD_SEL1_5 \
 579MOD_SEL0_4_3		MOD_SEL1_4 \
 580			MOD_SEL1_3 \
 581			MOD_SEL1_2 \
 582			MOD_SEL1_1 \
 583			MOD_SEL1_0		MOD_SEL2_0
 584
 585/*
 586 * These pins are not able to be muxed but have other properties
 587 * that can be set, such as drive-strength or pull-up/pull-down enable.
 588 */
 589#define PINMUX_STATIC \
 590	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 591	FM(QSPI0_IO2) FM(QSPI0_IO3) \
 592	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 593	FM(QSPI1_IO2) FM(QSPI1_IO3) \
 594	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 595	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 596	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 597	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 598	FM(PRESETOUT) \
 599	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
 600	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 601
 602#define PINMUX_PHYS \
 603	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 604
 605enum {
 606	PINMUX_RESERVED = 0,
 607
 608	PINMUX_DATA_BEGIN,
 609	GP_ALL(DATA),
 610	PINMUX_DATA_END,
 611
 612#define F_(x, y)
 613#define FM(x)	FN_##x,
 614	PINMUX_FUNCTION_BEGIN,
 615	GP_ALL(FN),
 616	PINMUX_GPSR
 617	PINMUX_IPSR
 618	PINMUX_MOD_SELS
 619	PINMUX_FUNCTION_END,
 620#undef F_
 621#undef FM
 622
 623#define F_(x, y)
 624#define FM(x)	x##_MARK,
 625	PINMUX_MARK_BEGIN,
 626	PINMUX_GPSR
 627	PINMUX_IPSR
 628	PINMUX_MOD_SELS
 629	PINMUX_STATIC
 630	PINMUX_PHYS
 631	PINMUX_MARK_END,
 632#undef F_
 633#undef FM
 634};
 635
 636static const u16 pinmux_data[] = {
 637	PINMUX_DATA_GP_ALL(),
 638
 639	PINMUX_SINGLE(AVS1),
 640	PINMUX_SINGLE(AVS2),
 641	PINMUX_SINGLE(CLKOUT),
 642	PINMUX_SINGLE(GP7_03),
 643	PINMUX_SINGLE(GP7_02),
 644	PINMUX_SINGLE(MSIOF0_RXD),
 645	PINMUX_SINGLE(MSIOF0_SCK),
 646	PINMUX_SINGLE(MSIOF0_TXD),
 647	PINMUX_SINGLE(SSI_SCK5),
 648	PINMUX_SINGLE(SSI_SDATA5),
 649	PINMUX_SINGLE(SSI_WS5),
 650
 651	/* IPSR0 */
 652	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
 653	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
 654
 655	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
 656	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
 657	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
 658
 659	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
 660	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
 661	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
 662
 663	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
 664	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
 665	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
 666	PINMUX_IPSR_GPSR(IP0_19_16,	FSCLKST2_N_A),
 667
 668	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
 669	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
 670	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 671	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
 672
 673	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
 674	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
 675	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 676	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
 677
 678	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
 679	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
 680	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
 681	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
 682	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
 683	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
 684	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
 685
 686	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
 687	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
 688	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
 689	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
 690	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
 691	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
 692	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
 693
 694	/* IPSR1 */
 695	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
 696	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
 697	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
 698	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
 699	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
 700	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
 701
 702	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
 703	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
 704	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
 705	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
 706	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
 707	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
 708
 709	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
 710	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
 711	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
 712	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
 713	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
 714	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
 715
 716	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
 717	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
 718	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
 719	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
 720	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
 721	PINMUX_IPSR_GPSR(IP1_15_12,	FSCLKST2_N_B),
 722	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
 723
 724	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
 725	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
 726	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
 727	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
 728
 729	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
 730	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
 731	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
 732	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
 733	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
 734
 735	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
 736	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
 737	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
 738	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
 739
 740	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
 741	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
 742	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
 743	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
 744	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
 745	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
 746
 747	/* IPSR2 */
 748	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
 749	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
 750	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
 751	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
 752	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
 753	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
 754
 755	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
 756	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
 757	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
 758	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
 759	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
 760	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
 761
 762	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
 763	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
 764	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
 765	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
 766	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
 767	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
 768
 769	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
 770	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
 771	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
 772	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
 773	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
 774	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
 775
 776	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
 777	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
 778	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
 779	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
 780	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
 781	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
 782	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
 783
 784	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
 785	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
 786	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
 787	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
 788	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
 789	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
 790	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
 791
 792	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
 793	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
 794	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
 795	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
 796	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
 797	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
 798	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
 799
 800	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
 801	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
 802	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
 803	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
 804	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
 805	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
 806	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
 807
 808	/* IPSR3 */
 809	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
 810	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
 811	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
 812	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
 813
 814	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
 815	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
 816	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
 817	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
 818
 819	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
 820	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
 821	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
 822	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
 823	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
 824	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
 825	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
 826	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
 827	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
 828
 829	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
 830	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
 831	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
 832	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
 833	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
 834	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
 835
 836	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
 837	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
 838	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
 839	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
 840	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
 841	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
 842
 843	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
 844	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
 845	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
 846	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
 847	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
 848	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
 849
 850	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
 851	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
 852	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
 853	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
 854	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
 855	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
 856
 857	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
 858	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
 859	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
 860	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
 861
 862	/* IPSR4 */
 863	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
 864	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
 865	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
 866	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
 867
 868	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
 869	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
 870	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
 871	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
 872
 873	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
 874	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
 875	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
 876	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
 877
 878	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
 879	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
 880
 881	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
 882	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
 883	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
 884
 885	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
 886	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
 887	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
 888	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
 889	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
 890	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
 891	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
 892	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
 893
 894	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
 895	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
 896	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
 897	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
 898	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
 899	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
 900
 901	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
 902	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
 903	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
 904	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
 905	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
 906	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
 907
 908	/* IPSR5 */
 909	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
 910	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
 911	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
 912	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
 913	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
 914	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
 915	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
 916
 917	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
 918	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
 919	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
 920	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
 921	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
 922	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
 923	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
 924	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
 925
 926	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
 927	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
 928	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
 929	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
 930
 931	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
 932	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
 933	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
 934	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
 935	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
 936
 937	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
 938	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
 939	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
 940	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
 941	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
 942
 943	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
 944	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
 945	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
 946	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
 947
 948	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
 949	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
 950	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
 951	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
 952
 953	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
 954	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
 955	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
 956	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
 957
 958	/* IPSR6 */
 959	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
 960	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
 961	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
 962	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
 963
 964	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
 965	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
 966	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
 967	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
 968
 969	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
 970	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
 971	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
 972	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
 973
 974	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
 975	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
 976	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
 977	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
 978	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
 979	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
 980
 981	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
 982	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
 983	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
 984	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
 985	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
 986
 987	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
 988	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
 989	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
 990	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
 991	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
 992	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
 993	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
 994
 995	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
 996	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
 997	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
 998	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
 999	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
1000	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
1001	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
1002
1003	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
1004	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
1005	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
1006	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
1007	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
1008	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
1009
1010	/* IPSR7 */
1011	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
1012	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
1013	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
1014	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
1015	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
1016	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
1017
1018	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
1019	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
1020	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
1021	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
1022	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
1023	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
1024	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
1025
1026	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
1027	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
1028	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
1029	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
1030	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
1031	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
1032	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
1033
1034	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
1035	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
1036	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
1037
1038	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
1039	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
1040	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
1041
1042	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
1043	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
1044	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
1045	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
1046
1047	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
1048	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
1049	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
1050	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
1051
1052	/* IPSR8 */
1053	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
1054	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
1055	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
1056	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
1057
1058	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
1059	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
1060	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
1061	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
1062
1063	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
1064	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
1065	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
1066
1067	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
1068	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
1069	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
1070	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
1071	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
1072
1073	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
1074	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
1075	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
1076	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
1077	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
1078	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
1079
1080	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
1081	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
1082	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
1083	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
1084	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
1085	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
1086
1087	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
1088	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
1089	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
1090	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
1091	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
1092	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
1093
1094	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
1095	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
1096	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
1097	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
1098	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
1099	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
1100
1101	/* IPSR9 */
1102	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
1103	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
1104
1105	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
1106	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
1107
1108	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
1109	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
1110
1111	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
1112	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
1113
1114	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
1115	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
1116
1117	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
1118	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
1119
1120	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
1121	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
1122	PINMUX_IPSR_GPSR(IP9_27_24,	SATA_DEVSLP_B),
1123
1124	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
1125	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
1126
1127	/* IPSR10 */
1128	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
1129	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
1130
1131	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
1132	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
1133
1134	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
1135	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
1136
1137	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
1138	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
1139
1140	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
1141	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
1142
1143	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
1144	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
1145	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
1146
1147	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
1148	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
1149	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
1150
1151	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
1152	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
1153	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
1154
1155	/* IPSR11 */
1156	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
1157	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
1158	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
1159
1160	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
1161	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
1162
1163	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
1164	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDF_0),
1165	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
1166	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
1167
1168	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
1169	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDF_0),
1170	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
1171
1172	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
1173	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1174	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1175	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
1176
1177	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
1178	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1179	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1180	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
1181
1182	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
1183	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
1184	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
1185	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
1186	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
1187	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
1188	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
1189	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
1190	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
1191	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
1192
1193	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
1194	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
1195	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
1196	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
1197	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
1198
1199	/* IPSR12 */
1200	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
1201	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
1202	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
1203	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
1204	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
1205
1206	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
1207	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
1208	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
1209	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
1210	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
1211	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
1212	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
1213	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
1214
1215	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
1216	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
1217	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
1218	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
1219	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
1220	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
1221	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
1222	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
1223
1224	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
1225	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
1226	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
1227	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
1228	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
1229
1230	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
1231	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
1232	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
1233	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
1234	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
1235
1236	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
1237	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
1238	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
1239	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
1240	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
1241	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
1242	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
1243
1244	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
1245	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
1246	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
1247	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
1248	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
1249	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
1250	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
1251
1252	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
1253	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
1254	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
1255	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
1256	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
1257	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
1258	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
1259
1260	/* IPSR13 */
1261	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
1262	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
1263	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
1264	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
1265	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
1266	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
1267
1268	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
1269	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
1270	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
1271	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
1272	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
1273	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
1274
1275	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
1276	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
1277	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
1278	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
1279	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
1280	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
1281	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
1282	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
1283
1284	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
1285	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
1286	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
1287	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
1288	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
1289	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
1290
1291	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
1292	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
1293	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
1294	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
1295	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
1296	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
1297
1298	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
1299	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
1300	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
1301	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
1302	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
1303	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
1304	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
1305	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
1306
1307	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
1308	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
1309	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
1310	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
1311	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
1312	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
1313	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
1314
1315	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
1316	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
1317	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
1318	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
1319
1320	/* IPSR14 */
1321	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
1322	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
1323	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
1324	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
1325	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
1326	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
1327	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
1328	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
1329
1330	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
1331	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
1332	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
1333	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
1334	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
1335	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
1336	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
1337	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
1338
1339	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
1340	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
1341	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
1342
1343	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
1344	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
1345	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
1346	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
1347
1348	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
1349	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
1350	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
1351
1352	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
1353	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
1354
1355	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
1356	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
1357
1358	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
1359	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
1360
1361	/* IPSR15 */
1362	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
1363
1364	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
1365	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
1366
1367	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
1368	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
1369	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
1370
1371	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
1372	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
1373	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
1374	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
1375
1376	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
1377	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
1378	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
1379	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
1380	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
1381	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
1382	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
1383
1384	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
1385	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
1386	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
1387	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
1388	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
1389	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
1390	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
1391
1392	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
1393	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
1394	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
1395	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
1396	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
1397	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
1398	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
1399
1400	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
1401	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
1402	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
1403	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
1404	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
1405	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
1406	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
1407
1408	/* IPSR16 */
1409	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
1410	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
1411
1412	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
1413	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
1414
1415	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
1416	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
1417	PINMUX_IPSR_GPSR(IP16_11_8,	SATA_DEVSLP_A),
1418
1419	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
1420	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
1421	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
1422	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
1423	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
1424	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
1425	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
1426
1427	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
1428	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
1429	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
1430	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
1431	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
1432	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
1433	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
1434
1435	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
1436	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
1437	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
1438	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
1439	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
1440	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
1441	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
1442	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
1443
1444	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
1445	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
1446	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
1447	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
1448	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
1449	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
1450	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
1451
1452	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
1453	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
1454	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
1455	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
1456	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
1457	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
1458	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
1459	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
1460
1461	/* IPSR17 */
1462	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
1463
1464	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
1465	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
1466	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
1467	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
1468	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
1469
1470	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
1471	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
1472	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
1473	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
1474	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
1475	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
1476	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
1477
1478	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
1479	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
1480	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
1481	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
1482	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
1483	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
1484
1485	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
1486	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
1487	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
1488	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
1489	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
1490	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
1491	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
1492	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
1493	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
1494
1495	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
1496	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
1497	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
1498	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
1499	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
1500	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
1501	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
1502	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
1503	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
1504
1505	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
1506	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
1507	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
1508	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
1509	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
1510	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
1511	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
1512	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
1513	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
1514	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
1515	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
1516
1517	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
1518	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
1519	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
1520	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
1521	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
1522	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
1523	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
1524	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
1525	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
1526
1527	/* IPSR18 */
1528	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
1529	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
1530	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
1531	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
1532	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
1533	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
1534	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
1535	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
1536	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
1537
1538	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
1539	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
1540	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
1541	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
1542	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
1543	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
1544	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
1545	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
1546	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
1547
1548/*
1549 * Static pins can not be muxed between different functions but
1550 * still need mark entries in the pinmux list. Add each static
1551 * pin to the list without an associated function. The sh-pfc
1552 * core will do the right thing and skip trying to mux the pin
1553 * while still applying configuration to it.
1554 */
1555#define FM(x)	PINMUX_DATA(x##_MARK, 0),
1556	PINMUX_STATIC
1557#undef FM
1558};
1559
1560/*
1561 * Pins not associated with a GPIO port.
1562 */
1563enum {
1564	GP_ASSIGN_LAST(),
1565	NOGP_ALL(),
1566};
1567
1568static const struct sh_pfc_pin pinmux_pins[] = {
1569	PINMUX_GPIO_GP_ALL(),
1570	PINMUX_NOGP_ALL(),
1571};
1572
1573/* - AUDIO CLOCK ------------------------------------------------------------ */
1574static const unsigned int audio_clk_a_a_pins[] = {
1575	/* CLK A */
1576	RCAR_GP_PIN(6, 22),
1577};
1578static const unsigned int audio_clk_a_a_mux[] = {
1579	AUDIO_CLKA_A_MARK,
1580};
1581static const unsigned int audio_clk_a_b_pins[] = {
1582	/* CLK A */
1583	RCAR_GP_PIN(5, 4),
1584};
1585static const unsigned int audio_clk_a_b_mux[] = {
1586	AUDIO_CLKA_B_MARK,
1587};
1588static const unsigned int audio_clk_a_c_pins[] = {
1589	/* CLK A */
1590	RCAR_GP_PIN(5, 19),
1591};
1592static const unsigned int audio_clk_a_c_mux[] = {
1593	AUDIO_CLKA_C_MARK,
1594};
1595static const unsigned int audio_clk_b_a_pins[] = {
1596	/* CLK B */
1597	RCAR_GP_PIN(5, 12),
1598};
1599static const unsigned int audio_clk_b_a_mux[] = {
1600	AUDIO_CLKB_A_MARK,
1601};
1602static const unsigned int audio_clk_b_b_pins[] = {
1603	/* CLK B */
1604	RCAR_GP_PIN(6, 23),
1605};
1606static const unsigned int audio_clk_b_b_mux[] = {
1607	AUDIO_CLKB_B_MARK,
1608};
1609static const unsigned int audio_clk_c_a_pins[] = {
1610	/* CLK C */
1611	RCAR_GP_PIN(5, 21),
1612};
1613static const unsigned int audio_clk_c_a_mux[] = {
1614	AUDIO_CLKC_A_MARK,
1615};
1616static const unsigned int audio_clk_c_b_pins[] = {
1617	/* CLK C */
1618	RCAR_GP_PIN(5, 0),
1619};
1620static const unsigned int audio_clk_c_b_mux[] = {
1621	AUDIO_CLKC_B_MARK,
1622};
1623static const unsigned int audio_clkout_a_pins[] = {
1624	/* CLKOUT */
1625	RCAR_GP_PIN(5, 18),
1626};
1627static const unsigned int audio_clkout_a_mux[] = {
1628	AUDIO_CLKOUT_A_MARK,
1629};
1630static const unsigned int audio_clkout_b_pins[] = {
1631	/* CLKOUT */
1632	RCAR_GP_PIN(6, 28),
1633};
1634static const unsigned int audio_clkout_b_mux[] = {
1635	AUDIO_CLKOUT_B_MARK,
1636};
1637static const unsigned int audio_clkout_c_pins[] = {
1638	/* CLKOUT */
1639	RCAR_GP_PIN(5, 3),
1640};
1641static const unsigned int audio_clkout_c_mux[] = {
1642	AUDIO_CLKOUT_C_MARK,
1643};
1644static const unsigned int audio_clkout_d_pins[] = {
1645	/* CLKOUT */
1646	RCAR_GP_PIN(5, 21),
1647};
1648static const unsigned int audio_clkout_d_mux[] = {
1649	AUDIO_CLKOUT_D_MARK,
1650};
1651static const unsigned int audio_clkout1_a_pins[] = {
1652	/* CLKOUT1 */
1653	RCAR_GP_PIN(5, 15),
1654};
1655static const unsigned int audio_clkout1_a_mux[] = {
1656	AUDIO_CLKOUT1_A_MARK,
1657};
1658static const unsigned int audio_clkout1_b_pins[] = {
1659	/* CLKOUT1 */
1660	RCAR_GP_PIN(6, 29),
1661};
1662static const unsigned int audio_clkout1_b_mux[] = {
1663	AUDIO_CLKOUT1_B_MARK,
1664};
1665static const unsigned int audio_clkout2_a_pins[] = {
1666	/* CLKOUT2 */
1667	RCAR_GP_PIN(5, 16),
1668};
1669static const unsigned int audio_clkout2_a_mux[] = {
1670	AUDIO_CLKOUT2_A_MARK,
1671};
1672static const unsigned int audio_clkout2_b_pins[] = {
1673	/* CLKOUT2 */
1674	RCAR_GP_PIN(6, 30),
1675};
1676static const unsigned int audio_clkout2_b_mux[] = {
1677	AUDIO_CLKOUT2_B_MARK,
1678};
1679
1680static const unsigned int audio_clkout3_a_pins[] = {
1681	/* CLKOUT3 */
1682	RCAR_GP_PIN(5, 19),
1683};
1684static const unsigned int audio_clkout3_a_mux[] = {
1685	AUDIO_CLKOUT3_A_MARK,
1686};
1687static const unsigned int audio_clkout3_b_pins[] = {
1688	/* CLKOUT3 */
1689	RCAR_GP_PIN(6, 31),
1690};
1691static const unsigned int audio_clkout3_b_mux[] = {
1692	AUDIO_CLKOUT3_B_MARK,
1693};
1694
1695/* - EtherAVB --------------------------------------------------------------- */
1696static const unsigned int avb_link_pins[] = {
1697	/* AVB_LINK */
1698	RCAR_GP_PIN(2, 12),
1699};
1700static const unsigned int avb_link_mux[] = {
1701	AVB_LINK_MARK,
1702};
1703static const unsigned int avb_magic_pins[] = {
1704	/* AVB_MAGIC_ */
1705	RCAR_GP_PIN(2, 10),
1706};
1707static const unsigned int avb_magic_mux[] = {
1708	AVB_MAGIC_MARK,
1709};
1710static const unsigned int avb_phy_int_pins[] = {
1711	/* AVB_PHY_INT */
1712	RCAR_GP_PIN(2, 11),
1713};
1714static const unsigned int avb_phy_int_mux[] = {
1715	AVB_PHY_INT_MARK,
1716};
1717static const unsigned int avb_mdio_pins[] = {
1718	/* AVB_MDC, AVB_MDIO */
1719	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1720};
1721static const unsigned int avb_mdio_mux[] = {
1722	AVB_MDC_MARK, AVB_MDIO_MARK,
1723};
1724static const unsigned int avb_mii_pins[] = {
1725	/*
1726	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1727	 * AVB_TD1, AVB_TD2, AVB_TD3,
1728	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1729	 * AVB_RD1, AVB_RD2, AVB_RD3,
1730	 * AVB_TXCREFCLK
1731	 */
1732	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1733	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1734	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1735	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1736	PIN_AVB_TXCREFCLK,
1737};
1738static const unsigned int avb_mii_mux[] = {
1739	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1740	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1741	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1742	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1743	AVB_TXCREFCLK_MARK,
1744};
1745static const unsigned int avb_avtp_pps_pins[] = {
1746	/* AVB_AVTP_PPS */
1747	RCAR_GP_PIN(2, 6),
1748};
1749static const unsigned int avb_avtp_pps_mux[] = {
1750	AVB_AVTP_PPS_MARK,
1751};
1752static const unsigned int avb_avtp_match_a_pins[] = {
1753	/* AVB_AVTP_MATCH_A */
1754	RCAR_GP_PIN(2, 13),
1755};
1756static const unsigned int avb_avtp_match_a_mux[] = {
1757	AVB_AVTP_MATCH_A_MARK,
1758};
1759static const unsigned int avb_avtp_capture_a_pins[] = {
1760	/* AVB_AVTP_CAPTURE_A */
1761	RCAR_GP_PIN(2, 14),
1762};
1763static const unsigned int avb_avtp_capture_a_mux[] = {
1764	AVB_AVTP_CAPTURE_A_MARK,
1765};
1766static const unsigned int avb_avtp_match_b_pins[] = {
1767	/*  AVB_AVTP_MATCH_B */
1768	RCAR_GP_PIN(1, 8),
1769};
1770static const unsigned int avb_avtp_match_b_mux[] = {
1771	AVB_AVTP_MATCH_B_MARK,
1772};
1773static const unsigned int avb_avtp_capture_b_pins[] = {
1774	/* AVB_AVTP_CAPTURE_B */
1775	RCAR_GP_PIN(1, 11),
1776};
1777static const unsigned int avb_avtp_capture_b_mux[] = {
1778	AVB_AVTP_CAPTURE_B_MARK,
1779};
1780
1781/* - CAN ------------------------------------------------------------------ */
1782static const unsigned int can0_data_a_pins[] = {
1783	/* TX, RX */
1784	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
1785};
1786
1787static const unsigned int can0_data_a_mux[] = {
1788	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
1789};
1790
1791static const unsigned int can0_data_b_pins[] = {
1792	/* TX, RX */
1793	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
1794};
1795
1796static const unsigned int can0_data_b_mux[] = {
1797	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
1798};
1799
1800static const unsigned int can1_data_pins[] = {
1801	/* TX, RX */
1802	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
1803};
1804
1805static const unsigned int can1_data_mux[] = {
1806	CAN1_TX_MARK,		CAN1_RX_MARK,
1807};
1808
1809/* - CAN Clock -------------------------------------------------------------- */
1810static const unsigned int can_clk_pins[] = {
1811	/* CLK */
1812	RCAR_GP_PIN(1, 25),
1813};
1814
1815static const unsigned int can_clk_mux[] = {
1816	CAN_CLK_MARK,
1817};
1818
1819/* - CAN FD --------------------------------------------------------------- */
1820static const unsigned int canfd0_data_a_pins[] = {
1821	/* TX, RX */
1822	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1823};
1824
1825static const unsigned int canfd0_data_a_mux[] = {
1826	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1827};
1828
1829static const unsigned int canfd0_data_b_pins[] = {
1830	/* TX, RX */
1831	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1832};
1833
1834static const unsigned int canfd0_data_b_mux[] = {
1835	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1836};
1837
1838static const unsigned int canfd1_data_pins[] = {
1839	/* TX, RX */
1840	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1841};
1842
1843static const unsigned int canfd1_data_mux[] = {
1844	CANFD1_TX_MARK,         CANFD1_RX_MARK,
1845};
1846
1847#ifdef CONFIG_PINCTRL_PFC_R8A77965
1848/* - DRIF0 --------------------------------------------------------------- */
1849static const unsigned int drif0_ctrl_a_pins[] = {
1850	/* CLK, SYNC */
1851	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1852};
1853
1854static const unsigned int drif0_ctrl_a_mux[] = {
1855	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1856};
1857
1858static const unsigned int drif0_data0_a_pins[] = {
1859	/* D0 */
1860	RCAR_GP_PIN(6, 10),
1861};
1862
1863static const unsigned int drif0_data0_a_mux[] = {
1864	RIF0_D0_A_MARK,
1865};
1866
1867static const unsigned int drif0_data1_a_pins[] = {
1868	/* D1 */
1869	RCAR_GP_PIN(6, 7),
1870};
1871
1872static const unsigned int drif0_data1_a_mux[] = {
1873	RIF0_D1_A_MARK,
1874};
1875
1876static const unsigned int drif0_ctrl_b_pins[] = {
1877	/* CLK, SYNC */
1878	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1879};
1880
1881static const unsigned int drif0_ctrl_b_mux[] = {
1882	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1883};
1884
1885static const unsigned int drif0_data0_b_pins[] = {
1886	/* D0 */
1887	RCAR_GP_PIN(5, 1),
1888};
1889
1890static const unsigned int drif0_data0_b_mux[] = {
1891	RIF0_D0_B_MARK,
1892};
1893
1894static const unsigned int drif0_data1_b_pins[] = {
1895	/* D1 */
1896	RCAR_GP_PIN(5, 2),
1897};
1898
1899static const unsigned int drif0_data1_b_mux[] = {
1900	RIF0_D1_B_MARK,
1901};
1902
1903static const unsigned int drif0_ctrl_c_pins[] = {
1904	/* CLK, SYNC */
1905	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1906};
1907
1908static const unsigned int drif0_ctrl_c_mux[] = {
1909	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1910};
1911
1912static const unsigned int drif0_data0_c_pins[] = {
1913	/* D0 */
1914	RCAR_GP_PIN(5, 13),
1915};
1916
1917static const unsigned int drif0_data0_c_mux[] = {
1918	RIF0_D0_C_MARK,
1919};
1920
1921static const unsigned int drif0_data1_c_pins[] = {
1922	/* D1 */
1923	RCAR_GP_PIN(5, 14),
1924};
1925
1926static const unsigned int drif0_data1_c_mux[] = {
1927	RIF0_D1_C_MARK,
1928};
1929
1930/* - DRIF1 --------------------------------------------------------------- */
1931static const unsigned int drif1_ctrl_a_pins[] = {
1932	/* CLK, SYNC */
1933	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1934};
1935
1936static const unsigned int drif1_ctrl_a_mux[] = {
1937	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1938};
1939
1940static const unsigned int drif1_data0_a_pins[] = {
1941	/* D0 */
1942	RCAR_GP_PIN(6, 19),
1943};
1944
1945static const unsigned int drif1_data0_a_mux[] = {
1946	RIF1_D0_A_MARK,
1947};
1948
1949static const unsigned int drif1_data1_a_pins[] = {
1950	/* D1 */
1951	RCAR_GP_PIN(6, 20),
1952};
1953
1954static const unsigned int drif1_data1_a_mux[] = {
1955	RIF1_D1_A_MARK,
1956};
1957
1958static const unsigned int drif1_ctrl_b_pins[] = {
1959	/* CLK, SYNC */
1960	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1961};
1962
1963static const unsigned int drif1_ctrl_b_mux[] = {
1964	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1965};
1966
1967static const unsigned int drif1_data0_b_pins[] = {
1968	/* D0 */
1969	RCAR_GP_PIN(5, 7),
1970};
1971
1972static const unsigned int drif1_data0_b_mux[] = {
1973	RIF1_D0_B_MARK,
1974};
1975
1976static const unsigned int drif1_data1_b_pins[] = {
1977	/* D1 */
1978	RCAR_GP_PIN(5, 8),
1979};
1980
1981static const unsigned int drif1_data1_b_mux[] = {
1982	RIF1_D1_B_MARK,
1983};
1984
1985static const unsigned int drif1_ctrl_c_pins[] = {
1986	/* CLK, SYNC */
1987	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1988};
1989
1990static const unsigned int drif1_ctrl_c_mux[] = {
1991	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1992};
1993
1994static const unsigned int drif1_data0_c_pins[] = {
1995	/* D0 */
1996	RCAR_GP_PIN(5, 6),
1997};
1998
1999static const unsigned int drif1_data0_c_mux[] = {
2000	RIF1_D0_C_MARK,
2001};
2002
2003static const unsigned int drif1_data1_c_pins[] = {
2004	/* D1 */
2005	RCAR_GP_PIN(5, 10),
2006};
2007
2008static const unsigned int drif1_data1_c_mux[] = {
2009	RIF1_D1_C_MARK,
2010};
2011
2012/* - DRIF2 --------------------------------------------------------------- */
2013static const unsigned int drif2_ctrl_a_pins[] = {
2014	/* CLK, SYNC */
2015	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2016};
2017
2018static const unsigned int drif2_ctrl_a_mux[] = {
2019	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2020};
2021
2022static const unsigned int drif2_data0_a_pins[] = {
2023	/* D0 */
2024	RCAR_GP_PIN(6, 7),
2025};
2026
2027static const unsigned int drif2_data0_a_mux[] = {
2028	RIF2_D0_A_MARK,
2029};
2030
2031static const unsigned int drif2_data1_a_pins[] = {
2032	/* D1 */
2033	RCAR_GP_PIN(6, 10),
2034};
2035
2036static const unsigned int drif2_data1_a_mux[] = {
2037	RIF2_D1_A_MARK,
2038};
2039
2040static const unsigned int drif2_ctrl_b_pins[] = {
2041	/* CLK, SYNC */
2042	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2043};
2044
2045static const unsigned int drif2_ctrl_b_mux[] = {
2046	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2047};
2048
2049static const unsigned int drif2_data0_b_pins[] = {
2050	/* D0 */
2051	RCAR_GP_PIN(6, 30),
2052};
2053
2054static const unsigned int drif2_data0_b_mux[] = {
2055	RIF2_D0_B_MARK,
2056};
2057
2058static const unsigned int drif2_data1_b_pins[] = {
2059	/* D1 */
2060	RCAR_GP_PIN(6, 31),
2061};
2062
2063static const unsigned int drif2_data1_b_mux[] = {
2064	RIF2_D1_B_MARK,
2065};
2066
2067/* - DRIF3 --------------------------------------------------------------- */
2068static const unsigned int drif3_ctrl_a_pins[] = {
2069	/* CLK, SYNC */
2070	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2071};
2072
2073static const unsigned int drif3_ctrl_a_mux[] = {
2074	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2075};
2076
2077static const unsigned int drif3_data0_a_pins[] = {
2078	/* D0 */
2079	RCAR_GP_PIN(6, 19),
2080};
2081
2082static const unsigned int drif3_data0_a_mux[] = {
2083	RIF3_D0_A_MARK,
2084};
2085
2086static const unsigned int drif3_data1_a_pins[] = {
2087	/* D1 */
2088	RCAR_GP_PIN(6, 20),
2089};
2090
2091static const unsigned int drif3_data1_a_mux[] = {
2092	RIF3_D1_A_MARK,
2093};
2094
2095static const unsigned int drif3_ctrl_b_pins[] = {
2096	/* CLK, SYNC */
2097	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2098};
2099
2100static const unsigned int drif3_ctrl_b_mux[] = {
2101	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2102};
2103
2104static const unsigned int drif3_data0_b_pins[] = {
2105	/* D0 */
2106	RCAR_GP_PIN(6, 28),
2107};
2108
2109static const unsigned int drif3_data0_b_mux[] = {
2110	RIF3_D0_B_MARK,
2111};
2112
2113static const unsigned int drif3_data1_b_pins[] = {
2114	/* D1 */
2115	RCAR_GP_PIN(6, 29),
2116};
2117
2118static const unsigned int drif3_data1_b_mux[] = {
2119	RIF3_D1_B_MARK,
2120};
2121#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
2122
2123/* - DU --------------------------------------------------------------------- */
2124static const unsigned int du_rgb666_pins[] = {
2125	/* R[7:2], G[7:2], B[7:2] */
2126	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2127	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2128	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2129	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2130	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2131	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2132};
2133
2134static const unsigned int du_rgb666_mux[] = {
2135	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2136	DU_DR3_MARK, DU_DR2_MARK,
2137	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2138	DU_DG3_MARK, DU_DG2_MARK,
2139	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2140	DU_DB3_MARK, DU_DB2_MARK,
2141};
2142
2143static const unsigned int du_rgb888_pins[] = {
2144	/* R[7:0], G[7:0], B[7:0] */
2145	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2146	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2147	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2148	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2149	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2150	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2151	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2152	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2153	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2154};
2155
2156static const unsigned int du_rgb888_mux[] = {
2157	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2158	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2159	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2160	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2161	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2162	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2163};
2164
2165static const unsigned int du_clk_out_0_pins[] = {
2166	/* CLKOUT */
2167	RCAR_GP_PIN(1, 27),
2168};
2169
2170static const unsigned int du_clk_out_0_mux[] = {
2171	DU_DOTCLKOUT0_MARK
2172};
2173
2174static const unsigned int du_clk_out_1_pins[] = {
2175	/* CLKOUT */
2176	RCAR_GP_PIN(2, 3),
2177};
2178
2179static const unsigned int du_clk_out_1_mux[] = {
2180	DU_DOTCLKOUT1_MARK
2181};
2182
2183static const unsigned int du_sync_pins[] = {
2184	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2185	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2186};
2187
2188static const unsigned int du_sync_mux[] = {
2189	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2190};
2191
2192static const unsigned int du_oddf_pins[] = {
2193	/* EXDISP/EXODDF/EXCDE */
2194	RCAR_GP_PIN(2, 2),
2195};
2196
2197static const unsigned int du_oddf_mux[] = {
2198	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2199};
2200
2201static const unsigned int du_cde_pins[] = {
2202	/* CDE */
2203	RCAR_GP_PIN(2, 0),
2204};
2205
2206static const unsigned int du_cde_mux[] = {
2207	DU_CDE_MARK,
2208};
2209
2210static const unsigned int du_disp_pins[] = {
2211	/* DISP */
2212	RCAR_GP_PIN(2, 1),
2213};
2214
2215static const unsigned int du_disp_mux[] = {
2216	DU_DISP_MARK,
2217};
2218
2219/* - HSCIF0 ----------------------------------------------------------------- */
2220static const unsigned int hscif0_data_pins[] = {
2221	/* RX, TX */
2222	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2223};
2224
2225static const unsigned int hscif0_data_mux[] = {
2226	HRX0_MARK, HTX0_MARK,
2227};
2228
2229static const unsigned int hscif0_clk_pins[] = {
2230	/* SCK */
2231	RCAR_GP_PIN(5, 12),
2232};
2233
2234static const unsigned int hscif0_clk_mux[] = {
2235	HSCK0_MARK,
2236};
2237
2238static const unsigned int hscif0_ctrl_pins[] = {
2239	/* RTS, CTS */
2240	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2241};
2242
2243static const unsigned int hscif0_ctrl_mux[] = {
2244	HRTS0_N_MARK, HCTS0_N_MARK,
2245};
2246
2247/* - HSCIF1 ----------------------------------------------------------------- */
2248static const unsigned int hscif1_data_a_pins[] = {
2249	/* RX, TX */
2250	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2251};
2252
2253static const unsigned int hscif1_data_a_mux[] = {
2254	HRX1_A_MARK, HTX1_A_MARK,
2255};
2256
2257static const unsigned int hscif1_clk_a_pins[] = {
2258	/* SCK */
2259	RCAR_GP_PIN(6, 21),
2260};
2261
2262static const unsigned int hscif1_clk_a_mux[] = {
2263	HSCK1_A_MARK,
2264};
2265
2266static const unsigned int hscif1_ctrl_a_pins[] = {
2267	/* RTS, CTS */
2268	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2269};
2270
2271static const unsigned int hscif1_ctrl_a_mux[] = {
2272	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2273};
2274
2275static const unsigned int hscif1_data_b_pins[] = {
2276	/* RX, TX */
2277	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2278};
2279
2280static const unsigned int hscif1_data_b_mux[] = {
2281	HRX1_B_MARK, HTX1_B_MARK,
2282};
2283
2284static const unsigned int hscif1_clk_b_pins[] = {
2285	/* SCK */
2286	RCAR_GP_PIN(5, 0),
2287};
2288
2289static const unsigned int hscif1_clk_b_mux[] = {
2290	HSCK1_B_MARK,
2291};
2292
2293static const unsigned int hscif1_ctrl_b_pins[] = {
2294	/* RTS, CTS */
2295	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2296};
2297
2298static const unsigned int hscif1_ctrl_b_mux[] = {
2299	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2300};
2301
2302/* - HSCIF2 ----------------------------------------------------------------- */
2303static const unsigned int hscif2_data_a_pins[] = {
2304	/* RX, TX */
2305	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2306};
2307
2308static const unsigned int hscif2_data_a_mux[] = {
2309	HRX2_A_MARK, HTX2_A_MARK,
2310};
2311
2312static const unsigned int hscif2_clk_a_pins[] = {
2313	/* SCK */
2314	RCAR_GP_PIN(6, 10),
2315};
2316
2317static const unsigned int hscif2_clk_a_mux[] = {
2318	HSCK2_A_MARK,
2319};
2320
2321static const unsigned int hscif2_ctrl_a_pins[] = {
2322	/* RTS, CTS */
2323	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2324};
2325
2326static const unsigned int hscif2_ctrl_a_mux[] = {
2327	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2328};
2329
2330static const unsigned int hscif2_data_b_pins[] = {
2331	/* RX, TX */
2332	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2333};
2334
2335static const unsigned int hscif2_data_b_mux[] = {
2336	HRX2_B_MARK, HTX2_B_MARK,
2337};
2338
2339static const unsigned int hscif2_clk_b_pins[] = {
2340	/* SCK */
2341	RCAR_GP_PIN(6, 21),
2342};
2343
2344static const unsigned int hscif2_clk_b_mux[] = {
2345	HSCK2_B_MARK,
2346};
2347
2348static const unsigned int hscif2_ctrl_b_pins[] = {
2349	/* RTS, CTS */
2350	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2351};
2352
2353static const unsigned int hscif2_ctrl_b_mux[] = {
2354	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2355};
2356
2357static const unsigned int hscif2_data_c_pins[] = {
2358	/* RX, TX */
2359	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2360};
2361
2362static const unsigned int hscif2_data_c_mux[] = {
2363	HRX2_C_MARK, HTX2_C_MARK,
2364};
2365
2366static const unsigned int hscif2_clk_c_pins[] = {
2367	/* SCK */
2368	RCAR_GP_PIN(6, 24),
2369};
2370
2371static const unsigned int hscif2_clk_c_mux[] = {
2372	HSCK2_C_MARK,
2373};
2374
2375static const unsigned int hscif2_ctrl_c_pins[] = {
2376	/* RTS, CTS */
2377	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2378};
2379
2380static const unsigned int hscif2_ctrl_c_mux[] = {
2381	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2382};
2383
2384/* - HSCIF3 ----------------------------------------------------------------- */
2385static const unsigned int hscif3_data_a_pins[] = {
2386	/* RX, TX */
2387	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2388};
2389
2390static const unsigned int hscif3_data_a_mux[] = {
2391	HRX3_A_MARK, HTX3_A_MARK,
2392};
2393
2394static const unsigned int hscif3_clk_pins[] = {
2395	/* SCK */
2396	RCAR_GP_PIN(1, 22),
2397};
2398
2399static const unsigned int hscif3_clk_mux[] = {
2400	HSCK3_MARK,
2401};
2402
2403static const unsigned int hscif3_ctrl_pins[] = {
2404	/* RTS, CTS */
2405	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2406};
2407
2408static const unsigned int hscif3_ctrl_mux[] = {
2409	HRTS3_N_MARK, HCTS3_N_MARK,
2410};
2411
2412static const unsigned int hscif3_data_b_pins[] = {
2413	/* RX, TX */
2414	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2415};
2416
2417static const unsigned int hscif3_data_b_mux[] = {
2418	HRX3_B_MARK, HTX3_B_MARK,
2419};
2420
2421static const unsigned int hscif3_data_c_pins[] = {
2422	/* RX, TX */
2423	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2424};
2425
2426static const unsigned int hscif3_data_c_mux[] = {
2427	HRX3_C_MARK, HTX3_C_MARK,
2428};
2429
2430static const unsigned int hscif3_data_d_pins[] = {
2431	/* RX, TX */
2432	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2433};
2434
2435static const unsigned int hscif3_data_d_mux[] = {
2436	HRX3_D_MARK, HTX3_D_MARK,
2437};
2438
2439/* - HSCIF4 ----------------------------------------------------------------- */
2440static const unsigned int hscif4_data_a_pins[] = {
2441	/* RX, TX */
2442	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2443};
2444
2445static const unsigned int hscif4_data_a_mux[] = {
2446	HRX4_A_MARK, HTX4_A_MARK,
2447};
2448
2449static const unsigned int hscif4_clk_pins[] = {
2450	/* SCK */
2451	RCAR_GP_PIN(1, 11),
2452};
2453
2454static const unsigned int hscif4_clk_mux[] = {
2455	HSCK4_MARK,
2456};
2457
2458static const unsigned int hscif4_ctrl_pins[] = {
2459	/* RTS, CTS */
2460	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2461};
2462
2463static const unsigned int hscif4_ctrl_mux[] = {
2464	HRTS4_N_MARK, HCTS4_N_MARK,
2465};
2466
2467static const unsigned int hscif4_data_b_pins[] = {
2468	/* RX, TX */
2469	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2470};
2471
2472static const unsigned int hscif4_data_b_mux[] = {
2473	HRX4_B_MARK, HTX4_B_MARK,
2474};
2475
2476/* - I2C -------------------------------------------------------------------- */
2477static const unsigned int i2c0_pins[] = {
2478	/* SCL, SDA */
2479	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2480};
2481
2482static const unsigned int i2c0_mux[] = {
2483	SCL0_MARK, SDA0_MARK,
2484};
2485
2486static const unsigned int i2c1_a_pins[] = {
2487	/* SDA, SCL */
2488	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2489};
2490
2491static const unsigned int i2c1_a_mux[] = {
2492	SDA1_A_MARK, SCL1_A_MARK,
2493};
2494
2495static const unsigned int i2c1_b_pins[] = {
2496	/* SDA, SCL */
2497	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2498};
2499
2500static const unsigned int i2c1_b_mux[] = {
2501	SDA1_B_MARK, SCL1_B_MARK,
2502};
2503
2504static const unsigned int i2c2_a_pins[] = {
2505	/* SDA, SCL */
2506	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2507};
2508
2509static const unsigned int i2c2_a_mux[] = {
2510	SDA2_A_MARK, SCL2_A_MARK,
2511};
2512
2513static const unsigned int i2c2_b_pins[] = {
2514	/* SDA, SCL */
2515	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2516};
2517
2518static const unsigned int i2c2_b_mux[] = {
2519	SDA2_B_MARK, SCL2_B_MARK,
2520};
2521
2522static const unsigned int i2c3_pins[] = {
2523	/* SCL, SDA */
2524	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2525};
2526
2527static const unsigned int i2c3_mux[] = {
2528	SCL3_MARK, SDA3_MARK,
2529};
2530
2531static const unsigned int i2c5_pins[] = {
2532	/* SCL, SDA */
2533	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2534};
2535
2536static const unsigned int i2c5_mux[] = {
2537	SCL5_MARK, SDA5_MARK,
2538};
2539
2540static const unsigned int i2c6_a_pins[] = {
2541	/* SDA, SCL */
2542	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2543};
2544
2545static const unsigned int i2c6_a_mux[] = {
2546	SDA6_A_MARK, SCL6_A_MARK,
2547};
2548
2549static const unsigned int i2c6_b_pins[] = {
2550	/* SDA, SCL */
2551	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2552};
2553
2554static const unsigned int i2c6_b_mux[] = {
2555	SDA6_B_MARK, SCL6_B_MARK,
2556};
2557
2558static const unsigned int i2c6_c_pins[] = {
2559	/* SDA, SCL */
2560	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2561};
2562
2563static const unsigned int i2c6_c_mux[] = {
2564	SDA6_C_MARK, SCL6_C_MARK,
2565};
2566
2567/* - INTC-EX ---------------------------------------------------------------- */
2568static const unsigned int intc_ex_irq0_pins[] = {
2569	/* IRQ0 */
2570	RCAR_GP_PIN(2, 0),
2571};
2572static const unsigned int intc_ex_irq0_mux[] = {
2573	IRQ0_MARK,
2574};
2575static const unsigned int intc_ex_irq1_pins[] = {
2576	/* IRQ1 */
2577	RCAR_GP_PIN(2, 1),
2578};
2579static const unsigned int intc_ex_irq1_mux[] = {
2580	IRQ1_MARK,
2581};
2582static const unsigned int intc_ex_irq2_pins[] = {
2583	/* IRQ2 */
2584	RCAR_GP_PIN(2, 2),
2585};
2586static const unsigned int intc_ex_irq2_mux[] = {
2587	IRQ2_MARK,
2588};
2589static const unsigned int intc_ex_irq3_pins[] = {
2590	/* IRQ3 */
2591	RCAR_GP_PIN(2, 3),
2592};
2593static const unsigned int intc_ex_irq3_mux[] = {
2594	IRQ3_MARK,
2595};
2596static const unsigned int intc_ex_irq4_pins[] = {
2597	/* IRQ4 */
2598	RCAR_GP_PIN(2, 4),
2599};
2600static const unsigned int intc_ex_irq4_mux[] = {
2601	IRQ4_MARK,
2602};
2603static const unsigned int intc_ex_irq5_pins[] = {
2604	/* IRQ5 */
2605	RCAR_GP_PIN(2, 5),
2606};
2607static const unsigned int intc_ex_irq5_mux[] = {
2608	IRQ5_MARK,
2609};
2610
2611#ifdef CONFIG_PINCTRL_PFC_R8A77965
2612/* - MLB+ ------------------------------------------------------------------- */
2613static const unsigned int mlb_3pin_pins[] = {
2614	RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2615};
2616static const unsigned int mlb_3pin_mux[] = {
2617	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2618};
2619#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
2620
2621/* - MSIOF0 ----------------------------------------------------------------- */
2622static const unsigned int msiof0_clk_pins[] = {
2623	/* SCK */
2624	RCAR_GP_PIN(5, 17),
2625};
2626static const unsigned int msiof0_clk_mux[] = {
2627	MSIOF0_SCK_MARK,
2628};
2629static const unsigned int msiof0_sync_pins[] = {
2630	/* SYNC */
2631	RCAR_GP_PIN(5, 18),
2632};
2633static const unsigned int msiof0_sync_mux[] = {
2634	MSIOF0_SYNC_MARK,
2635};
2636static const unsigned int msiof0_ss1_pins[] = {
2637	/* SS1 */
2638	RCAR_GP_PIN(5, 19),
2639};
2640static const unsigned int msiof0_ss1_mux[] = {
2641	MSIOF0_SS1_MARK,
2642};
2643static const unsigned int msiof0_ss2_pins[] = {
2644	/* SS2 */
2645	RCAR_GP_PIN(5, 21),
2646};
2647static const unsigned int msiof0_ss2_mux[] = {
2648	MSIOF0_SS2_MARK,
2649};
2650static const unsigned int msiof0_txd_pins[] = {
2651	/* TXD */
2652	RCAR_GP_PIN(5, 20),
2653};
2654static const unsigned int msiof0_txd_mux[] = {
2655	MSIOF0_TXD_MARK,
2656};
2657static const unsigned int msiof0_rxd_pins[] = {
2658	/* RXD */
2659	RCAR_GP_PIN(5, 22),
2660};
2661static const unsigned int msiof0_rxd_mux[] = {
2662	MSIOF0_RXD_MARK,
2663};
2664/* - MSIOF1 ----------------------------------------------------------------- */
2665static const unsigned int msiof1_clk_a_pins[] = {
2666	/* SCK */
2667	RCAR_GP_PIN(6, 8),
2668};
2669static const unsigned int msiof1_clk_a_mux[] = {
2670	MSIOF1_SCK_A_MARK,
2671};
2672static const unsigned int msiof1_sync_a_pins[] = {
2673	/* SYNC */
2674	RCAR_GP_PIN(6, 9),
2675};
2676static const unsigned int msiof1_sync_a_mux[] = {
2677	MSIOF1_SYNC_A_MARK,
2678};
2679static const unsigned int msiof1_ss1_a_pins[] = {
2680	/* SS1 */
2681	RCAR_GP_PIN(6, 5),
2682};
2683static const unsigned int msiof1_ss1_a_mux[] = {
2684	MSIOF1_SS1_A_MARK,
2685};
2686static const unsigned int msiof1_ss2_a_pins[] = {
2687	/* SS2 */
2688	RCAR_GP_PIN(6, 6),
2689};
2690static const unsigned int msiof1_ss2_a_mux[] = {
2691	MSIOF1_SS2_A_MARK,
2692};
2693static const unsigned int msiof1_txd_a_pins[] = {
2694	/* TXD */
2695	RCAR_GP_PIN(6, 7),
2696};
2697static const unsigned int msiof1_txd_a_mux[] = {
2698	MSIOF1_TXD_A_MARK,
2699};
2700static const unsigned int msiof1_rxd_a_pins[] = {
2701	/* RXD */
2702	RCAR_GP_PIN(6, 10),
2703};
2704static const unsigned int msiof1_rxd_a_mux[] = {
2705	MSIOF1_RXD_A_MARK,
2706};
2707static const unsigned int msiof1_clk_b_pins[] = {
2708	/* SCK */
2709	RCAR_GP_PIN(5, 9),
2710};
2711static const unsigned int msiof1_clk_b_mux[] = {
2712	MSIOF1_SCK_B_MARK,
2713};
2714static const unsigned int msiof1_sync_b_pins[] = {
2715	/* SYNC */
2716	RCAR_GP_PIN(5, 3),
2717};
2718static const unsigned int msiof1_sync_b_mux[] = {
2719	MSIOF1_SYNC_B_MARK,
2720};
2721static const unsigned int msiof1_ss1_b_pins[] = {
2722	/* SS1 */
2723	RCAR_GP_PIN(5, 4),
2724};
2725static const unsigned int msiof1_ss1_b_mux[] = {
2726	MSIOF1_SS1_B_MARK,
2727};
2728static const unsigned int msiof1_ss2_b_pins[] = {
2729	/* SS2 */
2730	RCAR_GP_PIN(5, 0),
2731};
2732static const unsigned int msiof1_ss2_b_mux[] = {
2733	MSIOF1_SS2_B_MARK,
2734};
2735static const unsigned int msiof1_txd_b_pins[] = {
2736	/* TXD */
2737	RCAR_GP_PIN(5, 8),
2738};
2739static const unsigned int msiof1_txd_b_mux[] = {
2740	MSIOF1_TXD_B_MARK,
2741};
2742static const unsigned int msiof1_rxd_b_pins[] = {
2743	/* RXD */
2744	RCAR_GP_PIN(5, 7),
2745};
2746static const unsigned int msiof1_rxd_b_mux[] = {
2747	MSIOF1_RXD_B_MARK,
2748};
2749static const unsigned int msiof1_clk_c_pins[] = {
2750	/* SCK */
2751	RCAR_GP_PIN(6, 17),
2752};
2753static const unsigned int msiof1_clk_c_mux[] = {
2754	MSIOF1_SCK_C_MARK,
2755};
2756static const unsigned int msiof1_sync_c_pins[] = {
2757	/* SYNC */
2758	RCAR_GP_PIN(6, 18),
2759};
2760static const unsigned int msiof1_sync_c_mux[] = {
2761	MSIOF1_SYNC_C_MARK,
2762};
2763static const unsigned int msiof1_ss1_c_pins[] = {
2764	/* SS1 */
2765	RCAR_GP_PIN(6, 21),
2766};
2767static const unsigned int msiof1_ss1_c_mux[] = {
2768	MSIOF1_SS1_C_MARK,
2769};
2770static const unsigned int msiof1_ss2_c_pins[] = {
2771	/* SS2 */
2772	RCAR_GP_PIN(6, 27),
2773};
2774static const unsigned int msiof1_ss2_c_mux[] = {
2775	MSIOF1_SS2_C_MARK,
2776};
2777static const unsigned int msiof1_txd_c_pins[] = {
2778	/* TXD */
2779	RCAR_GP_PIN(6, 20),
2780};
2781static const unsigned int msiof1_txd_c_mux[] = {
2782	MSIOF1_TXD_C_MARK,
2783};
2784static const unsigned int msiof1_rxd_c_pins[] = {
2785	/* RXD */
2786	RCAR_GP_PIN(6, 19),
2787};
2788static const unsigned int msiof1_rxd_c_mux[] = {
2789	MSIOF1_RXD_C_MARK,
2790};
2791static const unsigned int msiof1_clk_d_pins[] = {
2792	/* SCK */
2793	RCAR_GP_PIN(5, 12),
2794};
2795static const unsigned int msiof1_clk_d_mux[] = {
2796	MSIOF1_SCK_D_MARK,
2797};
2798static const unsigned int msiof1_sync_d_pins[] = {
2799	/* SYNC */
2800	RCAR_GP_PIN(5, 15),
2801};
2802static const unsigned int msiof1_sync_d_mux[] = {
2803	MSIOF1_SYNC_D_MARK,
2804};
2805static const unsigned int msiof1_ss1_d_pins[] = {
2806	/* SS1 */
2807	RCAR_GP_PIN(5, 16),
2808};
2809static const unsigned int msiof1_ss1_d_mux[] = {
2810	MSIOF1_SS1_D_MARK,
2811};
2812static const unsigned int msiof1_ss2_d_pins[] = {
2813	/* SS2 */
2814	RCAR_GP_PIN(5, 21),
2815};
2816static const unsigned int msiof1_ss2_d_mux[] = {
2817	MSIOF1_SS2_D_MARK,
2818};
2819static const unsigned int msiof1_txd_d_pins[] = {
2820	/* TXD */
2821	RCAR_GP_PIN(5, 14),
2822};
2823static const unsigned int msiof1_txd_d_mux[] = {
2824	MSIOF1_TXD_D_MARK,
2825};
2826static const unsigned int msiof1_rxd_d_pins[] = {
2827	/* RXD */
2828	RCAR_GP_PIN(5, 13),
2829};
2830static const unsigned int msiof1_rxd_d_mux[] = {
2831	MSIOF1_RXD_D_MARK,
2832};
2833static const unsigned int msiof1_clk_e_pins[] = {
2834	/* SCK */
2835	RCAR_GP_PIN(3, 0),
2836};
2837static const unsigned int msiof1_clk_e_mux[] = {
2838	MSIOF1_SCK_E_MARK,
2839};
2840static const unsigned int msiof1_sync_e_pins[] = {
2841	/* SYNC */
2842	RCAR_GP_PIN(3, 1),
2843};
2844static const unsigned int msiof1_sync_e_mux[] = {
2845	MSIOF1_SYNC_E_MARK,
2846};
2847static const unsigned int msiof1_ss1_e_pins[] = {
2848	/* SS1 */
2849	RCAR_GP_PIN(3, 4),
2850};
2851static const unsigned int msiof1_ss1_e_mux[] = {
2852	MSIOF1_SS1_E_MARK,
2853};
2854static const unsigned int msiof1_ss2_e_pins[] = {
2855	/* SS2 */
2856	RCAR_GP_PIN(3, 5),
2857};
2858static const unsigned int msiof1_ss2_e_mux[] = {
2859	MSIOF1_SS2_E_MARK,
2860};
2861static const unsigned int msiof1_txd_e_pins[] = {
2862	/* TXD */
2863	RCAR_GP_PIN(3, 3),
2864};
2865static const unsigned int msiof1_txd_e_mux[] = {
2866	MSIOF1_TXD_E_MARK,
2867};
2868static const unsigned int msiof1_rxd_e_pins[] = {
2869	/* RXD */
2870	RCAR_GP_PIN(3, 2),
2871};
2872static const unsigned int msiof1_rxd_e_mux[] = {
2873	MSIOF1_RXD_E_MARK,
2874};
2875static const unsigned int msiof1_clk_f_pins[] = {
2876	/* SCK */
2877	RCAR_GP_PIN(5, 23),
2878};
2879static const unsigned int msiof1_clk_f_mux[] = {
2880	MSIOF1_SCK_F_MARK,
2881};
2882static const unsigned int msiof1_sync_f_pins[] = {
2883	/* SYNC */
2884	RCAR_GP_PIN(5, 24),
2885};
2886static const unsigned int msiof1_sync_f_mux[] = {
2887	MSIOF1_SYNC_F_MARK,
2888};
2889static const unsigned int msiof1_ss1_f_pins[] = {
2890	/* SS1 */
2891	RCAR_GP_PIN(6, 1),
2892};
2893static const unsigned int msiof1_ss1_f_mux[] = {
2894	MSIOF1_SS1_F_MARK,
2895};
2896static const unsigned int msiof1_ss2_f_pins[] = {
2897	/* SS2 */
2898	RCAR_GP_PIN(6, 2),
2899};
2900static const unsigned int msiof1_ss2_f_mux[] = {
2901	MSIOF1_SS2_F_MARK,
2902};
2903static const unsigned int msiof1_txd_f_pins[] = {
2904	/* TXD */
2905	RCAR_GP_PIN(6, 0),
2906};
2907static const unsigned int msiof1_txd_f_mux[] = {
2908	MSIOF1_TXD_F_MARK,
2909};
2910static const unsigned int msiof1_rxd_f_pins[] = {
2911	/* RXD */
2912	RCAR_GP_PIN(5, 25),
2913};
2914static const unsigned int msiof1_rxd_f_mux[] = {
2915	MSIOF1_RXD_F_MARK,
2916};
2917static const unsigned int msiof1_clk_g_pins[] = {
2918	/* SCK */
2919	RCAR_GP_PIN(3, 6),
2920};
2921static const unsigned int msiof1_clk_g_mux[] = {
2922	MSIOF1_SCK_G_MARK,
2923};
2924static const unsigned int msiof1_sync_g_pins[] = {
2925	/* SYNC */
2926	RCAR_GP_PIN(3, 7),
2927};
2928static const unsigned int msiof1_sync_g_mux[] = {
2929	MSIOF1_SYNC_G_MARK,
2930};
2931static const unsigned int msiof1_ss1_g_pins[] = {
2932	/* SS1 */
2933	RCAR_GP_PIN(3, 10),
2934};
2935static const unsigned int msiof1_ss1_g_mux[] = {
2936	MSIOF1_SS1_G_MARK,
2937};
2938static const unsigned int msiof1_ss2_g_pins[] = {
2939	/* SS2 */
2940	RCAR_GP_PIN(3, 11),
2941};
2942static const unsigned int msiof1_ss2_g_mux[] = {
2943	MSIOF1_SS2_G_MARK,
2944};
2945static const unsigned int msiof1_txd_g_pins[] = {
2946	/* TXD */
2947	RCAR_GP_PIN(3, 9),
2948};
2949static const unsigned int msiof1_txd_g_mux[] = {
2950	MSIOF1_TXD_G_MARK,
2951};
2952static const unsigned int msiof1_rxd_g_pins[] = {
2953	/* RXD */
2954	RCAR_GP_PIN(3, 8),
2955};
2956static const unsigned int msiof1_rxd_g_mux[] = {
2957	MSIOF1_RXD_G_MARK,
2958};
2959/* - MSIOF2 ----------------------------------------------------------------- */
2960static const unsigned int msiof2_clk_a_pins[] = {
2961	/* SCK */
2962	RCAR_GP_PIN(1, 9),
2963};
2964static const unsigned int msiof2_clk_a_mux[] = {
2965	MSIOF2_SCK_A_MARK,
2966};
2967static const unsigned int msiof2_sync_a_pins[] = {
2968	/* SYNC */
2969	RCAR_GP_PIN(1, 8),
2970};
2971static const unsigned int msiof2_sync_a_mux[] = {
2972	MSIOF2_SYNC_A_MARK,
2973};
2974static const unsigned int msiof2_ss1_a_pins[] = {
2975	/* SS1 */
2976	RCAR_GP_PIN(1, 6),
2977};
2978static const unsigned int msiof2_ss1_a_mux[] = {
2979	MSIOF2_SS1_A_MARK,
2980};
2981static const unsigned int msiof2_ss2_a_pins[] = {
2982	/* SS2 */
2983	RCAR_GP_PIN(1, 7),
2984};
2985static const unsigned int msiof2_ss2_a_mux[] = {
2986	MSIOF2_SS2_A_MARK,
2987};
2988static const unsigned int msiof2_txd_a_pins[] = {
2989	/* TXD */
2990	RCAR_GP_PIN(1, 11),
2991};
2992static const unsigned int msiof2_txd_a_mux[] = {
2993	MSIOF2_TXD_A_MARK,
2994};
2995static const unsigned int msiof2_rxd_a_pins[] = {
2996	/* RXD */
2997	RCAR_GP_PIN(1, 10),
2998};
2999static const unsigned int msiof2_rxd_a_mux[] = {
3000	MSIOF2_RXD_A_MARK,
3001};
3002static const unsigned int msiof2_clk_b_pins[] = {
3003	/* SCK */
3004	RCAR_GP_PIN(0, 4),
3005};
3006static const unsigned int msiof2_clk_b_mux[] = {
3007	MSIOF2_SCK_B_MARK,
3008};
3009static const unsigned int msiof2_sync_b_pins[] = {
3010	/* SYNC */
3011	RCAR_GP_PIN(0, 5),
3012};
3013static const unsigned int msiof2_sync_b_mux[] = {
3014	MSIOF2_SYNC_B_MARK,
3015};
3016static const unsigned int msiof2_ss1_b_pins[] = {
3017	/* SS1 */
3018	RCAR_GP_PIN(0, 0),
3019};
3020static const unsigned int msiof2_ss1_b_mux[] = {
3021	MSIOF2_SS1_B_MARK,
3022};
3023static const unsigned int msiof2_ss2_b_pins[] = {
3024	/* SS2 */
3025	RCAR_GP_PIN(0, 1),
3026};
3027static const unsigned int msiof2_ss2_b_mux[] = {
3028	MSIOF2_SS2_B_MARK,
3029};
3030static const unsigned int msiof2_txd_b_pins[] = {
3031	/* TXD */
3032	RCAR_GP_PIN(0, 7),
3033};
3034static const unsigned int msiof2_txd_b_mux[] = {
3035	MSIOF2_TXD_B_MARK,
3036};
3037static const unsigned int msiof2_rxd_b_pins[] = {
3038	/* RXD */
3039	RCAR_GP_PIN(0, 6),
3040};
3041static const unsigned int msiof2_rxd_b_mux[] = {
3042	MSIOF2_RXD_B_MARK,
3043};
3044static const unsigned int msiof2_clk_c_pins[] = {
3045	/* SCK */
3046	RCAR_GP_PIN(2, 12),
3047};
3048static const unsigned int msiof2_clk_c_mux[] = {
3049	MSIOF2_SCK_C_MARK,
3050};
3051static const unsigned int msiof2_sync_c_pins[] = {
3052	/* SYNC */
3053	RCAR_GP_PIN(2, 11),
3054};
3055static const unsigned int msiof2_sync_c_mux[] = {
3056	MSIOF2_SYNC_C_MARK,
3057};
3058static const unsigned int msiof2_ss1_c_pins[] = {
3059	/* SS1 */
3060	RCAR_GP_PIN(2, 10),
3061};
3062static const unsigned int msiof2_ss1_c_mux[] = {
3063	MSIOF2_SS1_C_MARK,
3064};
3065static const unsigned int msiof2_ss2_c_pins[] = {
3066	/* SS2 */
3067	RCAR_GP_PIN(2, 9),
3068};
3069static const unsigned int msiof2_ss2_c_mux[] = {
3070	MSIOF2_SS2_C_MARK,
3071};
3072static const unsigned int msiof2_txd_c_pins[] = {
3073	/* TXD */
3074	RCAR_GP_PIN(2, 14),
3075};
3076static const unsigned int msiof2_txd_c_mux[] = {
3077	MSIOF2_TXD_C_MARK,
3078};
3079static const unsigned int msiof2_rxd_c_pins[] = {
3080	/* RXD */
3081	RCAR_GP_PIN(2, 13),
3082};
3083static const unsigned int msiof2_rxd_c_mux[] = {
3084	MSIOF2_RXD_C_MARK,
3085};
3086static const unsigned int msiof2_clk_d_pins[] = {
3087	/* SCK */
3088	RCAR_GP_PIN(0, 8),
3089};
3090static const unsigned int msiof2_clk_d_mux[] = {
3091	MSIOF2_SCK_D_MARK,
3092};
3093static const unsigned int msiof2_sync_d_pins[] = {
3094	/* SYNC */
3095	RCAR_GP_PIN(0, 9),
3096};
3097static const unsigned int msiof2_sync_d_mux[] = {
3098	MSIOF2_SYNC_D_MARK,
3099};
3100static const unsigned int msiof2_ss1_d_pins[] = {
3101	/* SS1 */
3102	RCAR_GP_PIN(0, 12),
3103};
3104static const unsigned int msiof2_ss1_d_mux[] = {
3105	MSIOF2_SS1_D_MARK,
3106};
3107static const unsigned int msiof2_ss2_d_pins[] = {
3108	/* SS2 */
3109	RCAR_GP_PIN(0, 13),
3110};
3111static const unsigned int msiof2_ss2_d_mux[] = {
3112	MSIOF2_SS2_D_MARK,
3113};
3114static const unsigned int msiof2_txd_d_pins[] = {
3115	/* TXD */
3116	RCAR_GP_PIN(0, 11),
3117};
3118static const unsigned int msiof2_txd_d_mux[] = {
3119	MSIOF2_TXD_D_MARK,
3120};
3121static const unsigned int msiof2_rxd_d_pins[] = {
3122	/* RXD */
3123	RCAR_GP_PIN(0, 10),
3124};
3125static const unsigned int msiof2_rxd_d_mux[] = {
3126	MSIOF2_RXD_D_MARK,
3127};
3128/* - MSIOF3 ----------------------------------------------------------------- */
3129static const unsigned int msiof3_clk_a_pins[] = {
3130	/* SCK */
3131	RCAR_GP_PIN(0, 0),
3132};
3133static const unsigned int msiof3_clk_a_mux[] = {
3134	MSIOF3_SCK_A_MARK,
3135};
3136static const unsigned int msiof3_sync_a_pins[] = {
3137	/* SYNC */
3138	RCAR_GP_PIN(0, 1),
3139};
3140static const unsigned int msiof3_sync_a_mux[] = {
3141	MSIOF3_SYNC_A_MARK,
3142};
3143static const unsigned int msiof3_ss1_a_pins[] = {
3144	/* SS1 */
3145	RCAR_GP_PIN(0, 14),
3146};
3147static const unsigned int msiof3_ss1_a_mux[] = {
3148	MSIOF3_SS1_A_MARK,
3149};
3150static const unsigned int msiof3_ss2_a_pins[] = {
3151	/* SS2 */
3152	RCAR_GP_PIN(0, 15),
3153};
3154static const unsigned int msiof3_ss2_a_mux[] = {
3155	MSIOF3_SS2_A_MARK,
3156};
3157static const unsigned int msiof3_txd_a_pins[] = {
3158	/* TXD */
3159	RCAR_GP_PIN(0, 3),
3160};
3161static const unsigned int msiof3_txd_a_mux[] = {
3162	MSIOF3_TXD_A_MARK,
3163};
3164static const unsigned int msiof3_rxd_a_pins[] = {
3165	/* RXD */
3166	RCAR_GP_PIN(0, 2),
3167};
3168static const unsigned int msiof3_rxd_a_mux[] = {
3169	MSIOF3_RXD_A_MARK,
3170};
3171static const unsigned int msiof3_clk_b_pins[] = {
3172	/* SCK */
3173	RCAR_GP_PIN(1, 2),
3174};
3175static const unsigned int msiof3_clk_b_mux[] = {
3176	MSIOF3_SCK_B_MARK,
3177};
3178static const unsigned int msiof3_sync_b_pins[] = {
3179	/* SYNC */
3180	RCAR_GP_PIN(1, 0),
3181};
3182static const unsigned int msiof3_sync_b_mux[] = {
3183	MSIOF3_SYNC_B_MARK,
3184};
3185static const unsigned int msiof3_ss1_b_pins[] = {
3186	/* SS1 */
3187	RCAR_GP_PIN(1, 4),
3188};
3189static const unsigned int msiof3_ss1_b_mux[] = {
3190	MSIOF3_SS1_B_MARK,
3191};
3192static const unsigned int msiof3_ss2_b_pins[] = {
3193	/* SS2 */
3194	RCAR_GP_PIN(1, 5),
3195};
3196static const unsigned int msiof3_ss2_b_mux[] = {
3197	MSIOF3_SS2_B_MARK,
3198};
3199static const unsigned int msiof3_txd_b_pins[] = {
3200	/* TXD */
3201	RCAR_GP_PIN(1, 1),
3202};
3203static const unsigned int msiof3_txd_b_mux[] = {
3204	MSIOF3_TXD_B_MARK,
3205};
3206static const unsigned int msiof3_rxd_b_pins[] = {
3207	/* RXD */
3208	RCAR_GP_PIN(1, 3),
3209};
3210static const unsigned int msiof3_rxd_b_mux[] = {
3211	MSIOF3_RXD_B_MARK,
3212};
3213static const unsigned int msiof3_clk_c_pins[] = {
3214	/* SCK */
3215	RCAR_GP_PIN(1, 12),
3216};
3217static const unsigned int msiof3_clk_c_mux[] = {
3218	MSIOF3_SCK_C_MARK,
3219};
3220static const unsigned int msiof3_sync_c_pins[] = {
3221	/* SYNC */
3222	RCAR_GP_PIN(1, 13),
3223};
3224static const unsigned int msiof3_sync_c_mux[] = {
3225	MSIOF3_SYNC_C_MARK,
3226};
3227static const unsigned int msiof3_txd_c_pins[] = {
3228	/* TXD */
3229	RCAR_GP_PIN(1, 15),
3230};
3231static const unsigned int msiof3_txd_c_mux[] = {
3232	MSIOF3_TXD_C_MARK,
3233};
3234static const unsigned int msiof3_rxd_c_pins[] = {
3235	/* RXD */
3236	RCAR_GP_PIN(1, 14),
3237};
3238static const unsigned int msiof3_rxd_c_mux[] = {
3239	MSIOF3_RXD_C_MARK,
3240};
3241static const unsigned int msiof3_clk_d_pins[] = {
3242	/* SCK */
3243	RCAR_GP_PIN(1, 22),
3244};
3245static const unsigned int msiof3_clk_d_mux[] = {
3246	MSIOF3_SCK_D_MARK,
3247};
3248static const unsigned int msiof3_sync_d_pins[] = {
3249	/* SYNC */
3250	RCAR_GP_PIN(1, 23),
3251};
3252static const unsigned int msiof3_sync_d_mux[] = {
3253	MSIOF3_SYNC_D_MARK,
3254};
3255static const unsigned int msiof3_ss1_d_pins[] = {
3256	/* SS1 */
3257	RCAR_GP_PIN(1, 26),
3258};
3259static const unsigned int msiof3_ss1_d_mux[] = {
3260	MSIOF3_SS1_D_MARK,
3261};
3262static const unsigned int msiof3_txd_d_pins[] = {
3263	/* TXD */
3264	RCAR_GP_PIN(1, 25),
3265};
3266static const unsigned int msiof3_txd_d_mux[] = {
3267	MSIOF3_TXD_D_MARK,
3268};
3269static const unsigned int msiof3_rxd_d_pins[] = {
3270	/* RXD */
3271	RCAR_GP_PIN(1, 24),
3272};
3273static const unsigned int msiof3_rxd_d_mux[] = {
3274	MSIOF3_RXD_D_MARK,
3275};
3276static const unsigned int msiof3_clk_e_pins[] = {
3277	/* SCK */
3278	RCAR_GP_PIN(2, 3),
3279};
3280static const unsigned int msiof3_clk_e_mux[] = {
3281	MSIOF3_SCK_E_MARK,
3282};
3283static const unsigned int msiof3_sync_e_pins[] = {
3284	/* SYNC */
3285	RCAR_GP_PIN(2, 2),
3286};
3287static const unsigned int msiof3_sync_e_mux[] = {
3288	MSIOF3_SYNC_E_MARK,
3289};
3290static const unsigned int msiof3_ss1_e_pins[] = {
3291	/* SS1 */
3292	RCAR_GP_PIN(2, 1),
3293};
3294static const unsigned int msiof3_ss1_e_mux[] = {
3295	MSIOF3_SS1_E_MARK,
3296};
3297static const unsigned int msiof3_ss2_e_pins[] = {
3298	/* SS2 */
3299	RCAR_GP_PIN(2, 0),
3300};
3301static const unsigned int msiof3_ss2_e_mux[] = {
3302	MSIOF3_SS2_E_MARK,
3303};
3304static const unsigned int msiof3_txd_e_pins[] = {
3305	/* TXD */
3306	RCAR_GP_PIN(2, 5),
3307};
3308static const unsigned int msiof3_txd_e_mux[] = {
3309	MSIOF3_TXD_E_MARK,
3310};
3311static const unsigned int msiof3_rxd_e_pins[] = {
3312	/* RXD */
3313	RCAR_GP_PIN(2, 4),
3314};
3315static const unsigned int msiof3_rxd_e_mux[] = {
3316	MSIOF3_RXD_E_MARK,
3317};
3318
3319/* - PWM0 --------------------------------------------------------------------*/
3320static const unsigned int pwm0_pins[] = {
3321	/* PWM */
3322	RCAR_GP_PIN(2, 6),
3323};
3324static const unsigned int pwm0_mux[] = {
3325	PWM0_MARK,
3326};
3327/* - PWM1 --------------------------------------------------------------------*/
3328static const unsigned int pwm1_a_pins[] = {
3329	/* PWM */
3330	RCAR_GP_PIN(2, 7),
3331};
3332static const unsigned int pwm1_a_mux[] = {
3333	PWM1_A_MARK,
3334};
3335static const unsigned int pwm1_b_pins[] = {
3336	/* PWM */
3337	RCAR_GP_PIN(1, 8),
3338};
3339static const unsigned int pwm1_b_mux[] = {
3340	PWM1_B_MARK,
3341};
3342/* - PWM2 --------------------------------------------------------------------*/
3343static const unsigned int pwm2_a_pins[] = {
3344	/* PWM */
3345	RCAR_GP_PIN(2, 8),
3346};
3347static const unsigned int pwm2_a_mux[] = {
3348	PWM2_A_MARK,
3349};
3350static const unsigned int pwm2_b_pins[] = {
3351	/* PWM */
3352	RCAR_GP_PIN(1, 11),
3353};
3354static const unsigned int pwm2_b_mux[] = {
3355	PWM2_B_MARK,
3356};
3357/* - PWM3 --------------------------------------------------------------------*/
3358static const unsigned int pwm3_a_pins[] = {
3359	/* PWM */
3360	RCAR_GP_PIN(1, 0),
3361};
3362static const unsigned int pwm3_a_mux[] = {
3363	PWM3_A_MARK,
3364};
3365static const unsigned int pwm3_b_pins[] = {
3366	/* PWM */
3367	RCAR_GP_PIN(2, 2),
3368};
3369static const unsigned int pwm3_b_mux[] = {
3370	PWM3_B_MARK,
3371};
3372/* - PWM4 --------------------------------------------------------------------*/
3373static const unsigned int pwm4_a_pins[] = {
3374	/* PWM */
3375	RCAR_GP_PIN(1, 1),
3376};
3377static const unsigned int pwm4_a_mux[] = {
3378	PWM4_A_MARK,
3379};
3380static const unsigned int pwm4_b_pins[] = {
3381	/* PWM */
3382	RCAR_GP_PIN(2, 3),
3383};
3384static const unsigned int pwm4_b_mux[] = {
3385	PWM4_B_MARK,
3386};
3387/* - PWM5 --------------------------------------------------------------------*/
3388static const unsigned int pwm5_a_pins[] = {
3389	/* PWM */
3390	RCAR_GP_PIN(1, 2),
3391};
3392static const unsigned int pwm5_a_mux[] = {
3393	PWM5_A_MARK,
3394};
3395static const unsigned int pwm5_b_pins[] = {
3396	/* PWM */
3397	RCAR_GP_PIN(2, 4),
3398};
3399static const unsigned int pwm5_b_mux[] = {
3400	PWM5_B_MARK,
3401};
3402/* - PWM6 --------------------------------------------------------------------*/
3403static const unsigned int pwm6_a_pins[] = {
3404	/* PWM */
3405	RCAR_GP_PIN(1, 3),
3406};
3407static const unsigned int pwm6_a_mux[] = {
3408	PWM6_A_MARK,
3409};
3410static const unsigned int pwm6_b_pins[] = {
3411	/* PWM */
3412	RCAR_GP_PIN(2, 5),
3413};
3414static const unsigned int pwm6_b_mux[] = {
3415	PWM6_B_MARK,
3416};
3417
3418/* - QSPI0 ------------------------------------------------------------------ */
3419static const unsigned int qspi0_ctrl_pins[] = {
3420	/* QSPI0_SPCLK, QSPI0_SSL */
3421	PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3422};
3423static const unsigned int qspi0_ctrl_mux[] = {
3424	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3425};
3426static const unsigned int qspi0_data_pins[] = {
3427	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3428	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3429	/* QSPI0_IO2, QSPI0_IO3 */
3430	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3431};
3432static const unsigned int qspi0_data_mux[] = {
3433	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3434	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3435};
3436/* - QSPI1 ------------------------------------------------------------------ */
3437static const unsigned int qspi1_ctrl_pins[] = {
3438	/* QSPI1_SPCLK, QSPI1_SSL */
3439	PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3440};
3441static const unsigned int qspi1_ctrl_mux[] = {
3442	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3443};
3444static const unsigned int qspi1_data_pins[] = {
3445	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3446	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3447	/* QSPI1_IO2, QSPI1_IO3 */
3448	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3449};
3450static const unsigned int qspi1_data_mux[] = {
3451	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3452	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3453};
3454
3455/* - SATA --------------------------------------------------------------------*/
3456static const unsigned int sata0_devslp_a_pins[] = {
3457	/* DEVSLP */
3458	RCAR_GP_PIN(6, 16),
3459};
3460
3461static const unsigned int sata0_devslp_a_mux[] = {
3462	SATA_DEVSLP_A_MARK,
3463};
3464
3465static const unsigned int sata0_devslp_b_pins[] = {
3466	/* DEVSLP */
3467	RCAR_GP_PIN(4, 6),
3468};
3469
3470static const unsigned int sata0_devslp_b_mux[] = {
3471	SATA_DEVSLP_B_MARK,
3472};
3473
3474/* - SCIF0 ------------------------------------------------------------------ */
3475static const unsigned int scif0_data_pins[] = {
3476	/* RX, TX */
3477	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3478};
3479static const unsigned int scif0_data_mux[] = {
3480	RX0_MARK, TX0_MARK,
3481};
3482static const unsigned int scif0_clk_pins[] = {
3483	/* SCK */
3484	RCAR_GP_PIN(5, 0),
3485};
3486static const unsigned int scif0_clk_mux[] = {
3487	SCK0_MARK,
3488};
3489static const unsigned int scif0_ctrl_pins[] = {
3490	/* RTS, CTS */
3491	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3492};
3493static const unsigned int scif0_ctrl_mux[] = {
3494	RTS0_N_MARK, CTS0_N_MARK,
3495};
3496/* - SCIF1 ------------------------------------------------------------------ */
3497static const unsigned int scif1_data_a_pins[] = {
3498	/* RX, TX */
3499	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3500};
3501static const unsigned int scif1_data_a_mux[] = {
3502	RX1_A_MARK, TX1_A_MARK,
3503};
3504static const unsigned int scif1_clk_pins[] = {
3505	/* SCK */
3506	RCAR_GP_PIN(6, 21),
3507};
3508static const unsigned int scif1_clk_mux[] = {
3509	SCK1_MARK,
3510};
3511static const unsigned int scif1_ctrl_pins[] = {
3512	/* RTS, CTS */
3513	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3514};
3515static const unsigned int scif1_ctrl_mux[] = {
3516	RTS1_N_MARK, CTS1_N_MARK,
3517};
3518static const unsigned int scif1_data_b_pins[] = {
3519	/* RX, TX */
3520	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3521};
3522static const unsigned int scif1_data_b_mux[] = {
3523	RX1_B_MARK, TX1_B_MARK,
3524};
3525/* - SCIF2 ------------------------------------------------------------------ */
3526static const unsigned int scif2_data_a_pins[] = {
3527	/* RX, TX */
3528	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3529};
3530static const unsigned int scif2_data_a_mux[] = {
3531	RX2_A_MARK, TX2_A_MARK,
3532};
3533static const unsigned int scif2_clk_pins[] = {
3534	/* SCK */
3535	RCAR_GP_PIN(5, 9),
3536};
3537static const unsigned int scif2_clk_mux[] = {
3538	SCK2_MARK,
3539};
3540static const unsigned int scif2_data_b_pins[] = {
3541	/* RX, TX */
3542	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3543};
3544static const unsigned int scif2_data_b_mux[] = {
3545	RX2_B_MARK, TX2_B_MARK,
3546};
3547/* - SCIF3 ------------------------------------------------------------------ */
3548static const unsigned int scif3_data_a_pins[] = {
3549	/* RX, TX */
3550	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3551};
3552static const unsigned int scif3_data_a_mux[] = {
3553	RX3_A_MARK, TX3_A_MARK,
3554};
3555static const unsigned int scif3_clk_pins[] = {
3556	/* SCK */
3557	RCAR_GP_PIN(1, 22),
3558};
3559static const unsigned int scif3_clk_mux[] = {
3560	SCK3_MARK,
3561};
3562static const unsigned int scif3_ctrl_pins[] = {
3563	/* RTS, CTS */
3564	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3565};
3566static const unsigned int scif3_ctrl_mux[] = {
3567	RTS3_N_MARK, CTS3_N_MARK,
3568};
3569static const unsigned int scif3_data_b_pins[] = {
3570	/* RX, TX */
3571	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3572};
3573static const unsigned int scif3_data_b_mux[] = {
3574	RX3_B_MARK, TX3_B_MARK,
3575};
3576/* - SCIF4 ------------------------------------------------------------------ */
3577static const unsigned int scif4_data_a_pins[] = {
3578	/* RX, TX */
3579	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3580};
3581static const unsigned int scif4_data_a_mux[] = {
3582	RX4_A_MARK, TX4_A_MARK,
3583};
3584static const unsigned int scif4_clk_a_pins[] = {
3585	/* SCK */
3586	RCAR_GP_PIN(2, 10),
3587};
3588static const unsigned int scif4_clk_a_mux[] = {
3589	SCK4_A_MARK,
3590};
3591static const unsigned int scif4_ctrl_a_pins[] = {
3592	/* RTS, CTS */
3593	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3594};
3595static const unsigned int scif4_ctrl_a_mux[] = {
3596	RTS4_N_A_MARK, CTS4_N_A_MARK,
3597};
3598static const unsigned int scif4_data_b_pins[] = {
3599	/* RX, TX */
3600	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3601};
3602static const unsigned int scif4_data_b_mux[] = {
3603	RX4_B_MARK, TX4_B_MARK,
3604};
3605static const unsigned int scif4_clk_b_pins[] = {
3606	/* SCK */
3607	RCAR_GP_PIN(1, 5),
3608};
3609static const unsigned int scif4_clk_b_mux[] = {
3610	SCK4_B_MARK,
3611};
3612static const unsigned int scif4_ctrl_b_pins[] = {
3613	/* RTS, CTS */
3614	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3615};
3616static const unsigned int scif4_ctrl_b_mux[] = {
3617	RTS4_N_B_MARK, CTS4_N_B_MARK,
3618};
3619static const unsigned int scif4_data_c_pins[] = {
3620	/* RX, TX */
3621	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3622};
3623static const unsigned int scif4_data_c_mux[] = {
3624	RX4_C_MARK, TX4_C_MARK,
3625};
3626static const unsigned int scif4_clk_c_pins[] = {
3627	/* SCK */
3628	RCAR_GP_PIN(0, 8),
3629};
3630static const unsigned int scif4_clk_c_mux[] = {
3631	SCK4_C_MARK,
3632};
3633static const unsigned int scif4_ctrl_c_pins[] = {
3634	/* RTS, CTS */
3635	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3636};
3637static const unsigned int scif4_ctrl_c_mux[] = {
3638	RTS4_N_C_MARK, CTS4_N_C_MARK,
3639};
3640/* - SCIF5 ------------------------------------------------------------------ */
3641static const unsigned int scif5_data_a_pins[] = {
3642	/* RX, TX */
3643	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3644};
3645static const unsigned int scif5_data_a_mux[] = {
3646	RX5_A_MARK, TX5_A_MARK,
3647};
3648static const unsigned int scif5_clk_a_pins[] = {
3649	/* SCK */
3650	RCAR_GP_PIN(6, 21),
3651};
3652static const unsigned int scif5_clk_a_mux[] = {
3653	SCK5_A_MARK,
3654};
3655static const unsigned int scif5_data_b_pins[] = {
3656	/* RX, TX */
3657	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3658};
3659static const unsigned int scif5_data_b_mux[] = {
3660	RX5_B_MARK, TX5_B_MARK,
3661};
3662static const unsigned int scif5_clk_b_pins[] = {
3663	/* SCK */
3664	RCAR_GP_PIN(5, 0),
3665};
3666static const unsigned int scif5_clk_b_mux[] = {
3667	SCK5_B_MARK,
3668};
3669/* - SCIF Clock ------------------------------------------------------------- */
3670static const unsigned int scif_clk_a_pins[] = {
3671	/* SCIF_CLK */
3672	RCAR_GP_PIN(6, 23),
3673};
3674static const unsigned int scif_clk_a_mux[] = {
3675	SCIF_CLK_A_MARK,
3676};
3677static const unsigned int scif_clk_b_pins[] = {
3678	/* SCIF_CLK */
3679	RCAR_GP_PIN(5, 9),
3680};
3681static const unsigned int scif_clk_b_mux[] = {
3682	SCIF_CLK_B_MARK,
3683};
3684
3685/* - SDHI0 ------------------------------------------------------------------ */
3686static const unsigned int sdhi0_data_pins[] = {
3687	/* D[0:3] */
3688	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3689	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3690};
3691
3692static const unsigned int sdhi0_data_mux[] = {
3693	SD0_DAT0_MARK, SD0_DAT1_MARK,
3694	SD0_DAT2_MARK, SD0_DAT3_MARK,
3695};
3696
3697static const unsigned int sdhi0_ctrl_pins[] = {
3698	/* CLK, CMD */
3699	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3700};
3701
3702static const unsigned int sdhi0_ctrl_mux[] = {
3703	SD0_CLK_MARK, SD0_CMD_MARK,
3704};
3705
3706static const unsigned int sdhi0_cd_pins[] = {
3707	/* CD */
3708	RCAR_GP_PIN(3, 12),
3709};
3710
3711static const unsigned int sdhi0_cd_mux[] = {
3712	SD0_CD_MARK,
3713};
3714
3715static const unsigned int sdhi0_wp_pins[] = {
3716	/* WP */
3717	RCAR_GP_PIN(3, 13),
3718};
3719
3720static const unsigned int sdhi0_wp_mux[] = {
3721	SD0_WP_MARK,
3722};
3723
3724/* - SDHI1 ------------------------------------------------------------------ */
3725static const unsigned int sdhi1_data_pins[] = {
3726	/* D[0:3] */
3727	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3728	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3729};
3730
3731static const unsigned int sdhi1_data_mux[] = {
3732	SD1_DAT0_MARK, SD1_DAT1_MARK,
3733	SD1_DAT2_MARK, SD1_DAT3_MARK,
3734};
3735
3736static const unsigned int sdhi1_ctrl_pins[] = {
3737	/* CLK, CMD */
3738	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3739};
3740
3741static const unsigned int sdhi1_ctrl_mux[] = {
3742	SD1_CLK_MARK, SD1_CMD_MARK,
3743};
3744
3745static const unsigned int sdhi1_cd_pins[] = {
3746	/* CD */
3747	RCAR_GP_PIN(3, 14),
3748};
3749
3750static const unsigned int sdhi1_cd_mux[] = {
3751	SD1_CD_MARK,
3752};
3753
3754static const unsigned int sdhi1_wp_pins[] = {
3755	/* WP */
3756	RCAR_GP_PIN(3, 15),
3757};
3758
3759static const unsigned int sdhi1_wp_mux[] = {
3760	SD1_WP_MARK,
3761};
3762
3763/* - SDHI2 ------------------------------------------------------------------ */
3764static const unsigned int sdhi2_data_pins[] = {
3765	/* D[0:7] */
3766	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3767	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3768	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3769	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3770};
3771
3772static const unsigned int sdhi2_data_mux[] = {
3773	SD2_DAT0_MARK, SD2_DAT1_MARK,
3774	SD2_DAT2_MARK, SD2_DAT3_MARK,
3775	SD2_DAT4_MARK, SD2_DAT5_MARK,
3776	SD2_DAT6_MARK, SD2_DAT7_MARK,
3777};
3778
3779static const unsigned int sdhi2_ctrl_pins[] = {
3780	/* CLK, CMD */
3781	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3782};
3783
3784static const unsigned int sdhi2_ctrl_mux[] = {
3785	SD2_CLK_MARK, SD2_CMD_MARK,
3786};
3787
3788static const unsigned int sdhi2_cd_a_pins[] = {
3789	/* CD */
3790	RCAR_GP_PIN(4, 13),
3791};
3792
3793static const unsigned int sdhi2_cd_a_mux[] = {
3794	SD2_CD_A_MARK,
3795};
3796
3797static const unsigned int sdhi2_cd_b_pins[] = {
3798	/* CD */
3799	RCAR_GP_PIN(5, 10),
3800};
3801
3802static const unsigned int sdhi2_cd_b_mux[] = {
3803	SD2_CD_B_MARK,
3804};
3805
3806static const unsigned int sdhi2_wp_a_pins[] = {
3807	/* WP */
3808	RCAR_GP_PIN(4, 14),
3809};
3810
3811static const unsigned int sdhi2_wp_a_mux[] = {
3812	SD2_WP_A_MARK,
3813};
3814
3815static const unsigned int sdhi2_wp_b_pins[] = {
3816	/* WP */
3817	RCAR_GP_PIN(5, 11),
3818};
3819
3820static const unsigned int sdhi2_wp_b_mux[] = {
3821	SD2_WP_B_MARK,
3822};
3823
3824static const unsigned int sdhi2_ds_pins[] = {
3825	/* DS */
3826	RCAR_GP_PIN(4, 6),
3827};
3828
3829static const unsigned int sdhi2_ds_mux[] = {
3830	SD2_DS_MARK,
3831};
3832
3833/* - SDHI3 ------------------------------------------------------------------ */
3834static const unsigned int sdhi3_data_pins[] = {
3835	/* D[0:7] */
3836	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3837	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3838	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3839	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3840};
3841
3842static const unsigned int sdhi3_data_mux[] = {
3843	SD3_DAT0_MARK, SD3_DAT1_MARK,
3844	SD3_DAT2_MARK, SD3_DAT3_MARK,
3845	SD3_DAT4_MARK, SD3_DAT5_MARK,
3846	SD3_DAT6_MARK, SD3_DAT7_MARK,
3847};
3848
3849static const unsigned int sdhi3_ctrl_pins[] = {
3850	/* CLK, CMD */
3851	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3852};
3853
3854static const unsigned int sdhi3_ctrl_mux[] = {
3855	SD3_CLK_MARK, SD3_CMD_MARK,
3856};
3857
3858static const unsigned int sdhi3_cd_pins[] = {
3859	/* CD */
3860	RCAR_GP_PIN(4, 15),
3861};
3862
3863static const unsigned int sdhi3_cd_mux[] = {
3864	SD3_CD_MARK,
3865};
3866
3867static const unsigned int sdhi3_wp_pins[] = {
3868	/* WP */
3869	RCAR_GP_PIN(4, 16),
3870};
3871
3872static const unsigned int sdhi3_wp_mux[] = {
3873	SD3_WP_MARK,
3874};
3875
3876static const unsigned int sdhi3_ds_pins[] = {
3877	/* DS */
3878	RCAR_GP_PIN(4, 17),
3879};
3880
3881static const unsigned int sdhi3_ds_mux[] = {
3882	SD3_DS_MARK,
3883};
3884
3885/* - SSI -------------------------------------------------------------------- */
3886static const unsigned int ssi0_data_pins[] = {
3887	/* SDATA */
3888	RCAR_GP_PIN(6, 2),
3889};
3890static const unsigned int ssi0_data_mux[] = {
3891	SSI_SDATA0_MARK,
3892};
3893static const unsigned int ssi01239_ctrl_pins[] = {
3894	/* SCK, WS */
3895	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3896};
3897static const unsigned int ssi01239_ctrl_mux[] = {
3898	SSI_SCK01239_MARK, SSI_WS01239_MARK,
3899};
3900static const unsigned int ssi1_data_a_pins[] = {
3901	/* SDATA */
3902	RCAR_GP_PIN(6, 3),
3903};
3904static const unsigned int ssi1_data_a_mux[] = {
3905	SSI_SDATA1_A_MARK,
3906};
3907static const unsigned int ssi1_data_b_pins[] = {
3908	/* SDATA */
3909	RCAR_GP_PIN(5, 12),
3910};
3911static const unsigned int ssi1_data_b_mux[] = {
3912	SSI_SDATA1_B_MARK,
3913};
3914static const unsigned int ssi1_ctrl_a_pins[] = {
3915	/* SCK, WS */
3916	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3917};
3918static const unsigned int ssi1_ctrl_a_mux[] = {
3919	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3920};
3921static const unsigned int ssi1_ctrl_b_pins[] = {
3922	/* SCK, WS */
3923	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3924};
3925static const unsigned int ssi1_ctrl_b_mux[] = {
3926	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3927};
3928static const unsigned int ssi2_data_a_pins[] = {
3929	/* SDATA */
3930	RCAR_GP_PIN(6, 4),
3931};
3932static const unsigned int ssi2_data_a_mux[] = {
3933	SSI_SDATA2_A_MARK,
3934};
3935static const unsigned int ssi2_data_b_pins[] = {
3936	/* SDATA */
3937	RCAR_GP_PIN(5, 13),
3938};
3939static const unsigned int ssi2_data_b_mux[] = {
3940	SSI_SDATA2_B_MARK,
3941};
3942static const unsigned int ssi2_ctrl_a_pins[] = {
3943	/* SCK, WS */
3944	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3945};
3946static const unsigned int ssi2_ctrl_a_mux[] = {
3947	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3948};
3949static const unsigned int ssi2_ctrl_b_pins[] = {
3950	/* SCK, WS */
3951	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3952};
3953static const unsigned int ssi2_ctrl_b_mux[] = {
3954	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3955};
3956static const unsigned int ssi3_data_pins[] = {
3957	/* SDATA */
3958	RCAR_GP_PIN(6, 7),
3959};
3960static const unsigned int ssi3_data_mux[] = {
3961	SSI_SDATA3_MARK,
3962};
3963static const unsigned int ssi349_ctrl_pins[] = {
3964	/* SCK, WS */
3965	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3966};
3967static const unsigned int ssi349_ctrl_mux[] = {
3968	SSI_SCK349_MARK, SSI_WS349_MARK,
3969};
3970static const unsigned int ssi4_data_pins[] = {
3971	/* SDATA */
3972	RCAR_GP_PIN(6, 10),
3973};
3974static const unsigned int ssi4_data_mux[] = {
3975	SSI_SDATA4_MARK,
3976};
3977static const unsigned int ssi4_ctrl_pins[] = {
3978	/* SCK, WS */
3979	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3980};
3981static const unsigned int ssi4_ctrl_mux[] = {
3982	SSI_SCK4_MARK, SSI_WS4_MARK,
3983};
3984static const unsigned int ssi5_data_pins[] = {
3985	/* SDATA */
3986	RCAR_GP_PIN(6, 13),
3987};
3988static const unsigned int ssi5_data_mux[] = {
3989	SSI_SDATA5_MARK,
3990};
3991static const unsigned int ssi5_ctrl_pins[] = {
3992	/* SCK, WS */
3993	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3994};
3995static const unsigned int ssi5_ctrl_mux[] = {
3996	SSI_SCK5_MARK, SSI_WS5_MARK,
3997};
3998static const unsigned int ssi6_data_pins[] = {
3999	/* SDATA */
4000	RCAR_GP_PIN(6, 16),
4001};
4002static const unsigned int ssi6_data_mux[] = {
4003	SSI_SDATA6_MARK,
4004};
4005static const unsigned int ssi6_ctrl_pins[] = {
4006	/* SCK, WS */
4007	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4008};
4009static const unsigned int ssi6_ctrl_mux[] = {
4010	SSI_SCK6_MARK, SSI_WS6_MARK,
4011};
4012static const unsigned int ssi7_data_pins[] = {
4013	/* SDATA */
4014	RCAR_GP_PIN(6, 19),
4015};
4016static const unsigned int ssi7_data_mux[] = {
4017	SSI_SDATA7_MARK,
4018};
4019static const unsigned int ssi78_ctrl_pins[] = {
4020	/* SCK, WS */
4021	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4022};
4023static const unsigned int ssi78_ctrl_mux[] = {
4024	SSI_SCK78_MARK, SSI_WS78_MARK,
4025};
4026static const unsigned int ssi8_data_pins[] = {
4027	/* SDATA */
4028	RCAR_GP_PIN(6, 20),
4029};
4030static const unsigned int ssi8_data_mux[] = {
4031	SSI_SDATA8_MARK,
4032};
4033static const unsigned int ssi9_data_a_pins[] = {
4034	/* SDATA */
4035	RCAR_GP_PIN(6, 21),
4036};
4037static const unsigned int ssi9_data_a_mux[] = {
4038	SSI_SDATA9_A_MARK,
4039};
4040static const unsigned int ssi9_data_b_pins[] = {
4041	/* SDATA */
4042	RCAR_GP_PIN(5, 14),
4043};
4044static const unsigned int ssi9_data_b_mux[] = {
4045	SSI_SDATA9_B_MARK,
4046};
4047static const unsigned int ssi9_ctrl_a_pins[] = {
4048	/* SCK, WS */
4049	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4050};
4051static const unsigned int ssi9_ctrl_a_mux[] = {
4052	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4053};
4054static const unsigned int ssi9_ctrl_b_pins[] = {
4055	/* SCK, WS */
4056	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4057};
4058static const unsigned int ssi9_ctrl_b_mux[] = {
4059	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4060};
4061
4062/* - TMU -------------------------------------------------------------------- */
4063static const unsigned int tmu_tclk1_a_pins[] = {
4064	/* TCLK */
4065	RCAR_GP_PIN(6, 23),
4066};
4067
4068static const unsigned int tmu_tclk1_a_mux[] = {
4069	TCLK1_A_MARK,
4070};
4071
4072static const unsigned int tmu_tclk1_b_pins[] = {
4073	/* TCLK */
4074	RCAR_GP_PIN(5, 19),
4075};
4076
4077static const unsigned int tmu_tclk1_b_mux[] = {
4078	TCLK1_B_MARK,
4079};
4080
4081static const unsigned int tmu_tclk2_a_pins[] = {
4082	/* TCLK */
4083	RCAR_GP_PIN(6, 19),
4084};
4085
4086static const unsigned int tmu_tclk2_a_mux[] = {
4087	TCLK2_A_MARK,
4088};
4089
4090static const unsigned int tmu_tclk2_b_pins[] = {
4091	/* TCLK */
4092	RCAR_GP_PIN(6, 28),
4093};
4094
4095static const unsigned int tmu_tclk2_b_mux[] = {
4096	TCLK2_B_MARK,
4097};
4098
4099/* - TPU ------------------------------------------------------------------- */
4100static const unsigned int tpu_to0_pins[] = {
4101	/* TPU0TO0 */
4102	RCAR_GP_PIN(6, 28),
4103};
4104static const unsigned int tpu_to0_mux[] = {
4105	TPU0TO0_MARK,
4106};
4107static const unsigned int tpu_to1_pins[] = {
4108	/* TPU0TO1 */
4109	RCAR_GP_PIN(6, 29),
4110};
4111static const unsigned int tpu_to1_mux[] = {
4112	TPU0TO1_MARK,
4113};
4114static const unsigned int tpu_to2_pins[] = {
4115	/* TPU0TO2 */
4116	RCAR_GP_PIN(6, 30),
4117};
4118static const unsigned int tpu_to2_mux[] = {
4119	TPU0TO2_MARK,
4120};
4121static const unsigned int tpu_to3_pins[] = {
4122	/* TPU0TO3 */
4123	RCAR_GP_PIN(6, 31),
4124};
4125static const unsigned int tpu_to3_mux[] = {
4126	TPU0TO3_MARK,
4127};
4128
4129/* - USB0 ------------------------------------------------------------------- */
4130static const unsigned int usb0_pins[] = {
4131	/* PWEN, OVC */
4132	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4133};
4134
4135static const unsigned int usb0_mux[] = {
4136	USB0_PWEN_MARK, USB0_OVC_MARK,
4137};
4138
4139/* - USB1 ------------------------------------------------------------------- */
4140static const unsigned int usb1_pins[] = {
4141	/* PWEN, OVC */
4142	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4143};
4144
4145static const unsigned int usb1_mux[] = {
4146	USB1_PWEN_MARK, USB1_OVC_MARK,
4147};
4148
4149/* - USB30 ------------------------------------------------------------------ */
4150static const unsigned int usb30_pins[] = {
4151	/* PWEN, OVC */
4152	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4153};
4154
4155static const unsigned int usb30_mux[] = {
4156	USB30_PWEN_MARK, USB30_OVC_MARK,
4157};
4158
4159/* - VIN4 ------------------------------------------------------------------- */
4160static const unsigned int vin4_data18_a_pins[] = {
4161	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4162	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4163	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4164	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4165	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4166	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4167	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4168	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4169	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4170};
4171
4172static const unsigned int vin4_data18_a_mux[] = {
4173	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4174	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4175	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4176	VI4_DATA10_MARK, VI4_DATA11_MARK,
4177	VI4_DATA12_MARK, VI4_DATA13_MARK,
4178	VI4_DATA14_MARK, VI4_DATA15_MARK,
4179	VI4_DATA18_MARK, VI4_DATA19_MARK,
4180	VI4_DATA20_MARK, VI4_DATA21_MARK,
4181	VI4_DATA22_MARK, VI4_DATA23_MARK,
4182};
4183
4184static const unsigned int vin4_data_a_pins[] = {
4185	RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 9),
4186	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4187	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4188	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4189	RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 1),
4190	RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),
4191	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4192	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4193	RCAR_GP_PIN(0, 0),  RCAR_GP_PIN(0, 1),
4194	RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
4195	RCAR_GP_PIN(0, 4),  RCAR_GP_PIN(0, 5),
4196	RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 7),
4197};
4198
4199static const unsigned int vin4_data_a_mux[] = {
4200	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4201	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4202	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4203	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4204	VI4_DATA8_MARK,   VI4_DATA9_MARK,
4205	VI4_DATA10_MARK,  VI4_DATA11_MARK,
4206	VI4_DATA12_MARK,  VI4_DATA13_MARK,
4207	VI4_DATA14_MARK,  VI4_DATA15_MARK,
4208	VI4_DATA16_MARK,  VI4_DATA17_MARK,
4209	VI4_DATA18_MARK,  VI4_DATA19_MARK,
4210	VI4_DATA20_MARK,  VI4_DATA21_MARK,
4211	VI4_DATA22_MARK,  VI4_DATA23_MARK,
4212};
4213
4214static const unsigned int vin4_data18_b_pins[] = {
4215	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4216	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4217	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4218	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4219	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4220	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4221	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4222	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4223	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4224};
4225
4226static const unsigned int vin4_data18_b_mux[] = {
4227	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4228	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4229	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4230	VI4_DATA10_MARK, VI4_DATA11_MARK,
4231	VI4_DATA12_MARK, VI4_DATA13_MARK,
4232	VI4_DATA14_MARK, VI4_DATA15_MARK,
4233	VI4_DATA18_MARK, VI4_DATA19_MARK,
4234	VI4_DATA20_MARK, VI4_DATA21_MARK,
4235	VI4_DATA22_MARK, VI4_DATA23_MARK,
4236};
4237
4238static const unsigned int vin4_data_b_pins[] = {
4239	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4240	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4241	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4242	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4243	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4244	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4245	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4246	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4247	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4248	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4249	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4250	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4251};
4252
4253static const unsigned int vin4_data_b_mux[] = {
4254	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4255	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4256	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4257	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4258	VI4_DATA8_MARK,   VI4_DATA9_MARK,
4259	VI4_DATA10_MARK,  VI4_DATA11_MARK,
4260	VI4_DATA12_MARK,  VI4_DATA13_MARK,
4261	VI4_DATA14_MARK,  VI4_DATA15_MARK,
4262	VI4_DATA16_MARK,  VI4_DATA17_MARK,
4263	VI4_DATA18_MARK,  VI4_DATA19_MARK,
4264	VI4_DATA20_MARK,  VI4_DATA21_MARK,
4265	VI4_DATA22_MARK,  VI4_DATA23_MARK,
4266};
4267
4268static const unsigned int vin4_sync_pins[] = {
4269	/* VSYNC_N, HSYNC_N */
4270	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4271};
4272
4273static const unsigned int vin4_sync_mux[] = {
4274	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4275};
4276
4277static const unsigned int vin4_field_pins[] = {
4278	RCAR_GP_PIN(1, 16),
4279};
4280
4281static const unsigned int vin4_field_mux[] = {
4282	VI4_FIELD_MARK,
4283};
4284
4285static const unsigned int vin4_clkenb_pins[] = {
4286	RCAR_GP_PIN(1, 19),
4287};
4288
4289static const unsigned int vin4_clkenb_mux[] = {
4290	VI4_CLKENB_MARK,
4291};
4292
4293static const unsigned int vin4_clk_pins[] = {
4294	RCAR_GP_PIN(1, 27),
4295};
4296
4297static const unsigned int vin4_clk_mux[] = {
4298	VI4_CLK_MARK,
4299};
4300
4301/* - VIN5 ------------------------------------------------------------------- */
4302static const unsigned int vin5_data_pins[] = {
4303	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4304	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4305	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4306	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4307	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4308	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4309	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
4310	RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
4311};
4312
4313static const unsigned int vin5_data_mux[] = {
4314	VI5_DATA0_MARK, VI5_DATA1_MARK,
4315	VI5_DATA2_MARK, VI5_DATA3_MARK,
4316	VI5_DATA4_MARK, VI5_DATA5_MARK,
4317	VI5_DATA6_MARK, VI5_DATA7_MARK,
4318	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4319	VI5_DATA10_MARK, VI5_DATA11_MARK,
4320	VI5_DATA12_MARK, VI5_DATA13_MARK,
4321	VI5_DATA14_MARK, VI5_DATA15_MARK,
4322};
4323
4324static const unsigned int vin5_sync_pins[] = {
4325	/* VSYNC_N, HSYNC_N */
4326	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4327};
4328
4329static const unsigned int vin5_sync_mux[] = {
4330	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4331};
4332
4333static const unsigned int vin5_field_pins[] = {
4334	RCAR_GP_PIN(1, 11),
4335};
4336
4337static const unsigned int vin5_field_mux[] = {
4338	VI5_FIELD_MARK,
4339};
4340
4341static const unsigned int vin5_clkenb_pins[] = {
4342	RCAR_GP_PIN(1, 20),
4343};
4344
4345static const unsigned int vin5_clkenb_mux[] = {
4346	VI5_CLKENB_MARK,
4347};
4348
4349static const unsigned int vin5_clk_pins[] = {
4350	RCAR_GP_PIN(1, 21),
4351};
4352
4353static const unsigned int vin5_clk_mux[] = {
4354	VI5_CLK_MARK,
4355};
4356
4357static const struct {
4358	struct sh_pfc_pin_group common[326];
4359#ifdef CONFIG_PINCTRL_PFC_R8A77965
4360	struct sh_pfc_pin_group automotive[31];
4361#endif
4362} pinmux_groups = {
4363	.common = {
4364		SH_PFC_PIN_GROUP(audio_clk_a_a),
4365		SH_PFC_PIN_GROUP(audio_clk_a_b),
4366		SH_PFC_PIN_GROUP(audio_clk_a_c),
4367		SH_PFC_PIN_GROUP(audio_clk_b_a),
4368		SH_PFC_PIN_GROUP(audio_clk_b_b),
4369		SH_PFC_PIN_GROUP(audio_clk_c_a),
4370		SH_PFC_PIN_GROUP(audio_clk_c_b),
4371		SH_PFC_PIN_GROUP(audio_clkout_a),
4372		SH_PFC_PIN_GROUP(audio_clkout_b),
4373		SH_PFC_PIN_GROUP(audio_clkout_c),
4374		SH_PFC_PIN_GROUP(audio_clkout_d),
4375		SH_PFC_PIN_GROUP(audio_clkout1_a),
4376		SH_PFC_PIN_GROUP(audio_clkout1_b),
4377		SH_PFC_PIN_GROUP(audio_clkout2_a),
4378		SH_PFC_PIN_GROUP(audio_clkout2_b),
4379		SH_PFC_PIN_GROUP(audio_clkout3_a),
4380		SH_PFC_PIN_GROUP(audio_clkout3_b),
4381		SH_PFC_PIN_GROUP(avb_link),
4382		SH_PFC_PIN_GROUP(avb_magic),
4383		SH_PFC_PIN_GROUP(avb_phy_int),
4384		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
4385		SH_PFC_PIN_GROUP(avb_mdio),
4386		SH_PFC_PIN_GROUP(avb_mii),
4387		SH_PFC_PIN_GROUP(avb_avtp_pps),
4388		SH_PFC_PIN_GROUP(avb_avtp_match_a),
4389		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4390		SH_PFC_PIN_GROUP(avb_avtp_match_b),
4391		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4392		SH_PFC_PIN_GROUP(can0_data_a),
4393		SH_PFC_PIN_GROUP(can0_data_b),
4394		SH_PFC_PIN_GROUP(can1_data),
4395		SH_PFC_PIN_GROUP(can_clk),
4396		SH_PFC_PIN_GROUP(canfd0_data_a),
4397		SH_PFC_PIN_GROUP(canfd0_data_b),
4398		SH_PFC_PIN_GROUP(canfd1_data),
4399		SH_PFC_PIN_GROUP(du_rgb666),
4400		SH_PFC_PIN_GROUP(du_rgb888),
4401		SH_PFC_PIN_GROUP(du_clk_out_0),
4402		SH_PFC_PIN_GROUP(du_clk_out_1),
4403		SH_PFC_PIN_GROUP(du_sync),
4404		SH_PFC_PIN_GROUP(du_oddf),
4405		SH_PFC_PIN_GROUP(du_cde),
4406		SH_PFC_PIN_GROUP(du_disp),
4407		SH_PFC_PIN_GROUP(hscif0_data),
4408		SH_PFC_PIN_GROUP(hscif0_clk),
4409		SH_PFC_PIN_GROUP(hscif0_ctrl),
4410		SH_PFC_PIN_GROUP(hscif1_data_a),
4411		SH_PFC_PIN_GROUP(hscif1_clk_a),
4412		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4413		SH_PFC_PIN_GROUP(hscif1_data_b),
4414		SH_PFC_PIN_GROUP(hscif1_clk_b),
4415		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4416		SH_PFC_PIN_GROUP(hscif2_data_a),
4417		SH_PFC_PIN_GROUP(hscif2_clk_a),
4418		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4419		SH_PFC_PIN_GROUP(hscif2_data_b),
4420		SH_PFC_PIN_GROUP(hscif2_clk_b),
4421		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4422		SH_PFC_PIN_GROUP(hscif2_data_c),
4423		SH_PFC_PIN_GROUP(hscif2_clk_c),
4424		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4425		SH_PFC_PIN_GROUP(hscif3_data_a),
4426		SH_PFC_PIN_GROUP(hscif3_clk),
4427		SH_PFC_PIN_GROUP(hscif3_ctrl),
4428		SH_PFC_PIN_GROUP(hscif3_data_b),
4429		SH_PFC_PIN_GROUP(hscif3_data_c),
4430		SH_PFC_PIN_GROUP(hscif3_data_d),
4431		SH_PFC_PIN_GROUP(hscif4_data_a),
4432		SH_PFC_PIN_GROUP(hscif4_clk),
4433		SH_PFC_PIN_GROUP(hscif4_ctrl),
4434		SH_PFC_PIN_GROUP(hscif4_data_b),
4435		SH_PFC_PIN_GROUP(i2c0),
4436		SH_PFC_PIN_GROUP(i2c1_a),
4437		SH_PFC_PIN_GROUP(i2c1_b),
4438		SH_PFC_PIN_GROUP(i2c2_a),
4439		SH_PFC_PIN_GROUP(i2c2_b),
4440		SH_PFC_PIN_GROUP(i2c3),
4441		SH_PFC_PIN_GROUP(i2c5),
4442		SH_PFC_PIN_GROUP(i2c6_a),
4443		SH_PFC_PIN_GROUP(i2c6_b),
4444		SH_PFC_PIN_GROUP(i2c6_c),
4445		SH_PFC_PIN_GROUP(intc_ex_irq0),
4446		SH_PFC_PIN_GROUP(intc_ex_irq1),
4447		SH_PFC_PIN_GROUP(intc_ex_irq2),
4448		SH_PFC_PIN_GROUP(intc_ex_irq3),
4449		SH_PFC_PIN_GROUP(intc_ex_irq4),
4450		SH_PFC_PIN_GROUP(intc_ex_irq5),
4451		SH_PFC_PIN_GROUP(msiof0_clk),
4452		SH_PFC_PIN_GROUP(msiof0_sync),
4453		SH_PFC_PIN_GROUP(msiof0_ss1),
4454		SH_PFC_PIN_GROUP(msiof0_ss2),
4455		SH_PFC_PIN_GROUP(msiof0_txd),
4456		SH_PFC_PIN_GROUP(msiof0_rxd),
4457		SH_PFC_PIN_GROUP(msiof1_clk_a),
4458		SH_PFC_PIN_GROUP(msiof1_sync_a),
4459		SH_PFC_PIN_GROUP(msiof1_ss1_a),
4460		SH_PFC_PIN_GROUP(msiof1_ss2_a),
4461		SH_PFC_PIN_GROUP(msiof1_txd_a),
4462		SH_PFC_PIN_GROUP(msiof1_rxd_a),
4463		SH_PFC_PIN_GROUP(msiof1_clk_b),
4464		SH_PFC_PIN_GROUP(msiof1_sync_b),
4465		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4466		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4467		SH_PFC_PIN_GROUP(msiof1_txd_b),
4468		SH_PFC_PIN_GROUP(msiof1_rxd_b),
4469		SH_PFC_PIN_GROUP(msiof1_clk_c),
4470		SH_PFC_PIN_GROUP(msiof1_sync_c),
4471		SH_PFC_PIN_GROUP(msiof1_ss1_c),
4472		SH_PFC_PIN_GROUP(msiof1_ss2_c),
4473		SH_PFC_PIN_GROUP(msiof1_txd_c),
4474		SH_PFC_PIN_GROUP(msiof1_rxd_c),
4475		SH_PFC_PIN_GROUP(msiof1_clk_d),
4476		SH_PFC_PIN_GROUP(msiof1_sync_d),
4477		SH_PFC_PIN_GROUP(msiof1_ss1_d),
4478		SH_PFC_PIN_GROUP(msiof1_ss2_d),
4479		SH_PFC_PIN_GROUP(msiof1_txd_d),
4480		SH_PFC_PIN_GROUP(msiof1_rxd_d),
4481		SH_PFC_PIN_GROUP(msiof1_clk_e),
4482		SH_PFC_PIN_GROUP(msiof1_sync_e),
4483		SH_PFC_PIN_GROUP(msiof1_ss1_e),
4484		SH_PFC_PIN_GROUP(msiof1_ss2_e),
4485		SH_PFC_PIN_GROUP(msiof1_txd_e),
4486		SH_PFC_PIN_GROUP(msiof1_rxd_e),
4487		SH_PFC_PIN_GROUP(msiof1_clk_f),
4488		SH_PFC_PIN_GROUP(msiof1_sync_f),
4489		SH_PFC_PIN_GROUP(msiof1_ss1_f),
4490		SH_PFC_PIN_GROUP(msiof1_ss2_f),
4491		SH_PFC_PIN_GROUP(msiof1_txd_f),
4492		SH_PFC_PIN_GROUP(msiof1_rxd_f),
4493		SH_PFC_PIN_GROUP(msiof1_clk_g),
4494		SH_PFC_PIN_GROUP(msiof1_sync_g),
4495		SH_PFC_PIN_GROUP(msiof1_ss1_g),
4496		SH_PFC_PIN_GROUP(msiof1_ss2_g),
4497		SH_PFC_PIN_GROUP(msiof1_txd_g),
4498		SH_PFC_PIN_GROUP(msiof1_rxd_g),
4499		SH_PFC_PIN_GROUP(msiof2_clk_a),
4500		SH_PFC_PIN_GROUP(msiof2_sync_a),
4501		SH_PFC_PIN_GROUP(msiof2_ss1_a),
4502		SH_PFC_PIN_GROUP(msiof2_ss2_a),
4503		SH_PFC_PIN_GROUP(msiof2_txd_a),
4504		SH_PFC_PIN_GROUP(msiof2_rxd_a),
4505		SH_PFC_PIN_GROUP(msiof2_clk_b),
4506		SH_PFC_PIN_GROUP(msiof2_sync_b),
4507		SH_PFC_PIN_GROUP(msiof2_ss1_b),
4508		SH_PFC_PIN_GROUP(msiof2_ss2_b),
4509		SH_PFC_PIN_GROUP(msiof2_txd_b),
4510		SH_PFC_PIN_GROUP(msiof2_rxd_b),
4511		SH_PFC_PIN_GROUP(msiof2_clk_c),
4512		SH_PFC_PIN_GROUP(msiof2_sync_c),
4513		SH_PFC_PIN_GROUP(msiof2_ss1_c),
4514		SH_PFC_PIN_GROUP(msiof2_ss2_c),
4515		SH_PFC_PIN_GROUP(msiof2_txd_c),
4516		SH_PFC_PIN_GROUP(msiof2_rxd_c),
4517		SH_PFC_PIN_GROUP(msiof2_clk_d),
4518		SH_PFC_PIN_GROUP(msiof2_sync_d),
4519		SH_PFC_PIN_GROUP(msiof2_ss1_d),
4520		SH_PFC_PIN_GROUP(msiof2_ss2_d),
4521		SH_PFC_PIN_GROUP(msiof2_txd_d),
4522		SH_PFC_PIN_GROUP(msiof2_rxd_d),
4523		SH_PFC_PIN_GROUP(msiof3_clk_a),
4524		SH_PFC_PIN_GROUP(msiof3_sync_a),
4525		SH_PFC_PIN_GROUP(msiof3_ss1_a),
4526		SH_PFC_PIN_GROUP(msiof3_ss2_a),
4527		SH_PFC_PIN_GROUP(msiof3_txd_a),
4528		SH_PFC_PIN_GROUP(msiof3_rxd_a),
4529		SH_PFC_PIN_GROUP(msiof3_clk_b),
4530		SH_PFC_PIN_GROUP(msiof3_sync_b),
4531		SH_PFC_PIN_GROUP(msiof3_ss1_b),
4532		SH_PFC_PIN_GROUP(msiof3_ss2_b),
4533		SH_PFC_PIN_GROUP(msiof3_txd_b),
4534		SH_PFC_PIN_GROUP(msiof3_rxd_b),
4535		SH_PFC_PIN_GROUP(msiof3_clk_c),
4536		SH_PFC_PIN_GROUP(msiof3_sync_c),
4537		SH_PFC_PIN_GROUP(msiof3_txd_c),
4538		SH_PFC_PIN_GROUP(msiof3_rxd_c),
4539		SH_PFC_PIN_GROUP(msiof3_clk_d),
4540		SH_PFC_PIN_GROUP(msiof3_sync_d),
4541		SH_PFC_PIN_GROUP(msiof3_ss1_d),
4542		SH_PFC_PIN_GROUP(msiof3_txd_d),
4543		SH_PFC_PIN_GROUP(msiof3_rxd_d),
4544		SH_PFC_PIN_GROUP(msiof3_clk_e),
4545		SH_PFC_PIN_GROUP(msiof3_sync_e),
4546		SH_PFC_PIN_GROUP(msiof3_ss1_e),
4547		SH_PFC_PIN_GROUP(msiof3_ss2_e),
4548		SH_PFC_PIN_GROUP(msiof3_txd_e),
4549		SH_PFC_PIN_GROUP(msiof3_rxd_e),
4550		SH_PFC_PIN_GROUP(pwm0),
4551		SH_PFC_PIN_GROUP(pwm1_a),
4552		SH_PFC_PIN_GROUP(pwm1_b),
4553		SH_PFC_PIN_GROUP(pwm2_a),
4554		SH_PFC_PIN_GROUP(pwm2_b),
4555		SH_PFC_PIN_GROUP(pwm3_a),
4556		SH_PFC_PIN_GROUP(pwm3_b),
4557		SH_PFC_PIN_GROUP(pwm4_a),
4558		SH_PFC_PIN_GROUP(pwm4_b),
4559		SH_PFC_PIN_GROUP(pwm5_a),
4560		SH_PFC_PIN_GROUP(pwm5_b),
4561		SH_PFC_PIN_GROUP(pwm6_a),
4562		SH_PFC_PIN_GROUP(pwm6_b),
4563		SH_PFC_PIN_GROUP(qspi0_ctrl),
4564		BUS_DATA_PIN_GROUP(qspi0_data, 2),
4565		BUS_DATA_PIN_GROUP(qspi0_data, 4),
4566		SH_PFC_PIN_GROUP(qspi1_ctrl),
4567		BUS_DATA_PIN_GROUP(qspi1_data, 2),
4568		BUS_DATA_PIN_GROUP(qspi1_data, 4),
4569		SH_PFC_PIN_GROUP(sata0_devslp_a),
4570		SH_PFC_PIN_GROUP(sata0_devslp_b),
4571		SH_PFC_PIN_GROUP(scif0_data),
4572		SH_PFC_PIN_GROUP(scif0_clk),
4573		SH_PFC_PIN_GROUP(scif0_ctrl),
4574		SH_PFC_PIN_GROUP(scif1_data_a),
4575		SH_PFC_PIN_GROUP(scif1_clk),
4576		SH_PFC_PIN_GROUP(scif1_ctrl),
4577		SH_PFC_PIN_GROUP(scif1_data_b),
4578		SH_PFC_PIN_GROUP(scif2_data_a),
4579		SH_PFC_PIN_GROUP(scif2_clk),
4580		SH_PFC_PIN_GROUP(scif2_data_b),
4581		SH_PFC_PIN_GROUP(scif3_data_a),
4582		SH_PFC_PIN_GROUP(scif3_clk),
4583		SH_PFC_PIN_GROUP(scif3_ctrl),
4584		SH_PFC_PIN_GROUP(scif3_data_b),
4585		SH_PFC_PIN_GROUP(scif4_data_a),
4586		SH_PFC_PIN_GROUP(scif4_clk_a),
4587		SH_PFC_PIN_GROUP(scif4_ctrl_a),
4588		SH_PFC_PIN_GROUP(scif4_data_b),
4589		SH_PFC_PIN_GROUP(scif4_clk_b),
4590		SH_PFC_PIN_GROUP(scif4_ctrl_b),
4591		SH_PFC_PIN_GROUP(scif4_data_c),
4592		SH_PFC_PIN_GROUP(scif4_clk_c),
4593		SH_PFC_PIN_GROUP(scif4_ctrl_c),
4594		SH_PFC_PIN_GROUP(scif5_data_a),
4595		SH_PFC_PIN_GROUP(scif5_clk_a),
4596		SH_PFC_PIN_GROUP(scif5_data_b),
4597		SH_PFC_PIN_GROUP(scif5_clk_b),
4598		SH_PFC_PIN_GROUP(scif_clk_a),
4599		SH_PFC_PIN_GROUP(scif_clk_b),
4600		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4601		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4602		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4603		SH_PFC_PIN_GROUP(sdhi0_cd),
4604		SH_PFC_PIN_GROUP(sdhi0_wp),
4605		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4606		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4607		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4608		SH_PFC_PIN_GROUP(sdhi1_cd),
4609		SH_PFC_PIN_GROUP(sdhi1_wp),
4610		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4611		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4612		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4613		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4614		SH_PFC_PIN_GROUP(sdhi2_cd_a),
4615		SH_PFC_PIN_GROUP(sdhi2_wp_a),
4616		SH_PFC_PIN_GROUP(sdhi2_cd_b),
4617		SH_PFC_PIN_GROUP(sdhi2_wp_b),
4618		SH_PFC_PIN_GROUP(sdhi2_ds),
4619		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4620		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4621		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4622		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4623		SH_PFC_PIN_GROUP(sdhi3_cd),
4624		SH_PFC_PIN_GROUP(sdhi3_wp),
4625		SH_PFC_PIN_GROUP(sdhi3_ds),
4626		SH_PFC_PIN_GROUP(ssi0_data),
4627		SH_PFC_PIN_GROUP(ssi01239_ctrl),
4628		SH_PFC_PIN_GROUP(ssi1_data_a),
4629		SH_PFC_PIN_GROUP(ssi1_data_b),
4630		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4631		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4632		SH_PFC_PIN_GROUP(ssi2_data_a),
4633		SH_PFC_PIN_GROUP(ssi2_data_b),
4634		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4635		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4636		SH_PFC_PIN_GROUP(ssi3_data),
4637		SH_PFC_PIN_GROUP(ssi349_ctrl),
4638		SH_PFC_PIN_GROUP(ssi4_data),
4639		SH_PFC_PIN_GROUP(ssi4_ctrl),
4640		SH_PFC_PIN_GROUP(ssi5_data),
4641		SH_PFC_PIN_GROUP(ssi5_ctrl),
4642		SH_PFC_PIN_GROUP(ssi6_data),
4643		SH_PFC_PIN_GROUP(ssi6_ctrl),
4644		SH_PFC_PIN_GROUP(ssi7_data),
4645		SH_PFC_PIN_GROUP(ssi78_ctrl),
4646		SH_PFC_PIN_GROUP(ssi8_data),
4647		SH_PFC_PIN_GROUP(ssi9_data_a),
4648		SH_PFC_PIN_GROUP(ssi9_data_b),
4649		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4650		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4651		SH_PFC_PIN_GROUP(tmu_tclk1_a),
4652		SH_PFC_PIN_GROUP(tmu_tclk1_b),
4653		SH_PFC_PIN_GROUP(tmu_tclk2_a),
4654		SH_PFC_PIN_GROUP(tmu_tclk2_b),
4655		SH_PFC_PIN_GROUP(tpu_to0),
4656		SH_PFC_PIN_GROUP(tpu_to1),
4657		SH_PFC_PIN_GROUP(tpu_to2),
4658		SH_PFC_PIN_GROUP(tpu_to3),
4659		SH_PFC_PIN_GROUP(usb0),
4660		SH_PFC_PIN_GROUP(usb1),
4661		SH_PFC_PIN_GROUP(usb30),
4662		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4663		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4664		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4665		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4666		SH_PFC_PIN_GROUP(vin4_data18_a),
4667		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4668		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4669		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4670		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4671		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4672		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4673		SH_PFC_PIN_GROUP(vin4_data18_b),
4674		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4675		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4676		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4677		SH_PFC_PIN_GROUP(vin4_sync),
4678		SH_PFC_PIN_GROUP(vin4_field),
4679		SH_PFC_PIN_GROUP(vin4_clkenb),
4680		SH_PFC_PIN_GROUP(vin4_clk),
4681		BUS_DATA_PIN_GROUP(vin5_data, 8),
4682		BUS_DATA_PIN_GROUP(vin5_data, 10),
4683		BUS_DATA_PIN_GROUP(vin5_data, 12),
4684		BUS_DATA_PIN_GROUP(vin5_data, 16),
4685		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4686		SH_PFC_PIN_GROUP(vin5_sync),
4687		SH_PFC_PIN_GROUP(vin5_field),
4688		SH_PFC_PIN_GROUP(vin5_clkenb),
4689		SH_PFC_PIN_GROUP(vin5_clk),
4690	},
4691#ifdef CONFIG_PINCTRL_PFC_R8A77965
4692	.automotive = {
4693		SH_PFC_PIN_GROUP(drif0_ctrl_a),
4694		SH_PFC_PIN_GROUP(drif0_data0_a),
4695		SH_PFC_PIN_GROUP(drif0_data1_a),
4696		SH_PFC_PIN_GROUP(drif0_ctrl_b),
4697		SH_PFC_PIN_GROUP(drif0_data0_b),
4698		SH_PFC_PIN_GROUP(drif0_data1_b),
4699		SH_PFC_PIN_GROUP(drif0_ctrl_c),
4700		SH_PFC_PIN_GROUP(drif0_data0_c),
4701		SH_PFC_PIN_GROUP(drif0_data1_c),
4702		SH_PFC_PIN_GROUP(drif1_ctrl_a),
4703		SH_PFC_PIN_GROUP(drif1_data0_a),
4704		SH_PFC_PIN_GROUP(drif1_data1_a),
4705		SH_PFC_PIN_GROUP(drif1_ctrl_b),
4706		SH_PFC_PIN_GROUP(drif1_data0_b),
4707		SH_PFC_PIN_GROUP(drif1_data1_b),
4708		SH_PFC_PIN_GROUP(drif1_ctrl_c),
4709		SH_PFC_PIN_GROUP(drif1_data0_c),
4710		SH_PFC_PIN_GROUP(drif1_data1_c),
4711		SH_PFC_PIN_GROUP(drif2_ctrl_a),
4712		SH_PFC_PIN_GROUP(drif2_data0_a),
4713		SH_PFC_PIN_GROUP(drif2_data1_a),
4714		SH_PFC_PIN_GROUP(drif2_ctrl_b),
4715		SH_PFC_PIN_GROUP(drif2_data0_b),
4716		SH_PFC_PIN_GROUP(drif2_data1_b),
4717		SH_PFC_PIN_GROUP(drif3_ctrl_a),
4718		SH_PFC_PIN_GROUP(drif3_data0_a),
4719		SH_PFC_PIN_GROUP(drif3_data1_a),
4720		SH_PFC_PIN_GROUP(drif3_ctrl_b),
4721		SH_PFC_PIN_GROUP(drif3_data0_b),
4722		SH_PFC_PIN_GROUP(drif3_data1_b),
4723		SH_PFC_PIN_GROUP(mlb_3pin),
4724	}
4725#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4726};
4727
4728static const char * const audio_clk_groups[] = {
4729	"audio_clk_a_a",
4730	"audio_clk_a_b",
4731	"audio_clk_a_c",
4732	"audio_clk_b_a",
4733	"audio_clk_b_b",
4734	"audio_clk_c_a",
4735	"audio_clk_c_b",
4736	"audio_clkout_a",
4737	"audio_clkout_b",
4738	"audio_clkout_c",
4739	"audio_clkout_d",
4740	"audio_clkout1_a",
4741	"audio_clkout1_b",
4742	"audio_clkout2_a",
4743	"audio_clkout2_b",
4744	"audio_clkout3_a",
4745	"audio_clkout3_b",
4746};
4747
4748static const char * const avb_groups[] = {
4749	"avb_link",
4750	"avb_magic",
4751	"avb_phy_int",
4752	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
4753	"avb_mdio",
4754	"avb_mii",
4755	"avb_avtp_pps",
4756	"avb_avtp_match_a",
4757	"avb_avtp_capture_a",
4758	"avb_avtp_match_b",
4759	"avb_avtp_capture_b",
4760};
4761
4762static const char * const can0_groups[] = {
4763	"can0_data_a",
4764	"can0_data_b",
4765};
4766
4767static const char * const can1_groups[] = {
4768	"can1_data",
4769};
4770
4771static const char * const can_clk_groups[] = {
4772	"can_clk",
4773};
4774
4775static const char * const canfd0_groups[] = {
4776	"canfd0_data_a",
4777	"canfd0_data_b",
4778};
4779
4780static const char * const canfd1_groups[] = {
4781	"canfd1_data",
4782};
4783
4784#ifdef CONFIG_PINCTRL_PFC_R8A77965
4785static const char * const drif0_groups[] = {
4786	"drif0_ctrl_a",
4787	"drif0_data0_a",
4788	"drif0_data1_a",
4789	"drif0_ctrl_b",
4790	"drif0_data0_b",
4791	"drif0_data1_b",
4792	"drif0_ctrl_c",
4793	"drif0_data0_c",
4794	"drif0_data1_c",
4795};
4796
4797static const char * const drif1_groups[] = {
4798	"drif1_ctrl_a",
4799	"drif1_data0_a",
4800	"drif1_data1_a",
4801	"drif1_ctrl_b",
4802	"drif1_data0_b",
4803	"drif1_data1_b",
4804	"drif1_ctrl_c",
4805	"drif1_data0_c",
4806	"drif1_data1_c",
4807};
4808
4809static const char * const drif2_groups[] = {
4810	"drif2_ctrl_a",
4811	"drif2_data0_a",
4812	"drif2_data1_a",
4813	"drif2_ctrl_b",
4814	"drif2_data0_b",
4815	"drif2_data1_b",
4816};
4817
4818static const char * const drif3_groups[] = {
4819	"drif3_ctrl_a",
4820	"drif3_data0_a",
4821	"drif3_data1_a",
4822	"drif3_ctrl_b",
4823	"drif3_data0_b",
4824	"drif3_data1_b",
4825};
4826#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4827
4828static const char * const du_groups[] = {
4829	"du_rgb666",
4830	"du_rgb888",
4831	"du_clk_out_0",
4832	"du_clk_out_1",
4833	"du_sync",
4834	"du_oddf",
4835	"du_cde",
4836	"du_disp",
4837};
4838
4839static const char * const hscif0_groups[] = {
4840	"hscif0_data",
4841	"hscif0_clk",
4842	"hscif0_ctrl",
4843};
4844
4845static const char * const hscif1_groups[] = {
4846	"hscif1_data_a",
4847	"hscif1_clk_a",
4848	"hscif1_ctrl_a",
4849	"hscif1_data_b",
4850	"hscif1_clk_b",
4851	"hscif1_ctrl_b",
4852};
4853
4854static const char * const hscif2_groups[] = {
4855	"hscif2_data_a",
4856	"hscif2_clk_a",
4857	"hscif2_ctrl_a",
4858	"hscif2_data_b",
4859	"hscif2_clk_b",
4860	"hscif2_ctrl_b",
4861	"hscif2_data_c",
4862	"hscif2_clk_c",
4863	"hscif2_ctrl_c",
4864};
4865
4866static const char * const hscif3_groups[] = {
4867	"hscif3_data_a",
4868	"hscif3_clk",
4869	"hscif3_ctrl",
4870	"hscif3_data_b",
4871	"hscif3_data_c",
4872	"hscif3_data_d",
4873};
4874
4875static const char * const hscif4_groups[] = {
4876	"hscif4_data_a",
4877	"hscif4_clk",
4878	"hscif4_ctrl",
4879	"hscif4_data_b",
4880};
4881
4882static const char * const i2c0_groups[] = {
4883	"i2c0",
4884};
4885
4886static const char * const i2c1_groups[] = {
4887	"i2c1_a",
4888	"i2c1_b",
4889};
4890
4891static const char * const i2c2_groups[] = {
4892	"i2c2_a",
4893	"i2c2_b",
4894};
4895
4896static const char * const i2c3_groups[] = {
4897	"i2c3",
4898};
4899
4900static const char * const i2c5_groups[] = {
4901	"i2c5",
4902};
4903
4904static const char * const i2c6_groups[] = {
4905	"i2c6_a",
4906	"i2c6_b",
4907	"i2c6_c",
4908};
4909
4910static const char * const intc_ex_groups[] = {
4911	"intc_ex_irq0",
4912	"intc_ex_irq1",
4913	"intc_ex_irq2",
4914	"intc_ex_irq3",
4915	"intc_ex_irq4",
4916	"intc_ex_irq5",
4917};
4918
4919#ifdef CONFIG_PINCTRL_PFC_R8A77965
4920static const char * const mlb_3pin_groups[] = {
4921	"mlb_3pin",
4922};
4923#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4924
4925static const char * const msiof0_groups[] = {
4926	"msiof0_clk",
4927	"msiof0_sync",
4928	"msiof0_ss1",
4929	"msiof0_ss2",
4930	"msiof0_txd",
4931	"msiof0_rxd",
4932};
4933
4934static const char * const msiof1_groups[] = {
4935	"msiof1_clk_a",
4936	"msiof1_sync_a",
4937	"msiof1_ss1_a",
4938	"msiof1_ss2_a",
4939	"msiof1_txd_a",
4940	"msiof1_rxd_a",
4941	"msiof1_clk_b",
4942	"msiof1_sync_b",
4943	"msiof1_ss1_b",
4944	"msiof1_ss2_b",
4945	"msiof1_txd_b",
4946	"msiof1_rxd_b",
4947	"msiof1_clk_c",
4948	"msiof1_sync_c",
4949	"msiof1_ss1_c",
4950	"msiof1_ss2_c",
4951	"msiof1_txd_c",
4952	"msiof1_rxd_c",
4953	"msiof1_clk_d",
4954	"msiof1_sync_d",
4955	"msiof1_ss1_d",
4956	"msiof1_ss2_d",
4957	"msiof1_txd_d",
4958	"msiof1_rxd_d",
4959	"msiof1_clk_e",
4960	"msiof1_sync_e",
4961	"msiof1_ss1_e",
4962	"msiof1_ss2_e",
4963	"msiof1_txd_e",
4964	"msiof1_rxd_e",
4965	"msiof1_clk_f",
4966	"msiof1_sync_f",
4967	"msiof1_ss1_f",
4968	"msiof1_ss2_f",
4969	"msiof1_txd_f",
4970	"msiof1_rxd_f",
4971	"msiof1_clk_g",
4972	"msiof1_sync_g",
4973	"msiof1_ss1_g",
4974	"msiof1_ss2_g",
4975	"msiof1_txd_g",
4976	"msiof1_rxd_g",
4977};
4978
4979static const char * const msiof2_groups[] = {
4980	"msiof2_clk_a",
4981	"msiof2_sync_a",
4982	"msiof2_ss1_a",
4983	"msiof2_ss2_a",
4984	"msiof2_txd_a",
4985	"msiof2_rxd_a",
4986	"msiof2_clk_b",
4987	"msiof2_sync_b",
4988	"msiof2_ss1_b",
4989	"msiof2_ss2_b",
4990	"msiof2_txd_b",
4991	"msiof2_rxd_b",
4992	"msiof2_clk_c",
4993	"msiof2_sync_c",
4994	"msiof2_ss1_c",
4995	"msiof2_ss2_c",
4996	"msiof2_txd_c",
4997	"msiof2_rxd_c",
4998	"msiof2_clk_d",
4999	"msiof2_sync_d",
5000	"msiof2_ss1_d",
5001	"msiof2_ss2_d",
5002	"msiof2_txd_d",
5003	"msiof2_rxd_d",
5004};
5005
5006static const char * const msiof3_groups[] = {
5007	"msiof3_clk_a",
5008	"msiof3_sync_a",
5009	"msiof3_ss1_a",
5010	"msiof3_ss2_a",
5011	"msiof3_txd_a",
5012	"msiof3_rxd_a",
5013	"msiof3_clk_b",
5014	"msiof3_sync_b",
5015	"msiof3_ss1_b",
5016	"msiof3_ss2_b",
5017	"msiof3_txd_b",
5018	"msiof3_rxd_b",
5019	"msiof3_clk_c",
5020	"msiof3_sync_c",
5021	"msiof3_txd_c",
5022	"msiof3_rxd_c",
5023	"msiof3_clk_d",
5024	"msiof3_sync_d",
5025	"msiof3_ss1_d",
5026	"msiof3_txd_d",
5027	"msiof3_rxd_d",
5028	"msiof3_clk_e",
5029	"msiof3_sync_e",
5030	"msiof3_ss1_e",
5031	"msiof3_ss2_e",
5032	"msiof3_txd_e",
5033	"msiof3_rxd_e",
5034};
5035
5036static const char * const pwm0_groups[] = {
5037	"pwm0",
5038};
5039
5040static const char * const pwm1_groups[] = {
5041	"pwm1_a",
5042	"pwm1_b",
5043};
5044
5045static const char * const pwm2_groups[] = {
5046	"pwm2_a",
5047	"pwm2_b",
5048};
5049
5050static const char * const pwm3_groups[] = {
5051	"pwm3_a",
5052	"pwm3_b",
5053};
5054
5055static const char * const pwm4_groups[] = {
5056	"pwm4_a",
5057	"pwm4_b",
5058};
5059
5060static const char * const pwm5_groups[] = {
5061	"pwm5_a",
5062	"pwm5_b",
5063};
5064
5065static const char * const pwm6_groups[] = {
5066	"pwm6_a",
5067	"pwm6_b",
5068};
5069
5070static const char * const qspi0_groups[] = {
5071	"qspi0_ctrl",
5072	"qspi0_data2",
5073	"qspi0_data4",
5074};
5075
5076static const char * const qspi1_groups[] = {
5077	"qspi1_ctrl",
5078	"qspi1_data2",
5079	"qspi1_data4",
5080};
5081
5082static const char * const sata0_groups[] = {
5083	"sata0_devslp_a",
5084	"sata0_devslp_b",
5085};
5086
5087static const char * const scif0_groups[] = {
5088	"scif0_data",
5089	"scif0_clk",
5090	"scif0_ctrl",
5091};
5092
5093static const char * const scif1_groups[] = {
5094	"scif1_data_a",
5095	"scif1_clk",
5096	"scif1_ctrl",
5097	"scif1_data_b",
5098};
5099static const char * const scif2_groups[] = {
5100	"scif2_data_a",
5101	"scif2_clk",
5102	"scif2_data_b",
5103};
5104
5105static const char * const scif3_groups[] = {
5106	"scif3_data_a",
5107	"scif3_clk",
5108	"scif3_ctrl",
5109	"scif3_data_b",
5110};
5111
5112static const char * const scif4_groups[] = {
5113	"scif4_data_a",
5114	"scif4_clk_a",
5115	"scif4_ctrl_a",
5116	"scif4_data_b",
5117	"scif4_clk_b",
5118	"scif4_ctrl_b",
5119	"scif4_data_c",
5120	"scif4_clk_c",
5121	"scif4_ctrl_c",
5122};
5123
5124static const char * const scif5_groups[] = {
5125	"scif5_data_a",
5126	"scif5_clk_a",
5127	"scif5_data_b",
5128	"scif5_clk_b",
5129};
5130
5131static const char * const scif_clk_groups[] = {
5132	"scif_clk_a",
5133	"scif_clk_b",
5134};
5135
5136static const char * const sdhi0_groups[] = {
5137	"sdhi0_data1",
5138	"sdhi0_data4",
5139	"sdhi0_ctrl",
5140	"sdhi0_cd",
5141	"sdhi0_wp",
5142};
5143
5144static const char * const sdhi1_groups[] = {
5145	"sdhi1_data1",
5146	"sdhi1_data4",
5147	"sdhi1_ctrl",
5148	"sdhi1_cd",
5149	"sdhi1_wp",
5150};
5151
5152static const char * const sdhi2_groups[] = {
5153	"sdhi2_data1",
5154	"sdhi2_data4",
5155	"sdhi2_data8",
5156	"sdhi2_ctrl",
5157	"sdhi2_cd_a",
5158	"sdhi2_wp_a",
5159	"sdhi2_cd_b",
5160	"sdhi2_wp_b",
5161	"sdhi2_ds",
5162};
5163
5164static const char * const sdhi3_groups[] = {
5165	"sdhi3_data1",
5166	"sdhi3_data4",
5167	"sdhi3_data8",
5168	"sdhi3_ctrl",
5169	"sdhi3_cd",
5170	"sdhi3_wp",
5171	"sdhi3_ds",
5172};
5173
5174static const char * const ssi_groups[] = {
5175	"ssi0_data",
5176	"ssi01239_ctrl",
5177	"ssi1_data_a",
5178	"ssi1_data_b",
5179	"ssi1_ctrl_a",
5180	"ssi1_ctrl_b",
5181	"ssi2_data_a",
5182	"ssi2_data_b",
5183	"ssi2_ctrl_a",
5184	"ssi2_ctrl_b",
5185	"ssi3_data",
5186	"ssi349_ctrl",
5187	"ssi4_data",
5188	"ssi4_ctrl",
5189	"ssi5_data",
5190	"ssi5_ctrl",
5191	"ssi6_data",
5192	"ssi6_ctrl",
5193	"ssi7_data",
5194	"ssi78_ctrl",
5195	"ssi8_data",
5196	"ssi9_data_a",
5197	"ssi9_data_b",
5198	"ssi9_ctrl_a",
5199	"ssi9_ctrl_b",
5200};
5201
5202static const char * const tmu_groups[] = {
5203	"tmu_tclk1_a",
5204	"tmu_tclk1_b",
5205	"tmu_tclk2_a",
5206	"tmu_tclk2_b",
5207};
5208
5209static const char * const tpu_groups[] = {
5210	"tpu_to0",
5211	"tpu_to1",
5212	"tpu_to2",
5213	"tpu_to3",
5214};
5215
5216static const char * const usb0_groups[] = {
5217	"usb0",
5218};
5219
5220static const char * const usb1_groups[] = {
5221	"usb1",
5222};
5223
5224static const char * const usb30_groups[] = {
5225	"usb30",
5226};
5227
5228static const char * const vin4_groups[] = {
5229	"vin4_data8_a",
5230	"vin4_data10_a",
5231	"vin4_data12_a",
5232	"vin4_data16_a",
5233	"vin4_data18_a",
5234	"vin4_data20_a",
5235	"vin4_data24_a",
5236	"vin4_data8_b",
5237	"vin4_data10_b",
5238	"vin4_data12_b",
5239	"vin4_data16_b",
5240	"vin4_data18_b",
5241	"vin4_data20_b",
5242	"vin4_data24_b",
5243	"vin4_g8",
5244	"vin4_sync",
5245	"vin4_field",
5246	"vin4_clkenb",
5247	"vin4_clk",
5248};
5249
5250static const char * const vin5_groups[] = {
5251	"vin5_data8",
5252	"vin5_data10",
5253	"vin5_data12",
5254	"vin5_data16",
5255	"vin5_high8",
5256	"vin5_sync",
5257	"vin5_field",
5258	"vin5_clkenb",
5259	"vin5_clk",
5260};
5261
5262static const struct {
5263	struct sh_pfc_function common[53];
5264#ifdef CONFIG_PINCTRL_PFC_R8A77965
5265	struct sh_pfc_function automotive[5];
5266#endif
5267} pinmux_functions = {
5268	.common = {
5269		SH_PFC_FUNCTION(audio_clk),
5270		SH_PFC_FUNCTION(avb),
5271		SH_PFC_FUNCTION(can0),
5272		SH_PFC_FUNCTION(can1),
5273		SH_PFC_FUNCTION(can_clk),
5274		SH_PFC_FUNCTION(canfd0),
5275		SH_PFC_FUNCTION(canfd1),
5276		SH_PFC_FUNCTION(du),
5277		SH_PFC_FUNCTION(hscif0),
5278		SH_PFC_FUNCTION(hscif1),
5279		SH_PFC_FUNCTION(hscif2),
5280		SH_PFC_FUNCTION(hscif3),
5281		SH_PFC_FUNCTION(hscif4),
5282		SH_PFC_FUNCTION(i2c0),
5283		SH_PFC_FUNCTION(i2c1),
5284		SH_PFC_FUNCTION(i2c2),
5285		SH_PFC_FUNCTION(i2c3),
5286		SH_PFC_FUNCTION(i2c5),
5287		SH_PFC_FUNCTION(i2c6),
5288		SH_PFC_FUNCTION(intc_ex),
5289		SH_PFC_FUNCTION(msiof0),
5290		SH_PFC_FUNCTION(msiof1),
5291		SH_PFC_FUNCTION(msiof2),
5292		SH_PFC_FUNCTION(msiof3),
5293		SH_PFC_FUNCTION(pwm0),
5294		SH_PFC_FUNCTION(pwm1),
5295		SH_PFC_FUNCTION(pwm2),
5296		SH_PFC_FUNCTION(pwm3),
5297		SH_PFC_FUNCTION(pwm4),
5298		SH_PFC_FUNCTION(pwm5),
5299		SH_PFC_FUNCTION(pwm6),
5300		SH_PFC_FUNCTION(qspi0),
5301		SH_PFC_FUNCTION(qspi1),
5302		SH_PFC_FUNCTION(sata0),
5303		SH_PFC_FUNCTION(scif0),
5304		SH_PFC_FUNCTION(scif1),
5305		SH_PFC_FUNCTION(scif2),
5306		SH_PFC_FUNCTION(scif3),
5307		SH_PFC_FUNCTION(scif4),
5308		SH_PFC_FUNCTION(scif5),
5309		SH_PFC_FUNCTION(scif_clk),
5310		SH_PFC_FUNCTION(sdhi0),
5311		SH_PFC_FUNCTION(sdhi1),
5312		SH_PFC_FUNCTION(sdhi2),
5313		SH_PFC_FUNCTION(sdhi3),
5314		SH_PFC_FUNCTION(ssi),
5315		SH_PFC_FUNCTION(tmu),
5316		SH_PFC_FUNCTION(tpu),
5317		SH_PFC_FUNCTION(usb0),
5318		SH_PFC_FUNCTION(usb1),
5319		SH_PFC_FUNCTION(usb30),
5320		SH_PFC_FUNCTION(vin4),
5321		SH_PFC_FUNCTION(vin5),
5322	},
5323#ifdef CONFIG_PINCTRL_PFC_R8A77965
5324	.automotive = {
5325		SH_PFC_FUNCTION(drif0),
5326		SH_PFC_FUNCTION(drif1),
5327		SH_PFC_FUNCTION(drif2),
5328		SH_PFC_FUNCTION(drif3),
5329		SH_PFC_FUNCTION(mlb_3pin),
5330	}
5331#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
5332};
5333
5334static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5335#define F_(x, y)	FN_##y
5336#define FM(x)		FN_##x
5337	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5338			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5339				   1, 1, 1, 1, 1),
5340			     GROUP(
5341		/* GP0_31_16 RESERVED */
5342		GP_0_15_FN,	GPSR0_15,
5343		GP_0_14_FN,	GPSR0_14,
5344		GP_0_13_FN,	GPSR0_13,
5345		GP_0_12_FN,	GPSR0_12,
5346		GP_0_11_FN,	GPSR0_11,
5347		GP_0_10_FN,	GPSR0_10,
5348		GP_0_9_FN,	GPSR0_9,
5349		GP_0_8_FN,	GPSR0_8,
5350		GP_0_7_FN,	GPSR0_7,
5351		GP_0_6_FN,	GPSR0_6,
5352		GP_0_5_FN,	GPSR0_5,
5353		GP_0_4_FN,	GPSR0_4,
5354		GP_0_3_FN,	GPSR0_3,
5355		GP_0_2_FN,	GPSR0_2,
5356		GP_0_1_FN,	GPSR0_1,
5357		GP_0_0_FN,	GPSR0_0, ))
5358	},
5359	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5360		0, 0,
5361		0, 0,
5362		0, 0,
5363		GP_1_28_FN,	GPSR1_28,
5364		GP_1_27_FN,	GPSR1_27,
5365		GP_1_26_FN,	GPSR1_26,
5366		GP_1_25_FN,	GPSR1_25,
5367		GP_1_24_FN,	GPSR1_24,
5368		GP_1_23_FN,	GPSR1_23,
5369		GP_1_22_FN,	GPSR1_22,
5370		GP_1_21_FN,	GPSR1_21,
5371		GP_1_20_FN,	GPSR1_20,
5372		GP_1_19_FN,	GPSR1_19,
5373		GP_1_18_FN,	GPSR1_18,
5374		GP_1_17_FN,	GPSR1_17,
5375		GP_1_16_FN,	GPSR1_16,
5376		GP_1_15_FN,	GPSR1_15,
5377		GP_1_14_FN,	GPSR1_14,
5378		GP_1_13_FN,	GPSR1_13,
5379		GP_1_12_FN,	GPSR1_12,
5380		GP_1_11_FN,	GPSR1_11,
5381		GP_1_10_FN,	GPSR1_10,
5382		GP_1_9_FN,	GPSR1_9,
5383		GP_1_8_FN,	GPSR1_8,
5384		GP_1_7_FN,	GPSR1_7,
5385		GP_1_6_FN,	GPSR1_6,
5386		GP_1_5_FN,	GPSR1_5,
5387		GP_1_4_FN,	GPSR1_4,
5388		GP_1_3_FN,	GPSR1_3,
5389		GP_1_2_FN,	GPSR1_2,
5390		GP_1_1_FN,	GPSR1_1,
5391		GP_1_0_FN,	GPSR1_0, ))
5392	},
5393	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5394			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5395				   1, 1, 1, 1),
5396			     GROUP(
5397		/* GP2_31_15 RESERVED */
5398		GP_2_14_FN,	GPSR2_14,
5399		GP_2_13_FN,	GPSR2_13,
5400		GP_2_12_FN,	GPSR2_12,
5401		GP_2_11_FN,	GPSR2_11,
5402		GP_2_10_FN,	GPSR2_10,
5403		GP_2_9_FN,	GPSR2_9,
5404		GP_2_8_FN,	GPSR2_8,
5405		GP_2_7_FN,	GPSR2_7,
5406		GP_2_6_FN,	GPSR2_6,
5407		GP_2_5_FN,	GPSR2_5,
5408		GP_2_4_FN,	GPSR2_4,
5409		GP_2_3_FN,	GPSR2_3,
5410		GP_2_2_FN,	GPSR2_2,
5411		GP_2_1_FN,	GPSR2_1,
5412		GP_2_0_FN,	GPSR2_0, ))
5413	},
5414	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5415			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5416				   1, 1, 1, 1, 1),
5417			     GROUP(
5418		/* GP3_31_16 RESERVED */
5419		GP_3_15_FN,	GPSR3_15,
5420		GP_3_14_FN,	GPSR3_14,
5421		GP_3_13_FN,	GPSR3_13,
5422		GP_3_12_FN,	GPSR3_12,
5423		GP_3_11_FN,	GPSR3_11,
5424		GP_3_10_FN,	GPSR3_10,
5425		GP_3_9_FN,	GPSR3_9,
5426		GP_3_8_FN,	GPSR3_8,
5427		GP_3_7_FN,	GPSR3_7,
5428		GP_3_6_FN,	GPSR3_6,
5429		GP_3_5_FN,	GPSR3_5,
5430		GP_3_4_FN,	GPSR3_4,
5431		GP_3_3_FN,	GPSR3_3,
5432		GP_3_2_FN,	GPSR3_2,
5433		GP_3_1_FN,	GPSR3_1,
5434		GP_3_0_FN,	GPSR3_0, ))
5435	},
5436	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5437			     GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5438				   1, 1, 1, 1, 1, 1, 1),
5439			     GROUP(
5440		/* GP4_31_18 RESERVED */
5441		GP_4_17_FN,	GPSR4_17,
5442		GP_4_16_FN,	GPSR4_16,
5443		GP_4_15_FN,	GPSR4_15,
5444		GP_4_14_FN,	GPSR4_14,
5445		GP_4_13_FN,	GPSR4_13,
5446		GP_4_12_FN,	GPSR4_12,
5447		GP_4_11_FN,	GPSR4_11,
5448		GP_4_10_FN,	GPSR4_10,
5449		GP_4_9_FN,	GPSR4_9,
5450		GP_4_8_FN,	GPSR4_8,
5451		GP_4_7_FN,	GPSR4_7,
5452		GP_4_6_FN,	GPSR4_6,
5453		GP_4_5_FN,	GPSR4_5,
5454		GP_4_4_FN,	GPSR4_4,
5455		GP_4_3_FN,	GPSR4_3,
5456		GP_4_2_FN,	GPSR4_2,
5457		GP_4_1_FN,	GPSR4_1,
5458		GP_4_0_FN,	GPSR4_0, ))
5459	},
5460	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5461		0, 0,
5462		0, 0,
5463		0, 0,
5464		0, 0,
5465		0, 0,
5466		0, 0,
5467		GP_5_25_FN,	GPSR5_25,
5468		GP_5_24_FN,	GPSR5_24,
5469		GP_5_23_FN,	GPSR5_23,
5470		GP_5_22_FN,	GPSR5_22,
5471		GP_5_21_FN,	GPSR5_21,
5472		GP_5_20_FN,	GPSR5_20,
5473		GP_5_19_FN,	GPSR5_19,
5474		GP_5_18_FN,	GPSR5_18,
5475		GP_5_17_FN,	GPSR5_17,
5476		GP_5_16_FN,	GPSR5_16,
5477		GP_5_15_FN,	GPSR5_15,
5478		GP_5_14_FN,	GPSR5_14,
5479		GP_5_13_FN,	GPSR5_13,
5480		GP_5_12_FN,	GPSR5_12,
5481		GP_5_11_FN,	GPSR5_11,
5482		GP_5_10_FN,	GPSR5_10,
5483		GP_5_9_FN,	GPSR5_9,
5484		GP_5_8_FN,	GPSR5_8,
5485		GP_5_7_FN,	GPSR5_7,
5486		GP_5_6_FN,	GPSR5_6,
5487		GP_5_5_FN,	GPSR5_5,
5488		GP_5_4_FN,	GPSR5_4,
5489		GP_5_3_FN,	GPSR5_3,
5490		GP_5_2_FN,	GPSR5_2,
5491		GP_5_1_FN,	GPSR5_1,
5492		GP_5_0_FN,	GPSR5_0, ))
5493	},
5494	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5495		GP_6_31_FN,	GPSR6_31,
5496		GP_6_30_FN,	GPSR6_30,
5497		GP_6_29_FN,	GPSR6_29,
5498		GP_6_28_FN,	GPSR6_28,
5499		GP_6_27_FN,	GPSR6_27,
5500		GP_6_26_FN,	GPSR6_26,
5501		GP_6_25_FN,	GPSR6_25,
5502		GP_6_24_FN,	GPSR6_24,
5503		GP_6_23_FN,	GPSR6_23,
5504		GP_6_22_FN,	GPSR6_22,
5505		GP_6_21_FN,	GPSR6_21,
5506		GP_6_20_FN,	GPSR6_20,
5507		GP_6_19_FN,	GPSR6_19,
5508		GP_6_18_FN,	GPSR6_18,
5509		GP_6_17_FN,	GPSR6_17,
5510		GP_6_16_FN,	GPSR6_16,
5511		GP_6_15_FN,	GPSR6_15,
5512		GP_6_14_FN,	GPSR6_14,
5513		GP_6_13_FN,	GPSR6_13,
5514		GP_6_12_FN,	GPSR6_12,
5515		GP_6_11_FN,	GPSR6_11,
5516		GP_6_10_FN,	GPSR6_10,
5517		GP_6_9_FN,	GPSR6_9,
5518		GP_6_8_FN,	GPSR6_8,
5519		GP_6_7_FN,	GPSR6_7,
5520		GP_6_6_FN,	GPSR6_6,
5521		GP_6_5_FN,	GPSR6_5,
5522		GP_6_4_FN,	GPSR6_4,
5523		GP_6_3_FN,	GPSR6_3,
5524		GP_6_2_FN,	GPSR6_2,
5525		GP_6_1_FN,	GPSR6_1,
5526		GP_6_0_FN,	GPSR6_0, ))
5527	},
5528	{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5529			     GROUP(-28, 1, 1, 1, 1),
5530			     GROUP(
5531		/* GP7_31_4 RESERVED */
5532		GP_7_3_FN, GPSR7_3,
5533		GP_7_2_FN, GPSR7_2,
5534		GP_7_1_FN, GPSR7_1,
5535		GP_7_0_FN, GPSR7_0, ))
5536	},
5537#undef F_
5538#undef FM
5539
5540#define F_(x, y)	x,
5541#define FM(x)		FN_##x,
5542	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5543		IP0_31_28
5544		IP0_27_24
5545		IP0_23_20
5546		IP0_19_16
5547		IP0_15_12
5548		IP0_11_8
5549		IP0_7_4
5550		IP0_3_0 ))
5551	},
5552	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5553		IP1_31_28
5554		IP1_27_24
5555		IP1_23_20
5556		IP1_19_16
5557		IP1_15_12
5558		IP1_11_8
5559		IP1_7_4
5560		IP1_3_0 ))
5561	},
5562	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5563		IP2_31_28
5564		IP2_27_24
5565		IP2_23_20
5566		IP2_19_16
5567		IP2_15_12
5568		IP2_11_8
5569		IP2_7_4
5570		IP2_3_0 ))
5571	},
5572	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5573		IP3_31_28
5574		IP3_27_24
5575		IP3_23_20
5576		IP3_19_16
5577		IP3_15_12
5578		IP3_11_8
5579		IP3_7_4
5580		IP3_3_0 ))
5581	},
5582	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5583		IP4_31_28
5584		IP4_27_24
5585		IP4_23_20
5586		IP4_19_16
5587		IP4_15_12
5588		IP4_11_8
5589		IP4_7_4
5590		IP4_3_0 ))
5591	},
5592	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5593		IP5_31_28
5594		IP5_27_24
5595		IP5_23_20
5596		IP5_19_16
5597		IP5_15_12
5598		IP5_11_8
5599		IP5_7_4
5600		IP5_3_0 ))
5601	},
5602	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5603		IP6_31_28
5604		IP6_27_24
5605		IP6_23_20
5606		IP6_19_16
5607		IP6_15_12
5608		IP6_11_8
5609		IP6_7_4
5610		IP6_3_0 ))
5611	},
5612	{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5613			     GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5614			     GROUP(
5615		IP7_31_28
5616		IP7_27_24
5617		IP7_23_20
5618		IP7_19_16
5619		/* IP7_15_12 RESERVED */
5620		IP7_11_8
5621		IP7_7_4
5622		IP7_3_0 ))
5623	},
5624	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5625		IP8_31_28
5626		IP8_27_24
5627		IP8_23_20
5628		IP8_19_16
5629		IP8_15_12
5630		IP8_11_8
5631		IP8_7_4
5632		IP8_3_0 ))
5633	},
5634	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5635		IP9_31_28
5636		IP9_27_24
5637		IP9_23_20
5638		IP9_19_16
5639		IP9_15_12
5640		IP9_11_8
5641		IP9_7_4
5642		IP9_3_0 ))
5643	},
5644	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5645		IP10_31_28
5646		IP10_27_24
5647		IP10_23_20
5648		IP10_19_16
5649		IP10_15_12
5650		IP10_11_8
5651		IP10_7_4
5652		IP10_3_0 ))
5653	},
5654	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5655		IP11_31_28
5656		IP11_27_24
5657		IP11_23_20
5658		IP11_19_16
5659		IP11_15_12
5660		IP11_11_8
5661		IP11_7_4
5662		IP11_3_0 ))
5663	},
5664	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5665		IP12_31_28
5666		IP12_27_24
5667		IP12_23_20
5668		IP12_19_16
5669		IP12_15_12
5670		IP12_11_8
5671		IP12_7_4
5672		IP12_3_0 ))
5673	},
5674	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5675		IP13_31_28
5676		IP13_27_24
5677		IP13_23_20
5678		IP13_19_16
5679		IP13_15_12
5680		IP13_11_8
5681		IP13_7_4
5682		IP13_3_0 ))
5683	},
5684	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5685		IP14_31_28
5686		IP14_27_24
5687		IP14_23_20
5688		IP14_19_16
5689		IP14_15_12
5690		IP14_11_8
5691		IP14_7_4
5692		IP14_3_0 ))
5693	},
5694	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5695		IP15_31_28
5696		IP15_27_24
5697		IP15_23_20
5698		IP15_19_16
5699		IP15_15_12
5700		IP15_11_8
5701		IP15_7_4
5702		IP15_3_0 ))
5703	},
5704	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5705		IP16_31_28
5706		IP16_27_24
5707		IP16_23_20
5708		IP16_19_16
5709		IP16_15_12
5710		IP16_11_8
5711		IP16_7_4
5712		IP16_3_0 ))
5713	},
5714	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5715		IP17_31_28
5716		IP17_27_24
5717		IP17_23_20
5718		IP17_19_16
5719		IP17_15_12
5720		IP17_11_8
5721		IP17_7_4
5722		IP17_3_0 ))
5723	},
5724	{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5725			     GROUP(-24, 4, 4),
5726			     GROUP(
5727		/* IP18_31_8 RESERVED */
5728		IP18_7_4
5729		IP18_3_0 ))
5730	},
5731#undef F_
5732#undef FM
5733
5734#define F_(x, y)	x,
5735#define FM(x)		FN_##x,
5736	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5737			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5738				   1, 1, 1, 2, 2, 1, 2, -3),
5739			     GROUP(
5740		MOD_SEL0_31_30_29
5741		MOD_SEL0_28_27
5742		MOD_SEL0_26_25_24
5743		MOD_SEL0_23
5744		MOD_SEL0_22
5745		MOD_SEL0_21
5746		MOD_SEL0_20
5747		MOD_SEL0_19
5748		MOD_SEL0_18_17
5749		MOD_SEL0_16
5750		/* RESERVED 15 */
5751		MOD_SEL0_14_13
5752		MOD_SEL0_12
5753		MOD_SEL0_11
5754		MOD_SEL0_10
5755		MOD_SEL0_9_8
5756		MOD_SEL0_7_6
5757		MOD_SEL0_5
5758		MOD_SEL0_4_3
5759		/* RESERVED 2, 1, 0 */ ))
5760	},
5761	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5762			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5763				   1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5764			     GROUP(
5765		MOD_SEL1_31_30
5766		MOD_SEL1_29_28_27
5767		MOD_SEL1_26
5768		MOD_SEL1_25_24
5769		MOD_SEL1_23_22_21
5770		MOD_SEL1_20
5771		MOD_SEL1_19
5772		MOD_SEL1_18_17
5773		MOD_SEL1_16
5774		MOD_SEL1_15_14
5775		MOD_SEL1_13
5776		MOD_SEL1_12
5777		MOD_SEL1_11
5778		MOD_SEL1_10
5779		MOD_SEL1_9
5780		/* RESERVED 8, 7 */
5781		MOD_SEL1_6
5782		MOD_SEL1_5
5783		MOD_SEL1_4
5784		MOD_SEL1_3
5785		MOD_SEL1_2
5786		MOD_SEL1_1
5787		MOD_SEL1_0 ))
5788	},
5789	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5790			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5791				   -16, 1),
5792			     GROUP(
5793		MOD_SEL2_31
5794		MOD_SEL2_30
5795		MOD_SEL2_29
5796		MOD_SEL2_28_27
5797		MOD_SEL2_26
5798		MOD_SEL2_25_24_23
5799		MOD_SEL2_22
5800		MOD_SEL2_21
5801		MOD_SEL2_20
5802		MOD_SEL2_19
5803		MOD_SEL2_18
5804		MOD_SEL2_17
5805		/* RESERVED 16-1 */
5806		MOD_SEL2_0 ))
5807	},
5808	{ /* sentinel */ }
5809};
5810
5811static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5812	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5813		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
5814		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
5815		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
5816		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
5817		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
5818		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
5819		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
5820		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
5821	} },
5822	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5823		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
5824		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
5825		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
5826		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
5827		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
5828		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
5829		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
5830		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
5831	} },
5832	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5833		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
5834		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
5835		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
5836		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
5837		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
5838		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
5839		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
5840		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
5841	} },
5842	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5843		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
5844		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
5845		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
5846		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
5847		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
5848		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
5849		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
5850		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
5851	} },
5852	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5853		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
5854		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
5855		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
5856		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
5857		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
5858		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
5859		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
5860		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
5861	} },
5862	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5863		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
5864		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
5865		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
5866		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
5867		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
5868		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
5869		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
5870		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
5871	} },
5872	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5873		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
5874		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
5875		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
5876		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
5877		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
5878		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
5879		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
5880		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
5881	} },
5882	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5883		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
5884		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
5885		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
5886		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
5887		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
5888		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
5889		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
5890		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
5891	} },
5892	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5893		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
5894		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
5895		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
5896		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
5897		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
5898		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
5899		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
5900		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
5901	} },
5902	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5903		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
5904		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
5905		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
5906		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
5907		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
5908		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
5909		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
5910		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
5911	} },
5912	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5913		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
5914		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
5915		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
5916		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
5917		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
5918		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
5919		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
5920		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
5921	} },
5922	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5923		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
5924		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
5925		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
5926		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
5927		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
5928		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
5929		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
5930		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
5931	} },
5932	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5933		{ PIN_DU_DOTCLKIN3,   24, 2 },	/* DU_DOTCLKIN3 */
5934		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
5935		{ PIN_TMS,             4, 2 },	/* TMS */
5936	} },
5937	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5938		{ PIN_TDO,            28, 2 },	/* TDO */
5939		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
5940		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
5941		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
5942		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
5943		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
5944		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
5945		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
5946	} },
5947	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5948		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
5949		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
5950		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
5951		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
5952		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
5953		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
5954		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
5955		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
5956	} },
5957	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5958		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
5959		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
5960		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
5961		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
5962		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
5963		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
5964		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
5965		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
5966	} },
5967	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5968		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
5969		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
5970		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
5971		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
5972		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
5973		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
5974		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
5975		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
5976	} },
5977	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5978		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
5979		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
5980		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
5981		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
5982		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
5983		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
5984		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
5985		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
5986	} },
5987	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5988		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
5989		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
5990		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
5991		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
5992		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
5993		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
5994		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
5995		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
5996	} },
5997	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5998		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
5999		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
6000		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
6001		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
6002		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
6003		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
6004		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
6005		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
6006	} },
6007	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6008		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
6009		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
6010		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
6011		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
6012		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
6013		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
6014		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
6015		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
6016	} },
6017	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6018		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
6019		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
6020		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
6021		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
6022		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
6023		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
6024		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
6025		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
6026	} },
6027	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6028		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
6029		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
6030		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
6031		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
6032		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
6033		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
6034		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
6035		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
6036	} },
6037	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6038		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
6039		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
6040		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
6041		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
6042		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
6043		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
6044		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
6045		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
6046	} },
6047	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6048		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
6049		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
6050		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
6051		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
6052		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
6053		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
6054		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
6055	} },
6056	{ /* sentinel */ }
6057};
6058
6059enum ioctrl_regs {
6060	POCCTRL,
6061	TDSELCTRL,
6062};
6063
6064static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6065	[POCCTRL] = { 0xe6060380, },
6066	[TDSELCTRL] = { 0xe60603c0, },
6067	{ /* sentinel */ }
6068};
6069
6070static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
6071{
6072	int bit = -EINVAL;
6073
6074	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6075
6076	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6077		bit = pin & 0x1f;
6078
6079	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6080		bit = (pin & 0x1f) + 12;
6081
6082	return bit;
6083}
6084
6085static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6086	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6087		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
6088		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
6089		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
6090		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
6091		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
6092		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
6093		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
6094		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
6095		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
6096		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
6097		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
6098		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
6099		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
6100		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
6101		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
6102		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
6103		[16] = PIN_AVB_RXC,		/* AVB_RXC */
6104		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
6105		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
6106		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
6107		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
6108		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
6109		[22] = PIN_AVB_TXC,		/* AVB_TXC */
6110		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
6111		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
6112		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
6113		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
6114		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
6115		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
6116		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
6117		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
6118		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
6119	} },
6120	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6121		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
6122		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
6123		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
6124		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
6125		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
6126		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
6127		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
6128		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
6129		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
6130		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
6131		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
6132		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
6133		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
6134		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
6135		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
6136		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
6137		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
6138		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
6139		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
6140		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
6141		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
6142		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
6143		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
6144		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
6145		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
6146		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
6147		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
6148		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
6149		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
6150		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
6151		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
6152		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
6153	} },
6154	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6155		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
6156		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
6157		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
6158		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
6159		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
6160		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
6161		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
6162		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
6163		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
6164		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
6165		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
6166		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
6167		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
6168		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
6169		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
6170		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
6171		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
6172		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
6173		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
6174		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
6175		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
6176		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
6177		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
6178		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
6179		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
6180		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
6181		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
6182		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
6183		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
6184		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
6185		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
6186		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
6187	} },
6188	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6189		[ 0] = SH_PFC_PIN_NONE,
6190		[ 1] = PIN_DU_DOTCLKIN3,	/* DU_DOTCLKIN3 */
6191		[ 2] = PIN_FSCLKST,		/* FSCLKST */
6192		[ 3] = PIN_EXTALR,		/* EXTALR*/
6193		[ 4] = PIN_TRST_N,		/* TRST# */
6194		[ 5] = PIN_TCK,			/* TCK */
6195		[ 6] = PIN_TMS,			/* TMS */
6196		[ 7] = PIN_TDI,			/* TDI */
6197		[ 8] = SH_PFC_PIN_NONE,
6198		[ 9] = PIN_ASEBRK,		/* ASEBRK */
6199		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
6200		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
6201		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
6202		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
6203		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
6204		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
6205		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
6206		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
6207		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
6208		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
6209		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
6210		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
6211		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
6212		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
6213		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
6214		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
6215		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
6216		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
6217		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
6218		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
6219		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
6220		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
6221	} },
6222	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6223		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
6224		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
6225		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
6226		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
6227		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
6228		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
6229		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
6230		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
6231		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
6232		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
6233		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
6234		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
6235		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
6236		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
6237		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
6238		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
6239		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
6240		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
6241		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
6242		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
6243		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
6244		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
6245		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
6246		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
6247		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
6248		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
6249		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
6250		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
6251		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
6252		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
6253		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
6254		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
6255	} },
6256	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6257		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
6258		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
6259		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
6260		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
6261		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
6262		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
6263		[ 6] = PIN_MLB_REF,		/* MLB_REF */
6264		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
6265		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
6266		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
6267		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
6268		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
6269		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
6270		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
6271		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
6272		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
6273		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
6274		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
6275		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
6276		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
6277		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
6278		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
6279		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
6280		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
6281		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
6282		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
6283		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
6284		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
6285		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
6286		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
6287		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
6288		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
6289	} },
6290	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6291		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
6292		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
6293		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
6294		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
6295		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
6296		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
6297		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
6298		[ 7] = SH_PFC_PIN_NONE,
6299		[ 8] = SH_PFC_PIN_NONE,
6300		[ 9] = SH_PFC_PIN_NONE,
6301		[10] = SH_PFC_PIN_NONE,
6302		[11] = SH_PFC_PIN_NONE,
6303		[12] = SH_PFC_PIN_NONE,
6304		[13] = SH_PFC_PIN_NONE,
6305		[14] = SH_PFC_PIN_NONE,
6306		[15] = SH_PFC_PIN_NONE,
6307		[16] = SH_PFC_PIN_NONE,
6308		[17] = SH_PFC_PIN_NONE,
6309		[18] = SH_PFC_PIN_NONE,
6310		[19] = SH_PFC_PIN_NONE,
6311		[20] = SH_PFC_PIN_NONE,
6312		[21] = SH_PFC_PIN_NONE,
6313		[22] = SH_PFC_PIN_NONE,
6314		[23] = SH_PFC_PIN_NONE,
6315		[24] = SH_PFC_PIN_NONE,
6316		[25] = SH_PFC_PIN_NONE,
6317		[26] = SH_PFC_PIN_NONE,
6318		[27] = SH_PFC_PIN_NONE,
6319		[28] = SH_PFC_PIN_NONE,
6320		[29] = SH_PFC_PIN_NONE,
6321		[30] = SH_PFC_PIN_NONE,
6322		[31] = SH_PFC_PIN_NONE,
6323	} },
6324	{ /* sentinel */ }
6325};
6326
6327static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
6328	.pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6329	.get_bias = rcar_pinmux_get_bias,
6330	.set_bias = rcar_pinmux_set_bias,
6331};
6332
6333#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6334const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6335	.name = "r8a774b1_pfc",
6336	.ops = &r8a77965_pfc_ops,
6337	.unlock_reg = 0xe6060000, /* PMMR */
6338
6339	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6340
6341	.pins = pinmux_pins,
6342	.nr_pins = ARRAY_SIZE(pinmux_pins),
6343	.groups = pinmux_groups.common,
6344	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
6345	.functions = pinmux_functions.common,
6346	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
6347
6348	.cfg_regs = pinmux_config_regs,
6349	.drive_regs = pinmux_drive_regs,
6350	.bias_regs = pinmux_bias_regs,
6351	.ioctrl_regs = pinmux_ioctrl_regs,
6352
6353	.pinmux_data = pinmux_data,
6354	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6355};
6356#endif
6357
6358#ifdef CONFIG_PINCTRL_PFC_R8A77965
6359const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6360	.name = "r8a77965_pfc",
6361	.ops = &r8a77965_pfc_ops,
6362	.unlock_reg = 0xe6060000, /* PMMR */
6363
6364	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6365
6366	.pins = pinmux_pins,
6367	.nr_pins = ARRAY_SIZE(pinmux_pins),
6368	.groups = pinmux_groups.common,
6369	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6370		ARRAY_SIZE(pinmux_groups.automotive),
6371	.functions = pinmux_functions.common,
6372	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6373		ARRAY_SIZE(pinmux_functions.automotive),
6374
6375	.cfg_regs = pinmux_config_regs,
6376	.drive_regs = pinmux_drive_regs,
6377	.bias_regs = pinmux_bias_regs,
6378	.ioctrl_regs = pinmux_ioctrl_regs,
6379
6380	.pinmux_data = pinmux_data,
6381	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6382};
6383#endif