pfc-r8a7796.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
   4 *
   5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
   6 *
   7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
   8 *
   9 * R-Car Gen3 processor support - PFC hardware block.
  10 *
  11 * Copyright (C) 2015  Renesas Electronics Corporation
  12 */
  13
  14#include <linux/errno.h>
  15#include <linux/kernel.h>
  16
  17#include "sh_pfc.h"
  18
  19#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
  20
  21#define CPU_ALL_GP(fn, sfx)						\
  22	PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),	\
  23	PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),	\
  24	PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),	\
  25	PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  26	PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),	\
  27	PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),	\
  28	PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),	\
  29	PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),	\
  30	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
  31	PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),	\
  32	PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),	\
  33	PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
  34
  35#define CPU_ALL_NOGP(fn)						\
  36	PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),			\
  37	PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),		\
  38	PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),		\
  39	PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),		\
  40	PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),		\
  41	PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),		\
  42	PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),		\
  43	PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),		\
  44	PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),		\
  45	PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),		\
  46	PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),		\
  47	PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),		\
  48	PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),		\
  49	PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),	\
  50	PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),		\
  51	PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),	\
  52	PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),	\
  53	PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),	\
  54	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
  55	PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),		\
  56	PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),		\
  57	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),		\
  58	PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),		\
  59	PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),		\
  60	PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),	\
  61	PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),	\
  62	PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),	\
  63	PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),		\
  64	PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),		\
  65	PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),		\
  66	PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),	\
  67	PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),	\
  68	PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),	\
  69	PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),		\
  70	PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
  71	PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),		\
  72	PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),		\
  73	PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),		\
  74	PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  75	PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
  76	PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),	\
  77	PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),			\
  78	PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
  79
  80/*
  81 * F_() : just information
  82 * FM() : macro for FN_xxx / xxx_MARK
  83 */
  84
  85/* GPSR0 */
  86#define GPSR0_15	F_(D15,			IP7_11_8)
  87#define GPSR0_14	F_(D14,			IP7_7_4)
  88#define GPSR0_13	F_(D13,			IP7_3_0)
  89#define GPSR0_12	F_(D12,			IP6_31_28)
  90#define GPSR0_11	F_(D11,			IP6_27_24)
  91#define GPSR0_10	F_(D10,			IP6_23_20)
  92#define GPSR0_9		F_(D9,			IP6_19_16)
  93#define GPSR0_8		F_(D8,			IP6_15_12)
  94#define GPSR0_7		F_(D7,			IP6_11_8)
  95#define GPSR0_6		F_(D6,			IP6_7_4)
  96#define GPSR0_5		F_(D5,			IP6_3_0)
  97#define GPSR0_4		F_(D4,			IP5_31_28)
  98#define GPSR0_3		F_(D3,			IP5_27_24)
  99#define GPSR0_2		F_(D2,			IP5_23_20)
 100#define GPSR0_1		F_(D1,			IP5_19_16)
 101#define GPSR0_0		F_(D0,			IP5_15_12)
 102
 103/* GPSR1 */
 104#define GPSR1_28	FM(CLKOUT)
 105#define GPSR1_27	F_(EX_WAIT0_A,		IP5_11_8)
 106#define GPSR1_26	F_(WE1_N,		IP5_7_4)
 107#define GPSR1_25	F_(WE0_N,		IP5_3_0)
 108#define GPSR1_24	F_(RD_WR_N,		IP4_31_28)
 109#define GPSR1_23	F_(RD_N,		IP4_27_24)
 110#define GPSR1_22	F_(BS_N,		IP4_23_20)
 111#define GPSR1_21	F_(CS1_N,		IP4_19_16)
 112#define GPSR1_20	F_(CS0_N,		IP4_15_12)
 113#define GPSR1_19	F_(A19,			IP4_11_8)
 114#define GPSR1_18	F_(A18,			IP4_7_4)
 115#define GPSR1_17	F_(A17,			IP4_3_0)
 116#define GPSR1_16	F_(A16,			IP3_31_28)
 117#define GPSR1_15	F_(A15,			IP3_27_24)
 118#define GPSR1_14	F_(A14,			IP3_23_20)
 119#define GPSR1_13	F_(A13,			IP3_19_16)
 120#define GPSR1_12	F_(A12,			IP3_15_12)
 121#define GPSR1_11	F_(A11,			IP3_11_8)
 122#define GPSR1_10	F_(A10,			IP3_7_4)
 123#define GPSR1_9		F_(A9,			IP3_3_0)
 124#define GPSR1_8		F_(A8,			IP2_31_28)
 125#define GPSR1_7		F_(A7,			IP2_27_24)
 126#define GPSR1_6		F_(A6,			IP2_23_20)
 127#define GPSR1_5		F_(A5,			IP2_19_16)
 128#define GPSR1_4		F_(A4,			IP2_15_12)
 129#define GPSR1_3		F_(A3,			IP2_11_8)
 130#define GPSR1_2		F_(A2,			IP2_7_4)
 131#define GPSR1_1		F_(A1,			IP2_3_0)
 132#define GPSR1_0		F_(A0,			IP1_31_28)
 133
 134/* GPSR2 */
 135#define GPSR2_14	F_(AVB_AVTP_CAPTURE_A,	IP0_23_20)
 136#define GPSR2_13	F_(AVB_AVTP_MATCH_A,	IP0_19_16)
 137#define GPSR2_12	F_(AVB_LINK,		IP0_15_12)
 138#define GPSR2_11	F_(AVB_PHY_INT,		IP0_11_8)
 139#define GPSR2_10	F_(AVB_MAGIC,		IP0_7_4)
 140#define GPSR2_9		F_(AVB_MDC,		IP0_3_0)
 141#define GPSR2_8		F_(PWM2_A,		IP1_27_24)
 142#define GPSR2_7		F_(PWM1_A,		IP1_23_20)
 143#define GPSR2_6		F_(PWM0,		IP1_19_16)
 144#define GPSR2_5		F_(IRQ5,		IP1_15_12)
 145#define GPSR2_4		F_(IRQ4,		IP1_11_8)
 146#define GPSR2_3		F_(IRQ3,		IP1_7_4)
 147#define GPSR2_2		F_(IRQ2,		IP1_3_0)
 148#define GPSR2_1		F_(IRQ1,		IP0_31_28)
 149#define GPSR2_0		F_(IRQ0,		IP0_27_24)
 150
 151/* GPSR3 */
 152#define GPSR3_15	F_(SD1_WP,		IP11_23_20)
 153#define GPSR3_14	F_(SD1_CD,		IP11_19_16)
 154#define GPSR3_13	F_(SD0_WP,		IP11_15_12)
 155#define GPSR3_12	F_(SD0_CD,		IP11_11_8)
 156#define GPSR3_11	F_(SD1_DAT3,		IP8_31_28)
 157#define GPSR3_10	F_(SD1_DAT2,		IP8_27_24)
 158#define GPSR3_9		F_(SD1_DAT1,		IP8_23_20)
 159#define GPSR3_8		F_(SD1_DAT0,		IP8_19_16)
 160#define GPSR3_7		F_(SD1_CMD,		IP8_15_12)
 161#define GPSR3_6		F_(SD1_CLK,		IP8_11_8)
 162#define GPSR3_5		F_(SD0_DAT3,		IP8_7_4)
 163#define GPSR3_4		F_(SD0_DAT2,		IP8_3_0)
 164#define GPSR3_3		F_(SD0_DAT1,		IP7_31_28)
 165#define GPSR3_2		F_(SD0_DAT0,		IP7_27_24)
 166#define GPSR3_1		F_(SD0_CMD,		IP7_23_20)
 167#define GPSR3_0		F_(SD0_CLK,		IP7_19_16)
 168
 169/* GPSR4 */
 170#define GPSR4_17	F_(SD3_DS,		IP11_7_4)
 171#define GPSR4_16	F_(SD3_DAT7,		IP11_3_0)
 172#define GPSR4_15	F_(SD3_DAT6,		IP10_31_28)
 173#define GPSR4_14	F_(SD3_DAT5,		IP10_27_24)
 174#define GPSR4_13	F_(SD3_DAT4,		IP10_23_20)
 175#define GPSR4_12	F_(SD3_DAT3,		IP10_19_16)
 176#define GPSR4_11	F_(SD3_DAT2,		IP10_15_12)
 177#define GPSR4_10	F_(SD3_DAT1,		IP10_11_8)
 178#define GPSR4_9		F_(SD3_DAT0,		IP10_7_4)
 179#define GPSR4_8		F_(SD3_CMD,		IP10_3_0)
 180#define GPSR4_7		F_(SD3_CLK,		IP9_31_28)
 181#define GPSR4_6		F_(SD2_DS,		IP9_27_24)
 182#define GPSR4_5		F_(SD2_DAT3,		IP9_23_20)
 183#define GPSR4_4		F_(SD2_DAT2,		IP9_19_16)
 184#define GPSR4_3		F_(SD2_DAT1,		IP9_15_12)
 185#define GPSR4_2		F_(SD2_DAT0,		IP9_11_8)
 186#define GPSR4_1		F_(SD2_CMD,		IP9_7_4)
 187#define GPSR4_0		F_(SD2_CLK,		IP9_3_0)
 188
 189/* GPSR5 */
 190#define GPSR5_25	F_(MLB_DAT,		IP14_19_16)
 191#define GPSR5_24	F_(MLB_SIG,		IP14_15_12)
 192#define GPSR5_23	F_(MLB_CLK,		IP14_11_8)
 193#define GPSR5_22	FM(MSIOF0_RXD)
 194#define GPSR5_21	F_(MSIOF0_SS2,		IP14_7_4)
 195#define GPSR5_20	FM(MSIOF0_TXD)
 196#define GPSR5_19	F_(MSIOF0_SS1,		IP14_3_0)
 197#define GPSR5_18	F_(MSIOF0_SYNC,		IP13_31_28)
 198#define GPSR5_17	FM(MSIOF0_SCK)
 199#define GPSR5_16	F_(HRTS0_N,		IP13_27_24)
 200#define GPSR5_15	F_(HCTS0_N,		IP13_23_20)
 201#define GPSR5_14	F_(HTX0,		IP13_19_16)
 202#define GPSR5_13	F_(HRX0,		IP13_15_12)
 203#define GPSR5_12	F_(HSCK0,		IP13_11_8)
 204#define GPSR5_11	F_(RX2_A,		IP13_7_4)
 205#define GPSR5_10	F_(TX2_A,		IP13_3_0)
 206#define GPSR5_9		F_(SCK2,		IP12_31_28)
 207#define GPSR5_8		F_(RTS1_N,		IP12_27_24)
 208#define GPSR5_7		F_(CTS1_N,		IP12_23_20)
 209#define GPSR5_6		F_(TX1_A,		IP12_19_16)
 210#define GPSR5_5		F_(RX1_A,		IP12_15_12)
 211#define GPSR5_4		F_(RTS0_N,		IP12_11_8)
 212#define GPSR5_3		F_(CTS0_N,		IP12_7_4)
 213#define GPSR5_2		F_(TX0,			IP12_3_0)
 214#define GPSR5_1		F_(RX0,			IP11_31_28)
 215#define GPSR5_0		F_(SCK0,		IP11_27_24)
 216
 217/* GPSR6 */
 218#define GPSR6_31	F_(GP6_31,		IP18_7_4)
 219#define GPSR6_30	F_(GP6_30,		IP18_3_0)
 220#define GPSR6_29	F_(USB30_OVC,		IP17_31_28)
 221#define GPSR6_28	F_(USB30_PWEN,		IP17_27_24)
 222#define GPSR6_27	F_(USB1_OVC,		IP17_23_20)
 223#define GPSR6_26	F_(USB1_PWEN,		IP17_19_16)
 224#define GPSR6_25	F_(USB0_OVC,		IP17_15_12)
 225#define GPSR6_24	F_(USB0_PWEN,		IP17_11_8)
 226#define GPSR6_23	F_(AUDIO_CLKB_B,	IP17_7_4)
 227#define GPSR6_22	F_(AUDIO_CLKA_A,	IP17_3_0)
 228#define GPSR6_21	F_(SSI_SDATA9_A,	IP16_31_28)
 229#define GPSR6_20	F_(SSI_SDATA8,		IP16_27_24)
 230#define GPSR6_19	F_(SSI_SDATA7,		IP16_23_20)
 231#define GPSR6_18	F_(SSI_WS78,		IP16_19_16)
 232#define GPSR6_17	F_(SSI_SCK78,		IP16_15_12)
 233#define GPSR6_16	F_(SSI_SDATA6,		IP16_11_8)
 234#define GPSR6_15	F_(SSI_WS6,		IP16_7_4)
 235#define GPSR6_14	F_(SSI_SCK6,		IP16_3_0)
 236#define GPSR6_13	FM(SSI_SDATA5)
 237#define GPSR6_12	FM(SSI_WS5)
 238#define GPSR6_11	FM(SSI_SCK5)
 239#define GPSR6_10	F_(SSI_SDATA4,		IP15_31_28)
 240#define GPSR6_9		F_(SSI_WS4,		IP15_27_24)
 241#define GPSR6_8		F_(SSI_SCK4,		IP15_23_20)
 242#define GPSR6_7		F_(SSI_SDATA3,		IP15_19_16)
 243#define GPSR6_6		F_(SSI_WS349,		IP15_15_12)
 244#define GPSR6_5		F_(SSI_SCK349,		IP15_11_8)
 245#define GPSR6_4		F_(SSI_SDATA2_A,	IP15_7_4)
 246#define GPSR6_3		F_(SSI_SDATA1_A,	IP15_3_0)
 247#define GPSR6_2		F_(SSI_SDATA0,		IP14_31_28)
 248#define GPSR6_1		F_(SSI_WS01239,		IP14_27_24)
 249#define GPSR6_0		F_(SSI_SCK01239,	IP14_23_20)
 250
 251/* GPSR7 */
 252#define GPSR7_3		FM(GP7_03)
 253#define GPSR7_2		FM(GP7_02)
 254#define GPSR7_1		FM(AVS2)
 255#define GPSR7_0		FM(AVS1)
 256
 257/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 258#define IP0_3_0		FM(AVB_MDC)		F_(0, 0)	FM(MSIOF2_SS2_C)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 259#define IP0_7_4		FM(AVB_MAGIC)		F_(0, 0)	FM(MSIOF2_SS1_C)	FM(SCK4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 260#define IP0_11_8	FM(AVB_PHY_INT)		F_(0, 0)	FM(MSIOF2_SYNC_C)	FM(RX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 261#define IP0_15_12	FM(AVB_LINK)		F_(0, 0)	FM(MSIOF2_SCK_C)	FM(TX4_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 262#define IP0_19_16	FM(AVB_AVTP_MATCH_A)	F_(0, 0)	FM(MSIOF2_RXD_C)	FM(CTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 263#define IP0_23_20	FM(AVB_AVTP_CAPTURE_A)	F_(0, 0)	FM(MSIOF2_TXD_C)	FM(RTS4_N_A)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 264#define IP0_27_24	FM(IRQ0)		FM(QPOLB)	F_(0, 0)		FM(DU_CDE)			FM(VI4_DATA0_B) FM(CAN0_TX_B)	FM(CANFD0_TX_B)		FM(MSIOF3_SS2_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 265#define IP0_31_28	FM(IRQ1)		FM(QPOLA)	F_(0, 0)		FM(DU_DISP)			FM(VI4_DATA1_B) FM(CAN0_RX_B)	FM(CANFD0_RX_B)		FM(MSIOF3_SS1_E) F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 266#define IP1_3_0		FM(IRQ2)		FM(QCPV_QDE)	F_(0, 0)		FM(DU_EXODDF_DU_ODDF_DISP_CDE)	FM(VI4_DATA2_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SYNC_E) F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 267#define IP1_7_4		FM(IRQ3)		FM(QSTVB_QVE)	F_(0, 0)		FM(DU_DOTCLKOUT1)		FM(VI4_DATA3_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_SCK_E) F_(0, 0)		FM(PWM4_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 268#define IP1_11_8	FM(IRQ4)		FM(QSTH_QHS)	F_(0, 0)		FM(DU_EXHSYNC_DU_HSYNC)		FM(VI4_DATA4_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_RXD_E) F_(0, 0)		FM(PWM5_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 269#define IP1_15_12	FM(IRQ5)		FM(QSTB_QHE)	F_(0, 0)		FM(DU_EXVSYNC_DU_VSYNC)		FM(VI4_DATA5_B) F_(0, 0)	F_(0, 0)		FM(MSIOF3_TXD_E) F_(0, 0)		FM(PWM6_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 270#define IP1_19_16	FM(PWM0)		FM(AVB_AVTP_PPS)F_(0, 0)		F_(0, 0)			FM(VI4_DATA6_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IECLK_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 271#define IP1_23_20	FM(PWM1_A)		F_(0, 0)	F_(0, 0)		FM(HRX3_D)			FM(VI4_DATA7_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IERX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 272#define IP1_27_24	FM(PWM2_A)		F_(0, 0)	F_(0, 0)		FM(HTX3_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		FM(IETX_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 273#define IP1_31_28	FM(A0)			FM(LCDOUT16)	FM(MSIOF3_SYNC_B)	F_(0, 0)			FM(VI4_DATA8)	F_(0, 0)	FM(DU_DB0)		F_(0, 0)	F_(0, 0)		FM(PWM3_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 274#define IP2_3_0		FM(A1)			FM(LCDOUT17)	FM(MSIOF3_TXD_B)	F_(0, 0)			FM(VI4_DATA9)	F_(0, 0)	FM(DU_DB1)		F_(0, 0)	F_(0, 0)		FM(PWM4_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 275#define IP2_7_4		FM(A2)			FM(LCDOUT18)	FM(MSIOF3_SCK_B)	F_(0, 0)			FM(VI4_DATA10)	F_(0, 0)	FM(DU_DB2)		F_(0, 0)	F_(0, 0)		FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 276#define IP2_11_8	FM(A3)			FM(LCDOUT19)	FM(MSIOF3_RXD_B)	F_(0, 0)			FM(VI4_DATA11)	F_(0, 0)	FM(DU_DB3)		F_(0, 0)	F_(0, 0)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 277#define IP2_15_12	FM(A4)			FM(LCDOUT20)	FM(MSIOF3_SS1_B)	F_(0, 0)			FM(VI4_DATA12)	FM(VI5_DATA12)	FM(DU_DB4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 278#define IP2_19_16	FM(A5)			FM(LCDOUT21)	FM(MSIOF3_SS2_B)	FM(SCK4_B)			FM(VI4_DATA13)	FM(VI5_DATA13)	FM(DU_DB5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 279#define IP2_23_20	FM(A6)			FM(LCDOUT22)	FM(MSIOF2_SS1_A)	FM(RX4_B)			FM(VI4_DATA14)	FM(VI5_DATA14)	FM(DU_DB6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 280#define IP2_27_24	FM(A7)			FM(LCDOUT23)	FM(MSIOF2_SS2_A)	FM(TX4_B)			FM(VI4_DATA15)	FM(VI5_DATA15)	FM(DU_DB7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 281#define IP2_31_28	FM(A8)			FM(RX3_B)	FM(MSIOF2_SYNC_A)	FM(HRX4_B)			F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(SDA6_A)	FM(AVB_AVTP_MATCH_B)	FM(PWM1_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 282#define IP3_3_0		FM(A9)			F_(0, 0)	FM(MSIOF2_SCK_A)	FM(CTS4_N_B)			F_(0, 0)	FM(VI5_VSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 283#define IP3_7_4		FM(A10)			F_(0, 0)	FM(MSIOF2_RXD_A)	FM(RTS4_N_B)			F_(0, 0)	FM(VI5_HSYNC_N)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 284#define IP3_11_8	FM(A11)			FM(TX3_B)	FM(MSIOF2_TXD_A)	FM(HTX4_B)			FM(HSCK4)	FM(VI5_FIELD)	F_(0, 0)		FM(SCL6_A)	FM(AVB_AVTP_CAPTURE_B)	FM(PWM2_B)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 285
 286/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 287#define IP3_15_12	FM(A12)			FM(LCDOUT12)	FM(MSIOF3_SCK_C)	F_(0, 0)			FM(HRX4_A)	FM(VI5_DATA8)	FM(DU_DG4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 288#define IP3_19_16	FM(A13)			FM(LCDOUT13)	FM(MSIOF3_SYNC_C)	F_(0, 0)			FM(HTX4_A)	FM(VI5_DATA9)	FM(DU_DG5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 289#define IP3_23_20	FM(A14)			FM(LCDOUT14)	FM(MSIOF3_RXD_C)	F_(0, 0)			FM(HCTS4_N)	FM(VI5_DATA10)	FM(DU_DG6)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 290#define IP3_27_24	FM(A15)			FM(LCDOUT15)	FM(MSIOF3_TXD_C)	F_(0, 0)			FM(HRTS4_N)	FM(VI5_DATA11)	FM(DU_DG7)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 291#define IP3_31_28	FM(A16)			FM(LCDOUT8)	F_(0, 0)		F_(0, 0)			FM(VI4_FIELD)	F_(0, 0)	FM(DU_DG0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 292#define IP4_3_0		FM(A17)			FM(LCDOUT9)	F_(0, 0)		F_(0, 0)			FM(VI4_VSYNC_N)	F_(0, 0)	FM(DU_DG1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 293#define IP4_7_4		FM(A18)			FM(LCDOUT10)	F_(0, 0)		F_(0, 0)			FM(VI4_HSYNC_N)	F_(0, 0)	FM(DU_DG2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 294#define IP4_11_8	FM(A19)			FM(LCDOUT11)	F_(0, 0)		F_(0, 0)			FM(VI4_CLKENB)	F_(0, 0)	FM(DU_DG3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 295#define IP4_15_12	FM(CS0_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLKENB)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 296#define IP4_19_16	FM(CS1_N)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(VI5_CLK)	F_(0, 0)		FM(EX_WAIT0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 297#define IP4_23_20	FM(BS_N)		FM(QSTVA_QVS)	FM(MSIOF3_SCK_D)	FM(SCK3)			FM(HSCK3)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN1_TX)		FM(CANFD1_TX)	FM(IETX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 298#define IP4_27_24	FM(RD_N)		F_(0, 0)	FM(MSIOF3_SYNC_D)	FM(RX3_A)			FM(HRX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_TX_A)		FM(CANFD0_TX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 299#define IP4_31_28	FM(RD_WR_N)		F_(0, 0)	FM(MSIOF3_RXD_D)	FM(TX3_A)			FM(HTX3_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(CAN0_RX_A)		FM(CANFD0_RX_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 300#define IP5_3_0		FM(WE0_N)		F_(0, 0)	FM(MSIOF3_TXD_D)	FM(CTS3_N)			FM(HCTS3_N)	F_(0, 0)	F_(0, 0)		FM(SCL6_B)	FM(CAN_CLK)		F_(0, 0)	FM(IECLK_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 301#define IP5_7_4		FM(WE1_N)		F_(0, 0)	FM(MSIOF3_SS1_D)	FM(RTS3_N)			FM(HRTS3_N)	F_(0, 0)	F_(0, 0)		FM(SDA6_B)	FM(CAN1_RX)		FM(CANFD1_RX)	FM(IERX_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 302#define IP5_11_8	FM(EX_WAIT0_A)		FM(QCLK)	F_(0, 0)		F_(0, 0)			FM(VI4_CLK)	F_(0, 0)	FM(DU_DOTCLKOUT0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 303#define IP5_15_12	FM(D0)			FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)	F_(0, 0)			FM(VI4_DATA16)	FM(VI5_DATA0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 304#define IP5_19_16	FM(D1)			FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)	F_(0, 0)			FM(VI4_DATA17)	FM(VI5_DATA1)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 305#define IP5_23_20	FM(D2)			F_(0, 0)	FM(MSIOF3_RXD_A)	F_(0, 0)			FM(VI4_DATA18)	FM(VI5_DATA2)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 306#define IP5_27_24	FM(D3)			F_(0, 0)	FM(MSIOF3_TXD_A)	F_(0, 0)			FM(VI4_DATA19)	FM(VI5_DATA3)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 307#define IP5_31_28	FM(D4)			FM(MSIOF2_SCK_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA20)	FM(VI5_DATA4)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 308#define IP6_3_0		FM(D5)			FM(MSIOF2_SYNC_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA21)	FM(VI5_DATA5)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 309#define IP6_7_4		FM(D6)			FM(MSIOF2_RXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA22)	FM(VI5_DATA6)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 310#define IP6_11_8	FM(D7)			FM(MSIOF2_TXD_B)F_(0, 0)		F_(0, 0)			FM(VI4_DATA23)	FM(VI5_DATA7)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 311#define IP6_15_12	FM(D8)			FM(LCDOUT0)	FM(MSIOF2_SCK_D)	FM(SCK4_C)			FM(VI4_DATA0_A)	F_(0, 0)	FM(DU_DR0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 312#define IP6_19_16	FM(D9)			FM(LCDOUT1)	FM(MSIOF2_SYNC_D)	F_(0, 0)			FM(VI4_DATA1_A)	F_(0, 0)	FM(DU_DR1)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 313#define IP6_23_20	FM(D10)			FM(LCDOUT2)	FM(MSIOF2_RXD_D)	FM(HRX3_B)			FM(VI4_DATA2_A)	FM(CTS4_N_C)	FM(DU_DR2)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 314#define IP6_27_24	FM(D11)			FM(LCDOUT3)	FM(MSIOF2_TXD_D)	FM(HTX3_B)			FM(VI4_DATA3_A)	FM(RTS4_N_C)	FM(DU_DR3)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 315#define IP6_31_28	FM(D12)			FM(LCDOUT4)	FM(MSIOF2_SS1_D)	FM(RX4_C)			FM(VI4_DATA4_A)	F_(0, 0)	FM(DU_DR4)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 316
 317/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 318#define IP7_3_0		FM(D13)			FM(LCDOUT5)	FM(MSIOF2_SS2_D)	FM(TX4_C)			FM(VI4_DATA5_A)	F_(0, 0)	FM(DU_DR5)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 319#define IP7_7_4		FM(D14)			FM(LCDOUT6)	FM(MSIOF3_SS1_A)	FM(HRX3_C)			FM(VI4_DATA6_A)	F_(0, 0)	FM(DU_DR6)		FM(SCL6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 320#define IP7_11_8	FM(D15)			FM(LCDOUT7)	FM(MSIOF3_SS2_A)	FM(HTX3_C)			FM(VI4_DATA7_A)	F_(0, 0)	FM(DU_DR7)		FM(SDA6_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 321#define IP7_19_16	FM(SD0_CLK)		F_(0, 0)	FM(MSIOF1_SCK_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 322#define IP7_23_20	FM(SD0_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_E)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 323#define IP7_27_24	FM(SD0_DAT0)		F_(0, 0)	FM(MSIOF1_RXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_B)	FM(STP_ISCLK_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 324#define IP7_31_28	FM(SD0_DAT1)		F_(0, 0)	FM(MSIOF1_TXD_E)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 325#define IP8_3_0		FM(SD0_DAT2)		F_(0, 0)	FM(MSIOF1_SS1_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_B)	FM(STP_ISD_0_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 326#define IP8_7_4		FM(SD0_DAT3)		F_(0, 0)	FM(MSIOF1_SS2_E)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_B)	FM(STP_ISEN_0_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 327#define IP8_11_8	FM(SD1_CLK)		F_(0, 0)	FM(MSIOF1_SCK_G)	F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 328#define IP8_15_12	FM(SD1_CMD)		F_(0, 0)	FM(MSIOF1_SYNC_G)	FM(NFCE_N_B)			F_(0, 0)	FM(SIM0_D_A)	FM(STP_IVCXO27_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 329#define IP8_19_16	FM(SD1_DAT0)		FM(SD2_DAT4)	FM(MSIOF1_RXD_G)	FM(NFWP_N_B)			F_(0, 0)	FM(TS_SCK1_B)	FM(STP_ISCLK_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 330#define IP8_23_20	FM(SD1_DAT1)		FM(SD2_DAT5)	FM(MSIOF1_TXD_G)	FM(NFDATA14_B)			F_(0, 0)	FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 331#define IP8_27_24	FM(SD1_DAT2)		FM(SD2_DAT6)	FM(MSIOF1_SS1_G)	FM(NFDATA15_B)			F_(0, 0)	FM(TS_SDAT1_B)	FM(STP_ISD_1_B)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 332#define IP8_31_28	FM(SD1_DAT3)		FM(SD2_DAT7)	FM(MSIOF1_SS2_G)	FM(NFRB_N_B)			F_(0, 0)	FM(TS_SDEN1_B)	FM(STP_ISEN_1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 333#define IP9_3_0		FM(SD2_CLK)		F_(0, 0)	FM(NFDATA8)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 334#define IP9_7_4		FM(SD2_CMD)		F_(0, 0)	FM(NFDATA9)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 335#define IP9_11_8	FM(SD2_DAT0)		F_(0, 0)	FM(NFDATA10)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 336#define IP9_15_12	FM(SD2_DAT1)		F_(0, 0)	FM(NFDATA11)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 337#define IP9_19_16	FM(SD2_DAT2)		F_(0, 0)	FM(NFDATA12)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 338#define IP9_23_20	FM(SD2_DAT3)		F_(0, 0)	FM(NFDATA13)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 339#define IP9_27_24	FM(SD2_DS)		F_(0, 0)	FM(NFALE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 340#define IP9_31_28	FM(SD3_CLK)		F_(0, 0)	FM(NFWE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 341#define IP10_3_0	FM(SD3_CMD)		F_(0, 0)	FM(NFRE_N)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 342#define IP10_7_4	FM(SD3_DAT0)		F_(0, 0)	FM(NFDATA0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 343#define IP10_11_8	FM(SD3_DAT1)		F_(0, 0)	FM(NFDATA1)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 344#define IP10_15_12	FM(SD3_DAT2)		F_(0, 0)	FM(NFDATA2)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 345#define IP10_19_16	FM(SD3_DAT3)		F_(0, 0)	FM(NFDATA3)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 346#define IP10_23_20	FM(SD3_DAT4)		FM(SD2_CD_A)	FM(NFDATA4)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 347#define IP10_27_24	FM(SD3_DAT5)		FM(SD2_WP_A)	FM(NFDATA5)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 348#define IP10_31_28	FM(SD3_DAT6)		FM(SD3_CD)	FM(NFDATA6)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 349#define IP11_3_0	FM(SD3_DAT7)		FM(SD3_WP)	FM(NFDATA7)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 350#define IP11_7_4	FM(SD3_DS)		F_(0, 0)	FM(NFCLE)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 351#define IP11_11_8	FM(SD0_CD)		F_(0, 0)	FM(NFDATA14_A)		F_(0, 0)			FM(SCL2_B)	FM(SIM0_RST_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 352
 353/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 354#define IP11_15_12	FM(SD0_WP)		F_(0, 0)	FM(NFDATA15_A)		F_(0, 0)			FM(SDA2_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 355#define IP11_19_16	FM(SD1_CD)		F_(0, 0)	FM(NFRB_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_CLK_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 356#define IP11_23_20	FM(SD1_WP)		F_(0, 0)	FM(NFCE_N_A)		F_(0, 0)			F_(0, 0)	FM(SIM0_D_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 357#define IP11_27_24	FM(SCK0)		FM(HSCK1_B)	FM(MSIOF1_SS2_B)	FM(AUDIO_CLKC_B)		FM(SDA2_A)	FM(SIM0_RST_B)	FM(STP_OPWM_0_C)	FM(RIF0_CLK_B)	F_(0, 0)		FM(ADICHS2)	FM(SCK5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 358#define IP11_31_28	FM(RX0)			FM(HRX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SCK0_C)	FM(STP_ISCLK_0_C)	FM(RIF0_D0_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 359#define IP12_3_0	FM(TX0)			FM(HTX1_B)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)	FM(RIF0_D1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 360#define IP12_7_4	FM(CTS0_N)		FM(HCTS1_N_B)	FM(MSIOF1_SYNC_B)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)	FM(RIF1_SYNC_B)	FM(AUDIO_CLKOUT_C)	FM(ADICS_SAMP)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 361#define IP12_11_8	FM(RTS0_N)		FM(HRTS1_N_B)	FM(MSIOF1_SS1_B)	FM(AUDIO_CLKA_B)		FM(SCL2_A)	F_(0, 0)	FM(STP_IVCXO27_1_C)	FM(RIF0_SYNC_B)	F_(0, 0)		FM(ADICHS1)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 362#define IP12_15_12	FM(RX1_A)		FM(HRX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_C)	FM(STP_ISD_0_C)		FM(RIF1_CLK_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 363#define IP12_19_16	FM(TX1_A)		FM(HTX1_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_C)	FM(STP_ISEN_0_C)	FM(RIF1_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 364#define IP12_23_20	FM(CTS1_N)		FM(HCTS1_N_A)	FM(MSIOF1_RXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_C)	FM(STP_ISEN_1_C)	FM(RIF1_D0_B)	F_(0, 0)		FM(ADIDATA)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 365#define IP12_27_24	FM(RTS1_N)		FM(HRTS1_N_A)	FM(MSIOF1_TXD_B)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_C)	FM(STP_ISD_1_C)		FM(RIF1_D1_B)	F_(0, 0)		FM(ADICHS0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 366#define IP12_31_28	FM(SCK2)		FM(SCIF_CLK_B)	FM(MSIOF1_SCK_B)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_C)	FM(STP_ISCLK_1_C)	FM(RIF1_CLK_B)	F_(0, 0)		FM(ADICLK)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 367#define IP13_3_0	FM(TX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_CD_B)			FM(SCL1_A)	F_(0, 0)	FM(FMCLK_A)		FM(RIF1_D1_C)	F_(0, 0)		FM(FSO_CFE_0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 368#define IP13_7_4	FM(RX2_A)		F_(0, 0)	F_(0, 0)		FM(SD2_WP_B)			FM(SDA1_A)	F_(0, 0)	FM(FMIN_A)		FM(RIF1_SYNC_C)	F_(0, 0)		FM(FSO_CFE_1_N)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 369#define IP13_11_8	FM(HSCK0)		F_(0, 0)	FM(MSIOF1_SCK_D)	FM(AUDIO_CLKB_A)		FM(SSI_SDATA1_B)FM(TS_SCK0_D)	FM(STP_ISCLK_0_D)	FM(RIF0_CLK_C)	F_(0, 0)		F_(0, 0)	FM(RX5_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 370#define IP13_15_12	FM(HRX0)		F_(0, 0)	FM(MSIOF1_RXD_D)	F_(0, 0)			FM(SSI_SDATA2_B)FM(TS_SDEN0_D)	FM(STP_ISEN_0_D)	FM(RIF0_D0_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 371#define IP13_19_16	FM(HTX0)		F_(0, 0)	FM(MSIOF1_TXD_D)	F_(0, 0)			FM(SSI_SDATA9_B)FM(TS_SDAT0_D)	FM(STP_ISD_0_D)		FM(RIF0_D1_C)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 372#define IP13_23_20	FM(HCTS0_N)		FM(RX2_B)	FM(MSIOF1_SYNC_D)	F_(0, 0)			FM(SSI_SCK9_A)	FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)	FM(RIF0_SYNC_C)	FM(AUDIO_CLKOUT1_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 373#define IP13_27_24	FM(HRTS0_N)		FM(TX2_B)	FM(MSIOF1_SS1_D)	F_(0, 0)			FM(SSI_WS9_A)	F_(0, 0)	FM(STP_IVCXO27_0_D)	FM(BPFCLK_A)	FM(AUDIO_CLKOUT2_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 374#define IP13_31_28	FM(MSIOF0_SYNC)		F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	FM(AUDIO_CLKOUT_A)	F_(0, 0)	FM(TX5_B)	F_(0, 0)	F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
 375#define IP14_3_0	FM(MSIOF0_SS1)		FM(RX5_A)	FM(NFWP_N_A)		FM(AUDIO_CLKA_C)		FM(SSI_SCK2_A)	F_(0, 0)	FM(STP_IVCXO27_0_C)	F_(0, 0)	FM(AUDIO_CLKOUT3_A)	F_(0, 0)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 376#define IP14_7_4	FM(MSIOF0_SS2)		FM(TX5_A)	FM(MSIOF1_SS2_D)	FM(AUDIO_CLKC_A)		FM(SSI_WS2_A)	F_(0, 0)	FM(STP_OPWM_0_D)	F_(0, 0)	FM(AUDIO_CLKOUT_D)	F_(0, 0)	FM(SPEEDIN_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 377#define IP14_11_8	FM(MLB_CLK)		F_(0, 0)	FM(MSIOF1_SCK_F)	F_(0, 0)			FM(SCL1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 378#define IP14_15_12	FM(MLB_SIG)		FM(RX1_B)	FM(MSIOF1_SYNC_F)	F_(0, 0)			FM(SDA1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 379#define IP14_19_16	FM(MLB_DAT)		FM(TX1_B)	FM(MSIOF1_RXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 380#define IP14_23_20	FM(SSI_SCK01239)	F_(0, 0)	FM(MSIOF1_TXD_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 381#define IP14_27_24	FM(SSI_WS01239)		F_(0, 0)	FM(MSIOF1_SS1_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 382
 383/* IPSRx */		/* 0 */			/* 1 */		/* 2 */			/* 3 */				/* 4 */		/* 5 */		/* 6 */			/* 7 */		/* 8 */			/* 9 */		/* A */		/* B */		/* C - F */
 384#define IP14_31_28	FM(SSI_SDATA0)		F_(0, 0)	FM(MSIOF1_SS2_F)	F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 385#define IP15_3_0	FM(SSI_SDATA1_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 386#define IP15_7_4	FM(SSI_SDATA2_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			FM(SSI_SCK1_B)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 387#define IP15_11_8	FM(SSI_SCK349)		F_(0, 0)	FM(MSIOF1_SS1_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_OPWM_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 388#define IP15_15_12	FM(SSI_WS349)		FM(HCTS2_N_A)	FM(MSIOF1_SS2_A)	F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_0_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 389#define IP15_19_16	FM(SSI_SDATA3)		FM(HRTS2_N_A)	FM(MSIOF1_TXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SCK0_A)	FM(STP_ISCLK_0_A)	FM(RIF0_D1_A)	FM(RIF2_D0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 390#define IP15_23_20	FM(SSI_SCK4)		FM(HRX2_A)	FM(MSIOF1_SCK_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT0_A)	FM(STP_ISD_0_A)		FM(RIF0_CLK_A)	FM(RIF2_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 391#define IP15_27_24	FM(SSI_WS4)		FM(HTX2_A)	FM(MSIOF1_SYNC_A)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN0_A)	FM(STP_ISEN_0_A)	FM(RIF0_SYNC_A)	FM(RIF2_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 392#define IP15_31_28	FM(SSI_SDATA4)		FM(HSCK2_A)	FM(MSIOF1_RXD_A)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)	FM(RIF0_D0_A)	FM(RIF2_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 393#define IP16_3_0	FM(SSI_SCK6)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 394#define IP16_7_4	FM(SSI_WS6)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 395#define IP16_11_8	FM(SSI_SDATA6)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_D)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 396#define IP16_15_12	FM(SSI_SCK78)		FM(HRX2_B)	FM(MSIOF1_SCK_C)	F_(0, 0)			F_(0, 0)	FM(TS_SCK1_A)	FM(STP_ISCLK_1_A)	FM(RIF1_CLK_A)	FM(RIF3_CLK_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 397#define IP16_19_16	FM(SSI_WS78)		FM(HTX2_B)	FM(MSIOF1_SYNC_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDAT1_A)	FM(STP_ISD_1_A)		FM(RIF1_SYNC_A)	FM(RIF3_SYNC_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 398#define IP16_23_20	FM(SSI_SDATA7)		FM(HCTS2_N_B)	FM(MSIOF1_RXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SDEN1_A)	FM(STP_ISEN_1_A)	FM(RIF1_D0_A)	FM(RIF3_D0_A)		F_(0, 0)	FM(TCLK2_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 399#define IP16_27_24	FM(SSI_SDATA8)		FM(HRTS2_N_B)	FM(MSIOF1_TXD_C)	F_(0, 0)			F_(0, 0)	FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)	FM(RIF1_D1_A)	FM(RIF3_D1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 400#define IP16_31_28	FM(SSI_SDATA9_A)	FM(HSCK2_B)	FM(MSIOF1_SS1_C)	FM(HSCK1_A)			FM(SSI_WS1_B)	FM(SCK1)	FM(STP_IVCXO27_1_A)	FM(SCK5_A)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 401#define IP17_3_0	FM(AUDIO_CLKA_A)	F_(0, 0)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 402#define IP17_7_4	FM(AUDIO_CLKB_B)	FM(SCIF_CLK_A)	F_(0, 0)		F_(0, 0)			F_(0, 0)	F_(0, 0)	FM(STP_IVCXO27_1_D)	FM(REMOCON_A)	F_(0, 0)		F_(0, 0)	FM(TCLK1_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 403#define IP17_11_8	FM(USB0_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_RST_C)			F_(0, 0)	FM(TS_SCK1_D)	FM(STP_ISCLK_1_D)	FM(BPFCLK_B)	FM(RIF3_CLK_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
 404#define IP17_15_12	FM(USB0_OVC)		F_(0, 0)	F_(0, 0)		FM(SIM0_D_C)			F_(0, 0)	FM(TS_SDAT1_D)	FM(STP_ISD_1_D)		F_(0, 0)	FM(RIF3_SYNC_B)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
 405#define IP17_19_16	FM(USB1_PWEN)		F_(0, 0)	F_(0, 0)		FM(SIM0_CLK_C)			FM(SSI_SCK1_A)	FM(TS_SCK0_E)	FM(STP_ISCLK_0_E)	FM(FMCLK_B)	FM(RIF2_CLK_B)		F_(0, 0)	FM(SPEEDIN_A)	F_(0, 0)	F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
 406#define IP17_23_20	FM(USB1_OVC)		F_(0, 0)	FM(MSIOF1_SS2_C)	F_(0, 0)			FM(SSI_WS1_A)	FM(TS_SDAT0_E)	FM(STP_ISD_0_E)		FM(FMIN_B)	FM(RIF2_SYNC_B)		F_(0, 0)	FM(REMOCON_B)	F_(0, 0)	F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
 407#define IP17_27_24	FM(USB30_PWEN)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT_B)		FM(SSI_SCK2_B)	FM(TS_SDEN1_D)	FM(STP_ISEN_1_D)	FM(STP_OPWM_0_E)FM(RIF3_D0_B)		F_(0, 0)	FM(TCLK2_B)	FM(TPU0TO0)	FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 408#define IP17_31_28	FM(USB30_OVC)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT1_B)		FM(SSI_WS2_B)	FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)	FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)	F_(0, 0)	FM(FSO_TOE_N)	FM(TPU0TO1)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 409#define IP18_3_0	FM(GP6_30)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT2_B)		FM(SSI_SCK9_B)	FM(TS_SDEN0_E)	FM(STP_ISEN_0_E)	F_(0, 0)	FM(RIF2_D0_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO2)	FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
 410#define IP18_7_4	FM(GP6_31)		F_(0, 0)	F_(0, 0)		FM(AUDIO_CLKOUT3_B)		FM(SSI_WS9_B)	FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)	F_(0, 0)	FM(RIF2_D1_B)		F_(0, 0)	F_(0, 0)	FM(TPU0TO3)	FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
 411
 412#define PINMUX_GPSR	\
 413\
 414												GPSR6_31 \
 415												GPSR6_30 \
 416												GPSR6_29 \
 417		GPSR1_28									GPSR6_28 \
 418		GPSR1_27									GPSR6_27 \
 419		GPSR1_26									GPSR6_26 \
 420		GPSR1_25							GPSR5_25	GPSR6_25 \
 421		GPSR1_24							GPSR5_24	GPSR6_24 \
 422		GPSR1_23							GPSR5_23	GPSR6_23 \
 423		GPSR1_22							GPSR5_22	GPSR6_22 \
 424		GPSR1_21							GPSR5_21	GPSR6_21 \
 425		GPSR1_20							GPSR5_20	GPSR6_20 \
 426		GPSR1_19							GPSR5_19	GPSR6_19 \
 427		GPSR1_18							GPSR5_18	GPSR6_18 \
 428		GPSR1_17					GPSR4_17	GPSR5_17	GPSR6_17 \
 429		GPSR1_16					GPSR4_16	GPSR5_16	GPSR6_16 \
 430GPSR0_15	GPSR1_15			GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15 \
 431GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14 \
 432GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13 \
 433GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12 \
 434GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11 \
 435GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10 \
 436GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9 \
 437GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8 \
 438GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7 \
 439GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6 \
 440GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5 \
 441GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4 \
 442GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3 \
 443GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2 \
 444GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1 \
 445GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0
 446
 447#define PINMUX_IPSR				\
 448\
 449FM(IP0_3_0)	IP0_3_0		FM(IP1_3_0)	IP1_3_0		FM(IP2_3_0)	IP2_3_0		FM(IP3_3_0)	IP3_3_0 \
 450FM(IP0_7_4)	IP0_7_4		FM(IP1_7_4)	IP1_7_4		FM(IP2_7_4)	IP2_7_4		FM(IP3_7_4)	IP3_7_4 \
 451FM(IP0_11_8)	IP0_11_8	FM(IP1_11_8)	IP1_11_8	FM(IP2_11_8)	IP2_11_8	FM(IP3_11_8)	IP3_11_8 \
 452FM(IP0_15_12)	IP0_15_12	FM(IP1_15_12)	IP1_15_12	FM(IP2_15_12)	IP2_15_12	FM(IP3_15_12)	IP3_15_12 \
 453FM(IP0_19_16)	IP0_19_16	FM(IP1_19_16)	IP1_19_16	FM(IP2_19_16)	IP2_19_16	FM(IP3_19_16)	IP3_19_16 \
 454FM(IP0_23_20)	IP0_23_20	FM(IP1_23_20)	IP1_23_20	FM(IP2_23_20)	IP2_23_20	FM(IP3_23_20)	IP3_23_20 \
 455FM(IP0_27_24)	IP0_27_24	FM(IP1_27_24)	IP1_27_24	FM(IP2_27_24)	IP2_27_24	FM(IP3_27_24)	IP3_27_24 \
 456FM(IP0_31_28)	IP0_31_28	FM(IP1_31_28)	IP1_31_28	FM(IP2_31_28)	IP2_31_28	FM(IP3_31_28)	IP3_31_28 \
 457\
 458FM(IP4_3_0)	IP4_3_0		FM(IP5_3_0)	IP5_3_0		FM(IP6_3_0)	IP6_3_0		FM(IP7_3_0)	IP7_3_0 \
 459FM(IP4_7_4)	IP4_7_4		FM(IP5_7_4)	IP5_7_4		FM(IP6_7_4)	IP6_7_4		FM(IP7_7_4)	IP7_7_4 \
 460FM(IP4_11_8)	IP4_11_8	FM(IP5_11_8)	IP5_11_8	FM(IP6_11_8)	IP6_11_8	FM(IP7_11_8)	IP7_11_8 \
 461FM(IP4_15_12)	IP4_15_12	FM(IP5_15_12)	IP5_15_12	FM(IP6_15_12)	IP6_15_12 \
 462FM(IP4_19_16)	IP4_19_16	FM(IP5_19_16)	IP5_19_16	FM(IP6_19_16)	IP6_19_16	FM(IP7_19_16)	IP7_19_16 \
 463FM(IP4_23_20)	IP4_23_20	FM(IP5_23_20)	IP5_23_20	FM(IP6_23_20)	IP6_23_20	FM(IP7_23_20)	IP7_23_20 \
 464FM(IP4_27_24)	IP4_27_24	FM(IP5_27_24)	IP5_27_24	FM(IP6_27_24)	IP6_27_24	FM(IP7_27_24)	IP7_27_24 \
 465FM(IP4_31_28)	IP4_31_28	FM(IP5_31_28)	IP5_31_28	FM(IP6_31_28)	IP6_31_28	FM(IP7_31_28)	IP7_31_28 \
 466\
 467FM(IP8_3_0)	IP8_3_0		FM(IP9_3_0)	IP9_3_0		FM(IP10_3_0)	IP10_3_0	FM(IP11_3_0)	IP11_3_0 \
 468FM(IP8_7_4)	IP8_7_4		FM(IP9_7_4)	IP9_7_4		FM(IP10_7_4)	IP10_7_4	FM(IP11_7_4)	IP11_7_4 \
 469FM(IP8_11_8)	IP8_11_8	FM(IP9_11_8)	IP9_11_8	FM(IP10_11_8)	IP10_11_8	FM(IP11_11_8)	IP11_11_8 \
 470FM(IP8_15_12)	IP8_15_12	FM(IP9_15_12)	IP9_15_12	FM(IP10_15_12)	IP10_15_12	FM(IP11_15_12)	IP11_15_12 \
 471FM(IP8_19_16)	IP8_19_16	FM(IP9_19_16)	IP9_19_16	FM(IP10_19_16)	IP10_19_16	FM(IP11_19_16)	IP11_19_16 \
 472FM(IP8_23_20)	IP8_23_20	FM(IP9_23_20)	IP9_23_20	FM(IP10_23_20)	IP10_23_20	FM(IP11_23_20)	IP11_23_20 \
 473FM(IP8_27_24)	IP8_27_24	FM(IP9_27_24)	IP9_27_24	FM(IP10_27_24)	IP10_27_24	FM(IP11_27_24)	IP11_27_24 \
 474FM(IP8_31_28)	IP8_31_28	FM(IP9_31_28)	IP9_31_28	FM(IP10_31_28)	IP10_31_28	FM(IP11_31_28)	IP11_31_28 \
 475\
 476FM(IP12_3_0)	IP12_3_0	FM(IP13_3_0)	IP13_3_0	FM(IP14_3_0)	IP14_3_0	FM(IP15_3_0)	IP15_3_0 \
 477FM(IP12_7_4)	IP12_7_4	FM(IP13_7_4)	IP13_7_4	FM(IP14_7_4)	IP14_7_4	FM(IP15_7_4)	IP15_7_4 \
 478FM(IP12_11_8)	IP12_11_8	FM(IP13_11_8)	IP13_11_8	FM(IP14_11_8)	IP14_11_8	FM(IP15_11_8)	IP15_11_8 \
 479FM(IP12_15_12)	IP12_15_12	FM(IP13_15_12)	IP13_15_12	FM(IP14_15_12)	IP14_15_12	FM(IP15_15_12)	IP15_15_12 \
 480FM(IP12_19_16)	IP12_19_16	FM(IP13_19_16)	IP13_19_16	FM(IP14_19_16)	IP14_19_16	FM(IP15_19_16)	IP15_19_16 \
 481FM(IP12_23_20)	IP12_23_20	FM(IP13_23_20)	IP13_23_20	FM(IP14_23_20)	IP14_23_20	FM(IP15_23_20)	IP15_23_20 \
 482FM(IP12_27_24)	IP12_27_24	FM(IP13_27_24)	IP13_27_24	FM(IP14_27_24)	IP14_27_24	FM(IP15_27_24)	IP15_27_24 \
 483FM(IP12_31_28)	IP12_31_28	FM(IP13_31_28)	IP13_31_28	FM(IP14_31_28)	IP14_31_28	FM(IP15_31_28)	IP15_31_28 \
 484\
 485FM(IP16_3_0)	IP16_3_0	FM(IP17_3_0)	IP17_3_0	FM(IP18_3_0)	IP18_3_0 \
 486FM(IP16_7_4)	IP16_7_4	FM(IP17_7_4)	IP17_7_4	FM(IP18_7_4)	IP18_7_4 \
 487FM(IP16_11_8)	IP16_11_8	FM(IP17_11_8)	IP17_11_8 \
 488FM(IP16_15_12)	IP16_15_12	FM(IP17_15_12)	IP17_15_12 \
 489FM(IP16_19_16)	IP16_19_16	FM(IP17_19_16)	IP17_19_16 \
 490FM(IP16_23_20)	IP16_23_20	FM(IP17_23_20)	IP17_23_20 \
 491FM(IP16_27_24)	IP16_27_24	FM(IP17_27_24)	IP17_27_24 \
 492FM(IP16_31_28)	IP16_31_28	FM(IP17_31_28)	IP17_31_28
 493
 494/* MOD_SEL0 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 495#define MOD_SEL0_31_30_29	FM(SEL_MSIOF3_0)	FM(SEL_MSIOF3_1)	FM(SEL_MSIOF3_2)	FM(SEL_MSIOF3_3)	FM(SEL_MSIOF3_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
 496#define MOD_SEL0_28_27		FM(SEL_MSIOF2_0)	FM(SEL_MSIOF2_1)	FM(SEL_MSIOF2_2)	FM(SEL_MSIOF2_3)
 497#define MOD_SEL0_26_25_24	FM(SEL_MSIOF1_0)	FM(SEL_MSIOF1_1)	FM(SEL_MSIOF1_2)	FM(SEL_MSIOF1_3)	FM(SEL_MSIOF1_4)	FM(SEL_MSIOF1_5)	FM(SEL_MSIOF1_6)	F_(0, 0)
 498#define MOD_SEL0_23		FM(SEL_LBSC_0)		FM(SEL_LBSC_1)
 499#define MOD_SEL0_22		FM(SEL_IEBUS_0)		FM(SEL_IEBUS_1)
 500#define MOD_SEL0_21		FM(SEL_I2C2_0)		FM(SEL_I2C2_1)
 501#define MOD_SEL0_20		FM(SEL_I2C1_0)		FM(SEL_I2C1_1)
 502#define MOD_SEL0_19		FM(SEL_HSCIF4_0)	FM(SEL_HSCIF4_1)
 503#define MOD_SEL0_18_17		FM(SEL_HSCIF3_0)	FM(SEL_HSCIF3_1)	FM(SEL_HSCIF3_2)	FM(SEL_HSCIF3_3)
 504#define MOD_SEL0_16		FM(SEL_HSCIF1_0)	FM(SEL_HSCIF1_1)
 505#define MOD_SEL0_14_13		FM(SEL_HSCIF2_0)	FM(SEL_HSCIF2_1)	FM(SEL_HSCIF2_2)	F_(0, 0)
 506#define MOD_SEL0_12		FM(SEL_ETHERAVB_0)	FM(SEL_ETHERAVB_1)
 507#define MOD_SEL0_11		FM(SEL_DRIF3_0)		FM(SEL_DRIF3_1)
 508#define MOD_SEL0_10		FM(SEL_DRIF2_0)		FM(SEL_DRIF2_1)
 509#define MOD_SEL0_9_8		FM(SEL_DRIF1_0)		FM(SEL_DRIF1_1)		FM(SEL_DRIF1_2)		F_(0, 0)
 510#define MOD_SEL0_7_6		FM(SEL_DRIF0_0)		FM(SEL_DRIF0_1)		FM(SEL_DRIF0_2)		F_(0, 0)
 511#define MOD_SEL0_5		FM(SEL_CANFD0_0)	FM(SEL_CANFD0_1)
 512#define MOD_SEL0_4_3		FM(SEL_ADGA_0)		FM(SEL_ADGA_1)		FM(SEL_ADGA_2)		FM(SEL_ADGA_3)
 513
 514/* MOD_SEL1 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 515#define MOD_SEL1_31_30		FM(SEL_TSIF1_0)		FM(SEL_TSIF1_1)		FM(SEL_TSIF1_2)		FM(SEL_TSIF1_3)
 516#define MOD_SEL1_29_28_27	FM(SEL_TSIF0_0)		FM(SEL_TSIF0_1)		FM(SEL_TSIF0_2)		FM(SEL_TSIF0_3)		FM(SEL_TSIF0_4)		F_(0, 0)		F_(0, 0)		F_(0, 0)
 517#define MOD_SEL1_26		FM(SEL_TIMER_TMU_0)	FM(SEL_TIMER_TMU_1)
 518#define MOD_SEL1_25_24		FM(SEL_SSP1_1_0)	FM(SEL_SSP1_1_1)	FM(SEL_SSP1_1_2)	FM(SEL_SSP1_1_3)
 519#define MOD_SEL1_23_22_21	FM(SEL_SSP1_0_0)	FM(SEL_SSP1_0_1)	FM(SEL_SSP1_0_2)	FM(SEL_SSP1_0_3)	FM(SEL_SSP1_0_4)	F_(0, 0)		F_(0, 0)		F_(0, 0)
 520#define MOD_SEL1_20		FM(SEL_SSI1_0)		FM(SEL_SSI1_1)
 521#define MOD_SEL1_19		FM(SEL_SPEED_PULSE_0)	FM(SEL_SPEED_PULSE_1)
 522#define MOD_SEL1_18_17		FM(SEL_SIMCARD_0)	FM(SEL_SIMCARD_1)	FM(SEL_SIMCARD_2)	FM(SEL_SIMCARD_3)
 523#define MOD_SEL1_16		FM(SEL_SDHI2_0)		FM(SEL_SDHI2_1)
 524#define MOD_SEL1_15_14		FM(SEL_SCIF4_0)		FM(SEL_SCIF4_1)		FM(SEL_SCIF4_2)		F_(0, 0)
 525#define MOD_SEL1_13		FM(SEL_SCIF3_0)		FM(SEL_SCIF3_1)
 526#define MOD_SEL1_12		FM(SEL_SCIF2_0)		FM(SEL_SCIF2_1)
 527#define MOD_SEL1_11		FM(SEL_SCIF1_0)		FM(SEL_SCIF1_1)
 528#define MOD_SEL1_10		FM(SEL_SCIF_0)		FM(SEL_SCIF_1)
 529#define MOD_SEL1_9		FM(SEL_REMOCON_0)	FM(SEL_REMOCON_1)
 530#define MOD_SEL1_6		FM(SEL_RCAN0_0)		FM(SEL_RCAN0_1)
 531#define MOD_SEL1_5		FM(SEL_PWM6_0)		FM(SEL_PWM6_1)
 532#define MOD_SEL1_4		FM(SEL_PWM5_0)		FM(SEL_PWM5_1)
 533#define MOD_SEL1_3		FM(SEL_PWM4_0)		FM(SEL_PWM4_1)
 534#define MOD_SEL1_2		FM(SEL_PWM3_0)		FM(SEL_PWM3_1)
 535#define MOD_SEL1_1		FM(SEL_PWM2_0)		FM(SEL_PWM2_1)
 536#define MOD_SEL1_0		FM(SEL_PWM1_0)		FM(SEL_PWM1_1)
 537
 538/* MOD_SEL2 */			/* 0 */			/* 1 */			/* 2 */			/* 3 */			/* 4 */			/* 5 */			/* 6 */			/* 7 */
 539#define MOD_SEL2_31		FM(I2C_SEL_5_0)		FM(I2C_SEL_5_1)
 540#define MOD_SEL2_30		FM(I2C_SEL_3_0)		FM(I2C_SEL_3_1)
 541#define MOD_SEL2_29		FM(I2C_SEL_0_0)		FM(I2C_SEL_0_1)
 542#define MOD_SEL2_28_27		FM(SEL_FM_0)		FM(SEL_FM_1)		FM(SEL_FM_2)		FM(SEL_FM_3)
 543#define MOD_SEL2_26		FM(SEL_SCIF5_0)		FM(SEL_SCIF5_1)
 544#define MOD_SEL2_25_24_23	FM(SEL_I2C6_0)		FM(SEL_I2C6_1)		FM(SEL_I2C6_2)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)
 545#define MOD_SEL2_22		FM(SEL_NDF_0)		FM(SEL_NDF_1)
 546#define MOD_SEL2_21		FM(SEL_SSI2_0)		FM(SEL_SSI2_1)
 547#define MOD_SEL2_20		FM(SEL_SSI9_0)		FM(SEL_SSI9_1)
 548#define MOD_SEL2_19		FM(SEL_TIMER_TMU2_0)	FM(SEL_TIMER_TMU2_1)
 549#define MOD_SEL2_18		FM(SEL_ADGB_0)		FM(SEL_ADGB_1)
 550#define MOD_SEL2_17		FM(SEL_ADGC_0)		FM(SEL_ADGC_1)
 551#define MOD_SEL2_0		FM(SEL_VIN4_0)		FM(SEL_VIN4_1)
 552
 553#define PINMUX_MOD_SELS	\
 554\
 555MOD_SEL0_31_30_29	MOD_SEL1_31_30		MOD_SEL2_31 \
 556						MOD_SEL2_30 \
 557			MOD_SEL1_29_28_27	MOD_SEL2_29 \
 558MOD_SEL0_28_27					MOD_SEL2_28_27 \
 559MOD_SEL0_26_25_24	MOD_SEL1_26		MOD_SEL2_26 \
 560			MOD_SEL1_25_24		MOD_SEL2_25_24_23 \
 561MOD_SEL0_23		MOD_SEL1_23_22_21 \
 562MOD_SEL0_22					MOD_SEL2_22 \
 563MOD_SEL0_21					MOD_SEL2_21 \
 564MOD_SEL0_20		MOD_SEL1_20		MOD_SEL2_20 \
 565MOD_SEL0_19		MOD_SEL1_19		MOD_SEL2_19 \
 566MOD_SEL0_18_17		MOD_SEL1_18_17		MOD_SEL2_18 \
 567						MOD_SEL2_17 \
 568MOD_SEL0_16		MOD_SEL1_16 \
 569			MOD_SEL1_15_14 \
 570MOD_SEL0_14_13 \
 571			MOD_SEL1_13 \
 572MOD_SEL0_12		MOD_SEL1_12 \
 573MOD_SEL0_11		MOD_SEL1_11 \
 574MOD_SEL0_10		MOD_SEL1_10 \
 575MOD_SEL0_9_8		MOD_SEL1_9 \
 576MOD_SEL0_7_6 \
 577			MOD_SEL1_6 \
 578MOD_SEL0_5		MOD_SEL1_5 \
 579MOD_SEL0_4_3		MOD_SEL1_4 \
 580			MOD_SEL1_3 \
 581			MOD_SEL1_2 \
 582			MOD_SEL1_1 \
 583			MOD_SEL1_0		MOD_SEL2_0
 584
 585/*
 586 * These pins are not able to be muxed but have other properties
 587 * that can be set, such as drive-strength or pull-up/pull-down enable.
 588 */
 589#define PINMUX_STATIC \
 590	FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
 591	FM(QSPI0_IO2) FM(QSPI0_IO3) \
 592	FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
 593	FM(QSPI1_IO2) FM(QSPI1_IO3) \
 594	FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
 595	FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
 596	FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
 597	FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
 598	FM(PRESETOUT) \
 599	FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
 600	FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
 601
 602#define PINMUX_PHYS \
 603	FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
 604
 605enum {
 606	PINMUX_RESERVED = 0,
 607
 608	PINMUX_DATA_BEGIN,
 609	GP_ALL(DATA),
 610	PINMUX_DATA_END,
 611
 612#define F_(x, y)
 613#define FM(x)	FN_##x,
 614	PINMUX_FUNCTION_BEGIN,
 615	GP_ALL(FN),
 616	PINMUX_GPSR
 617	PINMUX_IPSR
 618	PINMUX_MOD_SELS
 619	PINMUX_FUNCTION_END,
 620#undef F_
 621#undef FM
 622
 623#define F_(x, y)
 624#define FM(x)	x##_MARK,
 625	PINMUX_MARK_BEGIN,
 626	PINMUX_GPSR
 627	PINMUX_IPSR
 628	PINMUX_MOD_SELS
 629	PINMUX_STATIC
 630	PINMUX_PHYS
 631	PINMUX_MARK_END,
 632#undef F_
 633#undef FM
 634};
 635
 636static const u16 pinmux_data[] = {
 637	PINMUX_DATA_GP_ALL(),
 638
 639	PINMUX_SINGLE(AVS1),
 640	PINMUX_SINGLE(AVS2),
 641	PINMUX_SINGLE(CLKOUT),
 642	PINMUX_SINGLE(GP7_03),
 643	PINMUX_SINGLE(GP7_02),
 644	PINMUX_SINGLE(MSIOF0_RXD),
 645	PINMUX_SINGLE(MSIOF0_SCK),
 646	PINMUX_SINGLE(MSIOF0_TXD),
 647	PINMUX_SINGLE(SSI_SCK5),
 648	PINMUX_SINGLE(SSI_SDATA5),
 649	PINMUX_SINGLE(SSI_WS5),
 650
 651	/* IPSR0 */
 652	PINMUX_IPSR_GPSR(IP0_3_0,	AVB_MDC),
 653	PINMUX_IPSR_MSEL(IP0_3_0,	MSIOF2_SS2_C,		SEL_MSIOF2_2),
 654
 655	PINMUX_IPSR_GPSR(IP0_7_4,	AVB_MAGIC),
 656	PINMUX_IPSR_MSEL(IP0_7_4,	MSIOF2_SS1_C,		SEL_MSIOF2_2),
 657	PINMUX_IPSR_MSEL(IP0_7_4,	SCK4_A,			SEL_SCIF4_0),
 658
 659	PINMUX_IPSR_GPSR(IP0_11_8,	AVB_PHY_INT),
 660	PINMUX_IPSR_MSEL(IP0_11_8,	MSIOF2_SYNC_C,		SEL_MSIOF2_2),
 661	PINMUX_IPSR_MSEL(IP0_11_8,	RX4_A,			SEL_SCIF4_0),
 662
 663	PINMUX_IPSR_GPSR(IP0_15_12,	AVB_LINK),
 664	PINMUX_IPSR_MSEL(IP0_15_12,	MSIOF2_SCK_C,		SEL_MSIOF2_2),
 665	PINMUX_IPSR_MSEL(IP0_15_12,	TX4_A,			SEL_SCIF4_0),
 666
 667	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
 668	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
 669	PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 670	PINMUX_IPSR_PHYS(IP0_19_16,	SCL5,			I2C_SEL_5_1),
 671
 672	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,	I2C_SEL_5_0,	SEL_ETHERAVB_0),
 673	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,		I2C_SEL_5_0,	SEL_MSIOF2_2),
 674	PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,		I2C_SEL_5_0,	SEL_SCIF4_0),
 675	PINMUX_IPSR_PHYS(IP0_23_20,	SDA5,			I2C_SEL_5_1),
 676
 677	PINMUX_IPSR_GPSR(IP0_27_24,	IRQ0),
 678	PINMUX_IPSR_GPSR(IP0_27_24,	QPOLB),
 679	PINMUX_IPSR_GPSR(IP0_27_24,	DU_CDE),
 680	PINMUX_IPSR_MSEL(IP0_27_24,	VI4_DATA0_B,		SEL_VIN4_1),
 681	PINMUX_IPSR_MSEL(IP0_27_24,	CAN0_TX_B,		SEL_RCAN0_1),
 682	PINMUX_IPSR_MSEL(IP0_27_24,	CANFD0_TX_B,		SEL_CANFD0_1),
 683	PINMUX_IPSR_MSEL(IP0_27_24,	MSIOF3_SS2_E,		SEL_MSIOF3_4),
 684
 685	PINMUX_IPSR_GPSR(IP0_31_28,	IRQ1),
 686	PINMUX_IPSR_GPSR(IP0_31_28,	QPOLA),
 687	PINMUX_IPSR_GPSR(IP0_31_28,	DU_DISP),
 688	PINMUX_IPSR_MSEL(IP0_31_28,	VI4_DATA1_B,		SEL_VIN4_1),
 689	PINMUX_IPSR_MSEL(IP0_31_28,	CAN0_RX_B,		SEL_RCAN0_1),
 690	PINMUX_IPSR_MSEL(IP0_31_28,	CANFD0_RX_B,		SEL_CANFD0_1),
 691	PINMUX_IPSR_MSEL(IP0_31_28,	MSIOF3_SS1_E,		SEL_MSIOF3_4),
 692
 693	/* IPSR1 */
 694	PINMUX_IPSR_GPSR(IP1_3_0,	IRQ2),
 695	PINMUX_IPSR_GPSR(IP1_3_0,	QCPV_QDE),
 696	PINMUX_IPSR_GPSR(IP1_3_0,	DU_EXODDF_DU_ODDF_DISP_CDE),
 697	PINMUX_IPSR_MSEL(IP1_3_0,	VI4_DATA2_B,		SEL_VIN4_1),
 698	PINMUX_IPSR_MSEL(IP1_3_0,	PWM3_B,			SEL_PWM3_1),
 699	PINMUX_IPSR_MSEL(IP1_3_0,	MSIOF3_SYNC_E,		SEL_MSIOF3_4),
 700
 701	PINMUX_IPSR_GPSR(IP1_7_4,	IRQ3),
 702	PINMUX_IPSR_GPSR(IP1_7_4,	QSTVB_QVE),
 703	PINMUX_IPSR_GPSR(IP1_7_4,	DU_DOTCLKOUT1),
 704	PINMUX_IPSR_MSEL(IP1_7_4,	VI4_DATA3_B,		SEL_VIN4_1),
 705	PINMUX_IPSR_MSEL(IP1_7_4,	PWM4_B,			SEL_PWM4_1),
 706	PINMUX_IPSR_MSEL(IP1_7_4,	MSIOF3_SCK_E,		SEL_MSIOF3_4),
 707
 708	PINMUX_IPSR_GPSR(IP1_11_8,	IRQ4),
 709	PINMUX_IPSR_GPSR(IP1_11_8,	QSTH_QHS),
 710	PINMUX_IPSR_GPSR(IP1_11_8,	DU_EXHSYNC_DU_HSYNC),
 711	PINMUX_IPSR_MSEL(IP1_11_8,	VI4_DATA4_B,		SEL_VIN4_1),
 712	PINMUX_IPSR_MSEL(IP1_11_8,	PWM5_B,			SEL_PWM5_1),
 713	PINMUX_IPSR_MSEL(IP1_11_8,	MSIOF3_RXD_E,		SEL_MSIOF3_4),
 714
 715	PINMUX_IPSR_GPSR(IP1_15_12,	IRQ5),
 716	PINMUX_IPSR_GPSR(IP1_15_12,	QSTB_QHE),
 717	PINMUX_IPSR_GPSR(IP1_15_12,	DU_EXVSYNC_DU_VSYNC),
 718	PINMUX_IPSR_MSEL(IP1_15_12,	VI4_DATA5_B,		SEL_VIN4_1),
 719	PINMUX_IPSR_MSEL(IP1_15_12,	PWM6_B,			SEL_PWM6_1),
 720	PINMUX_IPSR_MSEL(IP1_15_12,	MSIOF3_TXD_E,		SEL_MSIOF3_4),
 721
 722	PINMUX_IPSR_GPSR(IP1_19_16,	PWM0),
 723	PINMUX_IPSR_GPSR(IP1_19_16,	AVB_AVTP_PPS),
 724	PINMUX_IPSR_MSEL(IP1_19_16,	VI4_DATA6_B,		SEL_VIN4_1),
 725	PINMUX_IPSR_MSEL(IP1_19_16,	IECLK_B,		SEL_IEBUS_1),
 726
 727	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,		I2C_SEL_3_0,	SEL_PWM1_0),
 728	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
 729	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,		I2C_SEL_3_0,	SEL_VIN4_1),
 730	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
 731	PINMUX_IPSR_PHYS(IP1_23_20,	SCL3,			I2C_SEL_3_1),
 732
 733	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,		I2C_SEL_3_0,	SEL_PWM2_0),
 734	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,		I2C_SEL_3_0,	SEL_HSCIF3_3),
 735	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,		I2C_SEL_3_0,	SEL_IEBUS_1),
 736	PINMUX_IPSR_PHYS(IP1_27_24,	SDA3,			I2C_SEL_3_1),
 737
 738	PINMUX_IPSR_GPSR(IP1_31_28,	A0),
 739	PINMUX_IPSR_GPSR(IP1_31_28,	LCDOUT16),
 740	PINMUX_IPSR_MSEL(IP1_31_28,	MSIOF3_SYNC_B,		SEL_MSIOF3_1),
 741	PINMUX_IPSR_GPSR(IP1_31_28,	VI4_DATA8),
 742	PINMUX_IPSR_GPSR(IP1_31_28,	DU_DB0),
 743	PINMUX_IPSR_MSEL(IP1_31_28,	PWM3_A,			SEL_PWM3_0),
 744
 745	/* IPSR2 */
 746	PINMUX_IPSR_GPSR(IP2_3_0,	A1),
 747	PINMUX_IPSR_GPSR(IP2_3_0,	LCDOUT17),
 748	PINMUX_IPSR_MSEL(IP2_3_0,	MSIOF3_TXD_B,		SEL_MSIOF3_1),
 749	PINMUX_IPSR_GPSR(IP2_3_0,	VI4_DATA9),
 750	PINMUX_IPSR_GPSR(IP2_3_0,	DU_DB1),
 751	PINMUX_IPSR_MSEL(IP2_3_0,	PWM4_A,			SEL_PWM4_0),
 752
 753	PINMUX_IPSR_GPSR(IP2_7_4,	A2),
 754	PINMUX_IPSR_GPSR(IP2_7_4,	LCDOUT18),
 755	PINMUX_IPSR_MSEL(IP2_7_4,	MSIOF3_SCK_B,		SEL_MSIOF3_1),
 756	PINMUX_IPSR_GPSR(IP2_7_4,	VI4_DATA10),
 757	PINMUX_IPSR_GPSR(IP2_7_4,	DU_DB2),
 758	PINMUX_IPSR_MSEL(IP2_7_4,	PWM5_A,			SEL_PWM5_0),
 759
 760	PINMUX_IPSR_GPSR(IP2_11_8,	A3),
 761	PINMUX_IPSR_GPSR(IP2_11_8,	LCDOUT19),
 762	PINMUX_IPSR_MSEL(IP2_11_8,	MSIOF3_RXD_B,		SEL_MSIOF3_1),
 763	PINMUX_IPSR_GPSR(IP2_11_8,	VI4_DATA11),
 764	PINMUX_IPSR_GPSR(IP2_11_8,	DU_DB3),
 765	PINMUX_IPSR_MSEL(IP2_11_8,	PWM6_A,			SEL_PWM6_0),
 766
 767	PINMUX_IPSR_GPSR(IP2_15_12,	A4),
 768	PINMUX_IPSR_GPSR(IP2_15_12,	LCDOUT20),
 769	PINMUX_IPSR_MSEL(IP2_15_12,	MSIOF3_SS1_B,		SEL_MSIOF3_1),
 770	PINMUX_IPSR_GPSR(IP2_15_12,	VI4_DATA12),
 771	PINMUX_IPSR_GPSR(IP2_15_12,	VI5_DATA12),
 772	PINMUX_IPSR_GPSR(IP2_15_12,	DU_DB4),
 773
 774	PINMUX_IPSR_GPSR(IP2_19_16,	A5),
 775	PINMUX_IPSR_GPSR(IP2_19_16,	LCDOUT21),
 776	PINMUX_IPSR_MSEL(IP2_19_16,	MSIOF3_SS2_B,		SEL_MSIOF3_1),
 777	PINMUX_IPSR_MSEL(IP2_19_16,	SCK4_B,			SEL_SCIF4_1),
 778	PINMUX_IPSR_GPSR(IP2_19_16,	VI4_DATA13),
 779	PINMUX_IPSR_GPSR(IP2_19_16,	VI5_DATA13),
 780	PINMUX_IPSR_GPSR(IP2_19_16,	DU_DB5),
 781
 782	PINMUX_IPSR_GPSR(IP2_23_20,	A6),
 783	PINMUX_IPSR_GPSR(IP2_23_20,	LCDOUT22),
 784	PINMUX_IPSR_MSEL(IP2_23_20,	MSIOF2_SS1_A,		SEL_MSIOF2_0),
 785	PINMUX_IPSR_MSEL(IP2_23_20,	RX4_B,			SEL_SCIF4_1),
 786	PINMUX_IPSR_GPSR(IP2_23_20,	VI4_DATA14),
 787	PINMUX_IPSR_GPSR(IP2_23_20,	VI5_DATA14),
 788	PINMUX_IPSR_GPSR(IP2_23_20,	DU_DB6),
 789
 790	PINMUX_IPSR_GPSR(IP2_27_24,	A7),
 791	PINMUX_IPSR_GPSR(IP2_27_24,	LCDOUT23),
 792	PINMUX_IPSR_MSEL(IP2_27_24,	MSIOF2_SS2_A,		SEL_MSIOF2_0),
 793	PINMUX_IPSR_MSEL(IP2_27_24,	TX4_B,			SEL_SCIF4_1),
 794	PINMUX_IPSR_GPSR(IP2_27_24,	VI4_DATA15),
 795	PINMUX_IPSR_GPSR(IP2_27_24,	VI5_DATA15),
 796	PINMUX_IPSR_GPSR(IP2_27_24,	DU_DB7),
 797
 798	PINMUX_IPSR_GPSR(IP2_31_28,	A8),
 799	PINMUX_IPSR_MSEL(IP2_31_28,	RX3_B,			SEL_SCIF3_1),
 800	PINMUX_IPSR_MSEL(IP2_31_28,	MSIOF2_SYNC_A,		SEL_MSIOF2_0),
 801	PINMUX_IPSR_MSEL(IP2_31_28,	HRX4_B,			SEL_HSCIF4_1),
 802	PINMUX_IPSR_MSEL(IP2_31_28,	SDA6_A,			SEL_I2C6_0),
 803	PINMUX_IPSR_MSEL(IP2_31_28,	AVB_AVTP_MATCH_B,	SEL_ETHERAVB_1),
 804	PINMUX_IPSR_MSEL(IP2_31_28,	PWM1_B,			SEL_PWM1_1),
 805
 806	/* IPSR3 */
 807	PINMUX_IPSR_GPSR(IP3_3_0,	A9),
 808	PINMUX_IPSR_MSEL(IP3_3_0,	MSIOF2_SCK_A,		SEL_MSIOF2_0),
 809	PINMUX_IPSR_MSEL(IP3_3_0,	CTS4_N_B,		SEL_SCIF4_1),
 810	PINMUX_IPSR_GPSR(IP3_3_0,	VI5_VSYNC_N),
 811
 812	PINMUX_IPSR_GPSR(IP3_7_4,	A10),
 813	PINMUX_IPSR_MSEL(IP3_7_4,	MSIOF2_RXD_A,		SEL_MSIOF2_0),
 814	PINMUX_IPSR_MSEL(IP3_7_4,	RTS4_N_B,		SEL_SCIF4_1),
 815	PINMUX_IPSR_GPSR(IP3_7_4,	VI5_HSYNC_N),
 816
 817	PINMUX_IPSR_GPSR(IP3_11_8,	A11),
 818	PINMUX_IPSR_MSEL(IP3_11_8,	TX3_B,			SEL_SCIF3_1),
 819	PINMUX_IPSR_MSEL(IP3_11_8,	MSIOF2_TXD_A,		SEL_MSIOF2_0),
 820	PINMUX_IPSR_MSEL(IP3_11_8,	HTX4_B,			SEL_HSCIF4_1),
 821	PINMUX_IPSR_GPSR(IP3_11_8,	HSCK4),
 822	PINMUX_IPSR_GPSR(IP3_11_8,	VI5_FIELD),
 823	PINMUX_IPSR_MSEL(IP3_11_8,	SCL6_A,			SEL_I2C6_0),
 824	PINMUX_IPSR_MSEL(IP3_11_8,	AVB_AVTP_CAPTURE_B,	SEL_ETHERAVB_1),
 825	PINMUX_IPSR_MSEL(IP3_11_8,	PWM2_B,			SEL_PWM2_1),
 826
 827	PINMUX_IPSR_GPSR(IP3_15_12,	A12),
 828	PINMUX_IPSR_GPSR(IP3_15_12,	LCDOUT12),
 829	PINMUX_IPSR_MSEL(IP3_15_12,	MSIOF3_SCK_C,		SEL_MSIOF3_2),
 830	PINMUX_IPSR_MSEL(IP3_15_12,	HRX4_A,			SEL_HSCIF4_0),
 831	PINMUX_IPSR_GPSR(IP3_15_12,	VI5_DATA8),
 832	PINMUX_IPSR_GPSR(IP3_15_12,	DU_DG4),
 833
 834	PINMUX_IPSR_GPSR(IP3_19_16,	A13),
 835	PINMUX_IPSR_GPSR(IP3_19_16,	LCDOUT13),
 836	PINMUX_IPSR_MSEL(IP3_19_16,	MSIOF3_SYNC_C,		SEL_MSIOF3_2),
 837	PINMUX_IPSR_MSEL(IP3_19_16,	HTX4_A,			SEL_HSCIF4_0),
 838	PINMUX_IPSR_GPSR(IP3_19_16,	VI5_DATA9),
 839	PINMUX_IPSR_GPSR(IP3_19_16,	DU_DG5),
 840
 841	PINMUX_IPSR_GPSR(IP3_23_20,	A14),
 842	PINMUX_IPSR_GPSR(IP3_23_20,	LCDOUT14),
 843	PINMUX_IPSR_MSEL(IP3_23_20,	MSIOF3_RXD_C,		SEL_MSIOF3_2),
 844	PINMUX_IPSR_GPSR(IP3_23_20,	HCTS4_N),
 845	PINMUX_IPSR_GPSR(IP3_23_20,	VI5_DATA10),
 846	PINMUX_IPSR_GPSR(IP3_23_20,	DU_DG6),
 847
 848	PINMUX_IPSR_GPSR(IP3_27_24,	A15),
 849	PINMUX_IPSR_GPSR(IP3_27_24,	LCDOUT15),
 850	PINMUX_IPSR_MSEL(IP3_27_24,	MSIOF3_TXD_C,		SEL_MSIOF3_2),
 851	PINMUX_IPSR_GPSR(IP3_27_24,	HRTS4_N),
 852	PINMUX_IPSR_GPSR(IP3_27_24,	VI5_DATA11),
 853	PINMUX_IPSR_GPSR(IP3_27_24,	DU_DG7),
 854
 855	PINMUX_IPSR_GPSR(IP3_31_28,	A16),
 856	PINMUX_IPSR_GPSR(IP3_31_28,	LCDOUT8),
 857	PINMUX_IPSR_GPSR(IP3_31_28,	VI4_FIELD),
 858	PINMUX_IPSR_GPSR(IP3_31_28,	DU_DG0),
 859
 860	/* IPSR4 */
 861	PINMUX_IPSR_GPSR(IP4_3_0,	A17),
 862	PINMUX_IPSR_GPSR(IP4_3_0,	LCDOUT9),
 863	PINMUX_IPSR_GPSR(IP4_3_0,	VI4_VSYNC_N),
 864	PINMUX_IPSR_GPSR(IP4_3_0,	DU_DG1),
 865
 866	PINMUX_IPSR_GPSR(IP4_7_4,	A18),
 867	PINMUX_IPSR_GPSR(IP4_7_4,	LCDOUT10),
 868	PINMUX_IPSR_GPSR(IP4_7_4,	VI4_HSYNC_N),
 869	PINMUX_IPSR_GPSR(IP4_7_4,	DU_DG2),
 870
 871	PINMUX_IPSR_GPSR(IP4_11_8,	A19),
 872	PINMUX_IPSR_GPSR(IP4_11_8,	LCDOUT11),
 873	PINMUX_IPSR_GPSR(IP4_11_8,	VI4_CLKENB),
 874	PINMUX_IPSR_GPSR(IP4_11_8,	DU_DG3),
 875
 876	PINMUX_IPSR_GPSR(IP4_15_12,	CS0_N),
 877	PINMUX_IPSR_GPSR(IP4_15_12,	VI5_CLKENB),
 878
 879	PINMUX_IPSR_GPSR(IP4_19_16,	CS1_N),
 880	PINMUX_IPSR_GPSR(IP4_19_16,	VI5_CLK),
 881	PINMUX_IPSR_MSEL(IP4_19_16,	EX_WAIT0_B,		SEL_LBSC_1),
 882
 883	PINMUX_IPSR_GPSR(IP4_23_20,	BS_N),
 884	PINMUX_IPSR_GPSR(IP4_23_20,	QSTVA_QVS),
 885	PINMUX_IPSR_MSEL(IP4_23_20,	MSIOF3_SCK_D,		SEL_MSIOF3_3),
 886	PINMUX_IPSR_GPSR(IP4_23_20,	SCK3),
 887	PINMUX_IPSR_GPSR(IP4_23_20,	HSCK3),
 888	PINMUX_IPSR_GPSR(IP4_23_20,	CAN1_TX),
 889	PINMUX_IPSR_GPSR(IP4_23_20,	CANFD1_TX),
 890	PINMUX_IPSR_MSEL(IP4_23_20,	IETX_A,			SEL_IEBUS_0),
 891
 892	PINMUX_IPSR_GPSR(IP4_27_24,	RD_N),
 893	PINMUX_IPSR_MSEL(IP4_27_24,	MSIOF3_SYNC_D,		SEL_MSIOF3_3),
 894	PINMUX_IPSR_MSEL(IP4_27_24,	RX3_A,			SEL_SCIF3_0),
 895	PINMUX_IPSR_MSEL(IP4_27_24,	HRX3_A,			SEL_HSCIF3_0),
 896	PINMUX_IPSR_MSEL(IP4_27_24,	CAN0_TX_A,		SEL_RCAN0_0),
 897	PINMUX_IPSR_MSEL(IP4_27_24,	CANFD0_TX_A,		SEL_CANFD0_0),
 898
 899	PINMUX_IPSR_GPSR(IP4_31_28,	RD_WR_N),
 900	PINMUX_IPSR_MSEL(IP4_31_28,	MSIOF3_RXD_D,		SEL_MSIOF3_3),
 901	PINMUX_IPSR_MSEL(IP4_31_28,	TX3_A,			SEL_SCIF3_0),
 902	PINMUX_IPSR_MSEL(IP4_31_28,	HTX3_A,			SEL_HSCIF3_0),
 903	PINMUX_IPSR_MSEL(IP4_31_28,	CAN0_RX_A,		SEL_RCAN0_0),
 904	PINMUX_IPSR_MSEL(IP4_31_28,	CANFD0_RX_A,		SEL_CANFD0_0),
 905
 906	/* IPSR5 */
 907	PINMUX_IPSR_GPSR(IP5_3_0,	WE0_N),
 908	PINMUX_IPSR_MSEL(IP5_3_0,	MSIOF3_TXD_D,		SEL_MSIOF3_3),
 909	PINMUX_IPSR_GPSR(IP5_3_0,	CTS3_N),
 910	PINMUX_IPSR_GPSR(IP5_3_0,	HCTS3_N),
 911	PINMUX_IPSR_MSEL(IP5_3_0,	SCL6_B,			SEL_I2C6_1),
 912	PINMUX_IPSR_GPSR(IP5_3_0,	CAN_CLK),
 913	PINMUX_IPSR_MSEL(IP5_3_0,	IECLK_A,		SEL_IEBUS_0),
 914
 915	PINMUX_IPSR_GPSR(IP5_7_4,	WE1_N),
 916	PINMUX_IPSR_MSEL(IP5_7_4,	MSIOF3_SS1_D,		SEL_MSIOF3_3),
 917	PINMUX_IPSR_GPSR(IP5_7_4,	RTS3_N),
 918	PINMUX_IPSR_GPSR(IP5_7_4,	HRTS3_N),
 919	PINMUX_IPSR_MSEL(IP5_7_4,	SDA6_B,			SEL_I2C6_1),
 920	PINMUX_IPSR_GPSR(IP5_7_4,	CAN1_RX),
 921	PINMUX_IPSR_GPSR(IP5_7_4,	CANFD1_RX),
 922	PINMUX_IPSR_MSEL(IP5_7_4,	IERX_A,			SEL_IEBUS_0),
 923
 924	PINMUX_IPSR_MSEL(IP5_11_8,	EX_WAIT0_A,		SEL_LBSC_0),
 925	PINMUX_IPSR_GPSR(IP5_11_8,	QCLK),
 926	PINMUX_IPSR_GPSR(IP5_11_8,	VI4_CLK),
 927	PINMUX_IPSR_GPSR(IP5_11_8,	DU_DOTCLKOUT0),
 928
 929	PINMUX_IPSR_GPSR(IP5_15_12,	D0),
 930	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF2_SS1_B,		SEL_MSIOF2_1),
 931	PINMUX_IPSR_MSEL(IP5_15_12,	MSIOF3_SCK_A,		SEL_MSIOF3_0),
 932	PINMUX_IPSR_GPSR(IP5_15_12,	VI4_DATA16),
 933	PINMUX_IPSR_GPSR(IP5_15_12,	VI5_DATA0),
 934
 935	PINMUX_IPSR_GPSR(IP5_19_16,	D1),
 936	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF2_SS2_B,		SEL_MSIOF2_1),
 937	PINMUX_IPSR_MSEL(IP5_19_16,	MSIOF3_SYNC_A,		SEL_MSIOF3_0),
 938	PINMUX_IPSR_GPSR(IP5_19_16,	VI4_DATA17),
 939	PINMUX_IPSR_GPSR(IP5_19_16,	VI5_DATA1),
 940
 941	PINMUX_IPSR_GPSR(IP5_23_20,	D2),
 942	PINMUX_IPSR_MSEL(IP5_23_20,	MSIOF3_RXD_A,		SEL_MSIOF3_0),
 943	PINMUX_IPSR_GPSR(IP5_23_20,	VI4_DATA18),
 944	PINMUX_IPSR_GPSR(IP5_23_20,	VI5_DATA2),
 945
 946	PINMUX_IPSR_GPSR(IP5_27_24,	D3),
 947	PINMUX_IPSR_MSEL(IP5_27_24,	MSIOF3_TXD_A,		SEL_MSIOF3_0),
 948	PINMUX_IPSR_GPSR(IP5_27_24,	VI4_DATA19),
 949	PINMUX_IPSR_GPSR(IP5_27_24,	VI5_DATA3),
 950
 951	PINMUX_IPSR_GPSR(IP5_31_28,	D4),
 952	PINMUX_IPSR_MSEL(IP5_31_28,	MSIOF2_SCK_B,		SEL_MSIOF2_1),
 953	PINMUX_IPSR_GPSR(IP5_31_28,	VI4_DATA20),
 954	PINMUX_IPSR_GPSR(IP5_31_28,	VI5_DATA4),
 955
 956	/* IPSR6 */
 957	PINMUX_IPSR_GPSR(IP6_3_0,	D5),
 958	PINMUX_IPSR_MSEL(IP6_3_0,	MSIOF2_SYNC_B,		SEL_MSIOF2_1),
 959	PINMUX_IPSR_GPSR(IP6_3_0,	VI4_DATA21),
 960	PINMUX_IPSR_GPSR(IP6_3_0,	VI5_DATA5),
 961
 962	PINMUX_IPSR_GPSR(IP6_7_4,	D6),
 963	PINMUX_IPSR_MSEL(IP6_7_4,	MSIOF2_RXD_B,		SEL_MSIOF2_1),
 964	PINMUX_IPSR_GPSR(IP6_7_4,	VI4_DATA22),
 965	PINMUX_IPSR_GPSR(IP6_7_4,	VI5_DATA6),
 966
 967	PINMUX_IPSR_GPSR(IP6_11_8,	D7),
 968	PINMUX_IPSR_MSEL(IP6_11_8,	MSIOF2_TXD_B,		SEL_MSIOF2_1),
 969	PINMUX_IPSR_GPSR(IP6_11_8,	VI4_DATA23),
 970	PINMUX_IPSR_GPSR(IP6_11_8,	VI5_DATA7),
 971
 972	PINMUX_IPSR_GPSR(IP6_15_12,	D8),
 973	PINMUX_IPSR_GPSR(IP6_15_12,	LCDOUT0),
 974	PINMUX_IPSR_MSEL(IP6_15_12,	MSIOF2_SCK_D,		SEL_MSIOF2_3),
 975	PINMUX_IPSR_MSEL(IP6_15_12,	SCK4_C,			SEL_SCIF4_2),
 976	PINMUX_IPSR_MSEL(IP6_15_12,	VI4_DATA0_A,		SEL_VIN4_0),
 977	PINMUX_IPSR_GPSR(IP6_15_12,	DU_DR0),
 978
 979	PINMUX_IPSR_GPSR(IP6_19_16,	D9),
 980	PINMUX_IPSR_GPSR(IP6_19_16,	LCDOUT1),
 981	PINMUX_IPSR_MSEL(IP6_19_16,	MSIOF2_SYNC_D,		SEL_MSIOF2_3),
 982	PINMUX_IPSR_MSEL(IP6_19_16,	VI4_DATA1_A,		SEL_VIN4_0),
 983	PINMUX_IPSR_GPSR(IP6_19_16,	DU_DR1),
 984
 985	PINMUX_IPSR_GPSR(IP6_23_20,	D10),
 986	PINMUX_IPSR_GPSR(IP6_23_20,	LCDOUT2),
 987	PINMUX_IPSR_MSEL(IP6_23_20,	MSIOF2_RXD_D,		SEL_MSIOF2_3),
 988	PINMUX_IPSR_MSEL(IP6_23_20,	HRX3_B,			SEL_HSCIF3_1),
 989	PINMUX_IPSR_MSEL(IP6_23_20,	VI4_DATA2_A,		SEL_VIN4_0),
 990	PINMUX_IPSR_MSEL(IP6_23_20,	CTS4_N_C,		SEL_SCIF4_2),
 991	PINMUX_IPSR_GPSR(IP6_23_20,	DU_DR2),
 992
 993	PINMUX_IPSR_GPSR(IP6_27_24,	D11),
 994	PINMUX_IPSR_GPSR(IP6_27_24,	LCDOUT3),
 995	PINMUX_IPSR_MSEL(IP6_27_24,	MSIOF2_TXD_D,		SEL_MSIOF2_3),
 996	PINMUX_IPSR_MSEL(IP6_27_24,	HTX3_B,			SEL_HSCIF3_1),
 997	PINMUX_IPSR_MSEL(IP6_27_24,	VI4_DATA3_A,		SEL_VIN4_0),
 998	PINMUX_IPSR_MSEL(IP6_27_24,	RTS4_N_C,		SEL_SCIF4_2),
 999	PINMUX_IPSR_GPSR(IP6_27_24,	DU_DR3),
1000
1001	PINMUX_IPSR_GPSR(IP6_31_28,	D12),
1002	PINMUX_IPSR_GPSR(IP6_31_28,	LCDOUT4),
1003	PINMUX_IPSR_MSEL(IP6_31_28,	MSIOF2_SS1_D,		SEL_MSIOF2_3),
1004	PINMUX_IPSR_MSEL(IP6_31_28,	RX4_C,			SEL_SCIF4_2),
1005	PINMUX_IPSR_MSEL(IP6_31_28,	VI4_DATA4_A,		SEL_VIN4_0),
1006	PINMUX_IPSR_GPSR(IP6_31_28,	DU_DR4),
1007
1008	/* IPSR7 */
1009	PINMUX_IPSR_GPSR(IP7_3_0,	D13),
1010	PINMUX_IPSR_GPSR(IP7_3_0,	LCDOUT5),
1011	PINMUX_IPSR_MSEL(IP7_3_0,	MSIOF2_SS2_D,		SEL_MSIOF2_3),
1012	PINMUX_IPSR_MSEL(IP7_3_0,	TX4_C,			SEL_SCIF4_2),
1013	PINMUX_IPSR_MSEL(IP7_3_0,	VI4_DATA5_A,		SEL_VIN4_0),
1014	PINMUX_IPSR_GPSR(IP7_3_0,	DU_DR5),
1015
1016	PINMUX_IPSR_GPSR(IP7_7_4,	D14),
1017	PINMUX_IPSR_GPSR(IP7_7_4,	LCDOUT6),
1018	PINMUX_IPSR_MSEL(IP7_7_4,	MSIOF3_SS1_A,		SEL_MSIOF3_0),
1019	PINMUX_IPSR_MSEL(IP7_7_4,	HRX3_C,			SEL_HSCIF3_2),
1020	PINMUX_IPSR_MSEL(IP7_7_4,	VI4_DATA6_A,		SEL_VIN4_0),
1021	PINMUX_IPSR_GPSR(IP7_7_4,	DU_DR6),
1022	PINMUX_IPSR_MSEL(IP7_7_4,	SCL6_C,			SEL_I2C6_2),
1023
1024	PINMUX_IPSR_GPSR(IP7_11_8,	D15),
1025	PINMUX_IPSR_GPSR(IP7_11_8,	LCDOUT7),
1026	PINMUX_IPSR_MSEL(IP7_11_8,	MSIOF3_SS2_A,		SEL_MSIOF3_0),
1027	PINMUX_IPSR_MSEL(IP7_11_8,	HTX3_C,			SEL_HSCIF3_2),
1028	PINMUX_IPSR_MSEL(IP7_11_8,	VI4_DATA7_A,		SEL_VIN4_0),
1029	PINMUX_IPSR_GPSR(IP7_11_8,	DU_DR7),
1030	PINMUX_IPSR_MSEL(IP7_11_8,	SDA6_C,			SEL_I2C6_2),
1031
1032	PINMUX_IPSR_GPSR(IP7_19_16,	SD0_CLK),
1033	PINMUX_IPSR_MSEL(IP7_19_16,	MSIOF1_SCK_E,		SEL_MSIOF1_4),
1034	PINMUX_IPSR_MSEL(IP7_19_16,	STP_OPWM_0_B,		SEL_SSP1_0_1),
1035
1036	PINMUX_IPSR_GPSR(IP7_23_20,	SD0_CMD),
1037	PINMUX_IPSR_MSEL(IP7_23_20,	MSIOF1_SYNC_E,		SEL_MSIOF1_4),
1038	PINMUX_IPSR_MSEL(IP7_23_20,	STP_IVCXO27_0_B,	SEL_SSP1_0_1),
1039
1040	PINMUX_IPSR_GPSR(IP7_27_24,	SD0_DAT0),
1041	PINMUX_IPSR_MSEL(IP7_27_24,	MSIOF1_RXD_E,		SEL_MSIOF1_4),
1042	PINMUX_IPSR_MSEL(IP7_27_24,	TS_SCK0_B,		SEL_TSIF0_1),
1043	PINMUX_IPSR_MSEL(IP7_27_24,	STP_ISCLK_0_B,		SEL_SSP1_0_1),
1044
1045	PINMUX_IPSR_GPSR(IP7_31_28,	SD0_DAT1),
1046	PINMUX_IPSR_MSEL(IP7_31_28,	MSIOF1_TXD_E,		SEL_MSIOF1_4),
1047	PINMUX_IPSR_MSEL(IP7_31_28,	TS_SPSYNC0_B,		SEL_TSIF0_1),
1048	PINMUX_IPSR_MSEL(IP7_31_28,	STP_ISSYNC_0_B,		SEL_SSP1_0_1),
1049
1050	/* IPSR8 */
1051	PINMUX_IPSR_GPSR(IP8_3_0,	SD0_DAT2),
1052	PINMUX_IPSR_MSEL(IP8_3_0,	MSIOF1_SS1_E,		SEL_MSIOF1_4),
1053	PINMUX_IPSR_MSEL(IP8_3_0,	TS_SDAT0_B,		SEL_TSIF0_1),
1054	PINMUX_IPSR_MSEL(IP8_3_0,	STP_ISD_0_B,		SEL_SSP1_0_1),
1055
1056	PINMUX_IPSR_GPSR(IP8_7_4,	SD0_DAT3),
1057	PINMUX_IPSR_MSEL(IP8_7_4,	MSIOF1_SS2_E,		SEL_MSIOF1_4),
1058	PINMUX_IPSR_MSEL(IP8_7_4,	TS_SDEN0_B,		SEL_TSIF0_1),
1059	PINMUX_IPSR_MSEL(IP8_7_4,	STP_ISEN_0_B,		SEL_SSP1_0_1),
1060
1061	PINMUX_IPSR_GPSR(IP8_11_8,	SD1_CLK),
1062	PINMUX_IPSR_MSEL(IP8_11_8,	MSIOF1_SCK_G,		SEL_MSIOF1_6),
1063	PINMUX_IPSR_MSEL(IP8_11_8,	SIM0_CLK_A,		SEL_SIMCARD_0),
1064
1065	PINMUX_IPSR_GPSR(IP8_15_12,	SD1_CMD),
1066	PINMUX_IPSR_MSEL(IP8_15_12,	MSIOF1_SYNC_G,		SEL_MSIOF1_6),
1067	PINMUX_IPSR_MSEL(IP8_15_12,	NFCE_N_B,		SEL_NDF_1),
1068	PINMUX_IPSR_MSEL(IP8_15_12,	SIM0_D_A,		SEL_SIMCARD_0),
1069	PINMUX_IPSR_MSEL(IP8_15_12,	STP_IVCXO27_1_B,	SEL_SSP1_1_1),
1070
1071	PINMUX_IPSR_GPSR(IP8_19_16,	SD1_DAT0),
1072	PINMUX_IPSR_GPSR(IP8_19_16,	SD2_DAT4),
1073	PINMUX_IPSR_MSEL(IP8_19_16,	MSIOF1_RXD_G,		SEL_MSIOF1_6),
1074	PINMUX_IPSR_MSEL(IP8_19_16,	NFWP_N_B,		SEL_NDF_1),
1075	PINMUX_IPSR_MSEL(IP8_19_16,	TS_SCK1_B,		SEL_TSIF1_1),
1076	PINMUX_IPSR_MSEL(IP8_19_16,	STP_ISCLK_1_B,		SEL_SSP1_1_1),
1077
1078	PINMUX_IPSR_GPSR(IP8_23_20,	SD1_DAT1),
1079	PINMUX_IPSR_GPSR(IP8_23_20,	SD2_DAT5),
1080	PINMUX_IPSR_MSEL(IP8_23_20,	MSIOF1_TXD_G,		SEL_MSIOF1_6),
1081	PINMUX_IPSR_MSEL(IP8_23_20,	NFDATA14_B,		SEL_NDF_1),
1082	PINMUX_IPSR_MSEL(IP8_23_20,	TS_SPSYNC1_B,		SEL_TSIF1_1),
1083	PINMUX_IPSR_MSEL(IP8_23_20,	STP_ISSYNC_1_B,		SEL_SSP1_1_1),
1084
1085	PINMUX_IPSR_GPSR(IP8_27_24,	SD1_DAT2),
1086	PINMUX_IPSR_GPSR(IP8_27_24,	SD2_DAT6),
1087	PINMUX_IPSR_MSEL(IP8_27_24,	MSIOF1_SS1_G,		SEL_MSIOF1_6),
1088	PINMUX_IPSR_MSEL(IP8_27_24,	NFDATA15_B,		SEL_NDF_1),
1089	PINMUX_IPSR_MSEL(IP8_27_24,	TS_SDAT1_B,		SEL_TSIF1_1),
1090	PINMUX_IPSR_MSEL(IP8_27_24,	STP_ISD_1_B,		SEL_SSP1_1_1),
1091
1092	PINMUX_IPSR_GPSR(IP8_31_28,	SD1_DAT3),
1093	PINMUX_IPSR_GPSR(IP8_31_28,	SD2_DAT7),
1094	PINMUX_IPSR_MSEL(IP8_31_28,	MSIOF1_SS2_G,		SEL_MSIOF1_6),
1095	PINMUX_IPSR_MSEL(IP8_31_28,	NFRB_N_B,		SEL_NDF_1),
1096	PINMUX_IPSR_MSEL(IP8_31_28,	TS_SDEN1_B,		SEL_TSIF1_1),
1097	PINMUX_IPSR_MSEL(IP8_31_28,	STP_ISEN_1_B,		SEL_SSP1_1_1),
1098
1099	/* IPSR9 */
1100	PINMUX_IPSR_GPSR(IP9_3_0,	SD2_CLK),
1101	PINMUX_IPSR_GPSR(IP9_3_0,	NFDATA8),
1102
1103	PINMUX_IPSR_GPSR(IP9_7_4,	SD2_CMD),
1104	PINMUX_IPSR_GPSR(IP9_7_4,	NFDATA9),
1105
1106	PINMUX_IPSR_GPSR(IP9_11_8,	SD2_DAT0),
1107	PINMUX_IPSR_GPSR(IP9_11_8,	NFDATA10),
1108
1109	PINMUX_IPSR_GPSR(IP9_15_12,	SD2_DAT1),
1110	PINMUX_IPSR_GPSR(IP9_15_12,	NFDATA11),
1111
1112	PINMUX_IPSR_GPSR(IP9_19_16,	SD2_DAT2),
1113	PINMUX_IPSR_GPSR(IP9_19_16,	NFDATA12),
1114
1115	PINMUX_IPSR_GPSR(IP9_23_20,	SD2_DAT3),
1116	PINMUX_IPSR_GPSR(IP9_23_20,	NFDATA13),
1117
1118	PINMUX_IPSR_GPSR(IP9_27_24,	SD2_DS),
1119	PINMUX_IPSR_GPSR(IP9_27_24,	NFALE),
1120
1121	PINMUX_IPSR_GPSR(IP9_31_28,	SD3_CLK),
1122	PINMUX_IPSR_GPSR(IP9_31_28,	NFWE_N),
1123
1124	/* IPSR10 */
1125	PINMUX_IPSR_GPSR(IP10_3_0,	SD3_CMD),
1126	PINMUX_IPSR_GPSR(IP10_3_0,	NFRE_N),
1127
1128	PINMUX_IPSR_GPSR(IP10_7_4,	SD3_DAT0),
1129	PINMUX_IPSR_GPSR(IP10_7_4,	NFDATA0),
1130
1131	PINMUX_IPSR_GPSR(IP10_11_8,	SD3_DAT1),
1132	PINMUX_IPSR_GPSR(IP10_11_8,	NFDATA1),
1133
1134	PINMUX_IPSR_GPSR(IP10_15_12,	SD3_DAT2),
1135	PINMUX_IPSR_GPSR(IP10_15_12,	NFDATA2),
1136
1137	PINMUX_IPSR_GPSR(IP10_19_16,	SD3_DAT3),
1138	PINMUX_IPSR_GPSR(IP10_19_16,	NFDATA3),
1139
1140	PINMUX_IPSR_GPSR(IP10_23_20,	SD3_DAT4),
1141	PINMUX_IPSR_MSEL(IP10_23_20,	SD2_CD_A,		SEL_SDHI2_0),
1142	PINMUX_IPSR_GPSR(IP10_23_20,	NFDATA4),
1143
1144	PINMUX_IPSR_GPSR(IP10_27_24,	SD3_DAT5),
1145	PINMUX_IPSR_MSEL(IP10_27_24,	SD2_WP_A,		SEL_SDHI2_0),
1146	PINMUX_IPSR_GPSR(IP10_27_24,	NFDATA5),
1147
1148	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_DAT6),
1149	PINMUX_IPSR_GPSR(IP10_31_28,	SD3_CD),
1150	PINMUX_IPSR_GPSR(IP10_31_28,	NFDATA6),
1151
1152	/* IPSR11 */
1153	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_DAT7),
1154	PINMUX_IPSR_GPSR(IP11_3_0,	SD3_WP),
1155	PINMUX_IPSR_GPSR(IP11_3_0,	NFDATA7),
1156
1157	PINMUX_IPSR_GPSR(IP11_7_4,	SD3_DS),
1158	PINMUX_IPSR_GPSR(IP11_7_4,	NFCLE),
1159
1160	PINMUX_IPSR_GPSR(IP11_11_8,	SD0_CD),
1161	PINMUX_IPSR_MSEL(IP11_11_8,	NFDATA14_A,		SEL_NDF_0),
1162	PINMUX_IPSR_MSEL(IP11_11_8,	SCL2_B,			SEL_I2C2_1),
1163	PINMUX_IPSR_MSEL(IP11_11_8,	SIM0_RST_A,		SEL_SIMCARD_0),
1164
1165	PINMUX_IPSR_GPSR(IP11_15_12,	SD0_WP),
1166	PINMUX_IPSR_MSEL(IP11_15_12,	NFDATA15_A,		SEL_NDF_0),
1167	PINMUX_IPSR_MSEL(IP11_15_12,	SDA2_B,			SEL_I2C2_1),
1168
1169	PINMUX_IPSR_MSEL(IP11_19_16,	SD1_CD,			I2C_SEL_0_0),
1170	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1171	PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1172	PINMUX_IPSR_PHYS(IP11_19_16,	SCL0,			I2C_SEL_0_1),
1173
1174	PINMUX_IPSR_MSEL(IP11_23_20,	SD1_WP,			I2C_SEL_0_0),
1175	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,		I2C_SEL_0_0,	SEL_NDF_0),
1176	PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,		I2C_SEL_0_0,	SEL_SIMCARD_1),
1177	PINMUX_IPSR_PHYS(IP11_23_20,	SDA0,			I2C_SEL_0_1),
1178
1179	PINMUX_IPSR_GPSR(IP11_27_24,	SCK0),
1180	PINMUX_IPSR_MSEL(IP11_27_24,	HSCK1_B,		SEL_HSCIF1_1),
1181	PINMUX_IPSR_MSEL(IP11_27_24,	MSIOF1_SS2_B,		SEL_MSIOF1_1),
1182	PINMUX_IPSR_MSEL(IP11_27_24,	AUDIO_CLKC_B,		SEL_ADGC_1),
1183	PINMUX_IPSR_MSEL(IP11_27_24,	SDA2_A,			SEL_I2C2_0),
1184	PINMUX_IPSR_MSEL(IP11_27_24,	SIM0_RST_B,		SEL_SIMCARD_1),
1185	PINMUX_IPSR_MSEL(IP11_27_24,	STP_OPWM_0_C,		SEL_SSP1_0_2),
1186	PINMUX_IPSR_MSEL(IP11_27_24,	RIF0_CLK_B,		SEL_DRIF0_1),
1187	PINMUX_IPSR_GPSR(IP11_27_24,	ADICHS2),
1188	PINMUX_IPSR_MSEL(IP11_27_24,	SCK5_B,			SEL_SCIF5_1),
1189
1190	PINMUX_IPSR_GPSR(IP11_31_28,	RX0),
1191	PINMUX_IPSR_MSEL(IP11_31_28,	HRX1_B,			SEL_HSCIF1_1),
1192	PINMUX_IPSR_MSEL(IP11_31_28,	TS_SCK0_C,		SEL_TSIF0_2),
1193	PINMUX_IPSR_MSEL(IP11_31_28,	STP_ISCLK_0_C,		SEL_SSP1_0_2),
1194	PINMUX_IPSR_MSEL(IP11_31_28,	RIF0_D0_B,		SEL_DRIF0_1),
1195
1196	/* IPSR12 */
1197	PINMUX_IPSR_GPSR(IP12_3_0,	TX0),
1198	PINMUX_IPSR_MSEL(IP12_3_0,	HTX1_B,			SEL_HSCIF1_1),
1199	PINMUX_IPSR_MSEL(IP12_3_0,	TS_SPSYNC0_C,		SEL_TSIF0_2),
1200	PINMUX_IPSR_MSEL(IP12_3_0,	STP_ISSYNC_0_C,		SEL_SSP1_0_2),
1201	PINMUX_IPSR_MSEL(IP12_3_0,	RIF0_D1_B,		SEL_DRIF0_1),
1202
1203	PINMUX_IPSR_GPSR(IP12_7_4,	CTS0_N),
1204	PINMUX_IPSR_MSEL(IP12_7_4,	HCTS1_N_B,		SEL_HSCIF1_1),
1205	PINMUX_IPSR_MSEL(IP12_7_4,	MSIOF1_SYNC_B,		SEL_MSIOF1_1),
1206	PINMUX_IPSR_MSEL(IP12_7_4,	TS_SPSYNC1_C,		SEL_TSIF1_2),
1207	PINMUX_IPSR_MSEL(IP12_7_4,	STP_ISSYNC_1_C,		SEL_SSP1_1_2),
1208	PINMUX_IPSR_MSEL(IP12_7_4,	RIF1_SYNC_B,		SEL_DRIF1_1),
1209	PINMUX_IPSR_GPSR(IP12_7_4,	AUDIO_CLKOUT_C),
1210	PINMUX_IPSR_GPSR(IP12_7_4,	ADICS_SAMP),
1211
1212	PINMUX_IPSR_GPSR(IP12_11_8,	RTS0_N),
1213	PINMUX_IPSR_MSEL(IP12_11_8,	HRTS1_N_B,		SEL_HSCIF1_1),
1214	PINMUX_IPSR_MSEL(IP12_11_8,	MSIOF1_SS1_B,		SEL_MSIOF1_1),
1215	PINMUX_IPSR_MSEL(IP12_11_8,	AUDIO_CLKA_B,		SEL_ADGA_1),
1216	PINMUX_IPSR_MSEL(IP12_11_8,	SCL2_A,			SEL_I2C2_0),
1217	PINMUX_IPSR_MSEL(IP12_11_8,	STP_IVCXO27_1_C,	SEL_SSP1_1_2),
1218	PINMUX_IPSR_MSEL(IP12_11_8,	RIF0_SYNC_B,		SEL_DRIF0_1),
1219	PINMUX_IPSR_GPSR(IP12_11_8,	ADICHS1),
1220
1221	PINMUX_IPSR_MSEL(IP12_15_12,	RX1_A,			SEL_SCIF1_0),
1222	PINMUX_IPSR_MSEL(IP12_15_12,	HRX1_A,			SEL_HSCIF1_0),
1223	PINMUX_IPSR_MSEL(IP12_15_12,	TS_SDAT0_C,		SEL_TSIF0_2),
1224	PINMUX_IPSR_MSEL(IP12_15_12,	STP_ISD_0_C,		SEL_SSP1_0_2),
1225	PINMUX_IPSR_MSEL(IP12_15_12,	RIF1_CLK_C,		SEL_DRIF1_2),
1226
1227	PINMUX_IPSR_MSEL(IP12_19_16,	TX1_A,			SEL_SCIF1_0),
1228	PINMUX_IPSR_MSEL(IP12_19_16,	HTX1_A,			SEL_HSCIF1_0),
1229	PINMUX_IPSR_MSEL(IP12_19_16,	TS_SDEN0_C,		SEL_TSIF0_2),
1230	PINMUX_IPSR_MSEL(IP12_19_16,	STP_ISEN_0_C,		SEL_SSP1_0_2),
1231	PINMUX_IPSR_MSEL(IP12_19_16,	RIF1_D0_C,		SEL_DRIF1_2),
1232
1233	PINMUX_IPSR_GPSR(IP12_23_20,	CTS1_N),
1234	PINMUX_IPSR_MSEL(IP12_23_20,	HCTS1_N_A,		SEL_HSCIF1_0),
1235	PINMUX_IPSR_MSEL(IP12_23_20,	MSIOF1_RXD_B,		SEL_MSIOF1_1),
1236	PINMUX_IPSR_MSEL(IP12_23_20,	TS_SDEN1_C,		SEL_TSIF1_2),
1237	PINMUX_IPSR_MSEL(IP12_23_20,	STP_ISEN_1_C,		SEL_SSP1_1_2),
1238	PINMUX_IPSR_MSEL(IP12_23_20,	RIF1_D0_B,		SEL_DRIF1_1),
1239	PINMUX_IPSR_GPSR(IP12_23_20,	ADIDATA),
1240
1241	PINMUX_IPSR_GPSR(IP12_27_24,	RTS1_N),
1242	PINMUX_IPSR_MSEL(IP12_27_24,	HRTS1_N_A,		SEL_HSCIF1_0),
1243	PINMUX_IPSR_MSEL(IP12_27_24,	MSIOF1_TXD_B,		SEL_MSIOF1_1),
1244	PINMUX_IPSR_MSEL(IP12_27_24,	TS_SDAT1_C,		SEL_TSIF1_2),
1245	PINMUX_IPSR_MSEL(IP12_27_24,	STP_ISD_1_C,		SEL_SSP1_1_2),
1246	PINMUX_IPSR_MSEL(IP12_27_24,	RIF1_D1_B,		SEL_DRIF1_1),
1247	PINMUX_IPSR_GPSR(IP12_27_24,	ADICHS0),
1248
1249	PINMUX_IPSR_GPSR(IP12_31_28,	SCK2),
1250	PINMUX_IPSR_MSEL(IP12_31_28,	SCIF_CLK_B,		SEL_SCIF_1),
1251	PINMUX_IPSR_MSEL(IP12_31_28,	MSIOF1_SCK_B,		SEL_MSIOF1_1),
1252	PINMUX_IPSR_MSEL(IP12_31_28,	TS_SCK1_C,		SEL_TSIF1_2),
1253	PINMUX_IPSR_MSEL(IP12_31_28,	STP_ISCLK_1_C,		SEL_SSP1_1_2),
1254	PINMUX_IPSR_MSEL(IP12_31_28,	RIF1_CLK_B,		SEL_DRIF1_1),
1255	PINMUX_IPSR_GPSR(IP12_31_28,	ADICLK),
1256
1257	/* IPSR13 */
1258	PINMUX_IPSR_MSEL(IP13_3_0,	TX2_A,			SEL_SCIF2_0),
1259	PINMUX_IPSR_MSEL(IP13_3_0,	SD2_CD_B,		SEL_SDHI2_1),
1260	PINMUX_IPSR_MSEL(IP13_3_0,	SCL1_A,			SEL_I2C1_0),
1261	PINMUX_IPSR_MSEL(IP13_3_0,	FMCLK_A,		SEL_FM_0),
1262	PINMUX_IPSR_MSEL(IP13_3_0,	RIF1_D1_C,		SEL_DRIF1_2),
1263	PINMUX_IPSR_GPSR(IP13_3_0,	FSO_CFE_0_N),
1264
1265	PINMUX_IPSR_MSEL(IP13_7_4,	RX2_A,			SEL_SCIF2_0),
1266	PINMUX_IPSR_MSEL(IP13_7_4,	SD2_WP_B,		SEL_SDHI2_1),
1267	PINMUX_IPSR_MSEL(IP13_7_4,	SDA1_A,			SEL_I2C1_0),
1268	PINMUX_IPSR_MSEL(IP13_7_4,	FMIN_A,			SEL_FM_0),
1269	PINMUX_IPSR_MSEL(IP13_7_4,	RIF1_SYNC_C,		SEL_DRIF1_2),
1270	PINMUX_IPSR_GPSR(IP13_7_4,	FSO_CFE_1_N),
1271
1272	PINMUX_IPSR_GPSR(IP13_11_8,	HSCK0),
1273	PINMUX_IPSR_MSEL(IP13_11_8,	MSIOF1_SCK_D,		SEL_MSIOF1_3),
1274	PINMUX_IPSR_MSEL(IP13_11_8,	AUDIO_CLKB_A,		SEL_ADGB_0),
1275	PINMUX_IPSR_MSEL(IP13_11_8,	SSI_SDATA1_B,		SEL_SSI1_1),
1276	PINMUX_IPSR_MSEL(IP13_11_8,	TS_SCK0_D,		SEL_TSIF0_3),
1277	PINMUX_IPSR_MSEL(IP13_11_8,	STP_ISCLK_0_D,		SEL_SSP1_0_3),
1278	PINMUX_IPSR_MSEL(IP13_11_8,	RIF0_CLK_C,		SEL_DRIF0_2),
1279	PINMUX_IPSR_MSEL(IP13_11_8,	RX5_B,			SEL_SCIF5_1),
1280
1281	PINMUX_IPSR_GPSR(IP13_15_12,	HRX0),
1282	PINMUX_IPSR_MSEL(IP13_15_12,	MSIOF1_RXD_D,		SEL_MSIOF1_3),
1283	PINMUX_IPSR_MSEL(IP13_15_12,	SSI_SDATA2_B,		SEL_SSI2_1),
1284	PINMUX_IPSR_MSEL(IP13_15_12,	TS_SDEN0_D,		SEL_TSIF0_3),
1285	PINMUX_IPSR_MSEL(IP13_15_12,	STP_ISEN_0_D,		SEL_SSP1_0_3),
1286	PINMUX_IPSR_MSEL(IP13_15_12,	RIF0_D0_C,		SEL_DRIF0_2),
1287
1288	PINMUX_IPSR_GPSR(IP13_19_16,	HTX0),
1289	PINMUX_IPSR_MSEL(IP13_19_16,	MSIOF1_TXD_D,		SEL_MSIOF1_3),
1290	PINMUX_IPSR_MSEL(IP13_19_16,	SSI_SDATA9_B,		SEL_SSI9_1),
1291	PINMUX_IPSR_MSEL(IP13_19_16,	TS_SDAT0_D,		SEL_TSIF0_3),
1292	PINMUX_IPSR_MSEL(IP13_19_16,	STP_ISD_0_D,		SEL_SSP1_0_3),
1293	PINMUX_IPSR_MSEL(IP13_19_16,	RIF0_D1_C,		SEL_DRIF0_2),
1294
1295	PINMUX_IPSR_GPSR(IP13_23_20,	HCTS0_N),
1296	PINMUX_IPSR_MSEL(IP13_23_20,	RX2_B,			SEL_SCIF2_1),
1297	PINMUX_IPSR_MSEL(IP13_23_20,	MSIOF1_SYNC_D,		SEL_MSIOF1_3),
1298	PINMUX_IPSR_MSEL(IP13_23_20,	SSI_SCK9_A,		SEL_SSI9_0),
1299	PINMUX_IPSR_MSEL(IP13_23_20,	TS_SPSYNC0_D,		SEL_TSIF0_3),
1300	PINMUX_IPSR_MSEL(IP13_23_20,	STP_ISSYNC_0_D,		SEL_SSP1_0_3),
1301	PINMUX_IPSR_MSEL(IP13_23_20,	RIF0_SYNC_C,		SEL_DRIF0_2),
1302	PINMUX_IPSR_GPSR(IP13_23_20,	AUDIO_CLKOUT1_A),
1303
1304	PINMUX_IPSR_GPSR(IP13_27_24,	HRTS0_N),
1305	PINMUX_IPSR_MSEL(IP13_27_24,	TX2_B,			SEL_SCIF2_1),
1306	PINMUX_IPSR_MSEL(IP13_27_24,	MSIOF1_SS1_D,		SEL_MSIOF1_3),
1307	PINMUX_IPSR_MSEL(IP13_27_24,	SSI_WS9_A,		SEL_SSI9_0),
1308	PINMUX_IPSR_MSEL(IP13_27_24,	STP_IVCXO27_0_D,	SEL_SSP1_0_3),
1309	PINMUX_IPSR_MSEL(IP13_27_24,	BPFCLK_A,		SEL_FM_0),
1310	PINMUX_IPSR_GPSR(IP13_27_24,	AUDIO_CLKOUT2_A),
1311
1312	PINMUX_IPSR_GPSR(IP13_31_28,	MSIOF0_SYNC),
1313	PINMUX_IPSR_GPSR(IP13_31_28,	AUDIO_CLKOUT_A),
1314	PINMUX_IPSR_MSEL(IP13_31_28,	TX5_B,			SEL_SCIF5_1),
1315	PINMUX_IPSR_MSEL(IP13_31_28,	BPFCLK_D,		SEL_FM_3),
1316
1317	/* IPSR14 */
1318	PINMUX_IPSR_GPSR(IP14_3_0,	MSIOF0_SS1),
1319	PINMUX_IPSR_MSEL(IP14_3_0,	RX5_A,			SEL_SCIF5_0),
1320	PINMUX_IPSR_MSEL(IP14_3_0,	NFWP_N_A,		SEL_NDF_0),
1321	PINMUX_IPSR_MSEL(IP14_3_0,	AUDIO_CLKA_C,		SEL_ADGA_2),
1322	PINMUX_IPSR_MSEL(IP14_3_0,	SSI_SCK2_A,		SEL_SSI2_0),
1323	PINMUX_IPSR_MSEL(IP14_3_0,	STP_IVCXO27_0_C,	SEL_SSP1_0_2),
1324	PINMUX_IPSR_GPSR(IP14_3_0,	AUDIO_CLKOUT3_A),
1325	PINMUX_IPSR_MSEL(IP14_3_0,	TCLK1_B,		SEL_TIMER_TMU_1),
1326
1327	PINMUX_IPSR_GPSR(IP14_7_4,	MSIOF0_SS2),
1328	PINMUX_IPSR_MSEL(IP14_7_4,	TX5_A,			SEL_SCIF5_0),
1329	PINMUX_IPSR_MSEL(IP14_7_4,	MSIOF1_SS2_D,		SEL_MSIOF1_3),
1330	PINMUX_IPSR_MSEL(IP14_7_4,	AUDIO_CLKC_A,		SEL_ADGC_0),
1331	PINMUX_IPSR_MSEL(IP14_7_4,	SSI_WS2_A,		SEL_SSI2_0),
1332	PINMUX_IPSR_MSEL(IP14_7_4,	STP_OPWM_0_D,		SEL_SSP1_0_3),
1333	PINMUX_IPSR_GPSR(IP14_7_4,	AUDIO_CLKOUT_D),
1334	PINMUX_IPSR_MSEL(IP14_7_4,	SPEEDIN_B,		SEL_SPEED_PULSE_1),
1335
1336	PINMUX_IPSR_GPSR(IP14_11_8,	MLB_CLK),
1337	PINMUX_IPSR_MSEL(IP14_11_8,	MSIOF1_SCK_F,		SEL_MSIOF1_5),
1338	PINMUX_IPSR_MSEL(IP14_11_8,	SCL1_B,			SEL_I2C1_1),
1339
1340	PINMUX_IPSR_GPSR(IP14_15_12,	MLB_SIG),
1341	PINMUX_IPSR_MSEL(IP14_15_12,	RX1_B,			SEL_SCIF1_1),
1342	PINMUX_IPSR_MSEL(IP14_15_12,	MSIOF1_SYNC_F,		SEL_MSIOF1_5),
1343	PINMUX_IPSR_MSEL(IP14_15_12,	SDA1_B,			SEL_I2C1_1),
1344
1345	PINMUX_IPSR_GPSR(IP14_19_16,	MLB_DAT),
1346	PINMUX_IPSR_MSEL(IP14_19_16,	TX1_B,			SEL_SCIF1_1),
1347	PINMUX_IPSR_MSEL(IP14_19_16,	MSIOF1_RXD_F,		SEL_MSIOF1_5),
1348
1349	PINMUX_IPSR_GPSR(IP14_23_20,	SSI_SCK01239),
1350	PINMUX_IPSR_MSEL(IP14_23_20,	MSIOF1_TXD_F,		SEL_MSIOF1_5),
1351
1352	PINMUX_IPSR_GPSR(IP14_27_24,	SSI_WS01239),
1353	PINMUX_IPSR_MSEL(IP14_27_24,	MSIOF1_SS1_F,		SEL_MSIOF1_5),
1354
1355	PINMUX_IPSR_GPSR(IP14_31_28,	SSI_SDATA0),
1356	PINMUX_IPSR_MSEL(IP14_31_28,	MSIOF1_SS2_F,		SEL_MSIOF1_5),
1357
1358	/* IPSR15 */
1359	PINMUX_IPSR_MSEL(IP15_3_0,	SSI_SDATA1_A,		SEL_SSI1_0),
1360
1361	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SDATA2_A,		SEL_SSI2_0),
1362	PINMUX_IPSR_MSEL(IP15_7_4,	SSI_SCK1_B,		SEL_SSI1_1),
1363
1364	PINMUX_IPSR_GPSR(IP15_11_8,	SSI_SCK349),
1365	PINMUX_IPSR_MSEL(IP15_11_8,	MSIOF1_SS1_A,		SEL_MSIOF1_0),
1366	PINMUX_IPSR_MSEL(IP15_11_8,	STP_OPWM_0_A,		SEL_SSP1_0_0),
1367
1368	PINMUX_IPSR_GPSR(IP15_15_12,	SSI_WS349),
1369	PINMUX_IPSR_MSEL(IP15_15_12,	HCTS2_N_A,		SEL_HSCIF2_0),
1370	PINMUX_IPSR_MSEL(IP15_15_12,	MSIOF1_SS2_A,		SEL_MSIOF1_0),
1371	PINMUX_IPSR_MSEL(IP15_15_12,	STP_IVCXO27_0_A,	SEL_SSP1_0_0),
1372
1373	PINMUX_IPSR_GPSR(IP15_19_16,	SSI_SDATA3),
1374	PINMUX_IPSR_MSEL(IP15_19_16,	HRTS2_N_A,		SEL_HSCIF2_0),
1375	PINMUX_IPSR_MSEL(IP15_19_16,	MSIOF1_TXD_A,		SEL_MSIOF1_0),
1376	PINMUX_IPSR_MSEL(IP15_19_16,	TS_SCK0_A,		SEL_TSIF0_0),
1377	PINMUX_IPSR_MSEL(IP15_19_16,	STP_ISCLK_0_A,		SEL_SSP1_0_0),
1378	PINMUX_IPSR_MSEL(IP15_19_16,	RIF0_D1_A,		SEL_DRIF0_0),
1379	PINMUX_IPSR_MSEL(IP15_19_16,	RIF2_D0_A,		SEL_DRIF2_0),
1380
1381	PINMUX_IPSR_GPSR(IP15_23_20,	SSI_SCK4),
1382	PINMUX_IPSR_MSEL(IP15_23_20,	HRX2_A,			SEL_HSCIF2_0),
1383	PINMUX_IPSR_MSEL(IP15_23_20,	MSIOF1_SCK_A,		SEL_MSIOF1_0),
1384	PINMUX_IPSR_MSEL(IP15_23_20,	TS_SDAT0_A,		SEL_TSIF0_0),
1385	PINMUX_IPSR_MSEL(IP15_23_20,	STP_ISD_0_A,		SEL_SSP1_0_0),
1386	PINMUX_IPSR_MSEL(IP15_23_20,	RIF0_CLK_A,		SEL_DRIF0_0),
1387	PINMUX_IPSR_MSEL(IP15_23_20,	RIF2_CLK_A,		SEL_DRIF2_0),
1388
1389	PINMUX_IPSR_GPSR(IP15_27_24,	SSI_WS4),
1390	PINMUX_IPSR_MSEL(IP15_27_24,	HTX2_A,			SEL_HSCIF2_0),
1391	PINMUX_IPSR_MSEL(IP15_27_24,	MSIOF1_SYNC_A,		SEL_MSIOF1_0),
1392	PINMUX_IPSR_MSEL(IP15_27_24,	TS_SDEN0_A,		SEL_TSIF0_0),
1393	PINMUX_IPSR_MSEL(IP15_27_24,	STP_ISEN_0_A,		SEL_SSP1_0_0),
1394	PINMUX_IPSR_MSEL(IP15_27_24,	RIF0_SYNC_A,		SEL_DRIF0_0),
1395	PINMUX_IPSR_MSEL(IP15_27_24,	RIF2_SYNC_A,		SEL_DRIF2_0),
1396
1397	PINMUX_IPSR_GPSR(IP15_31_28,	SSI_SDATA4),
1398	PINMUX_IPSR_MSEL(IP15_31_28,	HSCK2_A,		SEL_HSCIF2_0),
1399	PINMUX_IPSR_MSEL(IP15_31_28,	MSIOF1_RXD_A,		SEL_MSIOF1_0),
1400	PINMUX_IPSR_MSEL(IP15_31_28,	TS_SPSYNC0_A,		SEL_TSIF0_0),
1401	PINMUX_IPSR_MSEL(IP15_31_28,	STP_ISSYNC_0_A,		SEL_SSP1_0_0),
1402	PINMUX_IPSR_MSEL(IP15_31_28,	RIF0_D0_A,		SEL_DRIF0_0),
1403	PINMUX_IPSR_MSEL(IP15_31_28,	RIF2_D1_A,		SEL_DRIF2_0),
1404
1405	/* IPSR16 */
1406	PINMUX_IPSR_GPSR(IP16_3_0,	SSI_SCK6),
1407	PINMUX_IPSR_MSEL(IP16_3_0,	SIM0_RST_D,		SEL_SIMCARD_3),
1408
1409	PINMUX_IPSR_GPSR(IP16_7_4,	SSI_WS6),
1410	PINMUX_IPSR_MSEL(IP16_7_4,	SIM0_D_D,		SEL_SIMCARD_3),
1411
1412	PINMUX_IPSR_GPSR(IP16_11_8,	SSI_SDATA6),
1413	PINMUX_IPSR_MSEL(IP16_11_8,	SIM0_CLK_D,		SEL_SIMCARD_3),
1414
1415	PINMUX_IPSR_GPSR(IP16_15_12,	SSI_SCK78),
1416	PINMUX_IPSR_MSEL(IP16_15_12,	HRX2_B,			SEL_HSCIF2_1),
1417	PINMUX_IPSR_MSEL(IP16_15_12,	MSIOF1_SCK_C,		SEL_MSIOF1_2),
1418	PINMUX_IPSR_MSEL(IP16_15_12,	TS_SCK1_A,		SEL_TSIF1_0),
1419	PINMUX_IPSR_MSEL(IP16_15_12,	STP_ISCLK_1_A,		SEL_SSP1_1_0),
1420	PINMUX_IPSR_MSEL(IP16_15_12,	RIF1_CLK_A,		SEL_DRIF1_0),
1421	PINMUX_IPSR_MSEL(IP16_15_12,	RIF3_CLK_A,		SEL_DRIF3_0),
1422
1423	PINMUX_IPSR_GPSR(IP16_19_16,	SSI_WS78),
1424	PINMUX_IPSR_MSEL(IP16_19_16,	HTX2_B,			SEL_HSCIF2_1),
1425	PINMUX_IPSR_MSEL(IP16_19_16,	MSIOF1_SYNC_C,		SEL_MSIOF1_2),
1426	PINMUX_IPSR_MSEL(IP16_19_16,	TS_SDAT1_A,		SEL_TSIF1_0),
1427	PINMUX_IPSR_MSEL(IP16_19_16,	STP_ISD_1_A,		SEL_SSP1_1_0),
1428	PINMUX_IPSR_MSEL(IP16_19_16,	RIF1_SYNC_A,		SEL_DRIF1_0),
1429	PINMUX_IPSR_MSEL(IP16_19_16,	RIF3_SYNC_A,		SEL_DRIF3_0),
1430
1431	PINMUX_IPSR_GPSR(IP16_23_20,	SSI_SDATA7),
1432	PINMUX_IPSR_MSEL(IP16_23_20,	HCTS2_N_B,		SEL_HSCIF2_1),
1433	PINMUX_IPSR_MSEL(IP16_23_20,	MSIOF1_RXD_C,		SEL_MSIOF1_2),
1434	PINMUX_IPSR_MSEL(IP16_23_20,	TS_SDEN1_A,		SEL_TSIF1_0),
1435	PINMUX_IPSR_MSEL(IP16_23_20,	STP_ISEN_1_A,		SEL_SSP1_1_0),
1436	PINMUX_IPSR_MSEL(IP16_23_20,	RIF1_D0_A,		SEL_DRIF1_0),
1437	PINMUX_IPSR_MSEL(IP16_23_20,	RIF3_D0_A,		SEL_DRIF3_0),
1438	PINMUX_IPSR_MSEL(IP16_23_20,	TCLK2_A,		SEL_TIMER_TMU2_0),
1439
1440	PINMUX_IPSR_GPSR(IP16_27_24,	SSI_SDATA8),
1441	PINMUX_IPSR_MSEL(IP16_27_24,	HRTS2_N_B,		SEL_HSCIF2_1),
1442	PINMUX_IPSR_MSEL(IP16_27_24,	MSIOF1_TXD_C,		SEL_MSIOF1_2),
1443	PINMUX_IPSR_MSEL(IP16_27_24,	TS_SPSYNC1_A,		SEL_TSIF1_0),
1444	PINMUX_IPSR_MSEL(IP16_27_24,	STP_ISSYNC_1_A,		SEL_SSP1_1_0),
1445	PINMUX_IPSR_MSEL(IP16_27_24,	RIF1_D1_A,		SEL_DRIF1_0),
1446	PINMUX_IPSR_MSEL(IP16_27_24,	RIF3_D1_A,		SEL_DRIF3_0),
1447
1448	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_SDATA9_A,		SEL_SSI9_0),
1449	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK2_B,		SEL_HSCIF2_1),
1450	PINMUX_IPSR_MSEL(IP16_31_28,	MSIOF1_SS1_C,		SEL_MSIOF1_2),
1451	PINMUX_IPSR_MSEL(IP16_31_28,	HSCK1_A,		SEL_HSCIF1_0),
1452	PINMUX_IPSR_MSEL(IP16_31_28,	SSI_WS1_B,		SEL_SSI1_1),
1453	PINMUX_IPSR_GPSR(IP16_31_28,	SCK1),
1454	PINMUX_IPSR_MSEL(IP16_31_28,	STP_IVCXO27_1_A,	SEL_SSP1_1_0),
1455	PINMUX_IPSR_MSEL(IP16_31_28,	SCK5_A,			SEL_SCIF5_0),
1456
1457	/* IPSR17 */
1458	PINMUX_IPSR_MSEL(IP17_3_0,	AUDIO_CLKA_A,		SEL_ADGA_0),
1459
1460	PINMUX_IPSR_MSEL(IP17_7_4,	AUDIO_CLKB_B,		SEL_ADGB_1),
1461	PINMUX_IPSR_MSEL(IP17_7_4,	SCIF_CLK_A,		SEL_SCIF_0),
1462	PINMUX_IPSR_MSEL(IP17_7_4,	STP_IVCXO27_1_D,	SEL_SSP1_1_3),
1463	PINMUX_IPSR_MSEL(IP17_7_4,	REMOCON_A,		SEL_REMOCON_0),
1464	PINMUX_IPSR_MSEL(IP17_7_4,	TCLK1_A,		SEL_TIMER_TMU_0),
1465
1466	PINMUX_IPSR_GPSR(IP17_11_8,	USB0_PWEN),
1467	PINMUX_IPSR_MSEL(IP17_11_8,	SIM0_RST_C,		SEL_SIMCARD_2),
1468	PINMUX_IPSR_MSEL(IP17_11_8,	TS_SCK1_D,		SEL_TSIF1_3),
1469	PINMUX_IPSR_MSEL(IP17_11_8,	STP_ISCLK_1_D,		SEL_SSP1_1_3),
1470	PINMUX_IPSR_MSEL(IP17_11_8,	BPFCLK_B,		SEL_FM_1),
1471	PINMUX_IPSR_MSEL(IP17_11_8,	RIF3_CLK_B,		SEL_DRIF3_1),
1472	PINMUX_IPSR_MSEL(IP17_11_8,	HSCK2_C,		SEL_HSCIF2_2),
1473
1474	PINMUX_IPSR_GPSR(IP17_15_12,	USB0_OVC),
1475	PINMUX_IPSR_MSEL(IP17_15_12,	SIM0_D_C,		SEL_SIMCARD_2),
1476	PINMUX_IPSR_MSEL(IP17_15_12,	TS_SDAT1_D,		SEL_TSIF1_3),
1477	PINMUX_IPSR_MSEL(IP17_15_12,	STP_ISD_1_D,		SEL_SSP1_1_3),
1478	PINMUX_IPSR_MSEL(IP17_15_12,	RIF3_SYNC_B,		SEL_DRIF3_1),
1479	PINMUX_IPSR_MSEL(IP17_15_12,	HRX2_C,			SEL_HSCIF2_2),
1480
1481	PINMUX_IPSR_GPSR(IP17_19_16,	USB1_PWEN),
1482	PINMUX_IPSR_MSEL(IP17_19_16,	SIM0_CLK_C,		SEL_SIMCARD_2),
1483	PINMUX_IPSR_MSEL(IP17_19_16,	SSI_SCK1_A,		SEL_SSI1_0),
1484	PINMUX_IPSR_MSEL(IP17_19_16,	TS_SCK0_E,		SEL_TSIF0_4),
1485	PINMUX_IPSR_MSEL(IP17_19_16,	STP_ISCLK_0_E,		SEL_SSP1_0_4),
1486	PINMUX_IPSR_MSEL(IP17_19_16,	FMCLK_B,		SEL_FM_1),
1487	PINMUX_IPSR_MSEL(IP17_19_16,	RIF2_CLK_B,		SEL_DRIF2_1),
1488	PINMUX_IPSR_MSEL(IP17_19_16,	SPEEDIN_A,		SEL_SPEED_PULSE_0),
1489	PINMUX_IPSR_MSEL(IP17_19_16,	HTX2_C,			SEL_HSCIF2_2),
1490
1491	PINMUX_IPSR_GPSR(IP17_23_20,	USB1_OVC),
1492	PINMUX_IPSR_MSEL(IP17_23_20,	MSIOF1_SS2_C,		SEL_MSIOF1_2),
1493	PINMUX_IPSR_MSEL(IP17_23_20,	SSI_WS1_A,		SEL_SSI1_0),
1494	PINMUX_IPSR_MSEL(IP17_23_20,	TS_SDAT0_E,		SEL_TSIF0_4),
1495	PINMUX_IPSR_MSEL(IP17_23_20,	STP_ISD_0_E,		SEL_SSP1_0_4),
1496	PINMUX_IPSR_MSEL(IP17_23_20,	FMIN_B,			SEL_FM_1),
1497	PINMUX_IPSR_MSEL(IP17_23_20,	RIF2_SYNC_B,		SEL_DRIF2_1),
1498	PINMUX_IPSR_MSEL(IP17_23_20,	REMOCON_B,		SEL_REMOCON_1),
1499	PINMUX_IPSR_MSEL(IP17_23_20,	HCTS2_N_C,		SEL_HSCIF2_2),
1500
1501	PINMUX_IPSR_GPSR(IP17_27_24,	USB30_PWEN),
1502	PINMUX_IPSR_GPSR(IP17_27_24,	AUDIO_CLKOUT_B),
1503	PINMUX_IPSR_MSEL(IP17_27_24,	SSI_SCK2_B,		SEL_SSI2_1),
1504	PINMUX_IPSR_MSEL(IP17_27_24,	TS_SDEN1_D,		SEL_TSIF1_3),
1505	PINMUX_IPSR_MSEL(IP17_27_24,	STP_ISEN_1_D,		SEL_SSP1_1_3),
1506	PINMUX_IPSR_MSEL(IP17_27_24,	STP_OPWM_0_E,		SEL_SSP1_0_4),
1507	PINMUX_IPSR_MSEL(IP17_27_24,	RIF3_D0_B,		SEL_DRIF3_1),
1508	PINMUX_IPSR_MSEL(IP17_27_24,	TCLK2_B,		SEL_TIMER_TMU2_1),
1509	PINMUX_IPSR_GPSR(IP17_27_24,	TPU0TO0),
1510	PINMUX_IPSR_MSEL(IP17_27_24,	BPFCLK_C,		SEL_FM_2),
1511	PINMUX_IPSR_MSEL(IP17_27_24,	HRTS2_N_C,		SEL_HSCIF2_2),
1512
1513	PINMUX_IPSR_GPSR(IP17_31_28,	USB30_OVC),
1514	PINMUX_IPSR_GPSR(IP17_31_28,	AUDIO_CLKOUT1_B),
1515	PINMUX_IPSR_MSEL(IP17_31_28,	SSI_WS2_B,		SEL_SSI2_1),
1516	PINMUX_IPSR_MSEL(IP17_31_28,	TS_SPSYNC1_D,		SEL_TSIF1_3),
1517	PINMUX_IPSR_MSEL(IP17_31_28,	STP_ISSYNC_1_D,		SEL_SSP1_1_3),
1518	PINMUX_IPSR_MSEL(IP17_31_28,	STP_IVCXO27_0_E,	SEL_SSP1_0_4),
1519	PINMUX_IPSR_MSEL(IP17_31_28,	RIF3_D1_B,		SEL_DRIF3_1),
1520	PINMUX_IPSR_GPSR(IP17_31_28,	FSO_TOE_N),
1521	PINMUX_IPSR_GPSR(IP17_31_28,	TPU0TO1),
1522
1523	/* IPSR18 */
1524	PINMUX_IPSR_GPSR(IP18_3_0,	GP6_30),
1525	PINMUX_IPSR_GPSR(IP18_3_0,	AUDIO_CLKOUT2_B),
1526	PINMUX_IPSR_MSEL(IP18_3_0,	SSI_SCK9_B,		SEL_SSI9_1),
1527	PINMUX_IPSR_MSEL(IP18_3_0,	TS_SDEN0_E,		SEL_TSIF0_4),
1528	PINMUX_IPSR_MSEL(IP18_3_0,	STP_ISEN_0_E,		SEL_SSP1_0_4),
1529	PINMUX_IPSR_MSEL(IP18_3_0,	RIF2_D0_B,		SEL_DRIF2_1),
1530	PINMUX_IPSR_GPSR(IP18_3_0,	TPU0TO2),
1531	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_C,		SEL_FM_2),
1532	PINMUX_IPSR_MSEL(IP18_3_0,	FMCLK_D,		SEL_FM_3),
1533
1534	PINMUX_IPSR_GPSR(IP18_7_4,	GP6_31),
1535	PINMUX_IPSR_GPSR(IP18_7_4,	AUDIO_CLKOUT3_B),
1536	PINMUX_IPSR_MSEL(IP18_7_4,	SSI_WS9_B,		SEL_SSI9_1),
1537	PINMUX_IPSR_MSEL(IP18_7_4,	TS_SPSYNC0_E,		SEL_TSIF0_4),
1538	PINMUX_IPSR_MSEL(IP18_7_4,	STP_ISSYNC_0_E,		SEL_SSP1_0_4),
1539	PINMUX_IPSR_MSEL(IP18_7_4,	RIF2_D1_B,		SEL_DRIF2_1),
1540	PINMUX_IPSR_GPSR(IP18_7_4,	TPU0TO3),
1541	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_C,			SEL_FM_2),
1542	PINMUX_IPSR_MSEL(IP18_7_4,	FMIN_D,			SEL_FM_3),
1543
1544/*
1545 * Static pins can not be muxed between different functions but
1546 * still need mark entries in the pinmux list. Add each static
1547 * pin to the list without an associated function. The sh-pfc
1548 * core will do the right thing and skip trying to mux the pin
1549 * while still applying configuration to it.
1550 */
1551#define FM(x)	PINMUX_DATA(x##_MARK, 0),
1552	PINMUX_STATIC
1553#undef FM
1554};
1555
1556/*
1557 * Pins not associated with a GPIO port.
1558 */
1559enum {
1560	GP_ASSIGN_LAST(),
1561	NOGP_ALL(),
1562};
1563
1564static const struct sh_pfc_pin pinmux_pins[] = {
1565	PINMUX_GPIO_GP_ALL(),
1566	PINMUX_NOGP_ALL(),
1567};
1568
1569/* - AUDIO CLOCK ------------------------------------------------------------ */
1570static const unsigned int audio_clk_a_a_pins[] = {
1571	/* CLK A */
1572	RCAR_GP_PIN(6, 22),
1573};
1574static const unsigned int audio_clk_a_a_mux[] = {
1575	AUDIO_CLKA_A_MARK,
1576};
1577static const unsigned int audio_clk_a_b_pins[] = {
1578	/* CLK A */
1579	RCAR_GP_PIN(5, 4),
1580};
1581static const unsigned int audio_clk_a_b_mux[] = {
1582	AUDIO_CLKA_B_MARK,
1583};
1584static const unsigned int audio_clk_a_c_pins[] = {
1585	/* CLK A */
1586	RCAR_GP_PIN(5, 19),
1587};
1588static const unsigned int audio_clk_a_c_mux[] = {
1589	AUDIO_CLKA_C_MARK,
1590};
1591static const unsigned int audio_clk_b_a_pins[] = {
1592	/* CLK B */
1593	RCAR_GP_PIN(5, 12),
1594};
1595static const unsigned int audio_clk_b_a_mux[] = {
1596	AUDIO_CLKB_A_MARK,
1597};
1598static const unsigned int audio_clk_b_b_pins[] = {
1599	/* CLK B */
1600	RCAR_GP_PIN(6, 23),
1601};
1602static const unsigned int audio_clk_b_b_mux[] = {
1603	AUDIO_CLKB_B_MARK,
1604};
1605static const unsigned int audio_clk_c_a_pins[] = {
1606	/* CLK C */
1607	RCAR_GP_PIN(5, 21),
1608};
1609static const unsigned int audio_clk_c_a_mux[] = {
1610	AUDIO_CLKC_A_MARK,
1611};
1612static const unsigned int audio_clk_c_b_pins[] = {
1613	/* CLK C */
1614	RCAR_GP_PIN(5, 0),
1615};
1616static const unsigned int audio_clk_c_b_mux[] = {
1617	AUDIO_CLKC_B_MARK,
1618};
1619static const unsigned int audio_clkout_a_pins[] = {
1620	/* CLKOUT */
1621	RCAR_GP_PIN(5, 18),
1622};
1623static const unsigned int audio_clkout_a_mux[] = {
1624	AUDIO_CLKOUT_A_MARK,
1625};
1626static const unsigned int audio_clkout_b_pins[] = {
1627	/* CLKOUT */
1628	RCAR_GP_PIN(6, 28),
1629};
1630static const unsigned int audio_clkout_b_mux[] = {
1631	AUDIO_CLKOUT_B_MARK,
1632};
1633static const unsigned int audio_clkout_c_pins[] = {
1634	/* CLKOUT */
1635	RCAR_GP_PIN(5, 3),
1636};
1637static const unsigned int audio_clkout_c_mux[] = {
1638	AUDIO_CLKOUT_C_MARK,
1639};
1640static const unsigned int audio_clkout_d_pins[] = {
1641	/* CLKOUT */
1642	RCAR_GP_PIN(5, 21),
1643};
1644static const unsigned int audio_clkout_d_mux[] = {
1645	AUDIO_CLKOUT_D_MARK,
1646};
1647static const unsigned int audio_clkout1_a_pins[] = {
1648	/* CLKOUT1 */
1649	RCAR_GP_PIN(5, 15),
1650};
1651static const unsigned int audio_clkout1_a_mux[] = {
1652	AUDIO_CLKOUT1_A_MARK,
1653};
1654static const unsigned int audio_clkout1_b_pins[] = {
1655	/* CLKOUT1 */
1656	RCAR_GP_PIN(6, 29),
1657};
1658static const unsigned int audio_clkout1_b_mux[] = {
1659	AUDIO_CLKOUT1_B_MARK,
1660};
1661static const unsigned int audio_clkout2_a_pins[] = {
1662	/* CLKOUT2 */
1663	RCAR_GP_PIN(5, 16),
1664};
1665static const unsigned int audio_clkout2_a_mux[] = {
1666	AUDIO_CLKOUT2_A_MARK,
1667};
1668static const unsigned int audio_clkout2_b_pins[] = {
1669	/* CLKOUT2 */
1670	RCAR_GP_PIN(6, 30),
1671};
1672static const unsigned int audio_clkout2_b_mux[] = {
1673	AUDIO_CLKOUT2_B_MARK,
1674};
1675
1676static const unsigned int audio_clkout3_a_pins[] = {
1677	/* CLKOUT3 */
1678	RCAR_GP_PIN(5, 19),
1679};
1680static const unsigned int audio_clkout3_a_mux[] = {
1681	AUDIO_CLKOUT3_A_MARK,
1682};
1683static const unsigned int audio_clkout3_b_pins[] = {
1684	/* CLKOUT3 */
1685	RCAR_GP_PIN(6, 31),
1686};
1687static const unsigned int audio_clkout3_b_mux[] = {
1688	AUDIO_CLKOUT3_B_MARK,
1689};
1690
1691/* - EtherAVB --------------------------------------------------------------- */
1692static const unsigned int avb_link_pins[] = {
1693	/* AVB_LINK */
1694	RCAR_GP_PIN(2, 12),
1695};
1696static const unsigned int avb_link_mux[] = {
1697	AVB_LINK_MARK,
1698};
1699static const unsigned int avb_magic_pins[] = {
1700	/* AVB_MAGIC_ */
1701	RCAR_GP_PIN(2, 10),
1702};
1703static const unsigned int avb_magic_mux[] = {
1704	AVB_MAGIC_MARK,
1705};
1706static const unsigned int avb_phy_int_pins[] = {
1707	/* AVB_PHY_INT */
1708	RCAR_GP_PIN(2, 11),
1709};
1710static const unsigned int avb_phy_int_mux[] = {
1711	AVB_PHY_INT_MARK,
1712};
1713static const unsigned int avb_mdio_pins[] = {
1714	/* AVB_MDC, AVB_MDIO */
1715	RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1716};
1717static const unsigned int avb_mdio_mux[] = {
1718	AVB_MDC_MARK, AVB_MDIO_MARK,
1719};
1720static const unsigned int avb_mii_pins[] = {
1721	/*
1722	 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1723	 * AVB_TD1, AVB_TD2, AVB_TD3,
1724	 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1725	 * AVB_RD1, AVB_RD2, AVB_RD3,
1726	 * AVB_TXCREFCLK
1727	 */
1728	PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1729	PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1730	PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1731	PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1732	PIN_AVB_TXCREFCLK,
1733};
1734static const unsigned int avb_mii_mux[] = {
1735	AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1736	AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1737	AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1738	AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1739	AVB_TXCREFCLK_MARK,
1740};
1741static const unsigned int avb_avtp_pps_pins[] = {
1742	/* AVB_AVTP_PPS */
1743	RCAR_GP_PIN(2, 6),
1744};
1745static const unsigned int avb_avtp_pps_mux[] = {
1746	AVB_AVTP_PPS_MARK,
1747};
1748static const unsigned int avb_avtp_match_a_pins[] = {
1749	/* AVB_AVTP_MATCH_A */
1750	RCAR_GP_PIN(2, 13),
1751};
1752static const unsigned int avb_avtp_match_a_mux[] = {
1753	AVB_AVTP_MATCH_A_MARK,
1754};
1755static const unsigned int avb_avtp_capture_a_pins[] = {
1756	/* AVB_AVTP_CAPTURE_A */
1757	RCAR_GP_PIN(2, 14),
1758};
1759static const unsigned int avb_avtp_capture_a_mux[] = {
1760	AVB_AVTP_CAPTURE_A_MARK,
1761};
1762static const unsigned int avb_avtp_match_b_pins[] = {
1763	/*  AVB_AVTP_MATCH_B */
1764	RCAR_GP_PIN(1, 8),
1765};
1766static const unsigned int avb_avtp_match_b_mux[] = {
1767	AVB_AVTP_MATCH_B_MARK,
1768};
1769static const unsigned int avb_avtp_capture_b_pins[] = {
1770	/* AVB_AVTP_CAPTURE_B */
1771	RCAR_GP_PIN(1, 11),
1772};
1773static const unsigned int avb_avtp_capture_b_mux[] = {
1774	AVB_AVTP_CAPTURE_B_MARK,
1775};
1776
1777/* - CAN ------------------------------------------------------------------ */
1778static const unsigned int can0_data_a_pins[] = {
1779	/* TX, RX */
1780	RCAR_GP_PIN(1, 23),	RCAR_GP_PIN(1, 24),
1781};
1782static const unsigned int can0_data_a_mux[] = {
1783	CAN0_TX_A_MARK,		CAN0_RX_A_MARK,
1784};
1785static const unsigned int can0_data_b_pins[] = {
1786	/* TX, RX */
1787	RCAR_GP_PIN(2, 0),	RCAR_GP_PIN(2, 1),
1788};
1789static const unsigned int can0_data_b_mux[] = {
1790	CAN0_TX_B_MARK,		CAN0_RX_B_MARK,
1791};
1792static const unsigned int can1_data_pins[] = {
1793	/* TX, RX */
1794	RCAR_GP_PIN(1, 22),	RCAR_GP_PIN(1, 26),
1795};
1796static const unsigned int can1_data_mux[] = {
1797	CAN1_TX_MARK,		CAN1_RX_MARK,
1798};
1799
1800/* - CAN Clock -------------------------------------------------------------- */
1801static const unsigned int can_clk_pins[] = {
1802	/* CLK */
1803	RCAR_GP_PIN(1, 25),
1804};
1805static const unsigned int can_clk_mux[] = {
1806	CAN_CLK_MARK,
1807};
1808
1809/* - CAN FD --------------------------------------------------------------- */
1810static const unsigned int canfd0_data_a_pins[] = {
1811	/* TX, RX */
1812	RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1813};
1814static const unsigned int canfd0_data_a_mux[] = {
1815	CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1816};
1817static const unsigned int canfd0_data_b_pins[] = {
1818	/* TX, RX */
1819	RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1820};
1821static const unsigned int canfd0_data_b_mux[] = {
1822	CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1823};
1824static const unsigned int canfd1_data_pins[] = {
1825	/* TX, RX */
1826	RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1827};
1828static const unsigned int canfd1_data_mux[] = {
1829	CANFD1_TX_MARK,         CANFD1_RX_MARK,
1830};
1831
1832#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1833/* - DRIF0 --------------------------------------------------------------- */
1834static const unsigned int drif0_ctrl_a_pins[] = {
1835	/* CLK, SYNC */
1836	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1837};
1838static const unsigned int drif0_ctrl_a_mux[] = {
1839	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1840};
1841static const unsigned int drif0_data0_a_pins[] = {
1842	/* D0 */
1843	RCAR_GP_PIN(6, 10),
1844};
1845static const unsigned int drif0_data0_a_mux[] = {
1846	RIF0_D0_A_MARK,
1847};
1848static const unsigned int drif0_data1_a_pins[] = {
1849	/* D1 */
1850	RCAR_GP_PIN(6, 7),
1851};
1852static const unsigned int drif0_data1_a_mux[] = {
1853	RIF0_D1_A_MARK,
1854};
1855static const unsigned int drif0_ctrl_b_pins[] = {
1856	/* CLK, SYNC */
1857	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1858};
1859static const unsigned int drif0_ctrl_b_mux[] = {
1860	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1861};
1862static const unsigned int drif0_data0_b_pins[] = {
1863	/* D0 */
1864	RCAR_GP_PIN(5, 1),
1865};
1866static const unsigned int drif0_data0_b_mux[] = {
1867	RIF0_D0_B_MARK,
1868};
1869static const unsigned int drif0_data1_b_pins[] = {
1870	/* D1 */
1871	RCAR_GP_PIN(5, 2),
1872};
1873static const unsigned int drif0_data1_b_mux[] = {
1874	RIF0_D1_B_MARK,
1875};
1876static const unsigned int drif0_ctrl_c_pins[] = {
1877	/* CLK, SYNC */
1878	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1879};
1880static const unsigned int drif0_ctrl_c_mux[] = {
1881	RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1882};
1883static const unsigned int drif0_data0_c_pins[] = {
1884	/* D0 */
1885	RCAR_GP_PIN(5, 13),
1886};
1887static const unsigned int drif0_data0_c_mux[] = {
1888	RIF0_D0_C_MARK,
1889};
1890static const unsigned int drif0_data1_c_pins[] = {
1891	/* D1 */
1892	RCAR_GP_PIN(5, 14),
1893};
1894static const unsigned int drif0_data1_c_mux[] = {
1895	RIF0_D1_C_MARK,
1896};
1897/* - DRIF1 --------------------------------------------------------------- */
1898static const unsigned int drif1_ctrl_a_pins[] = {
1899	/* CLK, SYNC */
1900	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1901};
1902static const unsigned int drif1_ctrl_a_mux[] = {
1903	RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1904};
1905static const unsigned int drif1_data0_a_pins[] = {
1906	/* D0 */
1907	RCAR_GP_PIN(6, 19),
1908};
1909static const unsigned int drif1_data0_a_mux[] = {
1910	RIF1_D0_A_MARK,
1911};
1912static const unsigned int drif1_data1_a_pins[] = {
1913	/* D1 */
1914	RCAR_GP_PIN(6, 20),
1915};
1916static const unsigned int drif1_data1_a_mux[] = {
1917	RIF1_D1_A_MARK,
1918};
1919static const unsigned int drif1_ctrl_b_pins[] = {
1920	/* CLK, SYNC */
1921	RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1922};
1923static const unsigned int drif1_ctrl_b_mux[] = {
1924	RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1925};
1926static const unsigned int drif1_data0_b_pins[] = {
1927	/* D0 */
1928	RCAR_GP_PIN(5, 7),
1929};
1930static const unsigned int drif1_data0_b_mux[] = {
1931	RIF1_D0_B_MARK,
1932};
1933static const unsigned int drif1_data1_b_pins[] = {
1934	/* D1 */
1935	RCAR_GP_PIN(5, 8),
1936};
1937static const unsigned int drif1_data1_b_mux[] = {
1938	RIF1_D1_B_MARK,
1939};
1940static const unsigned int drif1_ctrl_c_pins[] = {
1941	/* CLK, SYNC */
1942	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1943};
1944static const unsigned int drif1_ctrl_c_mux[] = {
1945	RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1946};
1947static const unsigned int drif1_data0_c_pins[] = {
1948	/* D0 */
1949	RCAR_GP_PIN(5, 6),
1950};
1951static const unsigned int drif1_data0_c_mux[] = {
1952	RIF1_D0_C_MARK,
1953};
1954static const unsigned int drif1_data1_c_pins[] = {
1955	/* D1 */
1956	RCAR_GP_PIN(5, 10),
1957};
1958static const unsigned int drif1_data1_c_mux[] = {
1959	RIF1_D1_C_MARK,
1960};
1961/* - DRIF2 --------------------------------------------------------------- */
1962static const unsigned int drif2_ctrl_a_pins[] = {
1963	/* CLK, SYNC */
1964	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1965};
1966static const unsigned int drif2_ctrl_a_mux[] = {
1967	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1968};
1969static const unsigned int drif2_data0_a_pins[] = {
1970	/* D0 */
1971	RCAR_GP_PIN(6, 7),
1972};
1973static const unsigned int drif2_data0_a_mux[] = {
1974	RIF2_D0_A_MARK,
1975};
1976static const unsigned int drif2_data1_a_pins[] = {
1977	/* D1 */
1978	RCAR_GP_PIN(6, 10),
1979};
1980static const unsigned int drif2_data1_a_mux[] = {
1981	RIF2_D1_A_MARK,
1982};
1983static const unsigned int drif2_ctrl_b_pins[] = {
1984	/* CLK, SYNC */
1985	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1986};
1987static const unsigned int drif2_ctrl_b_mux[] = {
1988	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1989};
1990static const unsigned int drif2_data0_b_pins[] = {
1991	/* D0 */
1992	RCAR_GP_PIN(6, 30),
1993};
1994static const unsigned int drif2_data0_b_mux[] = {
1995	RIF2_D0_B_MARK,
1996};
1997static const unsigned int drif2_data1_b_pins[] = {
1998	/* D1 */
1999	RCAR_GP_PIN(6, 31),
2000};
2001static const unsigned int drif2_data1_b_mux[] = {
2002	RIF2_D1_B_MARK,
2003};
2004/* - DRIF3 --------------------------------------------------------------- */
2005static const unsigned int drif3_ctrl_a_pins[] = {
2006	/* CLK, SYNC */
2007	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2008};
2009static const unsigned int drif3_ctrl_a_mux[] = {
2010	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2011};
2012static const unsigned int drif3_data0_a_pins[] = {
2013	/* D0 */
2014	RCAR_GP_PIN(6, 19),
2015};
2016static const unsigned int drif3_data0_a_mux[] = {
2017	RIF3_D0_A_MARK,
2018};
2019static const unsigned int drif3_data1_a_pins[] = {
2020	/* D1 */
2021	RCAR_GP_PIN(6, 20),
2022};
2023static const unsigned int drif3_data1_a_mux[] = {
2024	RIF3_D1_A_MARK,
2025};
2026static const unsigned int drif3_ctrl_b_pins[] = {
2027	/* CLK, SYNC */
2028	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2029};
2030static const unsigned int drif3_ctrl_b_mux[] = {
2031	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2032};
2033static const unsigned int drif3_data0_b_pins[] = {
2034	/* D0 */
2035	RCAR_GP_PIN(6, 28),
2036};
2037static const unsigned int drif3_data0_b_mux[] = {
2038	RIF3_D0_B_MARK,
2039};
2040static const unsigned int drif3_data1_b_pins[] = {
2041	/* D1 */
2042	RCAR_GP_PIN(6, 29),
2043};
2044static const unsigned int drif3_data1_b_mux[] = {
2045	RIF3_D1_B_MARK,
2046};
2047#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2048
2049/* - DU --------------------------------------------------------------------- */
2050static const unsigned int du_rgb666_pins[] = {
2051	/* R[7:2], G[7:2], B[7:2] */
2052	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2053	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2054	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2055	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2056	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2057	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2058};
2059static const unsigned int du_rgb666_mux[] = {
2060	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2061	DU_DR3_MARK, DU_DR2_MARK,
2062	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2063	DU_DG3_MARK, DU_DG2_MARK,
2064	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2065	DU_DB3_MARK, DU_DB2_MARK,
2066};
2067static const unsigned int du_rgb888_pins[] = {
2068	/* R[7:0], G[7:0], B[7:0] */
2069	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2070	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2071	RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2072	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2073	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2074	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2075	RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2076	RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2077	RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2078};
2079static const unsigned int du_rgb888_mux[] = {
2080	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2081	DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2082	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2083	DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2084	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2085	DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2086};
2087static const unsigned int du_clk_out_0_pins[] = {
2088	/* CLKOUT */
2089	RCAR_GP_PIN(1, 27),
2090};
2091static const unsigned int du_clk_out_0_mux[] = {
2092	DU_DOTCLKOUT0_MARK
2093};
2094static const unsigned int du_clk_out_1_pins[] = {
2095	/* CLKOUT */
2096	RCAR_GP_PIN(2, 3),
2097};
2098static const unsigned int du_clk_out_1_mux[] = {
2099	DU_DOTCLKOUT1_MARK
2100};
2101static const unsigned int du_sync_pins[] = {
2102	/* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2103	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2104};
2105static const unsigned int du_sync_mux[] = {
2106	DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2107};
2108static const unsigned int du_oddf_pins[] = {
2109	/* EXDISP/EXODDF/EXCDE */
2110	RCAR_GP_PIN(2, 2),
2111};
2112static const unsigned int du_oddf_mux[] = {
2113	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2114};
2115static const unsigned int du_cde_pins[] = {
2116	/* CDE */
2117	RCAR_GP_PIN(2, 0),
2118};
2119static const unsigned int du_cde_mux[] = {
2120	DU_CDE_MARK,
2121};
2122static const unsigned int du_disp_pins[] = {
2123	/* DISP */
2124	RCAR_GP_PIN(2, 1),
2125};
2126static const unsigned int du_disp_mux[] = {
2127	DU_DISP_MARK,
2128};
2129
2130/* - HSCIF0 ----------------------------------------------------------------- */
2131static const unsigned int hscif0_data_pins[] = {
2132	/* RX, TX */
2133	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2134};
2135static const unsigned int hscif0_data_mux[] = {
2136	HRX0_MARK, HTX0_MARK,
2137};
2138static const unsigned int hscif0_clk_pins[] = {
2139	/* SCK */
2140	RCAR_GP_PIN(5, 12),
2141};
2142static const unsigned int hscif0_clk_mux[] = {
2143	HSCK0_MARK,
2144};
2145static const unsigned int hscif0_ctrl_pins[] = {
2146	/* RTS, CTS */
2147	RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2148};
2149static const unsigned int hscif0_ctrl_mux[] = {
2150	HRTS0_N_MARK, HCTS0_N_MARK,
2151};
2152/* - HSCIF1 ----------------------------------------------------------------- */
2153static const unsigned int hscif1_data_a_pins[] = {
2154	/* RX, TX */
2155	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2156};
2157static const unsigned int hscif1_data_a_mux[] = {
2158	HRX1_A_MARK, HTX1_A_MARK,
2159};
2160static const unsigned int hscif1_clk_a_pins[] = {
2161	/* SCK */
2162	RCAR_GP_PIN(6, 21),
2163};
2164static const unsigned int hscif1_clk_a_mux[] = {
2165	HSCK1_A_MARK,
2166};
2167static const unsigned int hscif1_ctrl_a_pins[] = {
2168	/* RTS, CTS */
2169	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2170};
2171static const unsigned int hscif1_ctrl_a_mux[] = {
2172	HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2173};
2174
2175static const unsigned int hscif1_data_b_pins[] = {
2176	/* RX, TX */
2177	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2178};
2179static const unsigned int hscif1_data_b_mux[] = {
2180	HRX1_B_MARK, HTX1_B_MARK,
2181};
2182static const unsigned int hscif1_clk_b_pins[] = {
2183	/* SCK */
2184	RCAR_GP_PIN(5, 0),
2185};
2186static const unsigned int hscif1_clk_b_mux[] = {
2187	HSCK1_B_MARK,
2188};
2189static const unsigned int hscif1_ctrl_b_pins[] = {
2190	/* RTS, CTS */
2191	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2192};
2193static const unsigned int hscif1_ctrl_b_mux[] = {
2194	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2195};
2196/* - HSCIF2 ----------------------------------------------------------------- */
2197static const unsigned int hscif2_data_a_pins[] = {
2198	/* RX, TX */
2199	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2200};
2201static const unsigned int hscif2_data_a_mux[] = {
2202	HRX2_A_MARK, HTX2_A_MARK,
2203};
2204static const unsigned int hscif2_clk_a_pins[] = {
2205	/* SCK */
2206	RCAR_GP_PIN(6, 10),
2207};
2208static const unsigned int hscif2_clk_a_mux[] = {
2209	HSCK2_A_MARK,
2210};
2211static const unsigned int hscif2_ctrl_a_pins[] = {
2212	/* RTS, CTS */
2213	RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2214};
2215static const unsigned int hscif2_ctrl_a_mux[] = {
2216	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2217};
2218
2219static const unsigned int hscif2_data_b_pins[] = {
2220	/* RX, TX */
2221	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2222};
2223static const unsigned int hscif2_data_b_mux[] = {
2224	HRX2_B_MARK, HTX2_B_MARK,
2225};
2226static const unsigned int hscif2_clk_b_pins[] = {
2227	/* SCK */
2228	RCAR_GP_PIN(6, 21),
2229};
2230static const unsigned int hscif2_clk_b_mux[] = {
2231	HSCK2_B_MARK,
2232};
2233static const unsigned int hscif2_ctrl_b_pins[] = {
2234	/* RTS, CTS */
2235	RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2236};
2237static const unsigned int hscif2_ctrl_b_mux[] = {
2238	HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2239};
2240
2241static const unsigned int hscif2_data_c_pins[] = {
2242	/* RX, TX */
2243	RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2244};
2245static const unsigned int hscif2_data_c_mux[] = {
2246	HRX2_C_MARK, HTX2_C_MARK,
2247};
2248static const unsigned int hscif2_clk_c_pins[] = {
2249	/* SCK */
2250	RCAR_GP_PIN(6, 24),
2251};
2252static const unsigned int hscif2_clk_c_mux[] = {
2253	HSCK2_C_MARK,
2254};
2255static const unsigned int hscif2_ctrl_c_pins[] = {
2256	/* RTS, CTS */
2257	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2258};
2259static const unsigned int hscif2_ctrl_c_mux[] = {
2260	HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2261};
2262/* - HSCIF3 ----------------------------------------------------------------- */
2263static const unsigned int hscif3_data_a_pins[] = {
2264	/* RX, TX */
2265	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2266};
2267static const unsigned int hscif3_data_a_mux[] = {
2268	HRX3_A_MARK, HTX3_A_MARK,
2269};
2270static const unsigned int hscif3_clk_pins[] = {
2271	/* SCK */
2272	RCAR_GP_PIN(1, 22),
2273};
2274static const unsigned int hscif3_clk_mux[] = {
2275	HSCK3_MARK,
2276};
2277static const unsigned int hscif3_ctrl_pins[] = {
2278	/* RTS, CTS */
2279	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2280};
2281static const unsigned int hscif3_ctrl_mux[] = {
2282	HRTS3_N_MARK, HCTS3_N_MARK,
2283};
2284
2285static const unsigned int hscif3_data_b_pins[] = {
2286	/* RX, TX */
2287	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2288};
2289static const unsigned int hscif3_data_b_mux[] = {
2290	HRX3_B_MARK, HTX3_B_MARK,
2291};
2292static const unsigned int hscif3_data_c_pins[] = {
2293	/* RX, TX */
2294	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2295};
2296static const unsigned int hscif3_data_c_mux[] = {
2297	HRX3_C_MARK, HTX3_C_MARK,
2298};
2299static const unsigned int hscif3_data_d_pins[] = {
2300	/* RX, TX */
2301	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2302};
2303static const unsigned int hscif3_data_d_mux[] = {
2304	HRX3_D_MARK, HTX3_D_MARK,
2305};
2306/* - HSCIF4 ----------------------------------------------------------------- */
2307static const unsigned int hscif4_data_a_pins[] = {
2308	/* RX, TX */
2309	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2310};
2311static const unsigned int hscif4_data_a_mux[] = {
2312	HRX4_A_MARK, HTX4_A_MARK,
2313};
2314static const unsigned int hscif4_clk_pins[] = {
2315	/* SCK */
2316	RCAR_GP_PIN(1, 11),
2317};
2318static const unsigned int hscif4_clk_mux[] = {
2319	HSCK4_MARK,
2320};
2321static const unsigned int hscif4_ctrl_pins[] = {
2322	/* RTS, CTS */
2323	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2324};
2325static const unsigned int hscif4_ctrl_mux[] = {
2326	HRTS4_N_MARK, HCTS4_N_MARK,
2327};
2328
2329static const unsigned int hscif4_data_b_pins[] = {
2330	/* RX, TX */
2331	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2332};
2333static const unsigned int hscif4_data_b_mux[] = {
2334	HRX4_B_MARK, HTX4_B_MARK,
2335};
2336
2337/* - I2C -------------------------------------------------------------------- */
2338static const unsigned int i2c0_pins[] = {
2339	/* SCL, SDA */
2340	RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2341};
2342
2343static const unsigned int i2c0_mux[] = {
2344	SCL0_MARK, SDA0_MARK,
2345};
2346
2347static const unsigned int i2c1_a_pins[] = {
2348	/* SDA, SCL */
2349	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2350};
2351static const unsigned int i2c1_a_mux[] = {
2352	SDA1_A_MARK, SCL1_A_MARK,
2353};
2354static const unsigned int i2c1_b_pins[] = {
2355	/* SDA, SCL */
2356	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2357};
2358static const unsigned int i2c1_b_mux[] = {
2359	SDA1_B_MARK, SCL1_B_MARK,
2360};
2361static const unsigned int i2c2_a_pins[] = {
2362	/* SDA, SCL */
2363	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2364};
2365static const unsigned int i2c2_a_mux[] = {
2366	SDA2_A_MARK, SCL2_A_MARK,
2367};
2368static const unsigned int i2c2_b_pins[] = {
2369	/* SDA, SCL */
2370	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2371};
2372static const unsigned int i2c2_b_mux[] = {
2373	SDA2_B_MARK, SCL2_B_MARK,
2374};
2375
2376static const unsigned int i2c3_pins[] = {
2377	/* SCL, SDA */
2378	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2379};
2380
2381static const unsigned int i2c3_mux[] = {
2382	SCL3_MARK, SDA3_MARK,
2383};
2384
2385static const unsigned int i2c5_pins[] = {
2386	/* SCL, SDA */
2387	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2388};
2389
2390static const unsigned int i2c5_mux[] = {
2391	SCL5_MARK, SDA5_MARK,
2392};
2393
2394static const unsigned int i2c6_a_pins[] = {
2395	/* SDA, SCL */
2396	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2397};
2398static const unsigned int i2c6_a_mux[] = {
2399	SDA6_A_MARK, SCL6_A_MARK,
2400};
2401static const unsigned int i2c6_b_pins[] = {
2402	/* SDA, SCL */
2403	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2404};
2405static const unsigned int i2c6_b_mux[] = {
2406	SDA6_B_MARK, SCL6_B_MARK,
2407};
2408static const unsigned int i2c6_c_pins[] = {
2409	/* SDA, SCL */
2410	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2411};
2412static const unsigned int i2c6_c_mux[] = {
2413	SDA6_C_MARK, SCL6_C_MARK,
2414};
2415
2416/* - INTC-EX ---------------------------------------------------------------- */
2417static const unsigned int intc_ex_irq0_pins[] = {
2418	/* IRQ0 */
2419	RCAR_GP_PIN(2, 0),
2420};
2421static const unsigned int intc_ex_irq0_mux[] = {
2422	IRQ0_MARK,
2423};
2424static const unsigned int intc_ex_irq1_pins[] = {
2425	/* IRQ1 */
2426	RCAR_GP_PIN(2, 1),
2427};
2428static const unsigned int intc_ex_irq1_mux[] = {
2429	IRQ1_MARK,
2430};
2431static const unsigned int intc_ex_irq2_pins[] = {
2432	/* IRQ2 */
2433	RCAR_GP_PIN(2, 2),
2434};
2435static const unsigned int intc_ex_irq2_mux[] = {
2436	IRQ2_MARK,
2437};
2438static const unsigned int intc_ex_irq3_pins[] = {
2439	/* IRQ3 */
2440	RCAR_GP_PIN(2, 3),
2441};
2442static const unsigned int intc_ex_irq3_mux[] = {
2443	IRQ3_MARK,
2444};
2445static const unsigned int intc_ex_irq4_pins[] = {
2446	/* IRQ4 */
2447	RCAR_GP_PIN(2, 4),
2448};
2449static const unsigned int intc_ex_irq4_mux[] = {
2450	IRQ4_MARK,
2451};
2452static const unsigned int intc_ex_irq5_pins[] = {
2453	/* IRQ5 */
2454	RCAR_GP_PIN(2, 5),
2455};
2456static const unsigned int intc_ex_irq5_mux[] = {
2457	IRQ5_MARK,
2458};
2459
2460#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
2461/* - MLB+ ------------------------------------------------------------------- */
2462static const unsigned int mlb_3pin_pins[] = {
2463	RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2464};
2465static const unsigned int mlb_3pin_mux[] = {
2466	MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2467};
2468#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2469
2470/* - MSIOF0 ----------------------------------------------------------------- */
2471static const unsigned int msiof0_clk_pins[] = {
2472	/* SCK */
2473	RCAR_GP_PIN(5, 17),
2474};
2475static const unsigned int msiof0_clk_mux[] = {
2476	MSIOF0_SCK_MARK,
2477};
2478static const unsigned int msiof0_sync_pins[] = {
2479	/* SYNC */
2480	RCAR_GP_PIN(5, 18),
2481};
2482static const unsigned int msiof0_sync_mux[] = {
2483	MSIOF0_SYNC_MARK,
2484};
2485static const unsigned int msiof0_ss1_pins[] = {
2486	/* SS1 */
2487	RCAR_GP_PIN(5, 19),
2488};
2489static const unsigned int msiof0_ss1_mux[] = {
2490	MSIOF0_SS1_MARK,
2491};
2492static const unsigned int msiof0_ss2_pins[] = {
2493	/* SS2 */
2494	RCAR_GP_PIN(5, 21),
2495};
2496static const unsigned int msiof0_ss2_mux[] = {
2497	MSIOF0_SS2_MARK,
2498};
2499static const unsigned int msiof0_txd_pins[] = {
2500	/* TXD */
2501	RCAR_GP_PIN(5, 20),
2502};
2503static const unsigned int msiof0_txd_mux[] = {
2504	MSIOF0_TXD_MARK,
2505};
2506static const unsigned int msiof0_rxd_pins[] = {
2507	/* RXD */
2508	RCAR_GP_PIN(5, 22),
2509};
2510static const unsigned int msiof0_rxd_mux[] = {
2511	MSIOF0_RXD_MARK,
2512};
2513/* - MSIOF1 ----------------------------------------------------------------- */
2514static const unsigned int msiof1_clk_a_pins[] = {
2515	/* SCK */
2516	RCAR_GP_PIN(6, 8),
2517};
2518static const unsigned int msiof1_clk_a_mux[] = {
2519	MSIOF1_SCK_A_MARK,
2520};
2521static const unsigned int msiof1_sync_a_pins[] = {
2522	/* SYNC */
2523	RCAR_GP_PIN(6, 9),
2524};
2525static const unsigned int msiof1_sync_a_mux[] = {
2526	MSIOF1_SYNC_A_MARK,
2527};
2528static const unsigned int msiof1_ss1_a_pins[] = {
2529	/* SS1 */
2530	RCAR_GP_PIN(6, 5),
2531};
2532static const unsigned int msiof1_ss1_a_mux[] = {
2533	MSIOF1_SS1_A_MARK,
2534};
2535static const unsigned int msiof1_ss2_a_pins[] = {
2536	/* SS2 */
2537	RCAR_GP_PIN(6, 6),
2538};
2539static const unsigned int msiof1_ss2_a_mux[] = {
2540	MSIOF1_SS2_A_MARK,
2541};
2542static const unsigned int msiof1_txd_a_pins[] = {
2543	/* TXD */
2544	RCAR_GP_PIN(6, 7),
2545};
2546static const unsigned int msiof1_txd_a_mux[] = {
2547	MSIOF1_TXD_A_MARK,
2548};
2549static const unsigned int msiof1_rxd_a_pins[] = {
2550	/* RXD */
2551	RCAR_GP_PIN(6, 10),
2552};
2553static const unsigned int msiof1_rxd_a_mux[] = {
2554	MSIOF1_RXD_A_MARK,
2555};
2556static const unsigned int msiof1_clk_b_pins[] = {
2557	/* SCK */
2558	RCAR_GP_PIN(5, 9),
2559};
2560static const unsigned int msiof1_clk_b_mux[] = {
2561	MSIOF1_SCK_B_MARK,
2562};
2563static const unsigned int msiof1_sync_b_pins[] = {
2564	/* SYNC */
2565	RCAR_GP_PIN(5, 3),
2566};
2567static const unsigned int msiof1_sync_b_mux[] = {
2568	MSIOF1_SYNC_B_MARK,
2569};
2570static const unsigned int msiof1_ss1_b_pins[] = {
2571	/* SS1 */
2572	RCAR_GP_PIN(5, 4),
2573};
2574static const unsigned int msiof1_ss1_b_mux[] = {
2575	MSIOF1_SS1_B_MARK,
2576};
2577static const unsigned int msiof1_ss2_b_pins[] = {
2578	/* SS2 */
2579	RCAR_GP_PIN(5, 0),
2580};
2581static const unsigned int msiof1_ss2_b_mux[] = {
2582	MSIOF1_SS2_B_MARK,
2583};
2584static const unsigned int msiof1_txd_b_pins[] = {
2585	/* TXD */
2586	RCAR_GP_PIN(5, 8),
2587};
2588static const unsigned int msiof1_txd_b_mux[] = {
2589	MSIOF1_TXD_B_MARK,
2590};
2591static const unsigned int msiof1_rxd_b_pins[] = {
2592	/* RXD */
2593	RCAR_GP_PIN(5, 7),
2594};
2595static const unsigned int msiof1_rxd_b_mux[] = {
2596	MSIOF1_RXD_B_MARK,
2597};
2598static const unsigned int msiof1_clk_c_pins[] = {
2599	/* SCK */
2600	RCAR_GP_PIN(6, 17),
2601};
2602static const unsigned int msiof1_clk_c_mux[] = {
2603	MSIOF1_SCK_C_MARK,
2604};
2605static const unsigned int msiof1_sync_c_pins[] = {
2606	/* SYNC */
2607	RCAR_GP_PIN(6, 18),
2608};
2609static const unsigned int msiof1_sync_c_mux[] = {
2610	MSIOF1_SYNC_C_MARK,
2611};
2612static const unsigned int msiof1_ss1_c_pins[] = {
2613	/* SS1 */
2614	RCAR_GP_PIN(6, 21),
2615};
2616static const unsigned int msiof1_ss1_c_mux[] = {
2617	MSIOF1_SS1_C_MARK,
2618};
2619static const unsigned int msiof1_ss2_c_pins[] = {
2620	/* SS2 */
2621	RCAR_GP_PIN(6, 27),
2622};
2623static const unsigned int msiof1_ss2_c_mux[] = {
2624	MSIOF1_SS2_C_MARK,
2625};
2626static const unsigned int msiof1_txd_c_pins[] = {
2627	/* TXD */
2628	RCAR_GP_PIN(6, 20),
2629};
2630static const unsigned int msiof1_txd_c_mux[] = {
2631	MSIOF1_TXD_C_MARK,
2632};
2633static const unsigned int msiof1_rxd_c_pins[] = {
2634	/* RXD */
2635	RCAR_GP_PIN(6, 19),
2636};
2637static const unsigned int msiof1_rxd_c_mux[] = {
2638	MSIOF1_RXD_C_MARK,
2639};
2640static const unsigned int msiof1_clk_d_pins[] = {
2641	/* SCK */
2642	RCAR_GP_PIN(5, 12),
2643};
2644static const unsigned int msiof1_clk_d_mux[] = {
2645	MSIOF1_SCK_D_MARK,
2646};
2647static const unsigned int msiof1_sync_d_pins[] = {
2648	/* SYNC */
2649	RCAR_GP_PIN(5, 15),
2650};
2651static const unsigned int msiof1_sync_d_mux[] = {
2652	MSIOF1_SYNC_D_MARK,
2653};
2654static const unsigned int msiof1_ss1_d_pins[] = {
2655	/* SS1 */
2656	RCAR_GP_PIN(5, 16),
2657};
2658static const unsigned int msiof1_ss1_d_mux[] = {
2659	MSIOF1_SS1_D_MARK,
2660};
2661static const unsigned int msiof1_ss2_d_pins[] = {
2662	/* SS2 */
2663	RCAR_GP_PIN(5, 21),
2664};
2665static const unsigned int msiof1_ss2_d_mux[] = {
2666	MSIOF1_SS2_D_MARK,
2667};
2668static const unsigned int msiof1_txd_d_pins[] = {
2669	/* TXD */
2670	RCAR_GP_PIN(5, 14),
2671};
2672static const unsigned int msiof1_txd_d_mux[] = {
2673	MSIOF1_TXD_D_MARK,
2674};
2675static const unsigned int msiof1_rxd_d_pins[] = {
2676	/* RXD */
2677	RCAR_GP_PIN(5, 13),
2678};
2679static const unsigned int msiof1_rxd_d_mux[] = {
2680	MSIOF1_RXD_D_MARK,
2681};
2682static const unsigned int msiof1_clk_e_pins[] = {
2683	/* SCK */
2684	RCAR_GP_PIN(3, 0),
2685};
2686static const unsigned int msiof1_clk_e_mux[] = {
2687	MSIOF1_SCK_E_MARK,
2688};
2689static const unsigned int msiof1_sync_e_pins[] = {
2690	/* SYNC */
2691	RCAR_GP_PIN(3, 1),
2692};
2693static const unsigned int msiof1_sync_e_mux[] = {
2694	MSIOF1_SYNC_E_MARK,
2695};
2696static const unsigned int msiof1_ss1_e_pins[] = {
2697	/* SS1 */
2698	RCAR_GP_PIN(3, 4),
2699};
2700static const unsigned int msiof1_ss1_e_mux[] = {
2701	MSIOF1_SS1_E_MARK,
2702};
2703static const unsigned int msiof1_ss2_e_pins[] = {
2704	/* SS2 */
2705	RCAR_GP_PIN(3, 5),
2706};
2707static const unsigned int msiof1_ss2_e_mux[] = {
2708	MSIOF1_SS2_E_MARK,
2709};
2710static const unsigned int msiof1_txd_e_pins[] = {
2711	/* TXD */
2712	RCAR_GP_PIN(3, 3),
2713};
2714static const unsigned int msiof1_txd_e_mux[] = {
2715	MSIOF1_TXD_E_MARK,
2716};
2717static const unsigned int msiof1_rxd_e_pins[] = {
2718	/* RXD */
2719	RCAR_GP_PIN(3, 2),
2720};
2721static const unsigned int msiof1_rxd_e_mux[] = {
2722	MSIOF1_RXD_E_MARK,
2723};
2724static const unsigned int msiof1_clk_f_pins[] = {
2725	/* SCK */
2726	RCAR_GP_PIN(5, 23),
2727};
2728static const unsigned int msiof1_clk_f_mux[] = {
2729	MSIOF1_SCK_F_MARK,
2730};
2731static const unsigned int msiof1_sync_f_pins[] = {
2732	/* SYNC */
2733	RCAR_GP_PIN(5, 24),
2734};
2735static const unsigned int msiof1_sync_f_mux[] = {
2736	MSIOF1_SYNC_F_MARK,
2737};
2738static const unsigned int msiof1_ss1_f_pins[] = {
2739	/* SS1 */
2740	RCAR_GP_PIN(6, 1),
2741};
2742static const unsigned int msiof1_ss1_f_mux[] = {
2743	MSIOF1_SS1_F_MARK,
2744};
2745static const unsigned int msiof1_ss2_f_pins[] = {
2746	/* SS2 */
2747	RCAR_GP_PIN(6, 2),
2748};
2749static const unsigned int msiof1_ss2_f_mux[] = {
2750	MSIOF1_SS2_F_MARK,
2751};
2752static const unsigned int msiof1_txd_f_pins[] = {
2753	/* TXD */
2754	RCAR_GP_PIN(6, 0),
2755};
2756static const unsigned int msiof1_txd_f_mux[] = {
2757	MSIOF1_TXD_F_MARK,
2758};
2759static const unsigned int msiof1_rxd_f_pins[] = {
2760	/* RXD */
2761	RCAR_GP_PIN(5, 25),
2762};
2763static const unsigned int msiof1_rxd_f_mux[] = {
2764	MSIOF1_RXD_F_MARK,
2765};
2766static const unsigned int msiof1_clk_g_pins[] = {
2767	/* SCK */
2768	RCAR_GP_PIN(3, 6),
2769};
2770static const unsigned int msiof1_clk_g_mux[] = {
2771	MSIOF1_SCK_G_MARK,
2772};
2773static const unsigned int msiof1_sync_g_pins[] = {
2774	/* SYNC */
2775	RCAR_GP_PIN(3, 7),
2776};
2777static const unsigned int msiof1_sync_g_mux[] = {
2778	MSIOF1_SYNC_G_MARK,
2779};
2780static const unsigned int msiof1_ss1_g_pins[] = {
2781	/* SS1 */
2782	RCAR_GP_PIN(3, 10),
2783};
2784static const unsigned int msiof1_ss1_g_mux[] = {
2785	MSIOF1_SS1_G_MARK,
2786};
2787static const unsigned int msiof1_ss2_g_pins[] = {
2788	/* SS2 */
2789	RCAR_GP_PIN(3, 11),
2790};
2791static const unsigned int msiof1_ss2_g_mux[] = {
2792	MSIOF1_SS2_G_MARK,
2793};
2794static const unsigned int msiof1_txd_g_pins[] = {
2795	/* TXD */
2796	RCAR_GP_PIN(3, 9),
2797};
2798static const unsigned int msiof1_txd_g_mux[] = {
2799	MSIOF1_TXD_G_MARK,
2800};
2801static const unsigned int msiof1_rxd_g_pins[] = {
2802	/* RXD */
2803	RCAR_GP_PIN(3, 8),
2804};
2805static const unsigned int msiof1_rxd_g_mux[] = {
2806	MSIOF1_RXD_G_MARK,
2807};
2808/* - MSIOF2 ----------------------------------------------------------------- */
2809static const unsigned int msiof2_clk_a_pins[] = {
2810	/* SCK */
2811	RCAR_GP_PIN(1, 9),
2812};
2813static const unsigned int msiof2_clk_a_mux[] = {
2814	MSIOF2_SCK_A_MARK,
2815};
2816static const unsigned int msiof2_sync_a_pins[] = {
2817	/* SYNC */
2818	RCAR_GP_PIN(1, 8),
2819};
2820static const unsigned int msiof2_sync_a_mux[] = {
2821	MSIOF2_SYNC_A_MARK,
2822};
2823static const unsigned int msiof2_ss1_a_pins[] = {
2824	/* SS1 */
2825	RCAR_GP_PIN(1, 6),
2826};
2827static const unsigned int msiof2_ss1_a_mux[] = {
2828	MSIOF2_SS1_A_MARK,
2829};
2830static const unsigned int msiof2_ss2_a_pins[] = {
2831	/* SS2 */
2832	RCAR_GP_PIN(1, 7),
2833};
2834static const unsigned int msiof2_ss2_a_mux[] = {
2835	MSIOF2_SS2_A_MARK,
2836};
2837static const unsigned int msiof2_txd_a_pins[] = {
2838	/* TXD */
2839	RCAR_GP_PIN(1, 11),
2840};
2841static const unsigned int msiof2_txd_a_mux[] = {
2842	MSIOF2_TXD_A_MARK,
2843};
2844static const unsigned int msiof2_rxd_a_pins[] = {
2845	/* RXD */
2846	RCAR_GP_PIN(1, 10),
2847};
2848static const unsigned int msiof2_rxd_a_mux[] = {
2849	MSIOF2_RXD_A_MARK,
2850};
2851static const unsigned int msiof2_clk_b_pins[] = {
2852	/* SCK */
2853	RCAR_GP_PIN(0, 4),
2854};
2855static const unsigned int msiof2_clk_b_mux[] = {
2856	MSIOF2_SCK_B_MARK,
2857};
2858static const unsigned int msiof2_sync_b_pins[] = {
2859	/* SYNC */
2860	RCAR_GP_PIN(0, 5),
2861};
2862static const unsigned int msiof2_sync_b_mux[] = {
2863	MSIOF2_SYNC_B_MARK,
2864};
2865static const unsigned int msiof2_ss1_b_pins[] = {
2866	/* SS1 */
2867	RCAR_GP_PIN(0, 0),
2868};
2869static const unsigned int msiof2_ss1_b_mux[] = {
2870	MSIOF2_SS1_B_MARK,
2871};
2872static const unsigned int msiof2_ss2_b_pins[] = {
2873	/* SS2 */
2874	RCAR_GP_PIN(0, 1),
2875};
2876static const unsigned int msiof2_ss2_b_mux[] = {
2877	MSIOF2_SS2_B_MARK,
2878};
2879static const unsigned int msiof2_txd_b_pins[] = {
2880	/* TXD */
2881	RCAR_GP_PIN(0, 7),
2882};
2883static const unsigned int msiof2_txd_b_mux[] = {
2884	MSIOF2_TXD_B_MARK,
2885};
2886static const unsigned int msiof2_rxd_b_pins[] = {
2887	/* RXD */
2888	RCAR_GP_PIN(0, 6),
2889};
2890static const unsigned int msiof2_rxd_b_mux[] = {
2891	MSIOF2_RXD_B_MARK,
2892};
2893static const unsigned int msiof2_clk_c_pins[] = {
2894	/* SCK */
2895	RCAR_GP_PIN(2, 12),
2896};
2897static const unsigned int msiof2_clk_c_mux[] = {
2898	MSIOF2_SCK_C_MARK,
2899};
2900static const unsigned int msiof2_sync_c_pins[] = {
2901	/* SYNC */
2902	RCAR_GP_PIN(2, 11),
2903};
2904static const unsigned int msiof2_sync_c_mux[] = {
2905	MSIOF2_SYNC_C_MARK,
2906};
2907static const unsigned int msiof2_ss1_c_pins[] = {
2908	/* SS1 */
2909	RCAR_GP_PIN(2, 10),
2910};
2911static const unsigned int msiof2_ss1_c_mux[] = {
2912	MSIOF2_SS1_C_MARK,
2913};
2914static const unsigned int msiof2_ss2_c_pins[] = {
2915	/* SS2 */
2916	RCAR_GP_PIN(2, 9),
2917};
2918static const unsigned int msiof2_ss2_c_mux[] = {
2919	MSIOF2_SS2_C_MARK,
2920};
2921static const unsigned int msiof2_txd_c_pins[] = {
2922	/* TXD */
2923	RCAR_GP_PIN(2, 14),
2924};
2925static const unsigned int msiof2_txd_c_mux[] = {
2926	MSIOF2_TXD_C_MARK,
2927};
2928static const unsigned int msiof2_rxd_c_pins[] = {
2929	/* RXD */
2930	RCAR_GP_PIN(2, 13),
2931};
2932static const unsigned int msiof2_rxd_c_mux[] = {
2933	MSIOF2_RXD_C_MARK,
2934};
2935static const unsigned int msiof2_clk_d_pins[] = {
2936	/* SCK */
2937	RCAR_GP_PIN(0, 8),
2938};
2939static const unsigned int msiof2_clk_d_mux[] = {
2940	MSIOF2_SCK_D_MARK,
2941};
2942static const unsigned int msiof2_sync_d_pins[] = {
2943	/* SYNC */
2944	RCAR_GP_PIN(0, 9),
2945};
2946static const unsigned int msiof2_sync_d_mux[] = {
2947	MSIOF2_SYNC_D_MARK,
2948};
2949static const unsigned int msiof2_ss1_d_pins[] = {
2950	/* SS1 */
2951	RCAR_GP_PIN(0, 12),
2952};
2953static const unsigned int msiof2_ss1_d_mux[] = {
2954	MSIOF2_SS1_D_MARK,
2955};
2956static const unsigned int msiof2_ss2_d_pins[] = {
2957	/* SS2 */
2958	RCAR_GP_PIN(0, 13),
2959};
2960static const unsigned int msiof2_ss2_d_mux[] = {
2961	MSIOF2_SS2_D_MARK,
2962};
2963static const unsigned int msiof2_txd_d_pins[] = {
2964	/* TXD */
2965	RCAR_GP_PIN(0, 11),
2966};
2967static const unsigned int msiof2_txd_d_mux[] = {
2968	MSIOF2_TXD_D_MARK,
2969};
2970static const unsigned int msiof2_rxd_d_pins[] = {
2971	/* RXD */
2972	RCAR_GP_PIN(0, 10),
2973};
2974static const unsigned int msiof2_rxd_d_mux[] = {
2975	MSIOF2_RXD_D_MARK,
2976};
2977/* - MSIOF3 ----------------------------------------------------------------- */
2978static const unsigned int msiof3_clk_a_pins[] = {
2979	/* SCK */
2980	RCAR_GP_PIN(0, 0),
2981};
2982static const unsigned int msiof3_clk_a_mux[] = {
2983	MSIOF3_SCK_A_MARK,
2984};
2985static const unsigned int msiof3_sync_a_pins[] = {
2986	/* SYNC */
2987	RCAR_GP_PIN(0, 1),
2988};
2989static const unsigned int msiof3_sync_a_mux[] = {
2990	MSIOF3_SYNC_A_MARK,
2991};
2992static const unsigned int msiof3_ss1_a_pins[] = {
2993	/* SS1 */
2994	RCAR_GP_PIN(0, 14),
2995};
2996static const unsigned int msiof3_ss1_a_mux[] = {
2997	MSIOF3_SS1_A_MARK,
2998};
2999static const unsigned int msiof3_ss2_a_pins[] = {
3000	/* SS2 */
3001	RCAR_GP_PIN(0, 15),
3002};
3003static const unsigned int msiof3_ss2_a_mux[] = {
3004	MSIOF3_SS2_A_MARK,
3005};
3006static const unsigned int msiof3_txd_a_pins[] = {
3007	/* TXD */
3008	RCAR_GP_PIN(0, 3),
3009};
3010static const unsigned int msiof3_txd_a_mux[] = {
3011	MSIOF3_TXD_A_MARK,
3012};
3013static const unsigned int msiof3_rxd_a_pins[] = {
3014	/* RXD */
3015	RCAR_GP_PIN(0, 2),
3016};
3017static const unsigned int msiof3_rxd_a_mux[] = {
3018	MSIOF3_RXD_A_MARK,
3019};
3020static const unsigned int msiof3_clk_b_pins[] = {
3021	/* SCK */
3022	RCAR_GP_PIN(1, 2),
3023};
3024static const unsigned int msiof3_clk_b_mux[] = {
3025	MSIOF3_SCK_B_MARK,
3026};
3027static const unsigned int msiof3_sync_b_pins[] = {
3028	/* SYNC */
3029	RCAR_GP_PIN(1, 0),
3030};
3031static const unsigned int msiof3_sync_b_mux[] = {
3032	MSIOF3_SYNC_B_MARK,
3033};
3034static const unsigned int msiof3_ss1_b_pins[] = {
3035	/* SS1 */
3036	RCAR_GP_PIN(1, 4),
3037};
3038static const unsigned int msiof3_ss1_b_mux[] = {
3039	MSIOF3_SS1_B_MARK,
3040};
3041static const unsigned int msiof3_ss2_b_pins[] = {
3042	/* SS2 */
3043	RCAR_GP_PIN(1, 5),
3044};
3045static const unsigned int msiof3_ss2_b_mux[] = {
3046	MSIOF3_SS2_B_MARK,
3047};
3048static const unsigned int msiof3_txd_b_pins[] = {
3049	/* TXD */
3050	RCAR_GP_PIN(1, 1),
3051};
3052static const unsigned int msiof3_txd_b_mux[] = {
3053	MSIOF3_TXD_B_MARK,
3054};
3055static const unsigned int msiof3_rxd_b_pins[] = {
3056	/* RXD */
3057	RCAR_GP_PIN(1, 3),
3058};
3059static const unsigned int msiof3_rxd_b_mux[] = {
3060	MSIOF3_RXD_B_MARK,
3061};
3062static const unsigned int msiof3_clk_c_pins[] = {
3063	/* SCK */
3064	RCAR_GP_PIN(1, 12),
3065};
3066static const unsigned int msiof3_clk_c_mux[] = {
3067	MSIOF3_SCK_C_MARK,
3068};
3069static const unsigned int msiof3_sync_c_pins[] = {
3070	/* SYNC */
3071	RCAR_GP_PIN(1, 13),
3072};
3073static const unsigned int msiof3_sync_c_mux[] = {
3074	MSIOF3_SYNC_C_MARK,
3075};
3076static const unsigned int msiof3_txd_c_pins[] = {
3077	/* TXD */
3078	RCAR_GP_PIN(1, 15),
3079};
3080static const unsigned int msiof3_txd_c_mux[] = {
3081	MSIOF3_TXD_C_MARK,
3082};
3083static const unsigned int msiof3_rxd_c_pins[] = {
3084	/* RXD */
3085	RCAR_GP_PIN(1, 14),
3086};
3087static const unsigned int msiof3_rxd_c_mux[] = {
3088	MSIOF3_RXD_C_MARK,
3089};
3090static const unsigned int msiof3_clk_d_pins[] = {
3091	/* SCK */
3092	RCAR_GP_PIN(1, 22),
3093};
3094static const unsigned int msiof3_clk_d_mux[] = {
3095	MSIOF3_SCK_D_MARK,
3096};
3097static const unsigned int msiof3_sync_d_pins[] = {
3098	/* SYNC */
3099	RCAR_GP_PIN(1, 23),
3100};
3101static const unsigned int msiof3_sync_d_mux[] = {
3102	MSIOF3_SYNC_D_MARK,
3103};
3104static const unsigned int msiof3_ss1_d_pins[] = {
3105	/* SS1 */
3106	RCAR_GP_PIN(1, 26),
3107};
3108static const unsigned int msiof3_ss1_d_mux[] = {
3109	MSIOF3_SS1_D_MARK,
3110};
3111static const unsigned int msiof3_txd_d_pins[] = {
3112	/* TXD */
3113	RCAR_GP_PIN(1, 25),
3114};
3115static const unsigned int msiof3_txd_d_mux[] = {
3116	MSIOF3_TXD_D_MARK,
3117};
3118static const unsigned int msiof3_rxd_d_pins[] = {
3119	/* RXD */
3120	RCAR_GP_PIN(1, 24),
3121};
3122static const unsigned int msiof3_rxd_d_mux[] = {
3123	MSIOF3_RXD_D_MARK,
3124};
3125
3126static const unsigned int msiof3_clk_e_pins[] = {
3127	/* SCK */
3128	RCAR_GP_PIN(2, 3),
3129};
3130static const unsigned int msiof3_clk_e_mux[] = {
3131	MSIOF3_SCK_E_MARK,
3132};
3133static const unsigned int msiof3_sync_e_pins[] = {
3134	/* SYNC */
3135	RCAR_GP_PIN(2, 2),
3136};
3137static const unsigned int msiof3_sync_e_mux[] = {
3138	MSIOF3_SYNC_E_MARK,
3139};
3140static const unsigned int msiof3_ss1_e_pins[] = {
3141	/* SS1 */
3142	RCAR_GP_PIN(2, 1),
3143};
3144static const unsigned int msiof3_ss1_e_mux[] = {
3145	MSIOF3_SS1_E_MARK,
3146};
3147static const unsigned int msiof3_ss2_e_pins[] = {
3148	/* SS2 */
3149	RCAR_GP_PIN(2, 0),
3150};
3151static const unsigned int msiof3_ss2_e_mux[] = {
3152	MSIOF3_SS2_E_MARK,
3153};
3154static const unsigned int msiof3_txd_e_pins[] = {
3155	/* TXD */
3156	RCAR_GP_PIN(2, 5),
3157};
3158static const unsigned int msiof3_txd_e_mux[] = {
3159	MSIOF3_TXD_E_MARK,
3160};
3161static const unsigned int msiof3_rxd_e_pins[] = {
3162	/* RXD */
3163	RCAR_GP_PIN(2, 4),
3164};
3165static const unsigned int msiof3_rxd_e_mux[] = {
3166	MSIOF3_RXD_E_MARK,
3167};
3168
3169/* - PWM0 --------------------------------------------------------------------*/
3170static const unsigned int pwm0_pins[] = {
3171	/* PWM */
3172	RCAR_GP_PIN(2, 6),
3173};
3174static const unsigned int pwm0_mux[] = {
3175	PWM0_MARK,
3176};
3177/* - PWM1 --------------------------------------------------------------------*/
3178static const unsigned int pwm1_a_pins[] = {
3179	/* PWM */
3180	RCAR_GP_PIN(2, 7),
3181};
3182static const unsigned int pwm1_a_mux[] = {
3183	PWM1_A_MARK,
3184};
3185static const unsigned int pwm1_b_pins[] = {
3186	/* PWM */
3187	RCAR_GP_PIN(1, 8),
3188};
3189static const unsigned int pwm1_b_mux[] = {
3190	PWM1_B_MARK,
3191};
3192/* - PWM2 --------------------------------------------------------------------*/
3193static const unsigned int pwm2_a_pins[] = {
3194	/* PWM */
3195	RCAR_GP_PIN(2, 8),
3196};
3197static const unsigned int pwm2_a_mux[] = {
3198	PWM2_A_MARK,
3199};
3200static const unsigned int pwm2_b_pins[] = {
3201	/* PWM */
3202	RCAR_GP_PIN(1, 11),
3203};
3204static const unsigned int pwm2_b_mux[] = {
3205	PWM2_B_MARK,
3206};
3207/* - PWM3 --------------------------------------------------------------------*/
3208static const unsigned int pwm3_a_pins[] = {
3209	/* PWM */
3210	RCAR_GP_PIN(1, 0),
3211};
3212static const unsigned int pwm3_a_mux[] = {
3213	PWM3_A_MARK,
3214};
3215static const unsigned int pwm3_b_pins[] = {
3216	/* PWM */
3217	RCAR_GP_PIN(2, 2),
3218};
3219static const unsigned int pwm3_b_mux[] = {
3220	PWM3_B_MARK,
3221};
3222/* - PWM4 --------------------------------------------------------------------*/
3223static const unsigned int pwm4_a_pins[] = {
3224	/* PWM */
3225	RCAR_GP_PIN(1, 1),
3226};
3227static const unsigned int pwm4_a_mux[] = {
3228	PWM4_A_MARK,
3229};
3230static const unsigned int pwm4_b_pins[] = {
3231	/* PWM */
3232	RCAR_GP_PIN(2, 3),
3233};
3234static const unsigned int pwm4_b_mux[] = {
3235	PWM4_B_MARK,
3236};
3237/* - PWM5 --------------------------------------------------------------------*/
3238static const unsigned int pwm5_a_pins[] = {
3239	/* PWM */
3240	RCAR_GP_PIN(1, 2),
3241};
3242static const unsigned int pwm5_a_mux[] = {
3243	PWM5_A_MARK,
3244};
3245static const unsigned int pwm5_b_pins[] = {
3246	/* PWM */
3247	RCAR_GP_PIN(2, 4),
3248};
3249static const unsigned int pwm5_b_mux[] = {
3250	PWM5_B_MARK,
3251};
3252/* - PWM6 --------------------------------------------------------------------*/
3253static const unsigned int pwm6_a_pins[] = {
3254	/* PWM */
3255	RCAR_GP_PIN(1, 3),
3256};
3257static const unsigned int pwm6_a_mux[] = {
3258	PWM6_A_MARK,
3259};
3260static const unsigned int pwm6_b_pins[] = {
3261	/* PWM */
3262	RCAR_GP_PIN(2, 5),
3263};
3264static const unsigned int pwm6_b_mux[] = {
3265	PWM6_B_MARK,
3266};
3267
3268/* - QSPI0 ------------------------------------------------------------------ */
3269static const unsigned int qspi0_ctrl_pins[] = {
3270	/* QSPI0_SPCLK, QSPI0_SSL */
3271	PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3272};
3273static const unsigned int qspi0_ctrl_mux[] = {
3274	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3275};
3276static const unsigned int qspi0_data_pins[] = {
3277	/* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3278	PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3279	/* QSPI0_IO2, QSPI0_IO3 */
3280	PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3281};
3282static const unsigned int qspi0_data_mux[] = {
3283	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3284	QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3285};
3286/* - QSPI1 ------------------------------------------------------------------ */
3287static const unsigned int qspi1_ctrl_pins[] = {
3288	/* QSPI1_SPCLK, QSPI1_SSL */
3289	PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3290};
3291static const unsigned int qspi1_ctrl_mux[] = {
3292	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3293};
3294static const unsigned int qspi1_data_pins[] = {
3295	/* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3296	PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3297	/* QSPI1_IO2, QSPI1_IO3 */
3298	PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3299};
3300static const unsigned int qspi1_data_mux[] = {
3301	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3302	QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3303};
3304
3305/* - SCIF0 ------------------------------------------------------------------ */
3306static const unsigned int scif0_data_pins[] = {
3307	/* RX, TX */
3308	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3309};
3310static const unsigned int scif0_data_mux[] = {
3311	RX0_MARK, TX0_MARK,
3312};
3313static const unsigned int scif0_clk_pins[] = {
3314	/* SCK */
3315	RCAR_GP_PIN(5, 0),
3316};
3317static const unsigned int scif0_clk_mux[] = {
3318	SCK0_MARK,
3319};
3320static const unsigned int scif0_ctrl_pins[] = {
3321	/* RTS, CTS */
3322	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3323};
3324static const unsigned int scif0_ctrl_mux[] = {
3325	RTS0_N_MARK, CTS0_N_MARK,
3326};
3327/* - SCIF1 ------------------------------------------------------------------ */
3328static const unsigned int scif1_data_a_pins[] = {
3329	/* RX, TX */
3330	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3331};
3332static const unsigned int scif1_data_a_mux[] = {
3333	RX1_A_MARK, TX1_A_MARK,
3334};
3335static const unsigned int scif1_clk_pins[] = {
3336	/* SCK */
3337	RCAR_GP_PIN(6, 21),
3338};
3339static const unsigned int scif1_clk_mux[] = {
3340	SCK1_MARK,
3341};
3342static const unsigned int scif1_ctrl_pins[] = {
3343	/* RTS, CTS */
3344	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3345};
3346static const unsigned int scif1_ctrl_mux[] = {
3347	RTS1_N_MARK, CTS1_N_MARK,
3348};
3349
3350static const unsigned int scif1_data_b_pins[] = {
3351	/* RX, TX */
3352	RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3353};
3354static const unsigned int scif1_data_b_mux[] = {
3355	RX1_B_MARK, TX1_B_MARK,
3356};
3357/* - SCIF2 ------------------------------------------------------------------ */
3358static const unsigned int scif2_data_a_pins[] = {
3359	/* RX, TX */
3360	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3361};
3362static const unsigned int scif2_data_a_mux[] = {
3363	RX2_A_MARK, TX2_A_MARK,
3364};
3365static const unsigned int scif2_clk_pins[] = {
3366	/* SCK */
3367	RCAR_GP_PIN(5, 9),
3368};
3369static const unsigned int scif2_clk_mux[] = {
3370	SCK2_MARK,
3371};
3372static const unsigned int scif2_data_b_pins[] = {
3373	/* RX, TX */
3374	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3375};
3376static const unsigned int scif2_data_b_mux[] = {
3377	RX2_B_MARK, TX2_B_MARK,
3378};
3379/* - SCIF3 ------------------------------------------------------------------ */
3380static const unsigned int scif3_data_a_pins[] = {
3381	/* RX, TX */
3382	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3383};
3384static const unsigned int scif3_data_a_mux[] = {
3385	RX3_A_MARK, TX3_A_MARK,
3386};
3387static const unsigned int scif3_clk_pins[] = {
3388	/* SCK */
3389	RCAR_GP_PIN(1, 22),
3390};
3391static const unsigned int scif3_clk_mux[] = {
3392	SCK3_MARK,
3393};
3394static const unsigned int scif3_ctrl_pins[] = {
3395	/* RTS, CTS */
3396	RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3397};
3398static const unsigned int scif3_ctrl_mux[] = {
3399	RTS3_N_MARK, CTS3_N_MARK,
3400};
3401static const unsigned int scif3_data_b_pins[] = {
3402	/* RX, TX */
3403	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3404};
3405static const unsigned int scif3_data_b_mux[] = {
3406	RX3_B_MARK, TX3_B_MARK,
3407};
3408/* - SCIF4 ------------------------------------------------------------------ */
3409static const unsigned int scif4_data_a_pins[] = {
3410	/* RX, TX */
3411	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3412};
3413static const unsigned int scif4_data_a_mux[] = {
3414	RX4_A_MARK, TX4_A_MARK,
3415};
3416static const unsigned int scif4_clk_a_pins[] = {
3417	/* SCK */
3418	RCAR_GP_PIN(2, 10),
3419};
3420static const unsigned int scif4_clk_a_mux[] = {
3421	SCK4_A_MARK,
3422};
3423static const unsigned int scif4_ctrl_a_pins[] = {
3424	/* RTS, CTS */
3425	RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3426};
3427static const unsigned int scif4_ctrl_a_mux[] = {
3428	RTS4_N_A_MARK, CTS4_N_A_MARK,
3429};
3430static const unsigned int scif4_data_b_pins[] = {
3431	/* RX, TX */
3432	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3433};
3434static const unsigned int scif4_data_b_mux[] = {
3435	RX4_B_MARK, TX4_B_MARK,
3436};
3437static const unsigned int scif4_clk_b_pins[] = {
3438	/* SCK */
3439	RCAR_GP_PIN(1, 5),
3440};
3441static const unsigned int scif4_clk_b_mux[] = {
3442	SCK4_B_MARK,
3443};
3444static const unsigned int scif4_ctrl_b_pins[] = {
3445	/* RTS, CTS */
3446	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3447};
3448static const unsigned int scif4_ctrl_b_mux[] = {
3449	RTS4_N_B_MARK, CTS4_N_B_MARK,
3450};
3451static const unsigned int scif4_data_c_pins[] = {
3452	/* RX, TX */
3453	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3454};
3455static const unsigned int scif4_data_c_mux[] = {
3456	RX4_C_MARK, TX4_C_MARK,
3457};
3458static const unsigned int scif4_clk_c_pins[] = {
3459	/* SCK */
3460	RCAR_GP_PIN(0, 8),
3461};
3462static const unsigned int scif4_clk_c_mux[] = {
3463	SCK4_C_MARK,
3464};
3465static const unsigned int scif4_ctrl_c_pins[] = {
3466	/* RTS, CTS */
3467	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3468};
3469static const unsigned int scif4_ctrl_c_mux[] = {
3470	RTS4_N_C_MARK, CTS4_N_C_MARK,
3471};
3472/* - SCIF5 ------------------------------------------------------------------ */
3473static const unsigned int scif5_data_a_pins[] = {
3474	/* RX, TX */
3475	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3476};
3477static const unsigned int scif5_data_a_mux[] = {
3478	RX5_A_MARK, TX5_A_MARK,
3479};
3480static const unsigned int scif5_clk_a_pins[] = {
3481	/* SCK */
3482	RCAR_GP_PIN(6, 21),
3483};
3484static const unsigned int scif5_clk_a_mux[] = {
3485	SCK5_A_MARK,
3486};
3487
3488static const unsigned int scif5_data_b_pins[] = {
3489	/* RX, TX */
3490	RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3491};
3492static const unsigned int scif5_data_b_mux[] = {
3493	RX5_B_MARK, TX5_B_MARK,
3494};
3495static const unsigned int scif5_clk_b_pins[] = {
3496	/* SCK */
3497	RCAR_GP_PIN(5, 0),
3498};
3499static const unsigned int scif5_clk_b_mux[] = {
3500	SCK5_B_MARK,
3501};
3502
3503/* - SCIF Clock ------------------------------------------------------------- */
3504static const unsigned int scif_clk_a_pins[] = {
3505	/* SCIF_CLK */
3506	RCAR_GP_PIN(6, 23),
3507};
3508static const unsigned int scif_clk_a_mux[] = {
3509	SCIF_CLK_A_MARK,
3510};
3511static const unsigned int scif_clk_b_pins[] = {
3512	/* SCIF_CLK */
3513	RCAR_GP_PIN(5, 9),
3514};
3515static const unsigned int scif_clk_b_mux[] = {
3516	SCIF_CLK_B_MARK,
3517};
3518
3519/* - SDHI0 ------------------------------------------------------------------ */
3520static const unsigned int sdhi0_data_pins[] = {
3521	/* D[0:3] */
3522	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3523	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3524};
3525static const unsigned int sdhi0_data_mux[] = {
3526	SD0_DAT0_MARK, SD0_DAT1_MARK,
3527	SD0_DAT2_MARK, SD0_DAT3_MARK,
3528};
3529static const unsigned int sdhi0_ctrl_pins[] = {
3530	/* CLK, CMD */
3531	RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3532};
3533static const unsigned int sdhi0_ctrl_mux[] = {
3534	SD0_CLK_MARK, SD0_CMD_MARK,
3535};
3536static const unsigned int sdhi0_cd_pins[] = {
3537	/* CD */
3538	RCAR_GP_PIN(3, 12),
3539};
3540static const unsigned int sdhi0_cd_mux[] = {
3541	SD0_CD_MARK,
3542};
3543static const unsigned int sdhi0_wp_pins[] = {
3544	/* WP */
3545	RCAR_GP_PIN(3, 13),
3546};
3547static const unsigned int sdhi0_wp_mux[] = {
3548	SD0_WP_MARK,
3549};
3550/* - SDHI1 ------------------------------------------------------------------ */
3551static const unsigned int sdhi1_data_pins[] = {
3552	/* D[0:3] */
3553	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3554	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3555};
3556static const unsigned int sdhi1_data_mux[] = {
3557	SD1_DAT0_MARK, SD1_DAT1_MARK,
3558	SD1_DAT2_MARK, SD1_DAT3_MARK,
3559};
3560static const unsigned int sdhi1_ctrl_pins[] = {
3561	/* CLK, CMD */
3562	RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3563};
3564static const unsigned int sdhi1_ctrl_mux[] = {
3565	SD1_CLK_MARK, SD1_CMD_MARK,
3566};
3567static const unsigned int sdhi1_cd_pins[] = {
3568	/* CD */
3569	RCAR_GP_PIN(3, 14),
3570};
3571static const unsigned int sdhi1_cd_mux[] = {
3572	SD1_CD_MARK,
3573};
3574static const unsigned int sdhi1_wp_pins[] = {
3575	/* WP */
3576	RCAR_GP_PIN(3, 15),
3577};
3578static const unsigned int sdhi1_wp_mux[] = {
3579	SD1_WP_MARK,
3580};
3581/* - SDHI2 ------------------------------------------------------------------ */
3582static const unsigned int sdhi2_data_pins[] = {
3583	/* D[0:7] */
3584	RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3585	RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3586	RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3587	RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3588};
3589static const unsigned int sdhi2_data_mux[] = {
3590	SD2_DAT0_MARK, SD2_DAT1_MARK,
3591	SD2_DAT2_MARK, SD2_DAT3_MARK,
3592	SD2_DAT4_MARK, SD2_DAT5_MARK,
3593	SD2_DAT6_MARK, SD2_DAT7_MARK,
3594};
3595static const unsigned int sdhi2_ctrl_pins[] = {
3596	/* CLK, CMD */
3597	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3598};
3599static const unsigned int sdhi2_ctrl_mux[] = {
3600	SD2_CLK_MARK, SD2_CMD_MARK,
3601};
3602static const unsigned int sdhi2_cd_a_pins[] = {
3603	/* CD */
3604	RCAR_GP_PIN(4, 13),
3605};
3606static const unsigned int sdhi2_cd_a_mux[] = {
3607	SD2_CD_A_MARK,
3608};
3609static const unsigned int sdhi2_cd_b_pins[] = {
3610	/* CD */
3611	RCAR_GP_PIN(5, 10),
3612};
3613static const unsigned int sdhi2_cd_b_mux[] = {
3614	SD2_CD_B_MARK,
3615};
3616static const unsigned int sdhi2_wp_a_pins[] = {
3617	/* WP */
3618	RCAR_GP_PIN(4, 14),
3619};
3620static const unsigned int sdhi2_wp_a_mux[] = {
3621	SD2_WP_A_MARK,
3622};
3623static const unsigned int sdhi2_wp_b_pins[] = {
3624	/* WP */
3625	RCAR_GP_PIN(5, 11),
3626};
3627static const unsigned int sdhi2_wp_b_mux[] = {
3628	SD2_WP_B_MARK,
3629};
3630static const unsigned int sdhi2_ds_pins[] = {
3631	/* DS */
3632	RCAR_GP_PIN(4, 6),
3633};
3634static const unsigned int sdhi2_ds_mux[] = {
3635	SD2_DS_MARK,
3636};
3637/* - SDHI3 ------------------------------------------------------------------ */
3638static const unsigned int sdhi3_data_pins[] = {
3639	/* D[0:7] */
3640	RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3641	RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3642	RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3643	RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3644};
3645static const unsigned int sdhi3_data_mux[] = {
3646	SD3_DAT0_MARK, SD3_DAT1_MARK,
3647	SD3_DAT2_MARK, SD3_DAT3_MARK,
3648	SD3_DAT4_MARK, SD3_DAT5_MARK,
3649	SD3_DAT6_MARK, SD3_DAT7_MARK,
3650};
3651static const unsigned int sdhi3_ctrl_pins[] = {
3652	/* CLK, CMD */
3653	RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3654};
3655static const unsigned int sdhi3_ctrl_mux[] = {
3656	SD3_CLK_MARK, SD3_CMD_MARK,
3657};
3658static const unsigned int sdhi3_cd_pins[] = {
3659	/* CD */
3660	RCAR_GP_PIN(4, 15),
3661};
3662static const unsigned int sdhi3_cd_mux[] = {
3663	SD3_CD_MARK,
3664};
3665static const unsigned int sdhi3_wp_pins[] = {
3666	/* WP */
3667	RCAR_GP_PIN(4, 16),
3668};
3669static const unsigned int sdhi3_wp_mux[] = {
3670	SD3_WP_MARK,
3671};
3672static const unsigned int sdhi3_ds_pins[] = {
3673	/* DS */
3674	RCAR_GP_PIN(4, 17),
3675};
3676static const unsigned int sdhi3_ds_mux[] = {
3677	SD3_DS_MARK,
3678};
3679
3680/* - SSI -------------------------------------------------------------------- */
3681static const unsigned int ssi0_data_pins[] = {
3682	/* SDATA */
3683	RCAR_GP_PIN(6, 2),
3684};
3685static const unsigned int ssi0_data_mux[] = {
3686	SSI_SDATA0_MARK,
3687};
3688static const unsigned int ssi01239_ctrl_pins[] = {
3689	/* SCK, WS */
3690	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3691};
3692static const unsigned int ssi01239_ctrl_mux[] = {
3693	SSI_SCK01239_MARK, SSI_WS01239_MARK,
3694};
3695static const unsigned int ssi1_data_a_pins[] = {
3696	/* SDATA */
3697	RCAR_GP_PIN(6, 3),
3698};
3699static const unsigned int ssi1_data_a_mux[] = {
3700	SSI_SDATA1_A_MARK,
3701};
3702static const unsigned int ssi1_data_b_pins[] = {
3703	/* SDATA */
3704	RCAR_GP_PIN(5, 12),
3705};
3706static const unsigned int ssi1_data_b_mux[] = {
3707	SSI_SDATA1_B_MARK,
3708};
3709static const unsigned int ssi1_ctrl_a_pins[] = {
3710	/* SCK, WS */
3711	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3712};
3713static const unsigned int ssi1_ctrl_a_mux[] = {
3714	SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3715};
3716static const unsigned int ssi1_ctrl_b_pins[] = {
3717	/* SCK, WS */
3718	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3719};
3720static const unsigned int ssi1_ctrl_b_mux[] = {
3721	SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3722};
3723static const unsigned int ssi2_data_a_pins[] = {
3724	/* SDATA */
3725	RCAR_GP_PIN(6, 4),
3726};
3727static const unsigned int ssi2_data_a_mux[] = {
3728	SSI_SDATA2_A_MARK,
3729};
3730static const unsigned int ssi2_data_b_pins[] = {
3731	/* SDATA */
3732	RCAR_GP_PIN(5, 13),
3733};
3734static const unsigned int ssi2_data_b_mux[] = {
3735	SSI_SDATA2_B_MARK,
3736};
3737static const unsigned int ssi2_ctrl_a_pins[] = {
3738	/* SCK, WS */
3739	RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3740};
3741static const unsigned int ssi2_ctrl_a_mux[] = {
3742	SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3743};
3744static const unsigned int ssi2_ctrl_b_pins[] = {
3745	/* SCK, WS */
3746	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3747};
3748static const unsigned int ssi2_ctrl_b_mux[] = {
3749	SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3750};
3751static const unsigned int ssi3_data_pins[] = {
3752	/* SDATA */
3753	RCAR_GP_PIN(6, 7),
3754};
3755static const unsigned int ssi3_data_mux[] = {
3756	SSI_SDATA3_MARK,
3757};
3758static const unsigned int ssi349_ctrl_pins[] = {
3759	/* SCK, WS */
3760	RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3761};
3762static const unsigned int ssi349_ctrl_mux[] = {
3763	SSI_SCK349_MARK, SSI_WS349_MARK,
3764};
3765static const unsigned int ssi4_data_pins[] = {
3766	/* SDATA */
3767	RCAR_GP_PIN(6, 10),
3768};
3769static const unsigned int ssi4_data_mux[] = {
3770	SSI_SDATA4_MARK,
3771};
3772static const unsigned int ssi4_ctrl_pins[] = {
3773	/* SCK, WS */
3774	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3775};
3776static const unsigned int ssi4_ctrl_mux[] = {
3777	SSI_SCK4_MARK, SSI_WS4_MARK,
3778};
3779static const unsigned int ssi5_data_pins[] = {
3780	/* SDATA */
3781	RCAR_GP_PIN(6, 13),
3782};
3783static const unsigned int ssi5_data_mux[] = {
3784	SSI_SDATA5_MARK,
3785};
3786static const unsigned int ssi5_ctrl_pins[] = {
3787	/* SCK, WS */
3788	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3789};
3790static const unsigned int ssi5_ctrl_mux[] = {
3791	SSI_SCK5_MARK, SSI_WS5_MARK,
3792};
3793static const unsigned int ssi6_data_pins[] = {
3794	/* SDATA */
3795	RCAR_GP_PIN(6, 16),
3796};
3797static const unsigned int ssi6_data_mux[] = {
3798	SSI_SDATA6_MARK,
3799};
3800static const unsigned int ssi6_ctrl_pins[] = {
3801	/* SCK, WS */
3802	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3803};
3804static const unsigned int ssi6_ctrl_mux[] = {
3805	SSI_SCK6_MARK, SSI_WS6_MARK,
3806};
3807static const unsigned int ssi7_data_pins[] = {
3808	/* SDATA */
3809	RCAR_GP_PIN(6, 19),
3810};
3811static const unsigned int ssi7_data_mux[] = {
3812	SSI_SDATA7_MARK,
3813};
3814static const unsigned int ssi78_ctrl_pins[] = {
3815	/* SCK, WS */
3816	RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3817};
3818static const unsigned int ssi78_ctrl_mux[] = {
3819	SSI_SCK78_MARK, SSI_WS78_MARK,
3820};
3821static const unsigned int ssi8_data_pins[] = {
3822	/* SDATA */
3823	RCAR_GP_PIN(6, 20),
3824};
3825static const unsigned int ssi8_data_mux[] = {
3826	SSI_SDATA8_MARK,
3827};
3828static const unsigned int ssi9_data_a_pins[] = {
3829	/* SDATA */
3830	RCAR_GP_PIN(6, 21),
3831};
3832static const unsigned int ssi9_data_a_mux[] = {
3833	SSI_SDATA9_A_MARK,
3834};
3835static const unsigned int ssi9_data_b_pins[] = {
3836	/* SDATA */
3837	RCAR_GP_PIN(5, 14),
3838};
3839static const unsigned int ssi9_data_b_mux[] = {
3840	SSI_SDATA9_B_MARK,
3841};
3842static const unsigned int ssi9_ctrl_a_pins[] = {
3843	/* SCK, WS */
3844	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3845};
3846static const unsigned int ssi9_ctrl_a_mux[] = {
3847	SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3848};
3849static const unsigned int ssi9_ctrl_b_pins[] = {
3850	/* SCK, WS */
3851	RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3852};
3853static const unsigned int ssi9_ctrl_b_mux[] = {
3854	SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3855};
3856
3857/* - TMU -------------------------------------------------------------------- */
3858static const unsigned int tmu_tclk1_a_pins[] = {
3859	/* TCLK */
3860	RCAR_GP_PIN(6, 23),
3861};
3862static const unsigned int tmu_tclk1_a_mux[] = {
3863	TCLK1_A_MARK,
3864};
3865static const unsigned int tmu_tclk1_b_pins[] = {
3866	/* TCLK */
3867	RCAR_GP_PIN(5, 19),
3868};
3869static const unsigned int tmu_tclk1_b_mux[] = {
3870	TCLK1_B_MARK,
3871};
3872static const unsigned int tmu_tclk2_a_pins[] = {
3873	/* TCLK */
3874	RCAR_GP_PIN(6, 19),
3875};
3876static const unsigned int tmu_tclk2_a_mux[] = {
3877	TCLK2_A_MARK,
3878};
3879static const unsigned int tmu_tclk2_b_pins[] = {
3880	/* TCLK */
3881	RCAR_GP_PIN(6, 28),
3882};
3883static const unsigned int tmu_tclk2_b_mux[] = {
3884	TCLK2_B_MARK,
3885};
3886
3887/* - TPU ------------------------------------------------------------------- */
3888static const unsigned int tpu_to0_pins[] = {
3889	/* TPU0TO0 */
3890	RCAR_GP_PIN(6, 28),
3891};
3892static const unsigned int tpu_to0_mux[] = {
3893	TPU0TO0_MARK,
3894};
3895static const unsigned int tpu_to1_pins[] = {
3896	/* TPU0TO1 */
3897	RCAR_GP_PIN(6, 29),
3898};
3899static const unsigned int tpu_to1_mux[] = {
3900	TPU0TO1_MARK,
3901};
3902static const unsigned int tpu_to2_pins[] = {
3903	/* TPU0TO2 */
3904	RCAR_GP_PIN(6, 30),
3905};
3906static const unsigned int tpu_to2_mux[] = {
3907	TPU0TO2_MARK,
3908};
3909static const unsigned int tpu_to3_pins[] = {
3910	/* TPU0TO3 */
3911	RCAR_GP_PIN(6, 31),
3912};
3913static const unsigned int tpu_to3_mux[] = {
3914	TPU0TO3_MARK,
3915};
3916
3917/* - USB0 ------------------------------------------------------------------- */
3918static const unsigned int usb0_pins[] = {
3919	/* PWEN, OVC */
3920	RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3921};
3922static const unsigned int usb0_mux[] = {
3923	USB0_PWEN_MARK, USB0_OVC_MARK,
3924};
3925/* - USB1 ------------------------------------------------------------------- */
3926static const unsigned int usb1_pins[] = {
3927	/* PWEN, OVC */
3928	RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3929};
3930static const unsigned int usb1_mux[] = {
3931	USB1_PWEN_MARK, USB1_OVC_MARK,
3932};
3933
3934/* - USB30 ------------------------------------------------------------------ */
3935static const unsigned int usb30_pins[] = {
3936	/* PWEN, OVC */
3937	RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3938};
3939static const unsigned int usb30_mux[] = {
3940	USB30_PWEN_MARK, USB30_OVC_MARK,
3941};
3942
3943/* - VIN4 ------------------------------------------------------------------- */
3944static const unsigned int vin4_data18_a_pins[] = {
3945	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3946	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3947	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3948	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3949	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3950	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3951	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3952	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3953	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3954};
3955static const unsigned int vin4_data18_a_mux[] = {
3956	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3957	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3958	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3959	VI4_DATA10_MARK, VI4_DATA11_MARK,
3960	VI4_DATA12_MARK, VI4_DATA13_MARK,
3961	VI4_DATA14_MARK, VI4_DATA15_MARK,
3962	VI4_DATA18_MARK, VI4_DATA19_MARK,
3963	VI4_DATA20_MARK, VI4_DATA21_MARK,
3964	VI4_DATA22_MARK, VI4_DATA23_MARK,
3965};
3966static const unsigned int vin4_data18_b_pins[] = {
3967	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3968	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3969	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3970	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3971	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3972	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3973	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3974	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3975	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3976};
3977static const unsigned int vin4_data18_b_mux[] = {
3978	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3979	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3980	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3981	VI4_DATA10_MARK, VI4_DATA11_MARK,
3982	VI4_DATA12_MARK, VI4_DATA13_MARK,
3983	VI4_DATA14_MARK, VI4_DATA15_MARK,
3984	VI4_DATA18_MARK, VI4_DATA19_MARK,
3985	VI4_DATA20_MARK, VI4_DATA21_MARK,
3986	VI4_DATA22_MARK, VI4_DATA23_MARK,
3987};
3988static const unsigned int vin4_data_a_pins[] = {
3989	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3990	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3991	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3992	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3993	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3994	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3995	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3996	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3997	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3998	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3999	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4000	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4001};
4002static const unsigned int vin4_data_a_mux[] = {
4003	VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4004	VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4005	VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4006	VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4007	VI4_DATA8_MARK,  VI4_DATA9_MARK,
4008	VI4_DATA10_MARK, VI4_DATA11_MARK,
4009	VI4_DATA12_MARK, VI4_DATA13_MARK,
4010	VI4_DATA14_MARK, VI4_DATA15_MARK,
4011	VI4_DATA16_MARK, VI4_DATA17_MARK,
4012	VI4_DATA18_MARK, VI4_DATA19_MARK,
4013	VI4_DATA20_MARK, VI4_DATA21_MARK,
4014	VI4_DATA22_MARK, VI4_DATA23_MARK,
4015};
4016static const unsigned int vin4_data_b_pins[] = {
4017	RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4018	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4019	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4020	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4021	RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4022	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4023	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4024	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4025	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4026	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4027	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4028	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4029};
4030static const unsigned int vin4_data_b_mux[] = {
4031	VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4032	VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4033	VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4034	VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4035	VI4_DATA8_MARK,  VI4_DATA9_MARK,
4036	VI4_DATA10_MARK, VI4_DATA11_MARK,
4037	VI4_DATA12_MARK, VI4_DATA13_MARK,
4038	VI4_DATA14_MARK, VI4_DATA15_MARK,
4039	VI4_DATA16_MARK, VI4_DATA17_MARK,
4040	VI4_DATA18_MARK, VI4_DATA19_MARK,
4041	VI4_DATA20_MARK, VI4_DATA21_MARK,
4042	VI4_DATA22_MARK, VI4_DATA23_MARK,
4043};
4044static const unsigned int vin4_sync_pins[] = {
4045	/* HSYNC#, VSYNC# */
4046	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4047};
4048static const unsigned int vin4_sync_mux[] = {
4049	VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4050};
4051static const unsigned int vin4_field_pins[] = {
4052	/* FIELD */
4053	RCAR_GP_PIN(1, 16),
4054};
4055static const unsigned int vin4_field_mux[] = {
4056	VI4_FIELD_MARK,
4057};
4058static const unsigned int vin4_clkenb_pins[] = {
4059	/* CLKENB */
4060	RCAR_GP_PIN(1, 19),
4061};
4062static const unsigned int vin4_clkenb_mux[] = {
4063	VI4_CLKENB_MARK,
4064};
4065static const unsigned int vin4_clk_pins[] = {
4066	/* CLK */
4067	RCAR_GP_PIN(1, 27),
4068};
4069static const unsigned int vin4_clk_mux[] = {
4070	VI4_CLK_MARK,
4071};
4072
4073/* - VIN5 ------------------------------------------------------------------- */
4074static const unsigned int vin5_data_pins[] = {
4075	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4076	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4077	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4078	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4079	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4080	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4081	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4082	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4083};
4084static const unsigned int vin5_data_mux[] = {
4085	VI5_DATA0_MARK, VI5_DATA1_MARK,
4086	VI5_DATA2_MARK, VI5_DATA3_MARK,
4087	VI5_DATA4_MARK, VI5_DATA5_MARK,
4088	VI5_DATA6_MARK, VI5_DATA7_MARK,
4089	VI5_DATA8_MARK,  VI5_DATA9_MARK,
4090	VI5_DATA10_MARK, VI5_DATA11_MARK,
4091	VI5_DATA12_MARK, VI5_DATA13_MARK,
4092	VI5_DATA14_MARK, VI5_DATA15_MARK,
4093};
4094static const unsigned int vin5_sync_pins[] = {
4095	/* HSYNC#, VSYNC# */
4096	RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4097};
4098static const unsigned int vin5_sync_mux[] = {
4099	VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4100};
4101static const unsigned int vin5_field_pins[] = {
4102	RCAR_GP_PIN(1, 11),
4103};
4104static const unsigned int vin5_field_mux[] = {
4105	/* FIELD */
4106	VI5_FIELD_MARK,
4107};
4108static const unsigned int vin5_clkenb_pins[] = {
4109	RCAR_GP_PIN(1, 20),
4110};
4111static const unsigned int vin5_clkenb_mux[] = {
4112	/* CLKENB */
4113	VI5_CLKENB_MARK,
4114};
4115static const unsigned int vin5_clk_pins[] = {
4116	RCAR_GP_PIN(1, 21),
4117};
4118static const unsigned int vin5_clk_mux[] = {
4119	/* CLK */
4120	VI5_CLK_MARK,
4121};
4122
4123static const struct {
4124	struct sh_pfc_pin_group common[324];
4125#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4126	struct sh_pfc_pin_group automotive[31];
4127#endif
4128} pinmux_groups = {
4129	.common = {
4130		SH_PFC_PIN_GROUP(audio_clk_a_a),
4131		SH_PFC_PIN_GROUP(audio_clk_a_b),
4132		SH_PFC_PIN_GROUP(audio_clk_a_c),
4133		SH_PFC_PIN_GROUP(audio_clk_b_a),
4134		SH_PFC_PIN_GROUP(audio_clk_b_b),
4135		SH_PFC_PIN_GROUP(audio_clk_c_a),
4136		SH_PFC_PIN_GROUP(audio_clk_c_b),
4137		SH_PFC_PIN_GROUP(audio_clkout_a),
4138		SH_PFC_PIN_GROUP(audio_clkout_b),
4139		SH_PFC_PIN_GROUP(audio_clkout_c),
4140		SH_PFC_PIN_GROUP(audio_clkout_d),
4141		SH_PFC_PIN_GROUP(audio_clkout1_a),
4142		SH_PFC_PIN_GROUP(audio_clkout1_b),
4143		SH_PFC_PIN_GROUP(audio_clkout2_a),
4144		SH_PFC_PIN_GROUP(audio_clkout2_b),
4145		SH_PFC_PIN_GROUP(audio_clkout3_a),
4146		SH_PFC_PIN_GROUP(audio_clkout3_b),
4147		SH_PFC_PIN_GROUP(avb_link),
4148		SH_PFC_PIN_GROUP(avb_magic),
4149		SH_PFC_PIN_GROUP(avb_phy_int),
4150		SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),	/* Deprecated */
4151		SH_PFC_PIN_GROUP(avb_mdio),
4152		SH_PFC_PIN_GROUP(avb_mii),
4153		SH_PFC_PIN_GROUP(avb_avtp_pps),
4154		SH_PFC_PIN_GROUP(avb_avtp_match_a),
4155		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4156		SH_PFC_PIN_GROUP(avb_avtp_match_b),
4157		SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4158		SH_PFC_PIN_GROUP(can0_data_a),
4159		SH_PFC_PIN_GROUP(can0_data_b),
4160		SH_PFC_PIN_GROUP(can1_data),
4161		SH_PFC_PIN_GROUP(can_clk),
4162		SH_PFC_PIN_GROUP(canfd0_data_a),
4163		SH_PFC_PIN_GROUP(canfd0_data_b),
4164		SH_PFC_PIN_GROUP(canfd1_data),
4165		SH_PFC_PIN_GROUP(du_rgb666),
4166		SH_PFC_PIN_GROUP(du_rgb888),
4167		SH_PFC_PIN_GROUP(du_clk_out_0),
4168		SH_PFC_PIN_GROUP(du_clk_out_1),
4169		SH_PFC_PIN_GROUP(du_sync),
4170		SH_PFC_PIN_GROUP(du_oddf),
4171		SH_PFC_PIN_GROUP(du_cde),
4172		SH_PFC_PIN_GROUP(du_disp),
4173		SH_PFC_PIN_GROUP(hscif0_data),
4174		SH_PFC_PIN_GROUP(hscif0_clk),
4175		SH_PFC_PIN_GROUP(hscif0_ctrl),
4176		SH_PFC_PIN_GROUP(hscif1_data_a),
4177		SH_PFC_PIN_GROUP(hscif1_clk_a),
4178		SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4179		SH_PFC_PIN_GROUP(hscif1_data_b),
4180		SH_PFC_PIN_GROUP(hscif1_clk_b),
4181		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4182		SH_PFC_PIN_GROUP(hscif2_data_a),
4183		SH_PFC_PIN_GROUP(hscif2_clk_a),
4184		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4185		SH_PFC_PIN_GROUP(hscif2_data_b),
4186		SH_PFC_PIN_GROUP(hscif2_clk_b),
4187		SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4188		SH_PFC_PIN_GROUP(hscif2_data_c),
4189		SH_PFC_PIN_GROUP(hscif2_clk_c),
4190		SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4191		SH_PFC_PIN_GROUP(hscif3_data_a),
4192		SH_PFC_PIN_GROUP(hscif3_clk),
4193		SH_PFC_PIN_GROUP(hscif3_ctrl),
4194		SH_PFC_PIN_GROUP(hscif3_data_b),
4195		SH_PFC_PIN_GROUP(hscif3_data_c),
4196		SH_PFC_PIN_GROUP(hscif3_data_d),
4197		SH_PFC_PIN_GROUP(hscif4_data_a),
4198		SH_PFC_PIN_GROUP(hscif4_clk),
4199		SH_PFC_PIN_GROUP(hscif4_ctrl),
4200		SH_PFC_PIN_GROUP(hscif4_data_b),
4201		SH_PFC_PIN_GROUP(i2c0),
4202		SH_PFC_PIN_GROUP(i2c1_a),
4203		SH_PFC_PIN_GROUP(i2c1_b),
4204		SH_PFC_PIN_GROUP(i2c2_a),
4205		SH_PFC_PIN_GROUP(i2c2_b),
4206		SH_PFC_PIN_GROUP(i2c3),
4207		SH_PFC_PIN_GROUP(i2c5),
4208		SH_PFC_PIN_GROUP(i2c6_a),
4209		SH_PFC_PIN_GROUP(i2c6_b),
4210		SH_PFC_PIN_GROUP(i2c6_c),
4211		SH_PFC_PIN_GROUP(intc_ex_irq0),
4212		SH_PFC_PIN_GROUP(intc_ex_irq1),
4213		SH_PFC_PIN_GROUP(intc_ex_irq2),
4214		SH_PFC_PIN_GROUP(intc_ex_irq3),
4215		SH_PFC_PIN_GROUP(intc_ex_irq4),
4216		SH_PFC_PIN_GROUP(intc_ex_irq5),
4217		SH_PFC_PIN_GROUP(msiof0_clk),
4218		SH_PFC_PIN_GROUP(msiof0_sync),
4219		SH_PFC_PIN_GROUP(msiof0_ss1),
4220		SH_PFC_PIN_GROUP(msiof0_ss2),
4221		SH_PFC_PIN_GROUP(msiof0_txd),
4222		SH_PFC_PIN_GROUP(msiof0_rxd),
4223		SH_PFC_PIN_GROUP(msiof1_clk_a),
4224		SH_PFC_PIN_GROUP(msiof1_sync_a),
4225		SH_PFC_PIN_GROUP(msiof1_ss1_a),
4226		SH_PFC_PIN_GROUP(msiof1_ss2_a),
4227		SH_PFC_PIN_GROUP(msiof1_txd_a),
4228		SH_PFC_PIN_GROUP(msiof1_rxd_a),
4229		SH_PFC_PIN_GROUP(msiof1_clk_b),
4230		SH_PFC_PIN_GROUP(msiof1_sync_b),
4231		SH_PFC_PIN_GROUP(msiof1_ss1_b),
4232		SH_PFC_PIN_GROUP(msiof1_ss2_b),
4233		SH_PFC_PIN_GROUP(msiof1_txd_b),
4234		SH_PFC_PIN_GROUP(msiof1_rxd_b),
4235		SH_PFC_PIN_GROUP(msiof1_clk_c),
4236		SH_PFC_PIN_GROUP(msiof1_sync_c),
4237		SH_PFC_PIN_GROUP(msiof1_ss1_c),
4238		SH_PFC_PIN_GROUP(msiof1_ss2_c),
4239		SH_PFC_PIN_GROUP(msiof1_txd_c),
4240		SH_PFC_PIN_GROUP(msiof1_rxd_c),
4241		SH_PFC_PIN_GROUP(msiof1_clk_d),
4242		SH_PFC_PIN_GROUP(msiof1_sync_d),
4243		SH_PFC_PIN_GROUP(msiof1_ss1_d),
4244		SH_PFC_PIN_GROUP(msiof1_ss2_d),
4245		SH_PFC_PIN_GROUP(msiof1_txd_d),
4246		SH_PFC_PIN_GROUP(msiof1_rxd_d),
4247		SH_PFC_PIN_GROUP(msiof1_clk_e),
4248		SH_PFC_PIN_GROUP(msiof1_sync_e),
4249		SH_PFC_PIN_GROUP(msiof1_ss1_e),
4250		SH_PFC_PIN_GROUP(msiof1_ss2_e),
4251		SH_PFC_PIN_GROUP(msiof1_txd_e),
4252		SH_PFC_PIN_GROUP(msiof1_rxd_e),
4253		SH_PFC_PIN_GROUP(msiof1_clk_f),
4254		SH_PFC_PIN_GROUP(msiof1_sync_f),
4255		SH_PFC_PIN_GROUP(msiof1_ss1_f),
4256		SH_PFC_PIN_GROUP(msiof1_ss2_f),
4257		SH_PFC_PIN_GROUP(msiof1_txd_f),
4258		SH_PFC_PIN_GROUP(msiof1_rxd_f),
4259		SH_PFC_PIN_GROUP(msiof1_clk_g),
4260		SH_PFC_PIN_GROUP(msiof1_sync_g),
4261		SH_PFC_PIN_GROUP(msiof1_ss1_g),
4262		SH_PFC_PIN_GROUP(msiof1_ss2_g),
4263		SH_PFC_PIN_GROUP(msiof1_txd_g),
4264		SH_PFC_PIN_GROUP(msiof1_rxd_g),
4265		SH_PFC_PIN_GROUP(msiof2_clk_a),
4266		SH_PFC_PIN_GROUP(msiof2_sync_a),
4267		SH_PFC_PIN_GROUP(msiof2_ss1_a),
4268		SH_PFC_PIN_GROUP(msiof2_ss2_a),
4269		SH_PFC_PIN_GROUP(msiof2_txd_a),
4270		SH_PFC_PIN_GROUP(msiof2_rxd_a),
4271		SH_PFC_PIN_GROUP(msiof2_clk_b),
4272		SH_PFC_PIN_GROUP(msiof2_sync_b),
4273		SH_PFC_PIN_GROUP(msiof2_ss1_b),
4274		SH_PFC_PIN_GROUP(msiof2_ss2_b),
4275		SH_PFC_PIN_GROUP(msiof2_txd_b),
4276		SH_PFC_PIN_GROUP(msiof2_rxd_b),
4277		SH_PFC_PIN_GROUP(msiof2_clk_c),
4278		SH_PFC_PIN_GROUP(msiof2_sync_c),
4279		SH_PFC_PIN_GROUP(msiof2_ss1_c),
4280		SH_PFC_PIN_GROUP(msiof2_ss2_c),
4281		SH_PFC_PIN_GROUP(msiof2_txd_c),
4282		SH_PFC_PIN_GROUP(msiof2_rxd_c),
4283		SH_PFC_PIN_GROUP(msiof2_clk_d),
4284		SH_PFC_PIN_GROUP(msiof2_sync_d),
4285		SH_PFC_PIN_GROUP(msiof2_ss1_d),
4286		SH_PFC_PIN_GROUP(msiof2_ss2_d),
4287		SH_PFC_PIN_GROUP(msiof2_txd_d),
4288		SH_PFC_PIN_GROUP(msiof2_rxd_d),
4289		SH_PFC_PIN_GROUP(msiof3_clk_a),
4290		SH_PFC_PIN_GROUP(msiof3_sync_a),
4291		SH_PFC_PIN_GROUP(msiof3_ss1_a),
4292		SH_PFC_PIN_GROUP(msiof3_ss2_a),
4293		SH_PFC_PIN_GROUP(msiof3_txd_a),
4294		SH_PFC_PIN_GROUP(msiof3_rxd_a),
4295		SH_PFC_PIN_GROUP(msiof3_clk_b),
4296		SH_PFC_PIN_GROUP(msiof3_sync_b),
4297		SH_PFC_PIN_GROUP(msiof3_ss1_b),
4298		SH_PFC_PIN_GROUP(msiof3_ss2_b),
4299		SH_PFC_PIN_GROUP(msiof3_txd_b),
4300		SH_PFC_PIN_GROUP(msiof3_rxd_b),
4301		SH_PFC_PIN_GROUP(msiof3_clk_c),
4302		SH_PFC_PIN_GROUP(msiof3_sync_c),
4303		SH_PFC_PIN_GROUP(msiof3_txd_c),
4304		SH_PFC_PIN_GROUP(msiof3_rxd_c),
4305		SH_PFC_PIN_GROUP(msiof3_clk_d),
4306		SH_PFC_PIN_GROUP(msiof3_sync_d),
4307		SH_PFC_PIN_GROUP(msiof3_ss1_d),
4308		SH_PFC_PIN_GROUP(msiof3_txd_d),
4309		SH_PFC_PIN_GROUP(msiof3_rxd_d),
4310		SH_PFC_PIN_GROUP(msiof3_clk_e),
4311		SH_PFC_PIN_GROUP(msiof3_sync_e),
4312		SH_PFC_PIN_GROUP(msiof3_ss1_e),
4313		SH_PFC_PIN_GROUP(msiof3_ss2_e),
4314		SH_PFC_PIN_GROUP(msiof3_txd_e),
4315		SH_PFC_PIN_GROUP(msiof3_rxd_e),
4316		SH_PFC_PIN_GROUP(pwm0),
4317		SH_PFC_PIN_GROUP(pwm1_a),
4318		SH_PFC_PIN_GROUP(pwm1_b),
4319		SH_PFC_PIN_GROUP(pwm2_a),
4320		SH_PFC_PIN_GROUP(pwm2_b),
4321		SH_PFC_PIN_GROUP(pwm3_a),
4322		SH_PFC_PIN_GROUP(pwm3_b),
4323		SH_PFC_PIN_GROUP(pwm4_a),
4324		SH_PFC_PIN_GROUP(pwm4_b),
4325		SH_PFC_PIN_GROUP(pwm5_a),
4326		SH_PFC_PIN_GROUP(pwm5_b),
4327		SH_PFC_PIN_GROUP(pwm6_a),
4328		SH_PFC_PIN_GROUP(pwm6_b),
4329		SH_PFC_PIN_GROUP(qspi0_ctrl),
4330		BUS_DATA_PIN_GROUP(qspi0_data, 2),
4331		BUS_DATA_PIN_GROUP(qspi0_data, 4),
4332		SH_PFC_PIN_GROUP(qspi1_ctrl),
4333		BUS_DATA_PIN_GROUP(qspi1_data, 2),
4334		BUS_DATA_PIN_GROUP(qspi1_data, 4),
4335		SH_PFC_PIN_GROUP(scif0_data),
4336		SH_PFC_PIN_GROUP(scif0_clk),
4337		SH_PFC_PIN_GROUP(scif0_ctrl),
4338		SH_PFC_PIN_GROUP(scif1_data_a),
4339		SH_PFC_PIN_GROUP(scif1_clk),
4340		SH_PFC_PIN_GROUP(scif1_ctrl),
4341		SH_PFC_PIN_GROUP(scif1_data_b),
4342		SH_PFC_PIN_GROUP(scif2_data_a),
4343		SH_PFC_PIN_GROUP(scif2_clk),
4344		SH_PFC_PIN_GROUP(scif2_data_b),
4345		SH_PFC_PIN_GROUP(scif3_data_a),
4346		SH_PFC_PIN_GROUP(scif3_clk),
4347		SH_PFC_PIN_GROUP(scif3_ctrl),
4348		SH_PFC_PIN_GROUP(scif3_data_b),
4349		SH_PFC_PIN_GROUP(scif4_data_a),
4350		SH_PFC_PIN_GROUP(scif4_clk_a),
4351		SH_PFC_PIN_GROUP(scif4_ctrl_a),
4352		SH_PFC_PIN_GROUP(scif4_data_b),
4353		SH_PFC_PIN_GROUP(scif4_clk_b),
4354		SH_PFC_PIN_GROUP(scif4_ctrl_b),
4355		SH_PFC_PIN_GROUP(scif4_data_c),
4356		SH_PFC_PIN_GROUP(scif4_clk_c),
4357		SH_PFC_PIN_GROUP(scif4_ctrl_c),
4358		SH_PFC_PIN_GROUP(scif5_data_a),
4359		SH_PFC_PIN_GROUP(scif5_clk_a),
4360		SH_PFC_PIN_GROUP(scif5_data_b),
4361		SH_PFC_PIN_GROUP(scif5_clk_b),
4362		SH_PFC_PIN_GROUP(scif_clk_a),
4363		SH_PFC_PIN_GROUP(scif_clk_b),
4364		BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4365		BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4366		SH_PFC_PIN_GROUP(sdhi0_ctrl),
4367		SH_PFC_PIN_GROUP(sdhi0_cd),
4368		SH_PFC_PIN_GROUP(sdhi0_wp),
4369		BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4370		BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4371		SH_PFC_PIN_GROUP(sdhi1_ctrl),
4372		SH_PFC_PIN_GROUP(sdhi1_cd),
4373		SH_PFC_PIN_GROUP(sdhi1_wp),
4374		BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4375		BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4376		BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4377		SH_PFC_PIN_GROUP(sdhi2_ctrl),
4378		SH_PFC_PIN_GROUP(sdhi2_cd_a),
4379		SH_PFC_PIN_GROUP(sdhi2_wp_a),
4380		SH_PFC_PIN_GROUP(sdhi2_cd_b),
4381		SH_PFC_PIN_GROUP(sdhi2_wp_b),
4382		SH_PFC_PIN_GROUP(sdhi2_ds),
4383		BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4384		BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4385		BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4386		SH_PFC_PIN_GROUP(sdhi3_ctrl),
4387		SH_PFC_PIN_GROUP(sdhi3_cd),
4388		SH_PFC_PIN_GROUP(sdhi3_wp),
4389		SH_PFC_PIN_GROUP(sdhi3_ds),
4390		SH_PFC_PIN_GROUP(ssi0_data),
4391		SH_PFC_PIN_GROUP(ssi01239_ctrl),
4392		SH_PFC_PIN_GROUP(ssi1_data_a),
4393		SH_PFC_PIN_GROUP(ssi1_data_b),
4394		SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4395		SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4396		SH_PFC_PIN_GROUP(ssi2_data_a),
4397		SH_PFC_PIN_GROUP(ssi2_data_b),
4398		SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4399		SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4400		SH_PFC_PIN_GROUP(ssi3_data),
4401		SH_PFC_PIN_GROUP(ssi349_ctrl),
4402		SH_PFC_PIN_GROUP(ssi4_data),
4403		SH_PFC_PIN_GROUP(ssi4_ctrl),
4404		SH_PFC_PIN_GROUP(ssi5_data),
4405		SH_PFC_PIN_GROUP(ssi5_ctrl),
4406		SH_PFC_PIN_GROUP(ssi6_data),
4407		SH_PFC_PIN_GROUP(ssi6_ctrl),
4408		SH_PFC_PIN_GROUP(ssi7_data),
4409		SH_PFC_PIN_GROUP(ssi78_ctrl),
4410		SH_PFC_PIN_GROUP(ssi8_data),
4411		SH_PFC_PIN_GROUP(ssi9_data_a),
4412		SH_PFC_PIN_GROUP(ssi9_data_b),
4413		SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4414		SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4415		SH_PFC_PIN_GROUP(tmu_tclk1_a),
4416		SH_PFC_PIN_GROUP(tmu_tclk1_b),
4417		SH_PFC_PIN_GROUP(tmu_tclk2_a),
4418		SH_PFC_PIN_GROUP(tmu_tclk2_b),
4419		SH_PFC_PIN_GROUP(tpu_to0),
4420		SH_PFC_PIN_GROUP(tpu_to1),
4421		SH_PFC_PIN_GROUP(tpu_to2),
4422		SH_PFC_PIN_GROUP(tpu_to3),
4423		SH_PFC_PIN_GROUP(usb0),
4424		SH_PFC_PIN_GROUP(usb1),
4425		SH_PFC_PIN_GROUP(usb30),
4426		BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4427		BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4428		BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4429		BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4430		SH_PFC_PIN_GROUP(vin4_data18_a),
4431		BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4432		BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4433		BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4434		BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4435		BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4436		BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4437		SH_PFC_PIN_GROUP(vin4_data18_b),
4438		BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4439		BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4440		SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4441		SH_PFC_PIN_GROUP(vin4_sync),
4442		SH_PFC_PIN_GROUP(vin4_field),
4443		SH_PFC_PIN_GROUP(vin4_clkenb),
4444		SH_PFC_PIN_GROUP(vin4_clk),
4445		BUS_DATA_PIN_GROUP(vin5_data, 8),
4446		BUS_DATA_PIN_GROUP(vin5_data, 10),
4447		BUS_DATA_PIN_GROUP(vin5_data, 12),
4448		BUS_DATA_PIN_GROUP(vin5_data, 16),
4449		SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4450		SH_PFC_PIN_GROUP(vin5_sync),
4451		SH_PFC_PIN_GROUP(vin5_field),
4452		SH_PFC_PIN_GROUP(vin5_clkenb),
4453		SH_PFC_PIN_GROUP(vin5_clk),
4454	},
4455#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4456	.automotive = {
4457		SH_PFC_PIN_GROUP(drif0_ctrl_a),
4458		SH_PFC_PIN_GROUP(drif0_data0_a),
4459		SH_PFC_PIN_GROUP(drif0_data1_a),
4460		SH_PFC_PIN_GROUP(drif0_ctrl_b),
4461		SH_PFC_PIN_GROUP(drif0_data0_b),
4462		SH_PFC_PIN_GROUP(drif0_data1_b),
4463		SH_PFC_PIN_GROUP(drif0_ctrl_c),
4464		SH_PFC_PIN_GROUP(drif0_data0_c),
4465		SH_PFC_PIN_GROUP(drif0_data1_c),
4466		SH_PFC_PIN_GROUP(drif1_ctrl_a),
4467		SH_PFC_PIN_GROUP(drif1_data0_a),
4468		SH_PFC_PIN_GROUP(drif1_data1_a),
4469		SH_PFC_PIN_GROUP(drif1_ctrl_b),
4470		SH_PFC_PIN_GROUP(drif1_data0_b),
4471		SH_PFC_PIN_GROUP(drif1_data1_b),
4472		SH_PFC_PIN_GROUP(drif1_ctrl_c),
4473		SH_PFC_PIN_GROUP(drif1_data0_c),
4474		SH_PFC_PIN_GROUP(drif1_data1_c),
4475		SH_PFC_PIN_GROUP(drif2_ctrl_a),
4476		SH_PFC_PIN_GROUP(drif2_data0_a),
4477		SH_PFC_PIN_GROUP(drif2_data1_a),
4478		SH_PFC_PIN_GROUP(drif2_ctrl_b),
4479		SH_PFC_PIN_GROUP(drif2_data0_b),
4480		SH_PFC_PIN_GROUP(drif2_data1_b),
4481		SH_PFC_PIN_GROUP(drif3_ctrl_a),
4482		SH_PFC_PIN_GROUP(drif3_data0_a),
4483		SH_PFC_PIN_GROUP(drif3_data1_a),
4484		SH_PFC_PIN_GROUP(drif3_ctrl_b),
4485		SH_PFC_PIN_GROUP(drif3_data0_b),
4486		SH_PFC_PIN_GROUP(drif3_data1_b),
4487		SH_PFC_PIN_GROUP(mlb_3pin),
4488	}
4489#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4490};
4491
4492static const char * const audio_clk_groups[] = {
4493	"audio_clk_a_a",
4494	"audio_clk_a_b",
4495	"audio_clk_a_c",
4496	"audio_clk_b_a",
4497	"audio_clk_b_b",
4498	"audio_clk_c_a",
4499	"audio_clk_c_b",
4500	"audio_clkout_a",
4501	"audio_clkout_b",
4502	"audio_clkout_c",
4503	"audio_clkout_d",
4504	"audio_clkout1_a",
4505	"audio_clkout1_b",
4506	"audio_clkout2_a",
4507	"audio_clkout2_b",
4508	"audio_clkout3_a",
4509	"audio_clkout3_b",
4510};
4511
4512static const char * const avb_groups[] = {
4513	"avb_link",
4514	"avb_magic",
4515	"avb_phy_int",
4516	"avb_mdc",	/* Deprecated, please use "avb_mdio" instead */
4517	"avb_mdio",
4518	"avb_mii",
4519	"avb_avtp_pps",
4520	"avb_avtp_match_a",
4521	"avb_avtp_capture_a",
4522	"avb_avtp_match_b",
4523	"avb_avtp_capture_b",
4524};
4525
4526static const char * const can0_groups[] = {
4527	"can0_data_a",
4528	"can0_data_b",
4529};
4530
4531static const char * const can1_groups[] = {
4532	"can1_data",
4533};
4534
4535static const char * const can_clk_groups[] = {
4536	"can_clk",
4537};
4538
4539static const char * const canfd0_groups[] = {
4540	"canfd0_data_a",
4541	"canfd0_data_b",
4542};
4543
4544static const char * const canfd1_groups[] = {
4545	"canfd1_data",
4546};
4547
4548#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4549static const char * const drif0_groups[] = {
4550	"drif0_ctrl_a",
4551	"drif0_data0_a",
4552	"drif0_data1_a",
4553	"drif0_ctrl_b",
4554	"drif0_data0_b",
4555	"drif0_data1_b",
4556	"drif0_ctrl_c",
4557	"drif0_data0_c",
4558	"drif0_data1_c",
4559};
4560
4561static const char * const drif1_groups[] = {
4562	"drif1_ctrl_a",
4563	"drif1_data0_a",
4564	"drif1_data1_a",
4565	"drif1_ctrl_b",
4566	"drif1_data0_b",
4567	"drif1_data1_b",
4568	"drif1_ctrl_c",
4569	"drif1_data0_c",
4570	"drif1_data1_c",
4571};
4572
4573static const char * const drif2_groups[] = {
4574	"drif2_ctrl_a",
4575	"drif2_data0_a",
4576	"drif2_data1_a",
4577	"drif2_ctrl_b",
4578	"drif2_data0_b",
4579	"drif2_data1_b",
4580};
4581
4582static const char * const drif3_groups[] = {
4583	"drif3_ctrl_a",
4584	"drif3_data0_a",
4585	"drif3_data1_a",
4586	"drif3_ctrl_b",
4587	"drif3_data0_b",
4588	"drif3_data1_b",
4589};
4590#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4591
4592static const char * const du_groups[] = {
4593	"du_rgb666",
4594	"du_rgb888",
4595	"du_clk_out_0",
4596	"du_clk_out_1",
4597	"du_sync",
4598	"du_oddf",
4599	"du_cde",
4600	"du_disp",
4601};
4602
4603static const char * const hscif0_groups[] = {
4604	"hscif0_data",
4605	"hscif0_clk",
4606	"hscif0_ctrl",
4607};
4608
4609static const char * const hscif1_groups[] = {
4610	"hscif1_data_a",
4611	"hscif1_clk_a",
4612	"hscif1_ctrl_a",
4613	"hscif1_data_b",
4614	"hscif1_clk_b",
4615	"hscif1_ctrl_b",
4616};
4617
4618static const char * const hscif2_groups[] = {
4619	"hscif2_data_a",
4620	"hscif2_clk_a",
4621	"hscif2_ctrl_a",
4622	"hscif2_data_b",
4623	"hscif2_clk_b",
4624	"hscif2_ctrl_b",
4625	"hscif2_data_c",
4626	"hscif2_clk_c",
4627	"hscif2_ctrl_c",
4628};
4629
4630static const char * const hscif3_groups[] = {
4631	"hscif3_data_a",
4632	"hscif3_clk",
4633	"hscif3_ctrl",
4634	"hscif3_data_b",
4635	"hscif3_data_c",
4636	"hscif3_data_d",
4637};
4638
4639static const char * const hscif4_groups[] = {
4640	"hscif4_data_a",
4641	"hscif4_clk",
4642	"hscif4_ctrl",
4643	"hscif4_data_b",
4644};
4645
4646static const char * const i2c0_groups[] = {
4647	"i2c0",
4648};
4649
4650static const char * const i2c1_groups[] = {
4651	"i2c1_a",
4652	"i2c1_b",
4653};
4654
4655static const char * const i2c2_groups[] = {
4656	"i2c2_a",
4657	"i2c2_b",
4658};
4659
4660static const char * const i2c3_groups[] = {
4661	"i2c3",
4662};
4663
4664static const char * const i2c5_groups[] = {
4665	"i2c5",
4666};
4667
4668static const char * const i2c6_groups[] = {
4669	"i2c6_a",
4670	"i2c6_b",
4671	"i2c6_c",
4672};
4673
4674static const char * const intc_ex_groups[] = {
4675	"intc_ex_irq0",
4676	"intc_ex_irq1",
4677	"intc_ex_irq2",
4678	"intc_ex_irq3",
4679	"intc_ex_irq4",
4680	"intc_ex_irq5",
4681};
4682
4683#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4684static const char * const mlb_3pin_groups[] = {
4685	"mlb_3pin",
4686};
4687#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4688
4689static const char * const msiof0_groups[] = {
4690	"msiof0_clk",
4691	"msiof0_sync",
4692	"msiof0_ss1",
4693	"msiof0_ss2",
4694	"msiof0_txd",
4695	"msiof0_rxd",
4696};
4697
4698static const char * const msiof1_groups[] = {
4699	"msiof1_clk_a",
4700	"msiof1_sync_a",
4701	"msiof1_ss1_a",
4702	"msiof1_ss2_a",
4703	"msiof1_txd_a",
4704	"msiof1_rxd_a",
4705	"msiof1_clk_b",
4706	"msiof1_sync_b",
4707	"msiof1_ss1_b",
4708	"msiof1_ss2_b",
4709	"msiof1_txd_b",
4710	"msiof1_rxd_b",
4711	"msiof1_clk_c",
4712	"msiof1_sync_c",
4713	"msiof1_ss1_c",
4714	"msiof1_ss2_c",
4715	"msiof1_txd_c",
4716	"msiof1_rxd_c",
4717	"msiof1_clk_d",
4718	"msiof1_sync_d",
4719	"msiof1_ss1_d",
4720	"msiof1_ss2_d",
4721	"msiof1_txd_d",
4722	"msiof1_rxd_d",
4723	"msiof1_clk_e",
4724	"msiof1_sync_e",
4725	"msiof1_ss1_e",
4726	"msiof1_ss2_e",
4727	"msiof1_txd_e",
4728	"msiof1_rxd_e",
4729	"msiof1_clk_f",
4730	"msiof1_sync_f",
4731	"msiof1_ss1_f",
4732	"msiof1_ss2_f",
4733	"msiof1_txd_f",
4734	"msiof1_rxd_f",
4735	"msiof1_clk_g",
4736	"msiof1_sync_g",
4737	"msiof1_ss1_g",
4738	"msiof1_ss2_g",
4739	"msiof1_txd_g",
4740	"msiof1_rxd_g",
4741};
4742
4743static const char * const msiof2_groups[] = {
4744	"msiof2_clk_a",
4745	"msiof2_sync_a",
4746	"msiof2_ss1_a",
4747	"msiof2_ss2_a",
4748	"msiof2_txd_a",
4749	"msiof2_rxd_a",
4750	"msiof2_clk_b",
4751	"msiof2_sync_b",
4752	"msiof2_ss1_b",
4753	"msiof2_ss2_b",
4754	"msiof2_txd_b",
4755	"msiof2_rxd_b",
4756	"msiof2_clk_c",
4757	"msiof2_sync_c",
4758	"msiof2_ss1_c",
4759	"msiof2_ss2_c",
4760	"msiof2_txd_c",
4761	"msiof2_rxd_c",
4762	"msiof2_clk_d",
4763	"msiof2_sync_d",
4764	"msiof2_ss1_d",
4765	"msiof2_ss2_d",
4766	"msiof2_txd_d",
4767	"msiof2_rxd_d",
4768};
4769
4770static const char * const msiof3_groups[] = {
4771	"msiof3_clk_a",
4772	"msiof3_sync_a",
4773	"msiof3_ss1_a",
4774	"msiof3_ss2_a",
4775	"msiof3_txd_a",
4776	"msiof3_rxd_a",
4777	"msiof3_clk_b",
4778	"msiof3_sync_b",
4779	"msiof3_ss1_b",
4780	"msiof3_ss2_b",
4781	"msiof3_txd_b",
4782	"msiof3_rxd_b",
4783	"msiof3_clk_c",
4784	"msiof3_sync_c",
4785	"msiof3_txd_c",
4786	"msiof3_rxd_c",
4787	"msiof3_clk_d",
4788	"msiof3_sync_d",
4789	"msiof3_ss1_d",
4790	"msiof3_txd_d",
4791	"msiof3_rxd_d",
4792	"msiof3_clk_e",
4793	"msiof3_sync_e",
4794	"msiof3_ss1_e",
4795	"msiof3_ss2_e",
4796	"msiof3_txd_e",
4797	"msiof3_rxd_e",
4798};
4799
4800static const char * const pwm0_groups[] = {
4801	"pwm0",
4802};
4803
4804static const char * const pwm1_groups[] = {
4805	"pwm1_a",
4806	"pwm1_b",
4807};
4808
4809static const char * const pwm2_groups[] = {
4810	"pwm2_a",
4811	"pwm2_b",
4812};
4813
4814static const char * const pwm3_groups[] = {
4815	"pwm3_a",
4816	"pwm3_b",
4817};
4818
4819static const char * const pwm4_groups[] = {
4820	"pwm4_a",
4821	"pwm4_b",
4822};
4823
4824static const char * const pwm5_groups[] = {
4825	"pwm5_a",
4826	"pwm5_b",
4827};
4828
4829static const char * const pwm6_groups[] = {
4830	"pwm6_a",
4831	"pwm6_b",
4832};
4833
4834static const char * const qspi0_groups[] = {
4835	"qspi0_ctrl",
4836	"qspi0_data2",
4837	"qspi0_data4",
4838};
4839
4840static const char * const qspi1_groups[] = {
4841	"qspi1_ctrl",
4842	"qspi1_data2",
4843	"qspi1_data4",
4844};
4845
4846static const char * const scif0_groups[] = {
4847	"scif0_data",
4848	"scif0_clk",
4849	"scif0_ctrl",
4850};
4851
4852static const char * const scif1_groups[] = {
4853	"scif1_data_a",
4854	"scif1_clk",
4855	"scif1_ctrl",
4856	"scif1_data_b",
4857};
4858
4859static const char * const scif2_groups[] = {
4860	"scif2_data_a",
4861	"scif2_clk",
4862	"scif2_data_b",
4863};
4864
4865static const char * const scif3_groups[] = {
4866	"scif3_data_a",
4867	"scif3_clk",
4868	"scif3_ctrl",
4869	"scif3_data_b",
4870};
4871
4872static const char * const scif4_groups[] = {
4873	"scif4_data_a",
4874	"scif4_clk_a",
4875	"scif4_ctrl_a",
4876	"scif4_data_b",
4877	"scif4_clk_b",
4878	"scif4_ctrl_b",
4879	"scif4_data_c",
4880	"scif4_clk_c",
4881	"scif4_ctrl_c",
4882};
4883
4884static const char * const scif5_groups[] = {
4885	"scif5_data_a",
4886	"scif5_clk_a",
4887	"scif5_data_b",
4888	"scif5_clk_b",
4889};
4890
4891static const char * const scif_clk_groups[] = {
4892	"scif_clk_a",
4893	"scif_clk_b",
4894};
4895
4896static const char * const sdhi0_groups[] = {
4897	"sdhi0_data1",
4898	"sdhi0_data4",
4899	"sdhi0_ctrl",
4900	"sdhi0_cd",
4901	"sdhi0_wp",
4902};
4903
4904static const char * const sdhi1_groups[] = {
4905	"sdhi1_data1",
4906	"sdhi1_data4",
4907	"sdhi1_ctrl",
4908	"sdhi1_cd",
4909	"sdhi1_wp",
4910};
4911
4912static const char * const sdhi2_groups[] = {
4913	"sdhi2_data1",
4914	"sdhi2_data4",
4915	"sdhi2_data8",
4916	"sdhi2_ctrl",
4917	"sdhi2_cd_a",
4918	"sdhi2_wp_a",
4919	"sdhi2_cd_b",
4920	"sdhi2_wp_b",
4921	"sdhi2_ds",
4922};
4923
4924static const char * const sdhi3_groups[] = {
4925	"sdhi3_data1",
4926	"sdhi3_data4",
4927	"sdhi3_data8",
4928	"sdhi3_ctrl",
4929	"sdhi3_cd",
4930	"sdhi3_wp",
4931	"sdhi3_ds",
4932};
4933
4934static const char * const ssi_groups[] = {
4935	"ssi0_data",
4936	"ssi01239_ctrl",
4937	"ssi1_data_a",
4938	"ssi1_data_b",
4939	"ssi1_ctrl_a",
4940	"ssi1_ctrl_b",
4941	"ssi2_data_a",
4942	"ssi2_data_b",
4943	"ssi2_ctrl_a",
4944	"ssi2_ctrl_b",
4945	"ssi3_data",
4946	"ssi349_ctrl",
4947	"ssi4_data",
4948	"ssi4_ctrl",
4949	"ssi5_data",
4950	"ssi5_ctrl",
4951	"ssi6_data",
4952	"ssi6_ctrl",
4953	"ssi7_data",
4954	"ssi78_ctrl",
4955	"ssi8_data",
4956	"ssi9_data_a",
4957	"ssi9_data_b",
4958	"ssi9_ctrl_a",
4959	"ssi9_ctrl_b",
4960};
4961
4962static const char * const tmu_groups[] = {
4963	"tmu_tclk1_a",
4964	"tmu_tclk1_b",
4965	"tmu_tclk2_a",
4966	"tmu_tclk2_b",
4967};
4968
4969static const char * const tpu_groups[] = {
4970	"tpu_to0",
4971	"tpu_to1",
4972	"tpu_to2",
4973	"tpu_to3",
4974};
4975
4976static const char * const usb0_groups[] = {
4977	"usb0",
4978};
4979
4980static const char * const usb1_groups[] = {
4981	"usb1",
4982};
4983
4984static const char * const usb30_groups[] = {
4985	"usb30",
4986};
4987
4988static const char * const vin4_groups[] = {
4989	"vin4_data8_a",
4990	"vin4_data10_a",
4991	"vin4_data12_a",
4992	"vin4_data16_a",
4993	"vin4_data18_a",
4994	"vin4_data20_a",
4995	"vin4_data24_a",
4996	"vin4_data8_b",
4997	"vin4_data10_b",
4998	"vin4_data12_b",
4999	"vin4_data16_b",
5000	"vin4_data18_b",
5001	"vin4_data20_b",
5002	"vin4_data24_b",
5003	"vin4_g8",
5004	"vin4_sync",
5005	"vin4_field",
5006	"vin4_clkenb",
5007	"vin4_clk",
5008};
5009
5010static const char * const vin5_groups[] = {
5011	"vin5_data8",
5012	"vin5_data10",
5013	"vin5_data12",
5014	"vin5_data16",
5015	"vin5_high8",
5016	"vin5_sync",
5017	"vin5_field",
5018	"vin5_clkenb",
5019	"vin5_clk",
5020};
5021
5022static const struct {
5023	struct sh_pfc_function common[52];
5024#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5025	struct sh_pfc_function automotive[5];
5026#endif
5027} pinmux_functions = {
5028	.common = {
5029		SH_PFC_FUNCTION(audio_clk),
5030		SH_PFC_FUNCTION(avb),
5031		SH_PFC_FUNCTION(can0),
5032		SH_PFC_FUNCTION(can1),
5033		SH_PFC_FUNCTION(can_clk),
5034		SH_PFC_FUNCTION(canfd0),
5035		SH_PFC_FUNCTION(canfd1),
5036		SH_PFC_FUNCTION(du),
5037		SH_PFC_FUNCTION(hscif0),
5038		SH_PFC_FUNCTION(hscif1),
5039		SH_PFC_FUNCTION(hscif2),
5040		SH_PFC_FUNCTION(hscif3),
5041		SH_PFC_FUNCTION(hscif4),
5042		SH_PFC_FUNCTION(i2c0),
5043		SH_PFC_FUNCTION(i2c1),
5044		SH_PFC_FUNCTION(i2c2),
5045		SH_PFC_FUNCTION(i2c3),
5046		SH_PFC_FUNCTION(i2c5),
5047		SH_PFC_FUNCTION(i2c6),
5048		SH_PFC_FUNCTION(intc_ex),
5049		SH_PFC_FUNCTION(msiof0),
5050		SH_PFC_FUNCTION(msiof1),
5051		SH_PFC_FUNCTION(msiof2),
5052		SH_PFC_FUNCTION(msiof3),
5053		SH_PFC_FUNCTION(pwm0),
5054		SH_PFC_FUNCTION(pwm1),
5055		SH_PFC_FUNCTION(pwm2),
5056		SH_PFC_FUNCTION(pwm3),
5057		SH_PFC_FUNCTION(pwm4),
5058		SH_PFC_FUNCTION(pwm5),
5059		SH_PFC_FUNCTION(pwm6),
5060		SH_PFC_FUNCTION(qspi0),
5061		SH_PFC_FUNCTION(qspi1),
5062		SH_PFC_FUNCTION(scif0),
5063		SH_PFC_FUNCTION(scif1),
5064		SH_PFC_FUNCTION(scif2),
5065		SH_PFC_FUNCTION(scif3),
5066		SH_PFC_FUNCTION(scif4),
5067		SH_PFC_FUNCTION(scif5),
5068		SH_PFC_FUNCTION(scif_clk),
5069		SH_PFC_FUNCTION(sdhi0),
5070		SH_PFC_FUNCTION(sdhi1),
5071		SH_PFC_FUNCTION(sdhi2),
5072		SH_PFC_FUNCTION(sdhi3),
5073		SH_PFC_FUNCTION(ssi),
5074		SH_PFC_FUNCTION(tmu),
5075		SH_PFC_FUNCTION(tpu),
5076		SH_PFC_FUNCTION(usb0),
5077		SH_PFC_FUNCTION(usb1),
5078		SH_PFC_FUNCTION(usb30),
5079		SH_PFC_FUNCTION(vin4),
5080		SH_PFC_FUNCTION(vin5),
5081	},
5082#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5083	.automotive = {
5084		SH_PFC_FUNCTION(drif0),
5085		SH_PFC_FUNCTION(drif1),
5086		SH_PFC_FUNCTION(drif2),
5087		SH_PFC_FUNCTION(drif3),
5088		SH_PFC_FUNCTION(mlb_3pin),
5089	}
5090#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
5091};
5092
5093static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5094#define F_(x, y)	FN_##y
5095#define FM(x)		FN_##x
5096	{ PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5097			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5098				   1, 1, 1, 1, 1),
5099			     GROUP(
5100		/* GP0_31_16 RESERVED */
5101		GP_0_15_FN,	GPSR0_15,
5102		GP_0_14_FN,	GPSR0_14,
5103		GP_0_13_FN,	GPSR0_13,
5104		GP_0_12_FN,	GPSR0_12,
5105		GP_0_11_FN,	GPSR0_11,
5106		GP_0_10_FN,	GPSR0_10,
5107		GP_0_9_FN,	GPSR0_9,
5108		GP_0_8_FN,	GPSR0_8,
5109		GP_0_7_FN,	GPSR0_7,
5110		GP_0_6_FN,	GPSR0_6,
5111		GP_0_5_FN,	GPSR0_5,
5112		GP_0_4_FN,	GPSR0_4,
5113		GP_0_3_FN,	GPSR0_3,
5114		GP_0_2_FN,	GPSR0_2,
5115		GP_0_1_FN,	GPSR0_1,
5116		GP_0_0_FN,	GPSR0_0, ))
5117	},
5118	{ PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5119		0, 0,
5120		0, 0,
5121		0, 0,
5122		GP_1_28_FN,	GPSR1_28,
5123		GP_1_27_FN,	GPSR1_27,
5124		GP_1_26_FN,	GPSR1_26,
5125		GP_1_25_FN,	GPSR1_25,
5126		GP_1_24_FN,	GPSR1_24,
5127		GP_1_23_FN,	GPSR1_23,
5128		GP_1_22_FN,	GPSR1_22,
5129		GP_1_21_FN,	GPSR1_21,
5130		GP_1_20_FN,	GPSR1_20,
5131		GP_1_19_FN,	GPSR1_19,
5132		GP_1_18_FN,	GPSR1_18,
5133		GP_1_17_FN,	GPSR1_17,
5134		GP_1_16_FN,	GPSR1_16,
5135		GP_1_15_FN,	GPSR1_15,
5136		GP_1_14_FN,	GPSR1_14,
5137		GP_1_13_FN,	GPSR1_13,
5138		GP_1_12_FN,	GPSR1_12,
5139		GP_1_11_FN,	GPSR1_11,
5140		GP_1_10_FN,	GPSR1_10,
5141		GP_1_9_FN,	GPSR1_9,
5142		GP_1_8_FN,	GPSR1_8,
5143		GP_1_7_FN,	GPSR1_7,
5144		GP_1_6_FN,	GPSR1_6,
5145		GP_1_5_FN,	GPSR1_5,
5146		GP_1_4_FN,	GPSR1_4,
5147		GP_1_3_FN,	GPSR1_3,
5148		GP_1_2_FN,	GPSR1_2,
5149		GP_1_1_FN,	GPSR1_1,
5150		GP_1_0_FN,	GPSR1_0, ))
5151	},
5152	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5153			     GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5154				   1, 1, 1, 1),
5155			     GROUP(
5156		/* GP2_31_15 RESERVED */
5157		GP_2_14_FN,	GPSR2_14,
5158		GP_2_13_FN,	GPSR2_13,
5159		GP_2_12_FN,	GPSR2_12,
5160		GP_2_11_FN,	GPSR2_11,
5161		GP_2_10_FN,	GPSR2_10,
5162		GP_2_9_FN,	GPSR2_9,
5163		GP_2_8_FN,	GPSR2_8,
5164		GP_2_7_FN,	GPSR2_7,
5165		GP_2_6_FN,	GPSR2_6,
5166		GP_2_5_FN,	GPSR2_5,
5167		GP_2_4_FN,	GPSR2_4,
5168		GP_2_3_FN,	GPSR2_3,
5169		GP_2_2_FN,	GPSR2_2,
5170		GP_2_1_FN,	GPSR2_1,
5171		GP_2_0_FN,	GPSR2_0, ))
5172	},
5173	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5174			     GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5175				   1, 1, 1, 1, 1),
5176			     GROUP(
5177		/* GP3_31_16 RESERVED */
5178		GP_3_15_FN,	GPSR3_15,
5179		GP_3_14_FN,	GPSR3_14,
5180		GP_3_13_FN,	GPSR3_13,
5181		GP_3_12_FN,	GPSR3_12,
5182		GP_3_11_FN,	GPSR3_11,
5183		GP_3_10_FN,	GPSR3_10,
5184		GP_3_9_FN,	GPSR3_9,
5185		GP_3_8_FN,	GPSR3_8,
5186		GP_3_7_FN,	GPSR3_7,
5187		GP_3_6_FN,	GPSR3_6,
5188		GP_3_5_FN,	GPSR3_5,
5189		GP_3_4_FN,	GPSR3_4,
5190		GP_3_3_FN,	GPSR3_3,
5191		GP_3_2_FN,	GPSR3_2,
5192		GP_3_1_FN,	GPSR3_1,
5193		GP_3_0_FN,	GPSR3_0, ))
5194	},
5195	{ PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5196			     GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5197				   1, 1, 1, 1, 1, 1, 1),
5198			     GROUP(
5199		/* GP4_31_18 RESERVED */
5200		GP_4_17_FN,	GPSR4_17,
5201		GP_4_16_FN,	GPSR4_16,
5202		GP_4_15_FN,	GPSR4_15,
5203		GP_4_14_FN,	GPSR4_14,
5204		GP_4_13_FN,	GPSR4_13,
5205		GP_4_12_FN,	GPSR4_12,
5206		GP_4_11_FN,	GPSR4_11,
5207		GP_4_10_FN,	GPSR4_10,
5208		GP_4_9_FN,	GPSR4_9,
5209		GP_4_8_FN,	GPSR4_8,
5210		GP_4_7_FN,	GPSR4_7,
5211		GP_4_6_FN,	GPSR4_6,
5212		GP_4_5_FN,	GPSR4_5,
5213		GP_4_4_FN,	GPSR4_4,
5214		GP_4_3_FN,	GPSR4_3,
5215		GP_4_2_FN,	GPSR4_2,
5216		GP_4_1_FN,	GPSR4_1,
5217		GP_4_0_FN,	GPSR4_0, ))
5218	},
5219	{ PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5220		0, 0,
5221		0, 0,
5222		0, 0,
5223		0, 0,
5224		0, 0,
5225		0, 0,
5226		GP_5_25_FN,	GPSR5_25,
5227		GP_5_24_FN,	GPSR5_24,
5228		GP_5_23_FN,	GPSR5_23,
5229		GP_5_22_FN,	GPSR5_22,
5230		GP_5_21_FN,	GPSR5_21,
5231		GP_5_20_FN,	GPSR5_20,
5232		GP_5_19_FN,	GPSR5_19,
5233		GP_5_18_FN,	GPSR5_18,
5234		GP_5_17_FN,	GPSR5_17,
5235		GP_5_16_FN,	GPSR5_16,
5236		GP_5_15_FN,	GPSR5_15,
5237		GP_5_14_FN,	GPSR5_14,
5238		GP_5_13_FN,	GPSR5_13,
5239		GP_5_12_FN,	GPSR5_12,
5240		GP_5_11_FN,	GPSR5_11,
5241		GP_5_10_FN,	GPSR5_10,
5242		GP_5_9_FN,	GPSR5_9,
5243		GP_5_8_FN,	GPSR5_8,
5244		GP_5_7_FN,	GPSR5_7,
5245		GP_5_6_FN,	GPSR5_6,
5246		GP_5_5_FN,	GPSR5_5,
5247		GP_5_4_FN,	GPSR5_4,
5248		GP_5_3_FN,	GPSR5_3,
5249		GP_5_2_FN,	GPSR5_2,
5250		GP_5_1_FN,	GPSR5_1,
5251		GP_5_0_FN,	GPSR5_0, ))
5252	},
5253	{ PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5254		GP_6_31_FN,	GPSR6_31,
5255		GP_6_30_FN,	GPSR6_30,
5256		GP_6_29_FN,	GPSR6_29,
5257		GP_6_28_FN,	GPSR6_28,
5258		GP_6_27_FN,	GPSR6_27,
5259		GP_6_26_FN,	GPSR6_26,
5260		GP_6_25_FN,	GPSR6_25,
5261		GP_6_24_FN,	GPSR6_24,
5262		GP_6_23_FN,	GPSR6_23,
5263		GP_6_22_FN,	GPSR6_22,
5264		GP_6_21_FN,	GPSR6_21,
5265		GP_6_20_FN,	GPSR6_20,
5266		GP_6_19_FN,	GPSR6_19,
5267		GP_6_18_FN,	GPSR6_18,
5268		GP_6_17_FN,	GPSR6_17,
5269		GP_6_16_FN,	GPSR6_16,
5270		GP_6_15_FN,	GPSR6_15,
5271		GP_6_14_FN,	GPSR6_14,
5272		GP_6_13_FN,	GPSR6_13,
5273		GP_6_12_FN,	GPSR6_12,
5274		GP_6_11_FN,	GPSR6_11,
5275		GP_6_10_FN,	GPSR6_10,
5276		GP_6_9_FN,	GPSR6_9,
5277		GP_6_8_FN,	GPSR6_8,
5278		GP_6_7_FN,	GPSR6_7,
5279		GP_6_6_FN,	GPSR6_6,
5280		GP_6_5_FN,	GPSR6_5,
5281		GP_6_4_FN,	GPSR6_4,
5282		GP_6_3_FN,	GPSR6_3,
5283		GP_6_2_FN,	GPSR6_2,
5284		GP_6_1_FN,	GPSR6_1,
5285		GP_6_0_FN,	GPSR6_0, ))
5286	},
5287	{ PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5288			     GROUP(-28, 1, 1, 1, 1),
5289			     GROUP(
5290		/* GP7_31_4 RESERVED */
5291		GP_7_3_FN, GPSR7_3,
5292		GP_7_2_FN, GPSR7_2,
5293		GP_7_1_FN, GPSR7_1,
5294		GP_7_0_FN, GPSR7_0, ))
5295	},
5296#undef F_
5297#undef FM
5298
5299#define F_(x, y)	x,
5300#define FM(x)		FN_##x,
5301	{ PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5302		IP0_31_28
5303		IP0_27_24
5304		IP0_23_20
5305		IP0_19_16
5306		IP0_15_12
5307		IP0_11_8
5308		IP0_7_4
5309		IP0_3_0 ))
5310	},
5311	{ PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5312		IP1_31_28
5313		IP1_27_24
5314		IP1_23_20
5315		IP1_19_16
5316		IP1_15_12
5317		IP1_11_8
5318		IP1_7_4
5319		IP1_3_0 ))
5320	},
5321	{ PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5322		IP2_31_28
5323		IP2_27_24
5324		IP2_23_20
5325		IP2_19_16
5326		IP2_15_12
5327		IP2_11_8
5328		IP2_7_4
5329		IP2_3_0 ))
5330	},
5331	{ PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5332		IP3_31_28
5333		IP3_27_24
5334		IP3_23_20
5335		IP3_19_16
5336		IP3_15_12
5337		IP3_11_8
5338		IP3_7_4
5339		IP3_3_0 ))
5340	},
5341	{ PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5342		IP4_31_28
5343		IP4_27_24
5344		IP4_23_20
5345		IP4_19_16
5346		IP4_15_12
5347		IP4_11_8
5348		IP4_7_4
5349		IP4_3_0 ))
5350	},
5351	{ PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5352		IP5_31_28
5353		IP5_27_24
5354		IP5_23_20
5355		IP5_19_16
5356		IP5_15_12
5357		IP5_11_8
5358		IP5_7_4
5359		IP5_3_0 ))
5360	},
5361	{ PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5362		IP6_31_28
5363		IP6_27_24
5364		IP6_23_20
5365		IP6_19_16
5366		IP6_15_12
5367		IP6_11_8
5368		IP6_7_4
5369		IP6_3_0 ))
5370	},
5371	{ PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5372			     GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5373			     GROUP(
5374		IP7_31_28
5375		IP7_27_24
5376		IP7_23_20
5377		IP7_19_16
5378		/* IP7_15_12 RESERVED */
5379		IP7_11_8
5380		IP7_7_4
5381		IP7_3_0 ))
5382	},
5383	{ PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5384		IP8_31_28
5385		IP8_27_24
5386		IP8_23_20
5387		IP8_19_16
5388		IP8_15_12
5389		IP8_11_8
5390		IP8_7_4
5391		IP8_3_0 ))
5392	},
5393	{ PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5394		IP9_31_28
5395		IP9_27_24
5396		IP9_23_20
5397		IP9_19_16
5398		IP9_15_12
5399		IP9_11_8
5400		IP9_7_4
5401		IP9_3_0 ))
5402	},
5403	{ PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5404		IP10_31_28
5405		IP10_27_24
5406		IP10_23_20
5407		IP10_19_16
5408		IP10_15_12
5409		IP10_11_8
5410		IP10_7_4
5411		IP10_3_0 ))
5412	},
5413	{ PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5414		IP11_31_28
5415		IP11_27_24
5416		IP11_23_20
5417		IP11_19_16
5418		IP11_15_12
5419		IP11_11_8
5420		IP11_7_4
5421		IP11_3_0 ))
5422	},
5423	{ PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5424		IP12_31_28
5425		IP12_27_24
5426		IP12_23_20
5427		IP12_19_16
5428		IP12_15_12
5429		IP12_11_8
5430		IP12_7_4
5431		IP12_3_0 ))
5432	},
5433	{ PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5434		IP13_31_28
5435		IP13_27_24
5436		IP13_23_20
5437		IP13_19_16
5438		IP13_15_12
5439		IP13_11_8
5440		IP13_7_4
5441		IP13_3_0 ))
5442	},
5443	{ PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5444		IP14_31_28
5445		IP14_27_24
5446		IP14_23_20
5447		IP14_19_16
5448		IP14_15_12
5449		IP14_11_8
5450		IP14_7_4
5451		IP14_3_0 ))
5452	},
5453	{ PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5454		IP15_31_28
5455		IP15_27_24
5456		IP15_23_20
5457		IP15_19_16
5458		IP15_15_12
5459		IP15_11_8
5460		IP15_7_4
5461		IP15_3_0 ))
5462	},
5463	{ PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5464		IP16_31_28
5465		IP16_27_24
5466		IP16_23_20
5467		IP16_19_16
5468		IP16_15_12
5469		IP16_11_8
5470		IP16_7_4
5471		IP16_3_0 ))
5472	},
5473	{ PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5474		IP17_31_28
5475		IP17_27_24
5476		IP17_23_20
5477		IP17_19_16
5478		IP17_15_12
5479		IP17_11_8
5480		IP17_7_4
5481		IP17_3_0 ))
5482	},
5483	{ PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5484			     GROUP(-24, 4, 4),
5485			     GROUP(
5486		/* IP18_31_8 RESERVED */
5487		IP18_7_4
5488		IP18_3_0 ))
5489	},
5490#undef F_
5491#undef FM
5492
5493#define F_(x, y)	x,
5494#define FM(x)		FN_##x,
5495	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5496			     GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5497				   1, 1, 1, 2, 2, 1, 2, -3),
5498			     GROUP(
5499		MOD_SEL0_31_30_29
5500		MOD_SEL0_28_27
5501		MOD_SEL0_26_25_24
5502		MOD_SEL0_23
5503		MOD_SEL0_22
5504		MOD_SEL0_21
5505		MOD_SEL0_20
5506		MOD_SEL0_19
5507		MOD_SEL0_18_17
5508		MOD_SEL0_16
5509		/* RESERVED 15 */
5510		MOD_SEL0_14_13
5511		MOD_SEL0_12
5512		MOD_SEL0_11
5513		MOD_SEL0_10
5514		MOD_SEL0_9_8
5515		MOD_SEL0_7_6
5516		MOD_SEL0_5
5517		MOD_SEL0_4_3
5518		/* RESERVED 2, 1, 0 */ ))
5519	},
5520	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5521			     GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5522				   1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5523			     GROUP(
5524		MOD_SEL1_31_30
5525		MOD_SEL1_29_28_27
5526		MOD_SEL1_26
5527		MOD_SEL1_25_24
5528		MOD_SEL1_23_22_21
5529		MOD_SEL1_20
5530		MOD_SEL1_19
5531		MOD_SEL1_18_17
5532		MOD_SEL1_16
5533		MOD_SEL1_15_14
5534		MOD_SEL1_13
5535		MOD_SEL1_12
5536		MOD_SEL1_11
5537		MOD_SEL1_10
5538		MOD_SEL1_9
5539		/* RESERVED 8, 7 */
5540		MOD_SEL1_6
5541		MOD_SEL1_5
5542		MOD_SEL1_4
5543		MOD_SEL1_3
5544		MOD_SEL1_2
5545		MOD_SEL1_1
5546		MOD_SEL1_0 ))
5547	},
5548	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5549			     GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5550				   -16, 1),
5551			     GROUP(
5552		MOD_SEL2_31
5553		MOD_SEL2_30
5554		MOD_SEL2_29
5555		MOD_SEL2_28_27
5556		MOD_SEL2_26
5557		MOD_SEL2_25_24_23
5558		MOD_SEL2_22
5559		MOD_SEL2_21
5560		MOD_SEL2_20
5561		MOD_SEL2_19
5562		MOD_SEL2_18
5563		MOD_SEL2_17
5564		/* RESERVED 16-1 */
5565		MOD_SEL2_0 ))
5566	},
5567	{ /* sentinel */ }
5568};
5569
5570static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5571	{ PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5572		{ PIN_QSPI0_SPCLK,    28, 2 },	/* QSPI0_SPCLK */
5573		{ PIN_QSPI0_MOSI_IO0, 24, 2 },	/* QSPI0_MOSI_IO0 */
5574		{ PIN_QSPI0_MISO_IO1, 20, 2 },	/* QSPI0_MISO_IO1 */
5575		{ PIN_QSPI0_IO2,      16, 2 },	/* QSPI0_IO2 */
5576		{ PIN_QSPI0_IO3,      12, 2 },	/* QSPI0_IO3 */
5577		{ PIN_QSPI0_SSL,       8, 2 },	/* QSPI0_SSL */
5578		{ PIN_QSPI1_SPCLK,     4, 2 },	/* QSPI1_SPCLK */
5579		{ PIN_QSPI1_MOSI_IO0,  0, 2 },	/* QSPI1_MOSI_IO0 */
5580	} },
5581	{ PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5582		{ PIN_QSPI1_MISO_IO1, 28, 2 },	/* QSPI1_MISO_IO1 */
5583		{ PIN_QSPI1_IO2,      24, 2 },	/* QSPI1_IO2 */
5584		{ PIN_QSPI1_IO3,      20, 2 },	/* QSPI1_IO3 */
5585		{ PIN_QSPI1_SSL,      16, 2 },	/* QSPI1_SSL */
5586		{ PIN_RPC_INT_N,      12, 2 },	/* RPC_INT# */
5587		{ PIN_RPC_WP_N,        8, 2 },	/* RPC_WP# */
5588		{ PIN_RPC_RESET_N,     4, 2 },	/* RPC_RESET# */
5589		{ PIN_AVB_RX_CTL,      0, 3 },	/* AVB_RX_CTL */
5590	} },
5591	{ PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5592		{ PIN_AVB_RXC,        28, 3 },	/* AVB_RXC */
5593		{ PIN_AVB_RD0,        24, 3 },	/* AVB_RD0 */
5594		{ PIN_AVB_RD1,        20, 3 },	/* AVB_RD1 */
5595		{ PIN_AVB_RD2,        16, 3 },	/* AVB_RD2 */
5596		{ PIN_AVB_RD3,        12, 3 },	/* AVB_RD3 */
5597		{ PIN_AVB_TX_CTL,      8, 3 },	/* AVB_TX_CTL */
5598		{ PIN_AVB_TXC,         4, 3 },	/* AVB_TXC */
5599		{ PIN_AVB_TD0,         0, 3 },	/* AVB_TD0 */
5600	} },
5601	{ PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5602		{ PIN_AVB_TD1,        28, 3 },	/* AVB_TD1 */
5603		{ PIN_AVB_TD2,        24, 3 },	/* AVB_TD2 */
5604		{ PIN_AVB_TD3,        20, 3 },	/* AVB_TD3 */
5605		{ PIN_AVB_TXCREFCLK,  16, 3 },	/* AVB_TXCREFCLK */
5606		{ PIN_AVB_MDIO,       12, 3 },	/* AVB_MDIO */
5607		{ RCAR_GP_PIN(2,  9),  8, 3 },	/* AVB_MDC */
5608		{ RCAR_GP_PIN(2, 10),  4, 3 },	/* AVB_MAGIC */
5609		{ RCAR_GP_PIN(2, 11),  0, 3 },	/* AVB_PHY_INT */
5610	} },
5611	{ PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5612		{ RCAR_GP_PIN(2, 12), 28, 3 },	/* AVB_LINK */
5613		{ RCAR_GP_PIN(2, 13), 24, 3 },	/* AVB_AVTP_MATCH */
5614		{ RCAR_GP_PIN(2, 14), 20, 3 },	/* AVB_AVTP_CAPTURE */
5615		{ RCAR_GP_PIN(2,  0), 16, 3 },	/* IRQ0 */
5616		{ RCAR_GP_PIN(2,  1), 12, 3 },	/* IRQ1 */
5617		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* IRQ2 */
5618		{ RCAR_GP_PIN(2,  3),  4, 3 },	/* IRQ3 */
5619		{ RCAR_GP_PIN(2,  4),  0, 3 },	/* IRQ4 */
5620	} },
5621	{ PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5622		{ RCAR_GP_PIN(2,  5), 28, 3 },	/* IRQ5 */
5623		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* PWM0 */
5624		{ RCAR_GP_PIN(2,  7), 20, 3 },	/* PWM1 */
5625		{ RCAR_GP_PIN(2,  8), 16, 3 },	/* PWM2 */
5626		{ RCAR_GP_PIN(1,  0), 12, 3 },	/* A0 */
5627		{ RCAR_GP_PIN(1,  1),  8, 3 },	/* A1 */
5628		{ RCAR_GP_PIN(1,  2),  4, 3 },	/* A2 */
5629		{ RCAR_GP_PIN(1,  3),  0, 3 },	/* A3 */
5630	} },
5631	{ PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5632		{ RCAR_GP_PIN(1,  4), 28, 3 },	/* A4 */
5633		{ RCAR_GP_PIN(1,  5), 24, 3 },	/* A5 */
5634		{ RCAR_GP_PIN(1,  6), 20, 3 },	/* A6 */
5635		{ RCAR_GP_PIN(1,  7), 16, 3 },	/* A7 */
5636		{ RCAR_GP_PIN(1,  8), 12, 3 },	/* A8 */
5637		{ RCAR_GP_PIN(1,  9),  8, 3 },	/* A9 */
5638		{ RCAR_GP_PIN(1, 10),  4, 3 },	/* A10 */
5639		{ RCAR_GP_PIN(1, 11),  0, 3 },	/* A11 */
5640	} },
5641	{ PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5642		{ RCAR_GP_PIN(1, 12), 28, 3 },	/* A12 */
5643		{ RCAR_GP_PIN(1, 13), 24, 3 },	/* A13 */
5644		{ RCAR_GP_PIN(1, 14), 20, 3 },	/* A14 */
5645		{ RCAR_GP_PIN(1, 15), 16, 3 },	/* A15 */
5646		{ RCAR_GP_PIN(1, 16), 12, 3 },	/* A16 */
5647		{ RCAR_GP_PIN(1, 17),  8, 3 },	/* A17 */
5648		{ RCAR_GP_PIN(1, 18),  4, 3 },	/* A18 */
5649		{ RCAR_GP_PIN(1, 19),  0, 3 },	/* A19 */
5650	} },
5651	{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5652		{ RCAR_GP_PIN(1, 28), 28, 3 },	/* CLKOUT */
5653		{ RCAR_GP_PIN(1, 20), 24, 3 },	/* CS0 */
5654		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* CS1_A26 */
5655		{ RCAR_GP_PIN(1, 22), 16, 3 },	/* BS */
5656		{ RCAR_GP_PIN(1, 23), 12, 3 },	/* RD */
5657		{ RCAR_GP_PIN(1, 24),  8, 3 },	/* RD_WR */
5658		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* WE0 */
5659		{ RCAR_GP_PIN(1, 26),  0, 3 },	/* WE1 */
5660	} },
5661	{ PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5662		{ RCAR_GP_PIN(1, 27), 28, 3 },	/* EX_WAIT0 */
5663		{ PIN_PRESETOUT_N,    24, 3 },	/* PRESETOUT# */
5664		{ RCAR_GP_PIN(0,  0), 20, 3 },	/* D0 */
5665		{ RCAR_GP_PIN(0,  1), 16, 3 },	/* D1 */
5666		{ RCAR_GP_PIN(0,  2), 12, 3 },	/* D2 */
5667		{ RCAR_GP_PIN(0,  3),  8, 3 },	/* D3 */
5668		{ RCAR_GP_PIN(0,  4),  4, 3 },	/* D4 */
5669		{ RCAR_GP_PIN(0,  5),  0, 3 },	/* D5 */
5670	} },
5671	{ PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5672		{ RCAR_GP_PIN(0,  6), 28, 3 },	/* D6 */
5673		{ RCAR_GP_PIN(0,  7), 24, 3 },	/* D7 */
5674		{ RCAR_GP_PIN(0,  8), 20, 3 },	/* D8 */
5675		{ RCAR_GP_PIN(0,  9), 16, 3 },	/* D9 */
5676		{ RCAR_GP_PIN(0, 10), 12, 3 },	/* D10 */
5677		{ RCAR_GP_PIN(0, 11),  8, 3 },	/* D11 */
5678		{ RCAR_GP_PIN(0, 12),  4, 3 },	/* D12 */
5679		{ RCAR_GP_PIN(0, 13),  0, 3 },	/* D13 */
5680	} },
5681	{ PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5682		{ RCAR_GP_PIN(0, 14), 28, 3 },	/* D14 */
5683		{ RCAR_GP_PIN(0, 15), 24, 3 },	/* D15 */
5684		{ RCAR_GP_PIN(7,  0), 20, 3 },	/* AVS1 */
5685		{ RCAR_GP_PIN(7,  1), 16, 3 },	/* AVS2 */
5686		{ RCAR_GP_PIN(7,  2), 12, 3 },	/* GP7_02 */
5687		{ RCAR_GP_PIN(7,  3),  8, 3 },	/* GP7_03 */
5688		{ PIN_DU_DOTCLKIN0,    4, 2 },	/* DU_DOTCLKIN0 */
5689		{ PIN_DU_DOTCLKIN1,    0, 2 },	/* DU_DOTCLKIN1 */
5690	} },
5691	{ PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5692		{ PIN_DU_DOTCLKIN2,   28, 2 },	/* DU_DOTCLKIN2 */
5693		{ PIN_FSCLKST,        20, 2 },	/* FSCLKST */
5694		{ PIN_TMS,             4, 2 },	/* TMS */
5695	} },
5696	{ PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5697		{ PIN_TDO,            28, 2 },	/* TDO */
5698		{ PIN_ASEBRK,         24, 2 },	/* ASEBRK */
5699		{ RCAR_GP_PIN(3,  0), 20, 3 },	/* SD0_CLK */
5700		{ RCAR_GP_PIN(3,  1), 16, 3 },	/* SD0_CMD */
5701		{ RCAR_GP_PIN(3,  2), 12, 3 },	/* SD0_DAT0 */
5702		{ RCAR_GP_PIN(3,  3),  8, 3 },	/* SD0_DAT1 */
5703		{ RCAR_GP_PIN(3,  4),  4, 3 },	/* SD0_DAT2 */
5704		{ RCAR_GP_PIN(3,  5),  0, 3 },	/* SD0_DAT3 */
5705	} },
5706	{ PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5707		{ RCAR_GP_PIN(3,  6), 28, 3 },	/* SD1_CLK */
5708		{ RCAR_GP_PIN(3,  7), 24, 3 },	/* SD1_CMD */
5709		{ RCAR_GP_PIN(3,  8), 20, 3 },	/* SD1_DAT0 */
5710		{ RCAR_GP_PIN(3,  9), 16, 3 },	/* SD1_DAT1 */
5711		{ RCAR_GP_PIN(3, 10), 12, 3 },	/* SD1_DAT2 */
5712		{ RCAR_GP_PIN(3, 11),  8, 3 },	/* SD1_DAT3 */
5713		{ RCAR_GP_PIN(4,  0),  4, 3 },	/* SD2_CLK */
5714		{ RCAR_GP_PIN(4,  1),  0, 3 },	/* SD2_CMD */
5715	} },
5716	{ PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5717		{ RCAR_GP_PIN(4,  2), 28, 3 },	/* SD2_DAT0 */
5718		{ RCAR_GP_PIN(4,  3), 24, 3 },	/* SD2_DAT1 */
5719		{ RCAR_GP_PIN(4,  4), 20, 3 },	/* SD2_DAT2 */
5720		{ RCAR_GP_PIN(4,  5), 16, 3 },	/* SD2_DAT3 */
5721		{ RCAR_GP_PIN(4,  6), 12, 3 },	/* SD2_DS */
5722		{ RCAR_GP_PIN(4,  7),  8, 3 },	/* SD3_CLK */
5723		{ RCAR_GP_PIN(4,  8),  4, 3 },	/* SD3_CMD */
5724		{ RCAR_GP_PIN(4,  9),  0, 3 },	/* SD3_DAT0 */
5725	} },
5726	{ PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5727		{ RCAR_GP_PIN(4, 10), 28, 3 },	/* SD3_DAT1 */
5728		{ RCAR_GP_PIN(4, 11), 24, 3 },	/* SD3_DAT2 */
5729		{ RCAR_GP_PIN(4, 12), 20, 3 },	/* SD3_DAT3 */
5730		{ RCAR_GP_PIN(4, 13), 16, 3 },	/* SD3_DAT4 */
5731		{ RCAR_GP_PIN(4, 14), 12, 3 },	/* SD3_DAT5 */
5732		{ RCAR_GP_PIN(4, 15),  8, 3 },	/* SD3_DAT6 */
5733		{ RCAR_GP_PIN(4, 16),  4, 3 },	/* SD3_DAT7 */
5734		{ RCAR_GP_PIN(4, 17),  0, 3 },	/* SD3_DS */
5735	} },
5736	{ PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5737		{ RCAR_GP_PIN(3, 12), 28, 3 },	/* SD0_CD */
5738		{ RCAR_GP_PIN(3, 13), 24, 3 },	/* SD0_WP */
5739		{ RCAR_GP_PIN(3, 14), 20, 3 },	/* SD1_CD */
5740		{ RCAR_GP_PIN(3, 15), 16, 3 },	/* SD1_WP */
5741		{ RCAR_GP_PIN(5,  0), 12, 3 },	/* SCK0 */
5742		{ RCAR_GP_PIN(5,  1),  8, 3 },	/* RX0 */
5743		{ RCAR_GP_PIN(5,  2),  4, 3 },	/* TX0 */
5744		{ RCAR_GP_PIN(5,  3),  0, 3 },	/* CTS0 */
5745	} },
5746	{ PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5747		{ RCAR_GP_PIN(5,  4), 28, 3 },	/* RTS0 */
5748		{ RCAR_GP_PIN(5,  5), 24, 3 },	/* RX1 */
5749		{ RCAR_GP_PIN(5,  6), 20, 3 },	/* TX1 */
5750		{ RCAR_GP_PIN(5,  7), 16, 3 },	/* CTS1 */
5751		{ RCAR_GP_PIN(5,  8), 12, 3 },	/* RTS1 */
5752		{ RCAR_GP_PIN(5,  9),  8, 3 },	/* SCK2 */
5753		{ RCAR_GP_PIN(5, 10),  4, 3 },	/* TX2 */
5754		{ RCAR_GP_PIN(5, 11),  0, 3 },	/* RX2 */
5755	} },
5756	{ PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5757		{ RCAR_GP_PIN(5, 12), 28, 3 },	/* HSCK0 */
5758		{ RCAR_GP_PIN(5, 13), 24, 3 },	/* HRX0 */
5759		{ RCAR_GP_PIN(5, 14), 20, 3 },	/* HTX0 */
5760		{ RCAR_GP_PIN(5, 15), 16, 3 },	/* HCTS0 */
5761		{ RCAR_GP_PIN(5, 16), 12, 3 },	/* HRTS0 */
5762		{ RCAR_GP_PIN(5, 17),  8, 3 },	/* MSIOF0_SCK */
5763		{ RCAR_GP_PIN(5, 18),  4, 3 },	/* MSIOF0_SYNC */
5764		{ RCAR_GP_PIN(5, 19),  0, 3 },	/* MSIOF0_SS1 */
5765	} },
5766	{ PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5767		{ RCAR_GP_PIN(5, 20), 28, 3 },	/* MSIOF0_TXD */
5768		{ RCAR_GP_PIN(5, 21), 24, 3 },	/* MSIOF0_SS2 */
5769		{ RCAR_GP_PIN(5, 22), 20, 3 },	/* MSIOF0_RXD */
5770		{ RCAR_GP_PIN(5, 23), 16, 3 },	/* MLB_CLK */
5771		{ RCAR_GP_PIN(5, 24), 12, 3 },	/* MLB_SIG */
5772		{ RCAR_GP_PIN(5, 25),  8, 3 },	/* MLB_DAT */
5773		{ PIN_MLB_REF,         4, 3 },	/* MLB_REF */
5774		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* SSI_SCK01239 */
5775	} },
5776	{ PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5777		{ RCAR_GP_PIN(6,  1), 28, 3 },	/* SSI_WS01239 */
5778		{ RCAR_GP_PIN(6,  2), 24, 3 },	/* SSI_SDATA0 */
5779		{ RCAR_GP_PIN(6,  3), 20, 3 },	/* SSI_SDATA1 */
5780		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* SSI_SDATA2 */
5781		{ RCAR_GP_PIN(6,  5), 12, 3 },	/* SSI_SCK349 */
5782		{ RCAR_GP_PIN(6,  6),  8, 3 },	/* SSI_WS349 */
5783		{ RCAR_GP_PIN(6,  7),  4, 3 },	/* SSI_SDATA3 */
5784		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* SSI_SCK4 */
5785	} },
5786	{ PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5787		{ RCAR_GP_PIN(6,  9), 28, 3 },	/* SSI_WS4 */
5788		{ RCAR_GP_PIN(6, 10), 24, 3 },	/* SSI_SDATA4 */
5789		{ RCAR_GP_PIN(6, 11), 20, 3 },	/* SSI_SCK5 */
5790		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* SSI_WS5 */
5791		{ RCAR_GP_PIN(6, 13), 12, 3 },	/* SSI_SDATA5 */
5792		{ RCAR_GP_PIN(6, 14),  8, 3 },	/* SSI_SCK6 */
5793		{ RCAR_GP_PIN(6, 15),  4, 3 },	/* SSI_WS6 */
5794		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* SSI_SDATA6 */
5795	} },
5796	{ PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5797		{ RCAR_GP_PIN(6, 17), 28, 3 },	/* SSI_SCK78 */
5798		{ RCAR_GP_PIN(6, 18), 24, 3 },	/* SSI_WS78 */
5799		{ RCAR_GP_PIN(6, 19), 20, 3 },	/* SSI_SDATA7 */
5800		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* SSI_SDATA8 */
5801		{ RCAR_GP_PIN(6, 21), 12, 3 },	/* SSI_SDATA9 */
5802		{ RCAR_GP_PIN(6, 22),  8, 3 },	/* AUDIO_CLKA */
5803		{ RCAR_GP_PIN(6, 23),  4, 3 },	/* AUDIO_CLKB */
5804		{ RCAR_GP_PIN(6, 24),  0, 3 },	/* USB0_PWEN */
5805	} },
5806	{ PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5807		{ RCAR_GP_PIN(6, 25), 28, 3 },	/* USB0_OVC */
5808		{ RCAR_GP_PIN(6, 26), 24, 3 },	/* USB1_PWEN */
5809		{ RCAR_GP_PIN(6, 27), 20, 3 },	/* USB1_OVC */
5810		{ RCAR_GP_PIN(6, 28), 16, 3 },	/* USB30_PWEN */
5811		{ RCAR_GP_PIN(6, 29), 12, 3 },	/* USB30_OVC */
5812		{ RCAR_GP_PIN(6, 30),  8, 3 },	/* GP6_30 */
5813		{ RCAR_GP_PIN(6, 31),  4, 3 },	/* GP6_31 */
5814	} },
5815	{ /* sentinel */ }
5816};
5817
5818enum ioctrl_regs {
5819	POCCTRL,
5820	TDSELCTRL,
5821};
5822
5823static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5824	[POCCTRL] = { 0xe6060380, },
5825	[TDSELCTRL] = { 0xe60603c0, },
5826	{ /* sentinel */ }
5827};
5828
5829static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5830{
5831	int bit = -EINVAL;
5832
5833	*pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5834
5835	if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5836		bit = pin & 0x1f;
5837
5838	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5839		bit = (pin & 0x1f) + 12;
5840
5841	return bit;
5842}
5843
5844static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5845	{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5846		[ 0] = PIN_QSPI0_SPCLK,		/* QSPI0_SPCLK */
5847		[ 1] = PIN_QSPI0_MOSI_IO0,	/* QSPI0_MOSI_IO0 */
5848		[ 2] = PIN_QSPI0_MISO_IO1,	/* QSPI0_MISO_IO1 */
5849		[ 3] = PIN_QSPI0_IO2,		/* QSPI0_IO2 */
5850		[ 4] = PIN_QSPI0_IO3,		/* QSPI0_IO3 */
5851		[ 5] = PIN_QSPI0_SSL,		/* QSPI0_SSL */
5852		[ 6] = PIN_QSPI1_SPCLK,		/* QSPI1_SPCLK */
5853		[ 7] = PIN_QSPI1_MOSI_IO0,	/* QSPI1_MOSI_IO0 */
5854		[ 8] = PIN_QSPI1_MISO_IO1,	/* QSPI1_MISO_IO1 */
5855		[ 9] = PIN_QSPI1_IO2,		/* QSPI1_IO2 */
5856		[10] = PIN_QSPI1_IO3,		/* QSPI1_IO3 */
5857		[11] = PIN_QSPI1_SSL,		/* QSPI1_SSL */
5858		[12] = PIN_RPC_INT_N,		/* RPC_INT# */
5859		[13] = PIN_RPC_WP_N,		/* RPC_WP# */
5860		[14] = PIN_RPC_RESET_N,		/* RPC_RESET# */
5861		[15] = PIN_AVB_RX_CTL,		/* AVB_RX_CTL */
5862		[16] = PIN_AVB_RXC,		/* AVB_RXC */
5863		[17] = PIN_AVB_RD0,		/* AVB_RD0 */
5864		[18] = PIN_AVB_RD1,		/* AVB_RD1 */
5865		[19] = PIN_AVB_RD2,		/* AVB_RD2 */
5866		[20] = PIN_AVB_RD3,		/* AVB_RD3 */
5867		[21] = PIN_AVB_TX_CTL,		/* AVB_TX_CTL */
5868		[22] = PIN_AVB_TXC,		/* AVB_TXC */
5869		[23] = PIN_AVB_TD0,		/* AVB_TD0 */
5870		[24] = PIN_AVB_TD1,		/* AVB_TD1 */
5871		[25] = PIN_AVB_TD2,		/* AVB_TD2 */
5872		[26] = PIN_AVB_TD3,		/* AVB_TD3 */
5873		[27] = PIN_AVB_TXCREFCLK,	/* AVB_TXCREFCLK */
5874		[28] = PIN_AVB_MDIO,		/* AVB_MDIO */
5875		[29] = RCAR_GP_PIN(2,  9),	/* AVB_MDC */
5876		[30] = RCAR_GP_PIN(2, 10),	/* AVB_MAGIC */
5877		[31] = RCAR_GP_PIN(2, 11),	/* AVB_PHY_INT */
5878	} },
5879	{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5880		[ 0] = RCAR_GP_PIN(2, 12),	/* AVB_LINK */
5881		[ 1] = RCAR_GP_PIN(2, 13),	/* AVB_AVTP_MATCH_A */
5882		[ 2] = RCAR_GP_PIN(2, 14),	/* AVB_AVTP_CAPTURE_A */
5883		[ 3] = RCAR_GP_PIN(2,  0),	/* IRQ0 */
5884		[ 4] = RCAR_GP_PIN(2,  1),	/* IRQ1 */
5885		[ 5] = RCAR_GP_PIN(2,  2),	/* IRQ2 */
5886		[ 6] = RCAR_GP_PIN(2,  3),	/* IRQ3 */
5887		[ 7] = RCAR_GP_PIN(2,  4),	/* IRQ4 */
5888		[ 8] = RCAR_GP_PIN(2,  5),	/* IRQ5 */
5889		[ 9] = RCAR_GP_PIN(2,  6),	/* PWM0 */
5890		[10] = RCAR_GP_PIN(2,  7),	/* PWM1_A */
5891		[11] = RCAR_GP_PIN(2,  8),	/* PWM2_A */
5892		[12] = RCAR_GP_PIN(1,  0),	/* A0 */
5893		[13] = RCAR_GP_PIN(1,  1),	/* A1 */
5894		[14] = RCAR_GP_PIN(1,  2),	/* A2 */
5895		[15] = RCAR_GP_PIN(1,  3),	/* A3 */
5896		[16] = RCAR_GP_PIN(1,  4),	/* A4 */
5897		[17] = RCAR_GP_PIN(1,  5),	/* A5 */
5898		[18] = RCAR_GP_PIN(1,  6),	/* A6 */
5899		[19] = RCAR_GP_PIN(1,  7),	/* A7 */
5900		[20] = RCAR_GP_PIN(1,  8),	/* A8 */
5901		[21] = RCAR_GP_PIN(1,  9),	/* A9 */
5902		[22] = RCAR_GP_PIN(1, 10),	/* A10 */
5903		[23] = RCAR_GP_PIN(1, 11),	/* A11 */
5904		[24] = RCAR_GP_PIN(1, 12),	/* A12 */
5905		[25] = RCAR_GP_PIN(1, 13),	/* A13 */
5906		[26] = RCAR_GP_PIN(1, 14),	/* A14 */
5907		[27] = RCAR_GP_PIN(1, 15),	/* A15 */
5908		[28] = RCAR_GP_PIN(1, 16),	/* A16 */
5909		[29] = RCAR_GP_PIN(1, 17),	/* A17 */
5910		[30] = RCAR_GP_PIN(1, 18),	/* A18 */
5911		[31] = RCAR_GP_PIN(1, 19),	/* A19 */
5912	} },
5913	{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5914		[ 0] = RCAR_GP_PIN(1, 28),	/* CLKOUT */
5915		[ 1] = RCAR_GP_PIN(1, 20),	/* CS0_N */
5916		[ 2] = RCAR_GP_PIN(1, 21),	/* CS1_N */
5917		[ 3] = RCAR_GP_PIN(1, 22),	/* BS_N */
5918		[ 4] = RCAR_GP_PIN(1, 23),	/* RD_N */
5919		[ 5] = RCAR_GP_PIN(1, 24),	/* RD_WR_N */
5920		[ 6] = RCAR_GP_PIN(1, 25),	/* WE0_N */
5921		[ 7] = RCAR_GP_PIN(1, 26),	/* WE1_N */
5922		[ 8] = RCAR_GP_PIN(1, 27),	/* EX_WAIT0_A */
5923		[ 9] = PIN_PRESETOUT_N,		/* PRESETOUT# */
5924		[10] = RCAR_GP_PIN(0,  0),	/* D0 */
5925		[11] = RCAR_GP_PIN(0,  1),	/* D1 */
5926		[12] = RCAR_GP_PIN(0,  2),	/* D2 */
5927		[13] = RCAR_GP_PIN(0,  3),	/* D3 */
5928		[14] = RCAR_GP_PIN(0,  4),	/* D4 */
5929		[15] = RCAR_GP_PIN(0,  5),	/* D5 */
5930		[16] = RCAR_GP_PIN(0,  6),	/* D6 */
5931		[17] = RCAR_GP_PIN(0,  7),	/* D7 */
5932		[18] = RCAR_GP_PIN(0,  8),	/* D8 */
5933		[19] = RCAR_GP_PIN(0,  9),	/* D9 */
5934		[20] = RCAR_GP_PIN(0, 10),	/* D10 */
5935		[21] = RCAR_GP_PIN(0, 11),	/* D11 */
5936		[22] = RCAR_GP_PIN(0, 12),	/* D12 */
5937		[23] = RCAR_GP_PIN(0, 13),	/* D13 */
5938		[24] = RCAR_GP_PIN(0, 14),	/* D14 */
5939		[25] = RCAR_GP_PIN(0, 15),	/* D15 */
5940		[26] = RCAR_GP_PIN(7,  0),	/* AVS1 */
5941		[27] = RCAR_GP_PIN(7,  1),	/* AVS2 */
5942		[28] = RCAR_GP_PIN(7,  2),	/* GP7_02 */
5943		[29] = RCAR_GP_PIN(7,  3),	/* GP7_03 */
5944		[30] = PIN_DU_DOTCLKIN0,	/* DU_DOTCLKIN0 */
5945		[31] = PIN_DU_DOTCLKIN1,	/* DU_DOTCLKIN1 */
5946	} },
5947	{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5948		[ 0] = PIN_DU_DOTCLKIN2,	/* DU_DOTCLKIN2 */
5949		[ 1] = SH_PFC_PIN_NONE,
5950		[ 2] = PIN_FSCLKST,		/* FSCLKST */
5951		[ 3] = PIN_EXTALR,		/* EXTALR*/
5952		[ 4] = PIN_TRST_N,		/* TRST# */
5953		[ 5] = PIN_TCK,			/* TCK */
5954		[ 6] = PIN_TMS,			/* TMS */
5955		[ 7] = PIN_TDI,			/* TDI */
5956		[ 8] = SH_PFC_PIN_NONE,
5957		[ 9] = PIN_ASEBRK,		/* ASEBRK */
5958		[10] = RCAR_GP_PIN(3,  0),	/* SD0_CLK */
5959		[11] = RCAR_GP_PIN(3,  1),	/* SD0_CMD */
5960		[12] = RCAR_GP_PIN(3,  2),	/* SD0_DAT0 */
5961		[13] = RCAR_GP_PIN(3,  3),	/* SD0_DAT1 */
5962		[14] = RCAR_GP_PIN(3,  4),	/* SD0_DAT2 */
5963		[15] = RCAR_GP_PIN(3,  5),	/* SD0_DAT3 */
5964		[16] = RCAR_GP_PIN(3,  6),	/* SD1_CLK */
5965		[17] = RCAR_GP_PIN(3,  7),	/* SD1_CMD */
5966		[18] = RCAR_GP_PIN(3,  8),	/* SD1_DAT0 */
5967		[19] = RCAR_GP_PIN(3,  9),	/* SD1_DAT1 */
5968		[20] = RCAR_GP_PIN(3, 10),	/* SD1_DAT2 */
5969		[21] = RCAR_GP_PIN(3, 11),	/* SD1_DAT3 */
5970		[22] = RCAR_GP_PIN(4,  0),	/* SD2_CLK */
5971		[23] = RCAR_GP_PIN(4,  1),	/* SD2_CMD */
5972		[24] = RCAR_GP_PIN(4,  2),	/* SD2_DAT0 */
5973		[25] = RCAR_GP_PIN(4,  3),	/* SD2_DAT1 */
5974		[26] = RCAR_GP_PIN(4,  4),	/* SD2_DAT2 */
5975		[27] = RCAR_GP_PIN(4,  5),	/* SD2_DAT3 */
5976		[28] = RCAR_GP_PIN(4,  6),	/* SD2_DS */
5977		[29] = RCAR_GP_PIN(4,  7),	/* SD3_CLK */
5978		[30] = RCAR_GP_PIN(4,  8),	/* SD3_CMD */
5979		[31] = RCAR_GP_PIN(4,  9),	/* SD3_DAT0 */
5980	} },
5981	{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5982		[ 0] = RCAR_GP_PIN(4, 10),	/* SD3_DAT1 */
5983		[ 1] = RCAR_GP_PIN(4, 11),	/* SD3_DAT2 */
5984		[ 2] = RCAR_GP_PIN(4, 12),	/* SD3_DAT3 */
5985		[ 3] = RCAR_GP_PIN(4, 13),	/* SD3_DAT4 */
5986		[ 4] = RCAR_GP_PIN(4, 14),	/* SD3_DAT5 */
5987		[ 5] = RCAR_GP_PIN(4, 15),	/* SD3_DAT6 */
5988		[ 6] = RCAR_GP_PIN(4, 16),	/* SD3_DAT7 */
5989		[ 7] = RCAR_GP_PIN(4, 17),	/* SD3_DS */
5990		[ 8] = RCAR_GP_PIN(3, 12),	/* SD0_CD */
5991		[ 9] = RCAR_GP_PIN(3, 13),	/* SD0_WP */
5992		[10] = RCAR_GP_PIN(3, 14),	/* SD1_CD */
5993		[11] = RCAR_GP_PIN(3, 15),	/* SD1_WP */
5994		[12] = RCAR_GP_PIN(5,  0),	/* SCK0 */
5995		[13] = RCAR_GP_PIN(5,  1),	/* RX0 */
5996		[14] = RCAR_GP_PIN(5,  2),	/* TX0 */
5997		[15] = RCAR_GP_PIN(5,  3),	/* CTS0_N */
5998		[16] = RCAR_GP_PIN(5,  4),	/* RTS0_N */
5999		[17] = RCAR_GP_PIN(5,  5),	/* RX1_A */
6000		[18] = RCAR_GP_PIN(5,  6),	/* TX1_A */
6001		[19] = RCAR_GP_PIN(5,  7),	/* CTS1_N */
6002		[20] = RCAR_GP_PIN(5,  8),	/* RTS1_N */
6003		[21] = RCAR_GP_PIN(5,  9),	/* SCK2 */
6004		[22] = RCAR_GP_PIN(5, 10),	/* TX2_A */
6005		[23] = RCAR_GP_PIN(5, 11),	/* RX2_A */
6006		[24] = RCAR_GP_PIN(5, 12),	/* HSCK0 */
6007		[25] = RCAR_GP_PIN(5, 13),	/* HRX0 */
6008		[26] = RCAR_GP_PIN(5, 14),	/* HTX0 */
6009		[27] = RCAR_GP_PIN(5, 15),	/* HCTS0_N */
6010		[28] = RCAR_GP_PIN(5, 16),	/* HRTS0_N */
6011		[29] = RCAR_GP_PIN(5, 17),	/* MSIOF0_SCK */
6012		[30] = RCAR_GP_PIN(5, 18),	/* MSIOF0_SYNC */
6013		[31] = RCAR_GP_PIN(5, 19),	/* MSIOF0_SS1 */
6014	} },
6015	{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6016		[ 0] = RCAR_GP_PIN(5, 20),	/* MSIOF0_TXD */
6017		[ 1] = RCAR_GP_PIN(5, 21),	/* MSIOF0_SS2 */
6018		[ 2] = RCAR_GP_PIN(5, 22),	/* MSIOF0_RXD */
6019		[ 3] = RCAR_GP_PIN(5, 23),	/* MLB_CLK */
6020		[ 4] = RCAR_GP_PIN(5, 24),	/* MLB_SIG */
6021		[ 5] = RCAR_GP_PIN(5, 25),	/* MLB_DAT */
6022		[ 6] = PIN_MLB_REF,		/* MLB_REF */
6023		[ 7] = RCAR_GP_PIN(6,  0),	/* SSI_SCK01239 */
6024		[ 8] = RCAR_GP_PIN(6,  1),	/* SSI_WS01239 */
6025		[ 9] = RCAR_GP_PIN(6,  2),	/* SSI_SDATA0 */
6026		[10] = RCAR_GP_PIN(6,  3),	/* SSI_SDATA1_A */
6027		[11] = RCAR_GP_PIN(6,  4),	/* SSI_SDATA2_A */
6028		[12] = RCAR_GP_PIN(6,  5),	/* SSI_SCK349 */
6029		[13] = RCAR_GP_PIN(6,  6),	/* SSI_WS349 */
6030		[14] = RCAR_GP_PIN(6,  7),	/* SSI_SDATA3 */
6031		[15] = RCAR_GP_PIN(6,  8),	/* SSI_SCK4 */
6032		[16] = RCAR_GP_PIN(6,  9),	/* SSI_WS4 */
6033		[17] = RCAR_GP_PIN(6, 10),	/* SSI_SDATA4 */
6034		[18] = RCAR_GP_PIN(6, 11),	/* SSI_SCK5 */
6035		[19] = RCAR_GP_PIN(6, 12),	/* SSI_WS5 */
6036		[20] = RCAR_GP_PIN(6, 13),	/* SSI_SDATA5 */
6037		[21] = RCAR_GP_PIN(6, 14),	/* SSI_SCK6 */
6038		[22] = RCAR_GP_PIN(6, 15),	/* SSI_WS6 */
6039		[23] = RCAR_GP_PIN(6, 16),	/* SSI_SDATA6 */
6040		[24] = RCAR_GP_PIN(6, 17),	/* SSI_SCK78 */
6041		[25] = RCAR_GP_PIN(6, 18),	/* SSI_WS78 */
6042		[26] = RCAR_GP_PIN(6, 19),	/* SSI_SDATA7 */
6043		[27] = RCAR_GP_PIN(6, 20),	/* SSI_SDATA8 */
6044		[28] = RCAR_GP_PIN(6, 21),	/* SSI_SDATA9_A */
6045		[29] = RCAR_GP_PIN(6, 22),	/* AUDIO_CLKA_A */
6046		[30] = RCAR_GP_PIN(6, 23),	/* AUDIO_CLKB_B */
6047		[31] = RCAR_GP_PIN(6, 24),	/* USB0_PWEN */
6048	} },
6049	{ PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6050		[ 0] = RCAR_GP_PIN(6, 25),	/* USB0_OVC */
6051		[ 1] = RCAR_GP_PIN(6, 26),	/* USB1_PWEN */
6052		[ 2] = RCAR_GP_PIN(6, 27),	/* USB1_OVC */
6053		[ 3] = RCAR_GP_PIN(6, 28),	/* USB30_PWEN */
6054		[ 4] = RCAR_GP_PIN(6, 29),	/* USB30_OVC */
6055		[ 5] = RCAR_GP_PIN(6, 30),	/* GP6_30 */
6056		[ 6] = RCAR_GP_PIN(6, 31),	/* GP6_31 */
6057		[ 7] = PIN_PRESET_N,		/* PRESET# */
6058		[ 8] = SH_PFC_PIN_NONE,
6059		[ 9] = SH_PFC_PIN_NONE,
6060		[10] = SH_PFC_PIN_NONE,
6061		[11] = SH_PFC_PIN_NONE,
6062		[12] = SH_PFC_PIN_NONE,
6063		[13] = SH_PFC_PIN_NONE,
6064		[14] = SH_PFC_PIN_NONE,
6065		[15] = SH_PFC_PIN_NONE,
6066		[16] = SH_PFC_PIN_NONE,
6067		[17] = SH_PFC_PIN_NONE,
6068		[18] = SH_PFC_PIN_NONE,
6069		[19] = SH_PFC_PIN_NONE,
6070		[20] = SH_PFC_PIN_NONE,
6071		[21] = SH_PFC_PIN_NONE,
6072		[22] = SH_PFC_PIN_NONE,
6073		[23] = SH_PFC_PIN_NONE,
6074		[24] = SH_PFC_PIN_NONE,
6075		[25] = SH_PFC_PIN_NONE,
6076		[26] = SH_PFC_PIN_NONE,
6077		[27] = SH_PFC_PIN_NONE,
6078		[28] = SH_PFC_PIN_NONE,
6079		[29] = SH_PFC_PIN_NONE,
6080		[30] = SH_PFC_PIN_NONE,
6081		[31] = SH_PFC_PIN_NONE,
6082	} },
6083	{ /* sentinel */ }
6084};
6085
6086static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
6087	.pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6088	.get_bias = rcar_pinmux_get_bias,
6089	.set_bias = rcar_pinmux_set_bias,
6090};
6091
6092#ifdef CONFIG_PINCTRL_PFC_R8A774A1
6093const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6094	.name = "r8a774a1_pfc",
6095	.ops = &r8a7796_pfc_ops,
6096	.unlock_reg = 0xe6060000, /* PMMR */
6097
6098	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6099
6100	.pins = pinmux_pins,
6101	.nr_pins = ARRAY_SIZE(pinmux_pins),
6102	.groups = pinmux_groups.common,
6103	.nr_groups = ARRAY_SIZE(pinmux_groups.common),
6104	.functions = pinmux_functions.common,
6105	.nr_functions = ARRAY_SIZE(pinmux_functions.common),
6106
6107	.cfg_regs = pinmux_config_regs,
6108	.drive_regs = pinmux_drive_regs,
6109	.bias_regs = pinmux_bias_regs,
6110	.ioctrl_regs = pinmux_ioctrl_regs,
6111
6112	.pinmux_data = pinmux_data,
6113	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6114};
6115#endif
6116
6117#ifdef CONFIG_PINCTRL_PFC_R8A77960
6118const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6119	.name = "r8a77960_pfc",
6120	.ops = &r8a7796_pfc_ops,
6121	.unlock_reg = 0xe6060000, /* PMMR */
6122
6123	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6124
6125	.pins = pinmux_pins,
6126	.nr_pins = ARRAY_SIZE(pinmux_pins),
6127	.groups = pinmux_groups.common,
6128	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6129		ARRAY_SIZE(pinmux_groups.automotive),
6130	.functions = pinmux_functions.common,
6131	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6132		ARRAY_SIZE(pinmux_functions.automotive),
6133
6134	.cfg_regs = pinmux_config_regs,
6135	.drive_regs = pinmux_drive_regs,
6136	.bias_regs = pinmux_bias_regs,
6137	.ioctrl_regs = pinmux_ioctrl_regs,
6138
6139	.pinmux_data = pinmux_data,
6140	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6141};
6142#endif
6143
6144#ifdef CONFIG_PINCTRL_PFC_R8A77961
6145const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6146	.name = "r8a77961_pfc",
6147	.ops = &r8a7796_pfc_ops,
6148	.unlock_reg = 0xe6060000, /* PMMR */
6149
6150	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6151
6152	.pins = pinmux_pins,
6153	.nr_pins = ARRAY_SIZE(pinmux_pins),
6154	.groups = pinmux_groups.common,
6155	.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6156		ARRAY_SIZE(pinmux_groups.automotive),
6157	.functions = pinmux_functions.common,
6158	.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6159		ARRAY_SIZE(pinmux_functions.automotive),
6160
6161	.cfg_regs = pinmux_config_regs,
6162	.drive_regs = pinmux_drive_regs,
6163	.bias_regs = pinmux_bias_regs,
6164	.ioctrl_regs = pinmux_ioctrl_regs,
6165
6166	.pinmux_data = pinmux_data,
6167	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6168};
6169#endif