pfc-r8a73a4.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2012-2013  Renesas Solutions Corp.
   4 * Copyright (C) 2013  Magnus Damm
   5 * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6 */
   7#include <linux/io.h>
   8#include <linux/kernel.h>
   9#include <linux/pinctrl/pinconf-generic.h>
  10
  11#include "sh_pfc.h"
  12
  13#define CPU_ALL_PORT(fn, pfx, sfx)					\
  14	/*  Port0 - Port30 */						\
  15	PORT_10(0, fn, pfx, sfx),					\
  16	PORT_10(10, fn, pfx##1, sfx),					\
  17	PORT_10(20, fn, pfx##2, sfx),					\
  18	PORT_1(30, fn, pfx##30, sfx),					\
  19	/* Port32 - Port40 */						\
  20	PORT_1(32, fn, pfx##32, sfx),	PORT_1(33, fn, pfx##33, sfx),	\
  21	PORT_1(34, fn, pfx##34, sfx),	PORT_1(35, fn, pfx##35, sfx),	\
  22	PORT_1(36, fn, pfx##36, sfx),	PORT_1(37, fn, pfx##37, sfx),	\
  23	PORT_1(38, fn, pfx##38, sfx),	PORT_1(39, fn, pfx##39, sfx),	\
  24	PORT_1(40, fn, pfx##40, sfx),					\
  25	/* Port64  - Port85 */						\
  26	PORT_1(64, fn, pfx##64, sfx),	PORT_1(65, fn, pfx##65, sfx),	\
  27	PORT_1(66, fn, pfx##66, sfx),	PORT_1(67, fn, pfx##67, sfx),	\
  28	PORT_1(68, fn, pfx##68, sfx),	PORT_1(69, fn, pfx##69, sfx),	\
  29	PORT_10(70, fn, pfx##7, sfx),					\
  30	PORT_1(80, fn, pfx##80, sfx),	PORT_1(81, fn, pfx##81, sfx),	\
  31	PORT_1(82, fn, pfx##82, sfx),	PORT_1(83, fn, pfx##83, sfx),	\
  32	PORT_1(84, fn, pfx##84, sfx),	PORT_1(85, fn, pfx##85, sfx),	\
  33	/* Port96  - Port126 */						\
  34	PORT_1(96, fn, pfx##96, sfx),	PORT_1(97, fn, pfx##97, sfx),	\
  35	PORT_1(98, fn, pfx##98, sfx),	PORT_1(99, fn, pfx##99, sfx),	\
  36	PORT_10(100, fn, pfx##10, sfx),					\
  37	PORT_10(110, fn, pfx##11, sfx),					\
  38	PORT_1(120, fn, pfx##120, sfx),	PORT_1(121, fn, pfx##121, sfx),	\
  39	PORT_1(122, fn, pfx##122, sfx),	PORT_1(123, fn, pfx##123, sfx),	\
  40	PORT_1(124, fn, pfx##124, sfx),	PORT_1(125, fn, pfx##125, sfx),	\
  41	PORT_1(126, fn, pfx##126, sfx),					\
  42	/* Port128 - Port134 */						\
  43	PORT_1(128, fn, pfx##128, sfx),	PORT_1(129, fn, pfx##129, sfx),	\
  44	PORT_1(130, fn, pfx##130, sfx),	PORT_1(131, fn, pfx##131, sfx),	\
  45	PORT_1(132, fn, pfx##132, sfx),	PORT_1(133, fn, pfx##133, sfx),	\
  46	PORT_1(134, fn, pfx##134, sfx),					\
  47	/* Port160 - Port178 */						\
  48	PORT_10(160, fn, pfx##16, sfx),					\
  49	PORT_1(170, fn, pfx##170, sfx),	PORT_1(171, fn, pfx##171, sfx),	\
  50	PORT_1(172, fn, pfx##172, sfx),	PORT_1(173, fn, pfx##173, sfx),	\
  51	PORT_1(174, fn, pfx##174, sfx),	PORT_1(175, fn, pfx##175, sfx),	\
  52	PORT_1(176, fn, pfx##176, sfx),	PORT_1(177, fn, pfx##177, sfx),	\
  53	PORT_1(178, fn, pfx##178, sfx),					\
  54	/* Port192 - Port222 */						\
  55	PORT_1(192, fn, pfx##192, sfx),	PORT_1(193, fn, pfx##193, sfx),	\
  56	PORT_1(194, fn, pfx##194, sfx),	PORT_1(195, fn, pfx##195, sfx),	\
  57	PORT_1(196, fn, pfx##196, sfx),	PORT_1(197, fn, pfx##197, sfx),	\
  58	PORT_1(198, fn, pfx##198, sfx),	PORT_1(199, fn, pfx##199, sfx),	\
  59	PORT_10(200, fn, pfx##20, sfx),					\
  60	PORT_10(210, fn, pfx##21, sfx),					\
  61	PORT_1(220, fn, pfx##220, sfx),	PORT_1(221, fn, pfx##221, sfx),	\
  62	PORT_1(222, fn, pfx##222, sfx),					\
  63	/* Port224 - Port250 */						\
  64	PORT_1(224, fn, pfx##224, sfx),	PORT_1(225, fn, pfx##225, sfx),	\
  65	PORT_1(226, fn, pfx##226, sfx),	PORT_1(227, fn, pfx##227, sfx),	\
  66	PORT_1(228, fn, pfx##228, sfx),	PORT_1(229, fn, pfx##229, sfx),	\
  67	PORT_10(230, fn, pfx##23, sfx),					\
  68	PORT_10(240, fn, pfx##24, sfx),					\
  69	PORT_1(250, fn, pfx##250, sfx),					\
  70	/* Port256 - Port283 */						\
  71	PORT_1(256, fn, pfx##256, sfx),	PORT_1(257, fn, pfx##257, sfx),	\
  72	PORT_1(258, fn, pfx##258, sfx),	PORT_1(259, fn, pfx##259, sfx),	\
  73	PORT_10(260, fn, pfx##26, sfx),					\
  74	PORT_10(270, fn, pfx##27, sfx),					\
  75	PORT_1(280, fn, pfx##280, sfx),	PORT_1(281, fn, pfx##281, sfx),	\
  76	PORT_1(282, fn, pfx##282, sfx),	PORT_1(283, fn, pfx##283, sfx),	\
  77	/* Port288 - Port308 */						\
  78	PORT_1(288, fn, pfx##288, sfx),	PORT_1(289, fn, pfx##289, sfx),	\
  79	PORT_10(290, fn, pfx##29, sfx),					\
  80	PORT_1(300, fn, pfx##300, sfx),	PORT_1(301, fn, pfx##301, sfx),	\
  81	PORT_1(302, fn, pfx##302, sfx),	PORT_1(303, fn, pfx##303, sfx),	\
  82	PORT_1(304, fn, pfx##304, sfx),	PORT_1(305, fn, pfx##305, sfx),	\
  83	PORT_1(306, fn, pfx##306, sfx),	PORT_1(307, fn, pfx##307, sfx),	\
  84	PORT_1(308, fn, pfx##308, sfx),					\
  85	/* Port320 - Port329 */						\
  86	PORT_10(320, fn, pfx##32, sfx)
  87
  88enum {
  89	PINMUX_RESERVED = 0,
  90
  91	/* PORT0_DATA -> PORT329_DATA */
  92	PINMUX_DATA_BEGIN,
  93	PORT_ALL(DATA),
  94	PINMUX_DATA_END,
  95
  96	/* PORT0_IN -> PORT329_IN */
  97	PINMUX_INPUT_BEGIN,
  98	PORT_ALL(IN),
  99	PINMUX_INPUT_END,
 100
 101	/* PORT0_OUT -> PORT329_OUT */
 102	PINMUX_OUTPUT_BEGIN,
 103	PORT_ALL(OUT),
 104	PINMUX_OUTPUT_END,
 105
 106	PINMUX_FUNCTION_BEGIN,
 107	PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
 108	PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
 109	PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
 110	PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
 111	PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
 112	PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
 113	PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
 114	PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
 115	PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
 116	PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
 117
 118	MSEL1CR_31_0, MSEL1CR_31_1,
 119	MSEL1CR_27_0, MSEL1CR_27_1,
 120	MSEL1CR_25_0, MSEL1CR_25_1,
 121	MSEL1CR_24_0, MSEL1CR_24_1,
 122	MSEL1CR_22_0, MSEL1CR_22_1,
 123	MSEL1CR_21_0, MSEL1CR_21_1,
 124	MSEL1CR_20_0, MSEL1CR_20_1,
 125	MSEL1CR_19_0, MSEL1CR_19_1,
 126	MSEL1CR_18_0, MSEL1CR_18_1,
 127	MSEL1CR_17_0, MSEL1CR_17_1,
 128	MSEL1CR_16_0, MSEL1CR_16_1,
 129	MSEL1CR_15_0, MSEL1CR_15_1,
 130	MSEL1CR_14_0, MSEL1CR_14_1,
 131	MSEL1CR_13_0, MSEL1CR_13_1,
 132	MSEL1CR_12_0, MSEL1CR_12_1,
 133	MSEL1CR_11_0, MSEL1CR_11_1,
 134	MSEL1CR_10_0, MSEL1CR_10_1,
 135	MSEL1CR_09_0, MSEL1CR_09_1,
 136	MSEL1CR_08_0, MSEL1CR_08_1,
 137	MSEL1CR_07_0, MSEL1CR_07_1,
 138	MSEL1CR_06_0, MSEL1CR_06_1,
 139	MSEL1CR_05_0, MSEL1CR_05_1,
 140	MSEL1CR_04_0, MSEL1CR_04_1,
 141	MSEL1CR_03_0, MSEL1CR_03_1,
 142	MSEL1CR_02_0, MSEL1CR_02_1,
 143	MSEL1CR_01_0, MSEL1CR_01_1,
 144	MSEL1CR_00_0, MSEL1CR_00_1,
 145
 146	MSEL3CR_31_0, MSEL3CR_31_1,
 147	MSEL3CR_28_0, MSEL3CR_28_1,
 148	MSEL3CR_27_0, MSEL3CR_27_1,
 149	MSEL3CR_26_0, MSEL3CR_26_1,
 150	MSEL3CR_23_0, MSEL3CR_23_1,
 151	MSEL3CR_22_0, MSEL3CR_22_1,
 152	MSEL3CR_21_0, MSEL3CR_21_1,
 153	MSEL3CR_20_0, MSEL3CR_20_1,
 154	MSEL3CR_19_0, MSEL3CR_19_1,
 155	MSEL3CR_18_0, MSEL3CR_18_1,
 156	MSEL3CR_17_0, MSEL3CR_17_1,
 157	MSEL3CR_16_0, MSEL3CR_16_1,
 158	MSEL3CR_15_0, MSEL3CR_15_1,
 159	MSEL3CR_12_0, MSEL3CR_12_1,
 160	MSEL3CR_11_0, MSEL3CR_11_1,
 161	MSEL3CR_10_0, MSEL3CR_10_1,
 162	MSEL3CR_09_0, MSEL3CR_09_1,
 163	MSEL3CR_06_0, MSEL3CR_06_1,
 164	MSEL3CR_03_0, MSEL3CR_03_1,
 165	MSEL3CR_01_0, MSEL3CR_01_1,
 166	MSEL3CR_00_0, MSEL3CR_00_1,
 167
 168	MSEL4CR_30_0, MSEL4CR_30_1,
 169	MSEL4CR_29_0, MSEL4CR_29_1,
 170	MSEL4CR_28_0, MSEL4CR_28_1,
 171	MSEL4CR_27_0, MSEL4CR_27_1,
 172	MSEL4CR_26_0, MSEL4CR_26_1,
 173	MSEL4CR_25_0, MSEL4CR_25_1,
 174	MSEL4CR_24_0, MSEL4CR_24_1,
 175	MSEL4CR_23_0, MSEL4CR_23_1,
 176	MSEL4CR_22_0, MSEL4CR_22_1,
 177	MSEL4CR_21_0, MSEL4CR_21_1,
 178	MSEL4CR_20_0, MSEL4CR_20_1,
 179	MSEL4CR_19_0, MSEL4CR_19_1,
 180	MSEL4CR_18_0, MSEL4CR_18_1,
 181	MSEL4CR_17_0, MSEL4CR_17_1,
 182	MSEL4CR_16_0, MSEL4CR_16_1,
 183	MSEL4CR_15_0, MSEL4CR_15_1,
 184	MSEL4CR_14_0, MSEL4CR_14_1,
 185	MSEL4CR_13_0, MSEL4CR_13_1,
 186	MSEL4CR_12_0, MSEL4CR_12_1,
 187	MSEL4CR_11_0, MSEL4CR_11_1,
 188	MSEL4CR_10_0, MSEL4CR_10_1,
 189	MSEL4CR_09_0, MSEL4CR_09_1,
 190	MSEL4CR_07_0, MSEL4CR_07_1,
 191	MSEL4CR_04_0, MSEL4CR_04_1,
 192	MSEL4CR_01_0, MSEL4CR_01_1,
 193
 194	MSEL5CR_31_0, MSEL5CR_31_1,
 195	MSEL5CR_30_0, MSEL5CR_30_1,
 196	MSEL5CR_29_0, MSEL5CR_29_1,
 197	MSEL5CR_28_0, MSEL5CR_28_1,
 198	MSEL5CR_27_0, MSEL5CR_27_1,
 199	MSEL5CR_26_0, MSEL5CR_26_1,
 200	MSEL5CR_25_0, MSEL5CR_25_1,
 201	MSEL5CR_24_0, MSEL5CR_24_1,
 202	MSEL5CR_23_0, MSEL5CR_23_1,
 203	MSEL5CR_22_0, MSEL5CR_22_1,
 204	MSEL5CR_21_0, MSEL5CR_21_1,
 205	MSEL5CR_20_0, MSEL5CR_20_1,
 206	MSEL5CR_19_0, MSEL5CR_19_1,
 207	MSEL5CR_18_0, MSEL5CR_18_1,
 208	MSEL5CR_17_0, MSEL5CR_17_1,
 209	MSEL5CR_16_0, MSEL5CR_16_1,
 210	MSEL5CR_15_0, MSEL5CR_15_1,
 211	MSEL5CR_14_0, MSEL5CR_14_1,
 212	MSEL5CR_13_0, MSEL5CR_13_1,
 213	MSEL5CR_12_0, MSEL5CR_12_1,
 214	MSEL5CR_11_0, MSEL5CR_11_1,
 215	MSEL5CR_10_0, MSEL5CR_10_1,
 216	MSEL5CR_09_0, MSEL5CR_09_1,
 217	MSEL5CR_08_0, MSEL5CR_08_1,
 218	MSEL5CR_07_0, MSEL5CR_07_1,
 219	MSEL5CR_06_0, MSEL5CR_06_1,
 220
 221	MSEL8CR_16_0, MSEL8CR_16_1,
 222	MSEL8CR_01_0, MSEL8CR_01_1,
 223	MSEL8CR_00_0, MSEL8CR_00_1,
 224
 225	PINMUX_FUNCTION_END,
 226
 227	PINMUX_MARK_BEGIN,
 228
 229#define F1(a)	a##_MARK
 230#define F2(a)	a##_MARK
 231#define F3(a)	a##_MARK
 232#define F4(a)	a##_MARK
 233#define F5(a)	a##_MARK
 234#define F6(a)	a##_MARK
 235#define F7(a)	a##_MARK
 236#define IRQ(a)	IRQ##a##_MARK
 237
 238	F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
 239	F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
 240	F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
 241	F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
 242	F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
 243	F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
 244	F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
 245	F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
 246	F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
 247	F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
 248	F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
 249	F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
 250	F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
 251	F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
 252	F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
 253	F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
 254	F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
 255	F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
 256	F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
 257	F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
 258	F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
 259	F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
 260	F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
 261	F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
 262	F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
 263	F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
 264	F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
 265	F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
 266	F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
 267	F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
 268	F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
 269	F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
 270
 271	F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
 272	F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
 273	F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
 274	F1(SCIFA1_RTS), F7(CSCIF1_RTS),
 275	F1(SCIFA1_CTS), F7(CSCIF1_CTS),
 276	F1(SCIFA1_SCK), F7(CSCIF1_SCK),
 277	F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
 278	F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
 279	F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
 280	F7(CHSCIF0_HSCK), /* Port40 */
 281
 282	F1(PDM0_DATA), /* Port64 */
 283	F1(PDM1_DATA),
 284	F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
 285	IRQ(40),
 286	F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
 287	F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
 288	F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
 289	F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
 290	F7(CHSCIF1_HRTS), /* Port70 */
 291	F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
 292	F7(CHSCIF1_HCTS),
 293	F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
 294	F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
 295	F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
 296	F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
 297	F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
 298
 299	F1(KEYIN0), /* Port96 */
 300	F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
 301	F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
 302	F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
 303	F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
 304	F2(KEYOUT7), F5(RFANAEN), IRQ(45),
 305	F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
 306	F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
 307	F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
 308	F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
 309	F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
 310	F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
 311	F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
 312	F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
 313	F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
 314	F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
 315	F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
 316	F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
 317	F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
 318	F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
 319	F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
 320	F5(SIM0_VOLTSEL1), /* Port130 */
 321	F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
 322	F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
 323	F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
 324	IRQ(20), /* Port160 */
 325	IRQ(21), IRQ(22), IRQ(23),
 326	F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
 327	F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
 328	F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
 329	IRQ(24), IRQ(25), IRQ(26), IRQ(27),
 330	F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
 331	F1(A9), F2(MMCD1_6), IRQ(32),
 332	F1(A8), F2(MMCD1_5), IRQ(33),
 333	F1(A7), F2(MMCD1_4), IRQ(34),
 334	F1(A6), F2(MMCD1_3), IRQ(35),
 335	F1(A5), F2(MMCD1_2), IRQ(36),
 336	F1(A4), F2(MMCD1_1), IRQ(37),
 337	F1(A3), F2(MMCD1_0), IRQ(38),
 338	F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
 339	F1(A1),
 340	F1(A0), F2(BS),
 341	F1(CKO), F2(MMCCLK1),
 342	F1(CS0_N), F5(SIM0_GPO1),
 343	F1(CS2_N), F5(SIM0_GPO2),
 344	F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
 345	F1(D15), F5(GIO_OUT15),
 346	F1(D14), F5(GIO_OUT14),
 347	F1(D13), F5(GIO_OUT13),
 348	F1(D12), F5(GIO_OUT12), /* Port210 */
 349	F1(D11), F5(WGM_TXP2),
 350	F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
 351	F1(D9), F2(VIO_D9), F5(GIO_OUT9),
 352	F1(D8), F2(VIO_D8), F5(GIO_OUT8),
 353	F1(D7), F2(VIO_D7), F5(GIO_OUT7),
 354	F1(D6), F2(VIO_D6), F5(GIO_OUT6),
 355	F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
 356	F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
 357	F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
 358	F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
 359	F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
 360	F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
 361	F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
 362	F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
 363	F1(WE0_N), F2(RDWR_227),
 364	F1(WE1_N), F5(SIM0_GPO0),
 365	F1(PWMO), F2(VIO_CKO1_229),
 366	F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
 367	F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
 368	F2(VIO_CKO3_233), F4(SF_PORT_1_233),
 369	F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
 370	F1(FSIAISLD), F2(PDM3_DATA_235),
 371	F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
 372	F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
 373	F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
 374	F1(FSIBISLD), /* Port240 */
 375	F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
 376	F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
 377	F1(FSIBCK), F3(ISP_SHUTTER0_245),
 378	F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
 379	F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
 380	F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
 381	F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
 382	F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
 383	F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
 384	F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
 385	F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
 386	F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
 387	F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
 388	F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
 389	F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
 390	F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
 391	F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
 392	F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
 393	F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
 394	F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
 395	F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
 396	F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
 397	F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
 398	F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
 399	F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
 400	F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
 401	F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
 402	F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
 403	F4(MSIOF6_SS1), /* Port300 */
 404	F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
 405	F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
 406	F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
 407	F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
 408	IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
 409	IRQ(55), IRQ(56), IRQ(57),
 410	PINMUX_MARK_END,
 411};
 412
 413static const u16 pinmux_data[] = {
 414	/* specify valid pin states for each pin in GPIO mode */
 415	PINMUX_DATA_ALL(),
 416
 417	/* Port0 */
 418	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
 419	PINMUX_DATA(PDM2_CLK_0_MARK,	PORT0_FN3),
 420	PINMUX_DATA(DU0_DR0_MARK,	PORT0_FN7),
 421	PINMUX_DATA(IRQ0_MARK,		PORT0_FN0),
 422
 423	/* Port1 */
 424	PINMUX_DATA(LCDD1_MARK,		PORT1_FN1),
 425	PINMUX_DATA(PDM2_DATA_1_MARK,	PORT1_FN3,	MSEL3CR_12_0),
 426	PINMUX_DATA(DU0_DR19_MARK,	PORT1_FN7),
 427	PINMUX_DATA(IRQ1_MARK,		PORT1_FN0),
 428
 429	/* Port2 */
 430	PINMUX_DATA(LCDD2_MARK,		PORT2_FN1),
 431	PINMUX_DATA(PDM3_CLK_2_MARK,	PORT2_FN3),
 432	PINMUX_DATA(DU0_DR2_MARK,	PORT2_FN7),
 433	PINMUX_DATA(IRQ2_MARK,		PORT2_FN0),
 434
 435	/* Port3 */
 436	PINMUX_DATA(LCDD3_MARK,		PORT3_FN1),
 437	PINMUX_DATA(PDM3_DATA_3_MARK,	PORT3_FN3,	MSEL3CR_12_0),
 438	PINMUX_DATA(DU0_DR3_MARK,	PORT3_FN7),
 439	PINMUX_DATA(IRQ3_MARK,		PORT3_FN0),
 440
 441	/* Port4 */
 442	PINMUX_DATA(LCDD4_MARK,		PORT4_FN1),
 443	PINMUX_DATA(PDM4_CLK_4_MARK,	PORT4_FN3),
 444	PINMUX_DATA(DU0_DR4_MARK,	PORT4_FN7),
 445	PINMUX_DATA(IRQ4_MARK,		PORT4_FN0),
 446
 447	/* Port5 */
 448	PINMUX_DATA(LCDD5_MARK,		PORT5_FN1),
 449	PINMUX_DATA(PDM4_DATA_5_MARK,	PORT5_FN3,	MSEL3CR_12_0),
 450	PINMUX_DATA(DU0_DR5_MARK,	PORT5_FN7),
 451	PINMUX_DATA(IRQ5_MARK,		PORT5_FN0),
 452
 453	/* Port6 */
 454	PINMUX_DATA(LCDD6_MARK,		PORT6_FN1),
 455	PINMUX_DATA(PDM0_OUTCLK_6_MARK,	PORT6_FN3),
 456	PINMUX_DATA(DU0_DR6_MARK,	PORT6_FN7),
 457	PINMUX_DATA(IRQ6_MARK,		PORT6_FN0),
 458
 459	/* Port7 */
 460	PINMUX_DATA(LCDD7_MARK,			PORT7_FN1),
 461	PINMUX_DATA(PDM0_OUTDATA_7_MARK,	PORT7_FN3),
 462	PINMUX_DATA(DU0_DR7_MARK,		PORT7_FN7),
 463	PINMUX_DATA(IRQ7_MARK,			PORT7_FN0),
 464
 465	/* Port8 */
 466	PINMUX_DATA(LCDD8_MARK,		PORT8_FN1),
 467	PINMUX_DATA(PDM1_OUTCLK_8_MARK,	PORT8_FN3),
 468	PINMUX_DATA(DU0_DG0_MARK,	PORT8_FN7),
 469	PINMUX_DATA(IRQ8_MARK,		PORT8_FN0),
 470
 471	/* Port9 */
 472	PINMUX_DATA(LCDD9_MARK,		PORT9_FN1),
 473	PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
 474	PINMUX_DATA(DU0_DG1_MARK,	PORT9_FN7),
 475	PINMUX_DATA(IRQ9_MARK,		PORT9_FN0),
 476
 477	/* Port10 */
 478	PINMUX_DATA(LCDD10_MARK,		PORT10_FN1),
 479	PINMUX_DATA(FSICCK_MARK,		PORT10_FN3),
 480	PINMUX_DATA(DU0_DG2_MARK,		PORT10_FN7),
 481	PINMUX_DATA(IRQ10_MARK,			PORT10_FN0),
 482
 483	/* Port11 */
 484	PINMUX_DATA(LCDD11_MARK,		PORT11_FN1),
 485	PINMUX_DATA(FSICISLD_MARK,		PORT11_FN3),
 486	PINMUX_DATA(DU0_DG3_MARK,		PORT11_FN7),
 487	PINMUX_DATA(IRQ11_MARK,			PORT11_FN0),
 488
 489	/* Port12 */
 490	PINMUX_DATA(LCDD12_MARK,		PORT12_FN1),
 491	PINMUX_DATA(FSICOMC_MARK,		PORT12_FN3),
 492	PINMUX_DATA(DU0_DG4_MARK,		PORT12_FN7),
 493	PINMUX_DATA(IRQ12_MARK,			PORT12_FN0),
 494
 495	/* Port13 */
 496	PINMUX_DATA(LCDD13_MARK,		PORT13_FN1),
 497	PINMUX_DATA(FSICOLR_MARK,		PORT13_FN3),
 498	PINMUX_DATA(FSICILR_MARK,		PORT13_FN4),
 499	PINMUX_DATA(DU0_DG5_MARK,		PORT13_FN7),
 500	PINMUX_DATA(IRQ13_MARK,			PORT13_FN0),
 501
 502	/* Port14 */
 503	PINMUX_DATA(LCDD14_MARK,		PORT14_FN1),
 504	PINMUX_DATA(FSICOBT_MARK,		PORT14_FN3),
 505	PINMUX_DATA(FSICIBT_MARK,		PORT14_FN4),
 506	PINMUX_DATA(DU0_DG6_MARK,		PORT14_FN7),
 507	PINMUX_DATA(IRQ14_MARK,			PORT14_FN0),
 508
 509	/* Port15 */
 510	PINMUX_DATA(LCDD15_MARK,		PORT15_FN1),
 511	PINMUX_DATA(FSICOSLD_MARK,		PORT15_FN3),
 512	PINMUX_DATA(DU0_DG7_MARK,		PORT15_FN7),
 513	PINMUX_DATA(IRQ15_MARK,			PORT15_FN0),
 514
 515	/* Port16 */
 516	PINMUX_DATA(LCDD16_MARK,		PORT16_FN1),
 517	PINMUX_DATA(TPU1TO1_MARK,		PORT16_FN4),
 518	PINMUX_DATA(DU0_DB0_MARK,		PORT16_FN7),
 519
 520	/* Port17 */
 521	PINMUX_DATA(LCDD17_MARK,		PORT17_FN1),
 522	PINMUX_DATA(SF_IRQ_00_MARK,		PORT17_FN4),
 523	PINMUX_DATA(DU0_DB1_MARK,		PORT17_FN7),
 524
 525	/* Port18 */
 526	PINMUX_DATA(LCDD18_MARK,		PORT18_FN1),
 527	PINMUX_DATA(SF_IRQ_01_MARK,		PORT18_FN4),
 528	PINMUX_DATA(DU0_DB2_MARK,		PORT18_FN7),
 529
 530	/* Port19 */
 531	PINMUX_DATA(LCDD19_MARK,		PORT19_FN1),
 532	PINMUX_DATA(SCIFB3_RTS_19_MARK,		PORT19_FN3),
 533	PINMUX_DATA(DU0_DB3_MARK,		PORT19_FN7),
 534
 535	/* Port20 */
 536	PINMUX_DATA(LCDD20_MARK,		PORT20_FN1),
 537	PINMUX_DATA(SCIFB3_CTS_20_MARK,		PORT20_FN3,	MSEL3CR_09_0),
 538	PINMUX_DATA(DU0_DB4_MARK,		PORT20_FN7),
 539
 540	/* Port21 */
 541	PINMUX_DATA(LCDD21_MARK,		PORT21_FN1),
 542	PINMUX_DATA(SCIFB3_TXD_21_MARK,		PORT21_FN3,	MSEL3CR_09_0),
 543	PINMUX_DATA(DU0_DB5_MARK,		PORT21_FN7),
 544
 545	/* Port22 */
 546	PINMUX_DATA(LCDD22_MARK,		PORT22_FN1),
 547	PINMUX_DATA(SCIFB3_RXD_22_MARK,		PORT22_FN3,	MSEL3CR_09_0),
 548	PINMUX_DATA(DU0_DB6_MARK,		PORT22_FN7),
 549
 550	/* Port23 */
 551	PINMUX_DATA(LCDD23_MARK,		PORT23_FN1),
 552	PINMUX_DATA(SCIFB3_SCK_23_MARK,		PORT23_FN3),
 553	PINMUX_DATA(DU0_DB7_MARK,		PORT23_FN7),
 554
 555	/* Port24 */
 556	PINMUX_DATA(LCDHSYN_MARK,			PORT24_FN1),
 557	PINMUX_DATA(LCDCS_MARK,				PORT24_FN2),
 558	PINMUX_DATA(SCIFB1_RTS_24_MARK,			PORT24_FN3),
 559	PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK,	PORT24_FN7),
 560
 561	/* Port25 */
 562	PINMUX_DATA(LCDVSYN_MARK,			PORT25_FN1),
 563	PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
 564	PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK,	PORT25_FN7),
 565
 566	/* Port26 */
 567	PINMUX_DATA(LCDDCK_MARK,		PORT26_FN1),
 568	PINMUX_DATA(LCDWR_MARK,			PORT26_FN2),
 569	PINMUX_DATA(SCIFB1_TXD_26_MARK,		PORT26_FN3,	MSEL3CR_11_0),
 570	PINMUX_DATA(DU0_DOTCLKIN_MARK,		PORT26_FN7),
 571
 572	/* Port27 */
 573	PINMUX_DATA(LCDDISP_MARK,		PORT27_FN1),
 574	PINMUX_DATA(LCDRS_MARK,			PORT27_FN2),
 575	PINMUX_DATA(SCIFB1_RXD_27_MARK,		PORT27_FN3,	MSEL3CR_11_0),
 576	PINMUX_DATA(DU0_DOTCLKOUT_MARK,		PORT27_FN7),
 577
 578	/* Port28 */
 579	PINMUX_DATA(LCDRD_N_MARK,		PORT28_FN1),
 580	PINMUX_DATA(SCIFB1_SCK_28_MARK,		PORT28_FN3),
 581	PINMUX_DATA(DU0_DOTCLKOUTB_MARK,	PORT28_FN7),
 582
 583	/* Port29 */
 584	PINMUX_DATA(LCDLCLK_MARK,		PORT29_FN1),
 585	PINMUX_DATA(SF_IRQ_02_MARK,		PORT29_FN4),
 586	PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,	PORT29_FN7),
 587
 588	/* Port30 */
 589	PINMUX_DATA(LCDDON_MARK,		PORT30_FN1),
 590	PINMUX_DATA(SF_IRQ_03_MARK,		PORT30_FN4),
 591	PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,	PORT30_FN7),
 592
 593	/* Port32 */
 594	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT32_FN1),
 595	PINMUX_DATA(SIM0_DET_MARK,		PORT32_FN5),
 596	PINMUX_DATA(CSCIF0_RTS_MARK,		PORT32_FN7),
 597
 598	/* Port33 */
 599	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT33_FN1),
 600	PINMUX_DATA(SIM1_DET_MARK,		PORT33_FN5),
 601	PINMUX_DATA(CSCIF0_CTS_MARK,		PORT33_FN7),
 602
 603	/* Port34 */
 604	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT34_FN1),
 605	PINMUX_DATA(SIM0_PWRON_MARK,		PORT34_FN5),
 606	PINMUX_DATA(CSCIF0_SCK_MARK,		PORT34_FN7),
 607
 608	/* Port35 */
 609	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT35_FN1),
 610	PINMUX_DATA(CSCIF1_RTS_MARK,		PORT35_FN7),
 611
 612	/* Port36 */
 613	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT36_FN1),
 614	PINMUX_DATA(CSCIF1_CTS_MARK,		PORT36_FN7),
 615
 616	/* Port37 */
 617	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT37_FN1),
 618	PINMUX_DATA(CSCIF1_SCK_MARK,		PORT37_FN7),
 619
 620	/* Port38 */
 621	PINMUX_DATA(SCIFB0_RTS_MARK,		PORT38_FN1),
 622	PINMUX_DATA(TPU0TO1_MARK,		PORT38_FN3),
 623	PINMUX_DATA(SCIFB3_RTS_38_MARK,		PORT38_FN4),
 624	PINMUX_DATA(CHSCIF0_HRTS_MARK,		PORT38_FN7),
 625
 626	/* Port39 */
 627	PINMUX_DATA(SCIFB0_CTS_MARK,		PORT39_FN1),
 628	PINMUX_DATA(TPU0TO2_MARK,		PORT39_FN3),
 629	PINMUX_DATA(SCIFB3_CTS_39_MARK,		PORT39_FN4,	MSEL3CR_09_1),
 630	PINMUX_DATA(CHSCIF0_HCTS_MARK,		PORT39_FN7),
 631
 632	/* Port40 */
 633	PINMUX_DATA(SCIFB0_SCK_MARK,		PORT40_FN1),
 634	PINMUX_DATA(TPU0TO3_MARK,		PORT40_FN3),
 635	PINMUX_DATA(SCIFB3_SCK_40_MARK,		PORT40_FN4),
 636	PINMUX_DATA(CHSCIF0_HSCK_MARK,		PORT40_FN7),
 637
 638	/* Port64 */
 639	PINMUX_DATA(PDM0_DATA_MARK,		PORT64_FN1),
 640
 641	/* Port65 */
 642	PINMUX_DATA(PDM1_DATA_MARK,		PORT65_FN1),
 643
 644	/* Port66 */
 645	PINMUX_DATA(HSI_RX_WAKE_MARK,		PORT66_FN1),
 646	PINMUX_DATA(SCIFB2_CTS_66_MARK,		PORT66_FN2,	MSEL3CR_10_0),
 647	PINMUX_DATA(MSIOF3_SYNC_MARK,		PORT66_FN3),
 648	PINMUX_DATA(GenIO4_MARK,		PORT66_FN5),
 649	PINMUX_DATA(IRQ40_MARK,			PORT66_FN0),
 650
 651	/* Port67 */
 652	PINMUX_DATA(HSI_RX_READY_MARK,		PORT67_FN1),
 653	PINMUX_DATA(SCIFB1_TXD_67_MARK,		PORT67_FN2,	MSEL3CR_11_1),
 654	PINMUX_DATA(GIO_OUT3_67_MARK,		PORT67_FN5),
 655	PINMUX_DATA(CHSCIF1_HTX_MARK,		PORT67_FN7),
 656
 657	/* Port68 */
 658	PINMUX_DATA(HSI_RX_FLAG_MARK,		PORT68_FN1),
 659	PINMUX_DATA(SCIFB2_TXD_68_MARK,		PORT68_FN2,	MSEL3CR_10_0),
 660	PINMUX_DATA(MSIOF3_TXD_MARK,		PORT68_FN3),
 661	PINMUX_DATA(GIO_OUT4_68_MARK,		PORT68_FN5),
 662
 663	/* Port69 */
 664	PINMUX_DATA(HSI_RX_DATA_MARK,		PORT69_FN1),
 665	PINMUX_DATA(SCIFB2_RXD_69_MARK,		PORT69_FN2,	MSEL3CR_10_0),
 666	PINMUX_DATA(MSIOF3_RXD_MARK,		PORT69_FN3),
 667	PINMUX_DATA(GIO_OUT5_69_MARK,		PORT69_FN5),
 668
 669	/* Port70 */
 670	PINMUX_DATA(HSI_TX_FLAG_MARK,		PORT70_FN1),
 671	PINMUX_DATA(SCIFB1_RTS_70_MARK,		PORT70_FN2),
 672	PINMUX_DATA(GIO_OUT1_70_MARK,		PORT70_FN5),
 673	PINMUX_DATA(HSIC_TSTCLK0_MARK,		PORT70_FN6),
 674	PINMUX_DATA(CHSCIF1_HRTS_MARK,		PORT70_FN7),
 675
 676	/* Port71 */
 677	PINMUX_DATA(HSI_TX_DATA_MARK,		PORT71_FN1),
 678	PINMUX_DATA(SCIFB1_CTS_71_MARK,		PORT71_FN2,	MSEL3CR_11_1),
 679	PINMUX_DATA(GIO_OUT2_71_MARK,		PORT71_FN5),
 680	PINMUX_DATA(HSIC_TSTCLK1_MARK,		PORT71_FN6),
 681	PINMUX_DATA(CHSCIF1_HCTS_MARK,		PORT71_FN7),
 682
 683	/* Port72 */
 684	PINMUX_DATA(HSI_TX_WAKE_MARK,		PORT72_FN1),
 685	PINMUX_DATA(SCIFB1_RXD_72_MARK,		PORT72_FN2,	MSEL3CR_11_1),
 686	PINMUX_DATA(GenIO8_MARK,		PORT72_FN5),
 687	PINMUX_DATA(CHSCIF1_HRX_MARK,		PORT72_FN7),
 688
 689	/* Port73 */
 690	PINMUX_DATA(HSI_TX_READY_MARK,		PORT73_FN1),
 691	PINMUX_DATA(SCIFB2_RTS_73_MARK,		PORT73_FN2),
 692	PINMUX_DATA(MSIOF3_SCK_MARK,		PORT73_FN3),
 693	PINMUX_DATA(GIO_OUT0_73_MARK,		PORT73_FN5),
 694
 695	/* Port74 - Port85 */
 696	PINMUX_DATA(IRDA_OUT_MARK,		PORT74_FN1),
 697	PINMUX_DATA(IRDA_IN_MARK,		PORT75_FN1),
 698	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT76_FN1),
 699	PINMUX_DATA(TPU0TO0_MARK,		PORT77_FN1),
 700	PINMUX_DATA(DIGRFEN_MARK,		PORT78_FN1),
 701	PINMUX_DATA(GPS_TIMESTAMP_MARK,		PORT79_FN1),
 702	PINMUX_DATA(TXP_MARK,			PORT80_FN1),
 703	PINMUX_DATA(TXP2_MARK,			PORT81_FN1),
 704	PINMUX_DATA(COEX_0_MARK,		PORT82_FN1),
 705	PINMUX_DATA(COEX_1_MARK,		PORT83_FN1),
 706	PINMUX_DATA(IRQ19_MARK,			PORT84_FN0),
 707	PINMUX_DATA(IRQ18_MARK,			PORT85_FN0),
 708
 709	/* Port96 - Port101 */
 710	PINMUX_DATA(KEYIN0_MARK,		PORT96_FN1),
 711	PINMUX_DATA(KEYIN1_MARK,		PORT97_FN1),
 712	PINMUX_DATA(KEYIN2_MARK,		PORT98_FN1),
 713	PINMUX_DATA(KEYIN3_MARK,		PORT99_FN1),
 714	PINMUX_DATA(KEYIN4_MARK,		PORT100_FN1),
 715	PINMUX_DATA(KEYIN5_MARK,		PORT101_FN1),
 716
 717	/* Port102 */
 718	PINMUX_DATA(KEYIN6_MARK,		PORT102_FN1),
 719	PINMUX_DATA(IRQ41_MARK,			PORT102_FN0),
 720
 721	/* Port103 */
 722	PINMUX_DATA(KEYIN7_MARK,		PORT103_FN1),
 723	PINMUX_DATA(IRQ42_MARK,			PORT103_FN0),
 724
 725	/* Port104 - Port108 */
 726	PINMUX_DATA(KEYOUT0_MARK,		PORT104_FN2),
 727	PINMUX_DATA(KEYOUT1_MARK,		PORT105_FN2),
 728	PINMUX_DATA(KEYOUT2_MARK,		PORT106_FN2),
 729	PINMUX_DATA(KEYOUT3_MARK,		PORT107_FN2),
 730	PINMUX_DATA(KEYOUT4_MARK,		PORT108_FN2),
 731
 732	/* Port109 */
 733	PINMUX_DATA(KEYOUT5_MARK,		PORT109_FN2),
 734	PINMUX_DATA(IRQ43_MARK,			PORT109_FN0),
 735
 736	/* Port110 */
 737	PINMUX_DATA(KEYOUT6_MARK,		PORT110_FN2),
 738	PINMUX_DATA(IRQ44_MARK,			PORT110_FN0),
 739
 740	/* Port111 */
 741	PINMUX_DATA(KEYOUT7_MARK,		PORT111_FN2),
 742	PINMUX_DATA(RFANAEN_MARK,		PORT111_FN5),
 743	PINMUX_DATA(IRQ45_MARK,			PORT111_FN0),
 744
 745	/* Port112 */
 746	PINMUX_DATA(KEYIN8_MARK,		PORT112_FN1),
 747	PINMUX_DATA(KEYOUT8_MARK,		PORT112_FN2),
 748	PINMUX_DATA(SF_IRQ_04_MARK,		PORT112_FN4),
 749	PINMUX_DATA(IRQ46_MARK,			PORT112_FN0),
 750
 751	/* Port113 */
 752	PINMUX_DATA(KEYIN9_MARK,		PORT113_FN1),
 753	PINMUX_DATA(KEYOUT9_MARK,		PORT113_FN2),
 754	PINMUX_DATA(SF_IRQ_05_MARK,		PORT113_FN4),
 755	PINMUX_DATA(IRQ47_MARK,			PORT113_FN0),
 756
 757	/* Port114 */
 758	PINMUX_DATA(KEYIN10_MARK,		PORT114_FN1),
 759	PINMUX_DATA(KEYOUT10_MARK,		PORT114_FN2),
 760	PINMUX_DATA(SF_IRQ_06_MARK,		PORT114_FN4),
 761	PINMUX_DATA(IRQ48_MARK,			PORT114_FN0),
 762
 763	/* Port115 */
 764	PINMUX_DATA(KEYIN11_MARK,		PORT115_FN1),
 765	PINMUX_DATA(KEYOUT11_MARK,		PORT115_FN2),
 766	PINMUX_DATA(SF_IRQ_07_MARK,		PORT115_FN4),
 767	PINMUX_DATA(IRQ49_MARK,			PORT115_FN0),
 768
 769	/* Port116 */
 770	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT116_FN1),
 771	PINMUX_DATA(CSCIF0_TX_MARK,		PORT116_FN7),
 772
 773	/* Port117 */
 774	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT117_FN1),
 775	PINMUX_DATA(CSCIF0_RX_MARK,		PORT117_FN7),
 776
 777	/* Port118 */
 778	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT118_FN1),
 779	PINMUX_DATA(CSCIF1_TX_MARK,		PORT118_FN7),
 780
 781	/* Port119 */
 782	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT119_FN1),
 783	PINMUX_DATA(CSCIF1_RX_MARK,		PORT119_FN7),
 784
 785	/* Port120 */
 786	PINMUX_DATA(SF_PORT_1_120_MARK,		PORT120_FN3),
 787	PINMUX_DATA(SCIFB3_RXD_120_MARK,	PORT120_FN4,	MSEL3CR_09_1),
 788	PINMUX_DATA(DU0_CDE_MARK,		PORT120_FN7),
 789
 790	/* Port121 */
 791	PINMUX_DATA(SF_PORT_0_121_MARK,		PORT121_FN3),
 792	PINMUX_DATA(SCIFB3_TXD_121_MARK,	PORT121_FN4,	MSEL3CR_09_1),
 793
 794	/* Port122 */
 795	PINMUX_DATA(SCIFB0_TXD_MARK,		PORT122_FN1),
 796	PINMUX_DATA(CHSCIF0_HTX_MARK,		PORT122_FN7),
 797
 798	/* Port123 */
 799	PINMUX_DATA(SCIFB0_RXD_MARK,		PORT123_FN1),
 800	PINMUX_DATA(CHSCIF0_HRX_MARK,		PORT123_FN7),
 801
 802	/* Port124 */
 803	PINMUX_DATA(ISP_STROBE_124_MARK,	PORT124_FN3),
 804
 805	/* Port125 */
 806	PINMUX_DATA(STP_ISD_0_MARK,		PORT125_FN1),
 807	PINMUX_DATA(PDM4_CLK_125_MARK,		PORT125_FN2),
 808	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT125_FN3),
 809	PINMUX_DATA(SIM0_VOLTSEL0_MARK,		PORT125_FN5),
 810
 811	/* Port126 */
 812	PINMUX_DATA(TS_SDEN_MARK,		PORT126_FN1),
 813	PINMUX_DATA(MSIOF7_SYNC_MARK,		PORT126_FN2),
 814	PINMUX_DATA(STP_ISEN_1_MARK,		PORT126_FN3),
 815
 816	/* Port128 */
 817	PINMUX_DATA(STP_ISEN_0_MARK,		PORT128_FN1),
 818	PINMUX_DATA(PDM1_OUTDATA_128_MARK,	PORT128_FN2),
 819	PINMUX_DATA(MSIOF2_SYNC_MARK,		PORT128_FN3),
 820	PINMUX_DATA(SIM1_VOLTSEL1_MARK,		PORT128_FN5),
 821
 822	/* Port129 */
 823	PINMUX_DATA(TS_SPSYNC_MARK,		PORT129_FN1),
 824	PINMUX_DATA(MSIOF7_RXD_MARK,		PORT129_FN2),
 825	PINMUX_DATA(STP_ISSYNC_1_MARK,		PORT129_FN3),
 826
 827	/* Port130 */
 828	PINMUX_DATA(STP_ISSYNC_0_MARK,		PORT130_FN1),
 829	PINMUX_DATA(PDM4_DATA_130_MARK,		PORT130_FN2,	MSEL3CR_12_1),
 830	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT130_FN3),
 831	PINMUX_DATA(SIM0_VOLTSEL1_MARK,		PORT130_FN5),
 832
 833	/* Port131 */
 834	PINMUX_DATA(STP_OPWM_0_MARK,		PORT131_FN1),
 835	PINMUX_DATA(SIM1_PWRON_MARK,		PORT131_FN5),
 836
 837	/* Port132 */
 838	PINMUX_DATA(TS_SCK_MARK,		PORT132_FN1),
 839	PINMUX_DATA(MSIOF7_SCK_MARK,		PORT132_FN2),
 840	PINMUX_DATA(STP_ISCLK_1_MARK,		PORT132_FN3),
 841
 842	/* Port133 */
 843	PINMUX_DATA(STP_ISCLK_0_MARK,		PORT133_FN1),
 844	PINMUX_DATA(PDM1_OUTCLK_133_MARK,	PORT133_FN2),
 845	PINMUX_DATA(MSIOF2_SCK_MARK,		PORT133_FN3),
 846	PINMUX_DATA(SIM1_VOLTSEL0_MARK,		PORT133_FN5),
 847
 848	/* Port134 */
 849	PINMUX_DATA(TS_SDAT_MARK,		PORT134_FN1),
 850	PINMUX_DATA(MSIOF7_TXD_MARK,		PORT134_FN2),
 851	PINMUX_DATA(STP_ISD_1_MARK,		PORT134_FN3),
 852
 853	/* Port160 - Port178 */
 854	PINMUX_DATA(IRQ20_MARK,			PORT160_FN0),
 855	PINMUX_DATA(IRQ21_MARK,			PORT161_FN0),
 856	PINMUX_DATA(IRQ22_MARK,			PORT162_FN0),
 857	PINMUX_DATA(IRQ23_MARK,			PORT163_FN0),
 858	PINMUX_DATA(MMCD0_0_MARK,		PORT164_FN1),
 859	PINMUX_DATA(MMCD0_1_MARK,		PORT165_FN1),
 860	PINMUX_DATA(MMCD0_2_MARK,		PORT166_FN1),
 861	PINMUX_DATA(MMCD0_3_MARK,		PORT167_FN1),
 862	PINMUX_DATA(MMCD0_4_MARK,		PORT168_FN1),
 863	PINMUX_DATA(MMCD0_5_MARK,		PORT169_FN1),
 864	PINMUX_DATA(MMCD0_6_MARK,		PORT170_FN1),
 865	PINMUX_DATA(MMCD0_7_MARK,		PORT171_FN1),
 866	PINMUX_DATA(MMCCMD0_MARK,		PORT172_FN1),
 867	PINMUX_DATA(MMCCLK0_MARK,		PORT173_FN1),
 868	PINMUX_DATA(MMCRST_MARK,		PORT174_FN1),
 869	PINMUX_DATA(IRQ24_MARK,			PORT175_FN0),
 870	PINMUX_DATA(IRQ25_MARK,			PORT176_FN0),
 871	PINMUX_DATA(IRQ26_MARK,			PORT177_FN0),
 872	PINMUX_DATA(IRQ27_MARK,			PORT178_FN0),
 873
 874	/* Port192 - Port200 FN1 */
 875	PINMUX_DATA(A10_MARK,		PORT192_FN1),
 876	PINMUX_DATA(A9_MARK,		PORT193_FN1),
 877	PINMUX_DATA(A8_MARK,		PORT194_FN1),
 878	PINMUX_DATA(A7_MARK,		PORT195_FN1),
 879	PINMUX_DATA(A6_MARK,		PORT196_FN1),
 880	PINMUX_DATA(A5_MARK,		PORT197_FN1),
 881	PINMUX_DATA(A4_MARK,		PORT198_FN1),
 882	PINMUX_DATA(A3_MARK,		PORT199_FN1),
 883	PINMUX_DATA(A2_MARK,		PORT200_FN1),
 884
 885	/* Port192 - Port200 FN2 */
 886	PINMUX_DATA(MMCD1_7_MARK,		PORT192_FN2),
 887	PINMUX_DATA(MMCD1_6_MARK,		PORT193_FN2),
 888	PINMUX_DATA(MMCD1_5_MARK,		PORT194_FN2),
 889	PINMUX_DATA(MMCD1_4_MARK,		PORT195_FN2),
 890	PINMUX_DATA(MMCD1_3_MARK,		PORT196_FN2),
 891	PINMUX_DATA(MMCD1_2_MARK,		PORT197_FN2),
 892	PINMUX_DATA(MMCD1_1_MARK,		PORT198_FN2),
 893	PINMUX_DATA(MMCD1_0_MARK,		PORT199_FN2),
 894	PINMUX_DATA(MMCCMD1_MARK,		PORT200_FN2),
 895
 896	/* Port192 - Port200 IRQ */
 897	PINMUX_DATA(IRQ31_MARK,			PORT192_FN0),
 898	PINMUX_DATA(IRQ32_MARK,			PORT193_FN0),
 899	PINMUX_DATA(IRQ33_MARK,			PORT194_FN0),
 900	PINMUX_DATA(IRQ34_MARK,			PORT195_FN0),
 901	PINMUX_DATA(IRQ35_MARK,			PORT196_FN0),
 902	PINMUX_DATA(IRQ36_MARK,			PORT197_FN0),
 903	PINMUX_DATA(IRQ37_MARK,			PORT198_FN0),
 904	PINMUX_DATA(IRQ38_MARK,			PORT199_FN0),
 905	PINMUX_DATA(IRQ39_MARK,			PORT200_FN0),
 906
 907	/* Port201 */
 908	PINMUX_DATA(A1_MARK,		PORT201_FN1),
 909
 910	/* Port202 */
 911	PINMUX_DATA(A0_MARK,		PORT202_FN1),
 912	PINMUX_DATA(BS_MARK,		PORT202_FN2),
 913
 914	/* Port203 */
 915	PINMUX_DATA(CKO_MARK,		PORT203_FN1),
 916	PINMUX_DATA(MMCCLK1_MARK,	PORT203_FN2),
 917
 918	/* Port204 */
 919	PINMUX_DATA(CS0_N_MARK,		PORT204_FN1),
 920	PINMUX_DATA(SIM0_GPO1_MARK,	PORT204_FN5),
 921
 922	/* Port205 */
 923	PINMUX_DATA(CS2_N_MARK,		PORT205_FN1),
 924	PINMUX_DATA(SIM0_GPO2_MARK,	PORT205_FN5),
 925
 926	/* Port206 */
 927	PINMUX_DATA(CS4_N_MARK,		PORT206_FN1),
 928	PINMUX_DATA(VIO_VD_MARK,	PORT206_FN2),
 929	PINMUX_DATA(SIM1_GPO0_MARK,	PORT206_FN5),
 930
 931	/* Port207 - Port212 FN1 */
 932	PINMUX_DATA(D15_MARK,		PORT207_FN1),
 933	PINMUX_DATA(D14_MARK,		PORT208_FN1),
 934	PINMUX_DATA(D13_MARK,		PORT209_FN1),
 935	PINMUX_DATA(D12_MARK,		PORT210_FN1),
 936	PINMUX_DATA(D11_MARK,		PORT211_FN1),
 937	PINMUX_DATA(D10_MARK,		PORT212_FN1),
 938
 939	/* Port207 - Port212 FN5 */
 940	PINMUX_DATA(GIO_OUT15_MARK,			PORT207_FN5),
 941	PINMUX_DATA(GIO_OUT14_MARK,			PORT208_FN5),
 942	PINMUX_DATA(GIO_OUT13_MARK,			PORT209_FN5),
 943	PINMUX_DATA(GIO_OUT12_MARK,			PORT210_FN5),
 944	PINMUX_DATA(WGM_TXP2_MARK,			PORT211_FN5),
 945	PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,	PORT212_FN5),
 946
 947	/* Port213 - Port222 FN1 */
 948	PINMUX_DATA(D9_MARK,		PORT213_FN1),
 949	PINMUX_DATA(D8_MARK,		PORT214_FN1),
 950	PINMUX_DATA(D7_MARK,		PORT215_FN1),
 951	PINMUX_DATA(D6_MARK,		PORT216_FN1),
 952	PINMUX_DATA(D5_MARK,		PORT217_FN1),
 953	PINMUX_DATA(D4_MARK,		PORT218_FN1),
 954	PINMUX_DATA(D3_MARK,		PORT219_FN1),
 955	PINMUX_DATA(D2_MARK,		PORT220_FN1),
 956	PINMUX_DATA(D1_MARK,		PORT221_FN1),
 957	PINMUX_DATA(D0_MARK,		PORT222_FN1),
 958
 959	/* Port213 - Port222 FN2 */
 960	PINMUX_DATA(VIO_D9_MARK,	PORT213_FN2),
 961	PINMUX_DATA(VIO_D8_MARK,	PORT214_FN2),
 962	PINMUX_DATA(VIO_D7_MARK,	PORT215_FN2),
 963	PINMUX_DATA(VIO_D6_MARK,	PORT216_FN2),
 964	PINMUX_DATA(VIO_D5_MARK,	PORT217_FN2),
 965	PINMUX_DATA(VIO_D4_MARK,	PORT218_FN2),
 966	PINMUX_DATA(VIO_D3_MARK,	PORT219_FN2),
 967	PINMUX_DATA(VIO_D2_MARK,	PORT220_FN2),
 968	PINMUX_DATA(VIO_D1_MARK,	PORT221_FN2),
 969	PINMUX_DATA(VIO_D0_MARK,	PORT222_FN2),
 970
 971	/* Port213 - Port222 FN5 */
 972	PINMUX_DATA(GIO_OUT9_MARK,	PORT213_FN5),
 973	PINMUX_DATA(GIO_OUT8_MARK,	PORT214_FN5),
 974	PINMUX_DATA(GIO_OUT7_MARK,	PORT215_FN5),
 975	PINMUX_DATA(GIO_OUT6_MARK,	PORT216_FN5),
 976	PINMUX_DATA(GIO_OUT5_217_MARK,	PORT217_FN5),
 977	PINMUX_DATA(GIO_OUT4_218_MARK,	PORT218_FN5),
 978	PINMUX_DATA(GIO_OUT3_219_MARK,	PORT219_FN5),
 979	PINMUX_DATA(GIO_OUT2_220_MARK,	PORT220_FN5),
 980	PINMUX_DATA(GIO_OUT1_221_MARK,	PORT221_FN5),
 981	PINMUX_DATA(GIO_OUT0_222_MARK,	PORT222_FN5),
 982
 983	/* Port224 */
 984	PINMUX_DATA(RDWR_224_MARK,	PORT224_FN1),
 985	PINMUX_DATA(VIO_HD_MARK,	PORT224_FN2),
 986	PINMUX_DATA(SIM1_GPO2_MARK,	PORT224_FN5),
 987
 988	/* Port225 */
 989	PINMUX_DATA(RD_N_MARK,		PORT225_FN1),
 990
 991	/* Port226 */
 992	PINMUX_DATA(WAIT_N_MARK,	PORT226_FN1),
 993	PINMUX_DATA(VIO_CLK_MARK,	PORT226_FN2),
 994	PINMUX_DATA(SIM1_GPO1_MARK,	PORT226_FN5),
 995
 996	/* Port227 */
 997	PINMUX_DATA(WE0_N_MARK,		PORT227_FN1),
 998	PINMUX_DATA(RDWR_227_MARK,	PORT227_FN2),
 999
1000	/* Port228 */
1001	PINMUX_DATA(WE1_N_MARK,		PORT228_FN1),
1002	PINMUX_DATA(SIM0_GPO0_MARK,	PORT228_FN5),
1003
1004	/* Port229 */
1005	PINMUX_DATA(PWMO_MARK,		PORT229_FN1),
1006	PINMUX_DATA(VIO_CKO1_229_MARK,	PORT229_FN2),
1007
1008	/* Port230 */
1009	PINMUX_DATA(SLIM_CLK_MARK,	PORT230_FN1),
1010	PINMUX_DATA(VIO_CKO4_230_MARK,	PORT230_FN2),
1011
1012	/* Port231 */
1013	PINMUX_DATA(SLIM_DATA_MARK,	PORT231_FN1),
1014	PINMUX_DATA(VIO_CKO5_231_MARK,	PORT231_FN2),
1015
1016	/* Port232 */
1017	PINMUX_DATA(VIO_CKO2_232_MARK,	PORT232_FN2),
1018	PINMUX_DATA(SF_PORT_0_232_MARK,	PORT232_FN4),
1019
1020	/* Port233 */
1021	PINMUX_DATA(VIO_CKO3_233_MARK,	PORT233_FN2),
1022	PINMUX_DATA(SF_PORT_1_233_MARK,	PORT233_FN4),
1023
1024	/* Port234 */
1025	PINMUX_DATA(FSIACK_MARK,	PORT234_FN1),
1026	PINMUX_DATA(PDM3_CLK_234_MARK,	PORT234_FN2),
1027	PINMUX_DATA(ISP_IRIS1_234_MARK,	PORT234_FN3),
1028
1029	/* Port235 */
1030	PINMUX_DATA(FSIAISLD_MARK,	PORT235_FN1),
1031	PINMUX_DATA(PDM3_DATA_235_MARK,	PORT235_FN2,	MSEL3CR_12_1),
1032
1033	/* Port236 */
1034	PINMUX_DATA(FSIAOMC_MARK,		PORT236_FN1),
1035	PINMUX_DATA(PDM0_OUTCLK_236_MARK,	PORT236_FN2),
1036	PINMUX_DATA(ISP_IRIS0_236_MARK,		PORT236_FN3),
1037
1038	/* Port237 */
1039	PINMUX_DATA(FSIAOLR_MARK,	PORT237_FN1),
1040	PINMUX_DATA(FSIAILR_MARK,	PORT237_FN2),
1041
1042	/* Port238 */
1043	PINMUX_DATA(FSIAOBT_MARK,	PORT238_FN1),
1044	PINMUX_DATA(FSIAIBT_MARK,	PORT238_FN2),
1045
1046	/* Port239 */
1047	PINMUX_DATA(FSIAOSLD_MARK,		PORT239_FN1),
1048	PINMUX_DATA(PDM0_OUTDATA_239_MARK,	PORT239_FN2),
1049
1050	/* Port240 */
1051	PINMUX_DATA(FSIBISLD_MARK,	PORT240_FN1),
1052
1053	/* Port241 */
1054	PINMUX_DATA(FSIBOLR_MARK,	PORT241_FN1),
1055	PINMUX_DATA(FSIBILR_MARK,	PORT241_FN2),
1056
1057	/* Port242 */
1058	PINMUX_DATA(FSIBOMC_MARK,		PORT242_FN1),
1059	PINMUX_DATA(ISP_SHUTTER1_242_MARK,	PORT242_FN3),
1060
1061	/* Port243 */
1062	PINMUX_DATA(FSIBOBT_MARK,	PORT243_FN1),
1063	PINMUX_DATA(FSIBIBT_MARK,	PORT243_FN2),
1064
1065	/* Port244 */
1066	PINMUX_DATA(FSIBOSLD_MARK,	PORT244_FN1),
1067	PINMUX_DATA(FSIASPDIF_MARK,	PORT244_FN2),
1068
1069	/* Port245 */
1070	PINMUX_DATA(FSIBCK_MARK,		PORT245_FN1),
1071	PINMUX_DATA(ISP_SHUTTER0_245_MARK,	PORT245_FN3),
1072
1073	/* Port246 - Port250 FN1 */
1074	PINMUX_DATA(ISP_IRIS1_246_MARK,		PORT246_FN1),
1075	PINMUX_DATA(ISP_IRIS0_247_MARK,		PORT247_FN1),
1076	PINMUX_DATA(ISP_SHUTTER1_248_MARK,	PORT248_FN1),
1077	PINMUX_DATA(ISP_SHUTTER0_249_MARK,	PORT249_FN1),
1078	PINMUX_DATA(ISP_STROBE_250_MARK,	PORT250_FN1),
1079
1080	/* Port256 - Port258 */
1081	PINMUX_DATA(MSIOF0_SYNC_MARK,		PORT256_FN1),
1082	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT257_FN1),
1083	PINMUX_DATA(MSIOF0_SCK_MARK,		PORT258_FN1),
1084
1085	/* Port259 */
1086	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT259_FN1),
1087	PINMUX_DATA(VIO_CKO3_259_MARK,		PORT259_FN3),
1088
1089	/* Port260 */
1090	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT260_FN1),
1091
1092	/* Port261 */
1093	PINMUX_DATA(SCIFB1_SCK_261_MARK,	PORT261_FN2),
1094	PINMUX_DATA(CHSCIF1_HSCK_MARK,		PORT261_FN7),
1095
1096	/* Port262 */
1097	PINMUX_DATA(SCIFB2_SCK_262_MARK,	PORT262_FN2),
1098
1099	/* Port263 - Port266 FN1 */
1100	PINMUX_DATA(MSIOF1_SS2_MARK,		PORT263_FN1),
1101	PINMUX_DATA(MSIOF1_TXD_MARK,		PORT264_FN1),
1102	PINMUX_DATA(MSIOF1_RXD_MARK,		PORT265_FN1),
1103	PINMUX_DATA(MSIOF1_SS1_MARK,		PORT266_FN1),
1104
1105	/* Port263 - Port266 FN4 */
1106	PINMUX_DATA(MSIOF5_SS2_MARK,		PORT263_FN4),
1107	PINMUX_DATA(MSIOF5_TXD_MARK,		PORT264_FN4),
1108	PINMUX_DATA(MSIOF5_RXD_MARK,		PORT265_FN4),
1109	PINMUX_DATA(MSIOF5_SS1_MARK,		PORT266_FN4),
1110
1111	/* Port267 */
1112	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT267_FN1),
1113
1114	/* Port268 */
1115	PINMUX_DATA(MSIOF1_SCK_MARK,		PORT268_FN1),
1116	PINMUX_DATA(MSIOF5_SCK_MARK,		PORT268_FN4),
1117
1118	/* Port269 */
1119	PINMUX_DATA(MSIOF1_SYNC_MARK,		PORT269_FN1),
1120	PINMUX_DATA(MSIOF5_SYNC_MARK,		PORT269_FN4),
1121
1122	/* Port270 - Port273 FN1 */
1123	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT270_FN1),
1124	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT271_FN1),
1125	PINMUX_DATA(MSIOF3_SS2_MARK,		PORT272_FN1),
1126	PINMUX_DATA(MSIOF3_SS1_MARK,		PORT273_FN1),
1127
1128	/* Port270 - Port273 FN3 */
1129	PINMUX_DATA(VIO_CKO5_270_MARK,		PORT270_FN3),
1130	PINMUX_DATA(VIO_CKO2_271_MARK,		PORT271_FN3),
1131	PINMUX_DATA(VIO_CKO1_272_MARK,		PORT272_FN3),
1132	PINMUX_DATA(VIO_CKO4_273_MARK,		PORT273_FN3),
1133
1134	/* Port274 */
1135	PINMUX_DATA(MSIOF4_SS2_MARK,		PORT274_FN1),
1136	PINMUX_DATA(TPU1TO0_MARK,		PORT274_FN4),
1137
1138	/* Port275 - Port280 */
1139	PINMUX_DATA(IC_DP_MARK,			PORT275_FN1),
1140	PINMUX_DATA(SIM0_RST_MARK,		PORT276_FN1),
1141	PINMUX_DATA(IC_DM_MARK,			PORT277_FN1),
1142	PINMUX_DATA(SIM0_BSICOMP_MARK,		PORT278_FN1),
1143	PINMUX_DATA(SIM0_CLK_MARK,		PORT279_FN1),
1144	PINMUX_DATA(SIM0_IO_MARK,		PORT280_FN1),
1145
1146	/* Port281 */
1147	PINMUX_DATA(SIM1_IO_MARK,		PORT281_FN1),
1148	PINMUX_DATA(PDM2_DATA_281_MARK,		PORT281_FN2,	MSEL3CR_12_1),
1149
1150	/* Port282 */
1151	PINMUX_DATA(SIM1_CLK_MARK,		PORT282_FN1),
1152	PINMUX_DATA(PDM2_CLK_282_MARK,		PORT282_FN2),
1153
1154	/* Port283 */
1155	PINMUX_DATA(SIM1_RST_MARK,		PORT283_FN1),
1156
1157	/* Port289 */
1158	PINMUX_DATA(SDHID1_0_MARK,		PORT289_FN1),
1159	PINMUX_DATA(STMDATA0_2_MARK,		PORT289_FN3),
1160
1161	/* Port290 */
1162	PINMUX_DATA(SDHID1_1_MARK,		PORT290_FN1),
1163	PINMUX_DATA(STMDATA1_2_MARK,		PORT290_FN3),
1164	PINMUX_DATA(IRQ51_MARK,			PORT290_FN0),
1165
1166	/* Port291 - Port294 FN1 */
1167	PINMUX_DATA(SDHID1_2_MARK,		PORT291_FN1),
1168	PINMUX_DATA(SDHID1_3_MARK,		PORT292_FN1),
1169	PINMUX_DATA(SDHICLK1_MARK,		PORT293_FN1),
1170	PINMUX_DATA(SDHICMD1_MARK,		PORT294_FN1),
1171
1172	/* Port291 - Port294 FN3 */
1173	PINMUX_DATA(STMDATA2_2_MARK,		PORT291_FN3),
1174	PINMUX_DATA(STMDATA3_2_MARK,		PORT292_FN3),
1175	PINMUX_DATA(STMCLK_2_MARK,		PORT293_FN3),
1176	PINMUX_DATA(STMSIDI_2_MARK,		PORT294_FN3),
1177
1178	/* Port295 */
1179	PINMUX_DATA(SDHID2_0_MARK,		PORT295_FN1),
1180	PINMUX_DATA(MSIOF4_TXD_MARK,		PORT295_FN2),
1181	PINMUX_DATA(SCIFB2_TXD_295_MARK,	PORT295_FN3,	MSEL3CR_10_1),
1182	PINMUX_DATA(MSIOF6_TXD_MARK,		PORT295_FN4),
1183
1184	/* Port296 */
1185	PINMUX_DATA(SDHID2_1_MARK,		PORT296_FN1),
1186	PINMUX_DATA(MSIOF6_SS2_MARK,		PORT296_FN4),
1187	PINMUX_DATA(IRQ52_MARK,			PORT296_FN0),
1188
1189	/* Port297 - Port300 FN1 */
1190	PINMUX_DATA(SDHID2_2_MARK,		PORT297_FN1),
1191	PINMUX_DATA(SDHID2_3_MARK,		PORT298_FN1),
1192	PINMUX_DATA(SDHICLK2_MARK,		PORT299_FN1),
1193	PINMUX_DATA(SDHICMD2_MARK,		PORT300_FN1),
1194
1195	/* Port297 - Port300 FN2 */
1196	PINMUX_DATA(MSIOF4_RXD_MARK,		PORT297_FN2),
1197	PINMUX_DATA(MSIOF4_SYNC_MARK,		PORT298_FN2),
1198	PINMUX_DATA(MSIOF4_SCK_MARK,		PORT299_FN2),
1199	PINMUX_DATA(MSIOF4_SS1_MARK,		PORT300_FN2),
1200
1201	/* Port297 - Port300 FN3 */
1202	PINMUX_DATA(SCIFB2_RXD_297_MARK,	PORT297_FN3,	MSEL3CR_10_1),
1203	PINMUX_DATA(SCIFB2_CTS_298_MARK,	PORT298_FN3,	MSEL3CR_10_1),
1204	PINMUX_DATA(SCIFB2_SCK_299_MARK,	PORT299_FN3),
1205	PINMUX_DATA(SCIFB2_RTS_300_MARK,	PORT300_FN3),
1206
1207	/* Port297 - Port300 FN4 */
1208	PINMUX_DATA(MSIOF6_RXD_MARK,		PORT297_FN4),
1209	PINMUX_DATA(MSIOF6_SYNC_MARK,		PORT298_FN4),
1210	PINMUX_DATA(MSIOF6_SCK_MARK,		PORT299_FN4),
1211	PINMUX_DATA(MSIOF6_SS1_MARK,		PORT300_FN4),
1212
1213	/* Port301 */
1214	PINMUX_DATA(SDHICD0_MARK,		PORT301_FN1),
1215	PINMUX_DATA(IRQ50_MARK,			PORT301_FN0),
1216
1217	/* Port302 - Port306 FN1 */
1218	PINMUX_DATA(SDHID0_0_MARK,		PORT302_FN1),
1219	PINMUX_DATA(SDHID0_1_MARK,		PORT303_FN1),
1220	PINMUX_DATA(SDHID0_2_MARK,		PORT304_FN1),
1221	PINMUX_DATA(SDHID0_3_MARK,		PORT305_FN1),
1222	PINMUX_DATA(SDHICMD0_MARK,		PORT306_FN1),
1223
1224	/* Port302 - Port306 FN3 */
1225	PINMUX_DATA(STMDATA0_1_MARK,		PORT302_FN3),
1226	PINMUX_DATA(STMDATA1_1_MARK,		PORT303_FN3),
1227	PINMUX_DATA(STMDATA2_1_MARK,		PORT304_FN3),
1228	PINMUX_DATA(STMDATA3_1_MARK,		PORT305_FN3),
1229	PINMUX_DATA(STMSIDI_1_MARK,		PORT306_FN3),
1230
1231	/* Port307 */
1232	PINMUX_DATA(SDHIWP0_MARK,		PORT307_FN1),
1233
1234	/* Port308 */
1235	PINMUX_DATA(SDHICLK0_MARK,		PORT308_FN1),
1236	PINMUX_DATA(STMCLK_1_MARK,		PORT308_FN3),
1237
1238	/* Port320 - Port329 */
1239	PINMUX_DATA(IRQ16_MARK,			PORT320_FN0),
1240	PINMUX_DATA(IRQ17_MARK,			PORT321_FN0),
1241	PINMUX_DATA(IRQ28_MARK,			PORT322_FN0),
1242	PINMUX_DATA(IRQ29_MARK,			PORT323_FN0),
1243	PINMUX_DATA(IRQ30_MARK,			PORT324_FN0),
1244	PINMUX_DATA(IRQ53_MARK,			PORT325_FN0),
1245	PINMUX_DATA(IRQ54_MARK,			PORT326_FN0),
1246	PINMUX_DATA(IRQ55_MARK,			PORT327_FN0),
1247	PINMUX_DATA(IRQ56_MARK,			PORT328_FN0),
1248	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
1249};
1250
1251#define __O	(SH_PFC_PIN_CFG_OUTPUT)
1252#define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1253#define __PUD	(SH_PFC_PIN_CFG_PULL_UP_DOWN)
1254
1255#define R8A73A4_PIN_IO_PU_PD(pin)       SH_PFC_PIN_CFG(pin, __IO | __PUD)
1256#define R8A73A4_PIN_O(pin)              SH_PFC_PIN_CFG(pin, __O)
1257
1258static const struct sh_pfc_pin pinmux_pins[] = {
1259	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1260	R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1261	R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1262	R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1263	R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1264	R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1265	R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1266	R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1267	R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1268	R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1269	R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1270	R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1271	R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1272	R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1273	R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1274	R8A73A4_PIN_IO_PU_PD(30),
1275	R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1276	R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1277	R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1278	R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1279	R8A73A4_PIN_IO_PU_PD(40),
1280	R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1281	R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1282	R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1283	R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1284	R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1285	R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1286	R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1287	R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1288	R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1289	R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1290	R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1291	R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1292	R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1293	R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1294	R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1295	R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1296	R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1297	R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1298	R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1299	R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1300	R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1301	R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1302	R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1303	R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1304	R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1305	R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1306	R8A73A4_PIN_IO_PU_PD(126),
1307	R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1308	R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1309	R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1310	R8A73A4_PIN_IO_PU_PD(134),
1311	R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1312	R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1313	R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1314	R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1315	R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1316	R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1317	R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1318	R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1319	R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1320	R8A73A4_PIN_IO_PU_PD(178),
1321	R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1322	R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1323	R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1324	R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1325	R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1326	R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1327	R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1328	R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1329	R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1330	R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1331	R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1332	R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1333	R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1334	R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1335	R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1336	R8A73A4_PIN_IO_PU_PD(222),
1337	R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1338	R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1339	R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1340	R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1341	R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1342	R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1343	R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1344	R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1345	R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1346	R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1347	R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1348	R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1349	R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1350	R8A73A4_PIN_IO_PU_PD(250),
1351	R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1352	R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1353	R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1354	R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1355	R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1356	R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1357	R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1358	R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1359	R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1360	R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1361	R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1362	R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1363	R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1364	R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1365	R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1366	R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1367	R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1368	R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1369	R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1370	R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1371	R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1372	R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1373	R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1374	R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1375	R8A73A4_PIN_IO_PU_PD(308),
1376	R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1377	R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1378	R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1379	R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1380	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1381};
1382
1383/* - IRQC ------------------------------------------------------------------- */
1384#define IRQC_PINS_MUX(pin, irq_mark)				\
1385static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
1386	pin,							\
1387};								\
1388static const unsigned int irqc_irq##irq_mark##_mux[] = {	\
1389	IRQ##irq_mark##_MARK,					\
1390}
1391IRQC_PINS_MUX(0, 0);
1392IRQC_PINS_MUX(1, 1);
1393IRQC_PINS_MUX(2, 2);
1394IRQC_PINS_MUX(3, 3);
1395IRQC_PINS_MUX(4, 4);
1396IRQC_PINS_MUX(5, 5);
1397IRQC_PINS_MUX(6, 6);
1398IRQC_PINS_MUX(7, 7);
1399IRQC_PINS_MUX(8, 8);
1400IRQC_PINS_MUX(9, 9);
1401IRQC_PINS_MUX(10, 10);
1402IRQC_PINS_MUX(11, 11);
1403IRQC_PINS_MUX(12, 12);
1404IRQC_PINS_MUX(13, 13);
1405IRQC_PINS_MUX(14, 14);
1406IRQC_PINS_MUX(15, 15);
1407IRQC_PINS_MUX(66, 40);
1408IRQC_PINS_MUX(84, 19);
1409IRQC_PINS_MUX(85, 18);
1410IRQC_PINS_MUX(102, 41);
1411IRQC_PINS_MUX(103, 42);
1412IRQC_PINS_MUX(109, 43);
1413IRQC_PINS_MUX(110, 44);
1414IRQC_PINS_MUX(111, 45);
1415IRQC_PINS_MUX(112, 46);
1416IRQC_PINS_MUX(113, 47);
1417IRQC_PINS_MUX(114, 48);
1418IRQC_PINS_MUX(115, 49);
1419IRQC_PINS_MUX(160, 20);
1420IRQC_PINS_MUX(161, 21);
1421IRQC_PINS_MUX(162, 22);
1422IRQC_PINS_MUX(163, 23);
1423IRQC_PINS_MUX(175, 24);
1424IRQC_PINS_MUX(176, 25);
1425IRQC_PINS_MUX(177, 26);
1426IRQC_PINS_MUX(178, 27);
1427IRQC_PINS_MUX(192, 31);
1428IRQC_PINS_MUX(193, 32);
1429IRQC_PINS_MUX(194, 33);
1430IRQC_PINS_MUX(195, 34);
1431IRQC_PINS_MUX(196, 35);
1432IRQC_PINS_MUX(197, 36);
1433IRQC_PINS_MUX(198, 37);
1434IRQC_PINS_MUX(199, 38);
1435IRQC_PINS_MUX(200, 39);
1436IRQC_PINS_MUX(290, 51);
1437IRQC_PINS_MUX(296, 52);
1438IRQC_PINS_MUX(301, 50);
1439IRQC_PINS_MUX(320, 16);
1440IRQC_PINS_MUX(321, 17);
1441IRQC_PINS_MUX(322, 28);
1442IRQC_PINS_MUX(323, 29);
1443IRQC_PINS_MUX(324, 30);
1444IRQC_PINS_MUX(325, 53);
1445IRQC_PINS_MUX(326, 54);
1446IRQC_PINS_MUX(327, 55);
1447IRQC_PINS_MUX(328, 56);
1448IRQC_PINS_MUX(329, 57);
1449/* - MMCIF0 ----------------------------------------------------------------- */
1450static const unsigned int mmc0_data_pins[] = {
1451	/* D[0:7] */
1452	164, 165, 166, 167, 168, 169, 170, 171,
1453};
1454static const unsigned int mmc0_data_mux[] = {
1455	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1456	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1457};
1458static const unsigned int mmc0_ctrl_pins[] = {
1459	/* CMD, CLK */
1460	172, 173,
1461};
1462static const unsigned int mmc0_ctrl_mux[] = {
1463	MMCCMD0_MARK, MMCCLK0_MARK,
1464};
1465/* - MMCIF1 ----------------------------------------------------------------- */
1466static const unsigned int mmc1_data_pins[] = {
1467	/* D[0:7] */
1468	199, 198, 197, 196, 195, 194, 193, 192,
1469};
1470static const unsigned int mmc1_data_mux[] = {
1471	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1472	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1473};
1474static const unsigned int mmc1_ctrl_pins[] = {
1475	/* CMD, CLK */
1476	200, 203,
1477};
1478static const unsigned int mmc1_ctrl_mux[] = {
1479	MMCCMD1_MARK, MMCCLK1_MARK,
1480};
1481/* - SCIFA0 ----------------------------------------------------------------- */
1482static const unsigned int scifa0_data_pins[] = {
1483	/* SCIFA0_RXD, SCIFA0_TXD */
1484	117, 116,
1485};
1486static const unsigned int scifa0_data_mux[] = {
1487	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1488};
1489static const unsigned int scifa0_clk_pins[] = {
1490	/* SCIFA0_SCK */
1491	34,
1492};
1493static const unsigned int scifa0_clk_mux[] = {
1494	SCIFA0_SCK_MARK,
1495};
1496static const unsigned int scifa0_ctrl_pins[] = {
1497	/* SCIFA0_RTS, SCIFA0_CTS */
1498	32, 33,
1499};
1500static const unsigned int scifa0_ctrl_mux[] = {
1501	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1502};
1503/* - SCIFA1 ----------------------------------------------------------------- */
1504static const unsigned int scifa1_data_pins[] = {
1505	/* SCIFA1_RXD, SCIFA1_TXD */
1506	119, 118,
1507};
1508static const unsigned int scifa1_data_mux[] = {
1509	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1510};
1511static const unsigned int scifa1_clk_pins[] = {
1512	/* SCIFA1_SCK */
1513	37,
1514};
1515static const unsigned int scifa1_clk_mux[] = {
1516	SCIFA1_SCK_MARK,
1517};
1518static const unsigned int scifa1_ctrl_pins[] = {
1519	/* SCIFA1_RTS, SCIFA1_CTS */
1520	35, 36,
1521};
1522static const unsigned int scifa1_ctrl_mux[] = {
1523	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1524};
1525/* - SCIFB0 ----------------------------------------------------------------- */
1526static const unsigned int scifb0_data_pins[] = {
1527	/* SCIFB0_RXD, SCIFB0_TXD */
1528	123, 122,
1529};
1530static const unsigned int scifb0_data_mux[] = {
1531	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1532};
1533static const unsigned int scifb0_clk_pins[] = {
1534	/* SCIFB0_SCK */
1535	40,
1536};
1537static const unsigned int scifb0_clk_mux[] = {
1538	SCIFB0_SCK_MARK,
1539};
1540static const unsigned int scifb0_ctrl_pins[] = {
1541	/* SCIFB0_RTS, SCIFB0_CTS */
1542	38, 39,
1543};
1544static const unsigned int scifb0_ctrl_mux[] = {
1545	SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1546};
1547/* - SCIFB1 ----------------------------------------------------------------- */
1548static const unsigned int scifb1_data_pins[] = {
1549	/* SCIFB1_RXD, SCIFB1_TXD */
1550	27, 26,
1551};
1552static const unsigned int scifb1_data_mux[] = {
1553	SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1554};
1555static const unsigned int scifb1_clk_pins[] = {
1556	/* SCIFB1_SCK */
1557	28,
1558};
1559static const unsigned int scifb1_clk_mux[] = {
1560	SCIFB1_SCK_28_MARK,
1561};
1562static const unsigned int scifb1_ctrl_pins[] = {
1563	/* SCIFB1_RTS, SCIFB1_CTS */
1564	24, 25,
1565};
1566static const unsigned int scifb1_ctrl_mux[] = {
1567	SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1568};
1569static const unsigned int scifb1_data_b_pins[] = {
1570	/* SCIFB1_RXD, SCIFB1_TXD */
1571	72, 67,
1572};
1573static const unsigned int scifb1_data_b_mux[] = {
1574	SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1575};
1576static const unsigned int scifb1_clk_b_pins[] = {
1577	/* SCIFB1_SCK */
1578	261,
1579};
1580static const unsigned int scifb1_clk_b_mux[] = {
1581	SCIFB1_SCK_261_MARK,
1582};
1583static const unsigned int scifb1_ctrl_b_pins[] = {
1584	/* SCIFB1_RTS, SCIFB1_CTS */
1585	70, 71,
1586};
1587static const unsigned int scifb1_ctrl_b_mux[] = {
1588	SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1589};
1590/* - SCIFB2 ----------------------------------------------------------------- */
1591static const unsigned int scifb2_data_pins[] = {
1592	/* SCIFB2_RXD, SCIFB2_TXD */
1593	69, 68,
1594};
1595static const unsigned int scifb2_data_mux[] = {
1596	SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1597};
1598static const unsigned int scifb2_clk_pins[] = {
1599	/* SCIFB2_SCK */
1600	262,
1601};
1602static const unsigned int scifb2_clk_mux[] = {
1603	SCIFB2_SCK_262_MARK,
1604};
1605static const unsigned int scifb2_ctrl_pins[] = {
1606	/* SCIFB2_RTS, SCIFB2_CTS */
1607	73, 66,
1608};
1609static const unsigned int scifb2_ctrl_mux[] = {
1610	SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1611};
1612static const unsigned int scifb2_data_b_pins[] = {
1613	/* SCIFB2_RXD, SCIFB2_TXD */
1614	297, 295,
1615};
1616static const unsigned int scifb2_data_b_mux[] = {
1617	SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1618};
1619static const unsigned int scifb2_clk_b_pins[] = {
1620	/* SCIFB2_SCK */
1621	299,
1622};
1623static const unsigned int scifb2_clk_b_mux[] = {
1624	SCIFB2_SCK_299_MARK,
1625};
1626static const unsigned int scifb2_ctrl_b_pins[] = {
1627	/* SCIFB2_RTS, SCIFB2_CTS */
1628	300, 298,
1629};
1630static const unsigned int scifb2_ctrl_b_mux[] = {
1631	SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1632};
1633/* - SCIFB3 ----------------------------------------------------------------- */
1634static const unsigned int scifb3_data_pins[] = {
1635	/* SCIFB3_RXD, SCIFB3_TXD */
1636	22, 21,
1637};
1638static const unsigned int scifb3_data_mux[] = {
1639	SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1640};
1641static const unsigned int scifb3_clk_pins[] = {
1642	/* SCIFB3_SCK */
1643	23,
1644};
1645static const unsigned int scifb3_clk_mux[] = {
1646	SCIFB3_SCK_23_MARK,
1647};
1648static const unsigned int scifb3_ctrl_pins[] = {
1649	/* SCIFB3_RTS, SCIFB3_CTS */
1650	19, 20,
1651};
1652static const unsigned int scifb3_ctrl_mux[] = {
1653	SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1654};
1655static const unsigned int scifb3_data_b_pins[] = {
1656	/* SCIFB3_RXD, SCIFB3_TXD */
1657	120, 121,
1658};
1659static const unsigned int scifb3_data_b_mux[] = {
1660	SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1661};
1662static const unsigned int scifb3_clk_b_pins[] = {
1663	/* SCIFB3_SCK */
1664	40,
1665};
1666static const unsigned int scifb3_clk_b_mux[] = {
1667	SCIFB3_SCK_40_MARK,
1668};
1669static const unsigned int scifb3_ctrl_b_pins[] = {
1670	/* SCIFB3_RTS, SCIFB3_CTS */
1671	38, 39,
1672};
1673static const unsigned int scifb3_ctrl_b_mux[] = {
1674	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1675};
1676/* - SDHI0 ------------------------------------------------------------------ */
1677static const unsigned int sdhi0_data_pins[] = {
1678	/* D[0:3] */
1679	302, 303, 304, 305,
1680};
1681static const unsigned int sdhi0_data_mux[] = {
1682	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1683};
1684static const unsigned int sdhi0_ctrl_pins[] = {
1685	/* CLK, CMD */
1686	308, 306,
1687};
1688static const unsigned int sdhi0_ctrl_mux[] = {
1689	SDHICLK0_MARK, SDHICMD0_MARK,
1690};
1691static const unsigned int sdhi0_cd_pins[] = {
1692	/* CD */
1693	301,
1694};
1695static const unsigned int sdhi0_cd_mux[] = {
1696	SDHICD0_MARK,
1697};
1698static const unsigned int sdhi0_wp_pins[] = {
1699	/* WP */
1700	307,
1701};
1702static const unsigned int sdhi0_wp_mux[] = {
1703	SDHIWP0_MARK,
1704};
1705/* - SDHI1 ------------------------------------------------------------------ */
1706static const unsigned int sdhi1_data_pins[] = {
1707	/* D[0:3] */
1708	289, 290, 291, 292,
1709};
1710static const unsigned int sdhi1_data_mux[] = {
1711	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1712};
1713static const unsigned int sdhi1_ctrl_pins[] = {
1714	/* CLK, CMD */
1715	293, 294,
1716};
1717static const unsigned int sdhi1_ctrl_mux[] = {
1718	SDHICLK1_MARK, SDHICMD1_MARK,
1719};
1720/* - SDHI2 ------------------------------------------------------------------ */
1721static const unsigned int sdhi2_data_pins[] = {
1722	/* D[0:3] */
1723	295, 296, 297, 298,
1724};
1725static const unsigned int sdhi2_data_mux[] = {
1726	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1727};
1728static const unsigned int sdhi2_ctrl_pins[] = {
1729	/* CLK, CMD */
1730	299, 300,
1731};
1732static const unsigned int sdhi2_ctrl_mux[] = {
1733	SDHICLK2_MARK, SDHICMD2_MARK,
1734};
1735
1736static const struct sh_pfc_pin_group pinmux_groups[] = {
1737	SH_PFC_PIN_GROUP(irqc_irq0),
1738	SH_PFC_PIN_GROUP(irqc_irq1),
1739	SH_PFC_PIN_GROUP(irqc_irq2),
1740	SH_PFC_PIN_GROUP(irqc_irq3),
1741	SH_PFC_PIN_GROUP(irqc_irq4),
1742	SH_PFC_PIN_GROUP(irqc_irq5),
1743	SH_PFC_PIN_GROUP(irqc_irq6),
1744	SH_PFC_PIN_GROUP(irqc_irq7),
1745	SH_PFC_PIN_GROUP(irqc_irq8),
1746	SH_PFC_PIN_GROUP(irqc_irq9),
1747	SH_PFC_PIN_GROUP(irqc_irq10),
1748	SH_PFC_PIN_GROUP(irqc_irq11),
1749	SH_PFC_PIN_GROUP(irqc_irq12),
1750	SH_PFC_PIN_GROUP(irqc_irq13),
1751	SH_PFC_PIN_GROUP(irqc_irq14),
1752	SH_PFC_PIN_GROUP(irqc_irq15),
1753	SH_PFC_PIN_GROUP(irqc_irq16),
1754	SH_PFC_PIN_GROUP(irqc_irq17),
1755	SH_PFC_PIN_GROUP(irqc_irq18),
1756	SH_PFC_PIN_GROUP(irqc_irq19),
1757	SH_PFC_PIN_GROUP(irqc_irq20),
1758	SH_PFC_PIN_GROUP(irqc_irq21),
1759	SH_PFC_PIN_GROUP(irqc_irq22),
1760	SH_PFC_PIN_GROUP(irqc_irq23),
1761	SH_PFC_PIN_GROUP(irqc_irq24),
1762	SH_PFC_PIN_GROUP(irqc_irq25),
1763	SH_PFC_PIN_GROUP(irqc_irq26),
1764	SH_PFC_PIN_GROUP(irqc_irq27),
1765	SH_PFC_PIN_GROUP(irqc_irq28),
1766	SH_PFC_PIN_GROUP(irqc_irq29),
1767	SH_PFC_PIN_GROUP(irqc_irq30),
1768	SH_PFC_PIN_GROUP(irqc_irq31),
1769	SH_PFC_PIN_GROUP(irqc_irq32),
1770	SH_PFC_PIN_GROUP(irqc_irq33),
1771	SH_PFC_PIN_GROUP(irqc_irq34),
1772	SH_PFC_PIN_GROUP(irqc_irq35),
1773	SH_PFC_PIN_GROUP(irqc_irq36),
1774	SH_PFC_PIN_GROUP(irqc_irq37),
1775	SH_PFC_PIN_GROUP(irqc_irq38),
1776	SH_PFC_PIN_GROUP(irqc_irq39),
1777	SH_PFC_PIN_GROUP(irqc_irq40),
1778	SH_PFC_PIN_GROUP(irqc_irq41),
1779	SH_PFC_PIN_GROUP(irqc_irq42),
1780	SH_PFC_PIN_GROUP(irqc_irq43),
1781	SH_PFC_PIN_GROUP(irqc_irq44),
1782	SH_PFC_PIN_GROUP(irqc_irq45),
1783	SH_PFC_PIN_GROUP(irqc_irq46),
1784	SH_PFC_PIN_GROUP(irqc_irq47),
1785	SH_PFC_PIN_GROUP(irqc_irq48),
1786	SH_PFC_PIN_GROUP(irqc_irq49),
1787	SH_PFC_PIN_GROUP(irqc_irq50),
1788	SH_PFC_PIN_GROUP(irqc_irq51),
1789	SH_PFC_PIN_GROUP(irqc_irq52),
1790	SH_PFC_PIN_GROUP(irqc_irq53),
1791	SH_PFC_PIN_GROUP(irqc_irq54),
1792	SH_PFC_PIN_GROUP(irqc_irq55),
1793	SH_PFC_PIN_GROUP(irqc_irq56),
1794	SH_PFC_PIN_GROUP(irqc_irq57),
1795	BUS_DATA_PIN_GROUP(mmc0_data, 1),
1796	BUS_DATA_PIN_GROUP(mmc0_data, 4),
1797	BUS_DATA_PIN_GROUP(mmc0_data, 8),
1798	SH_PFC_PIN_GROUP(mmc0_ctrl),
1799	BUS_DATA_PIN_GROUP(mmc1_data, 1),
1800	BUS_DATA_PIN_GROUP(mmc1_data, 4),
1801	BUS_DATA_PIN_GROUP(mmc1_data, 8),
1802	SH_PFC_PIN_GROUP(mmc1_ctrl),
1803	SH_PFC_PIN_GROUP(scifa0_data),
1804	SH_PFC_PIN_GROUP(scifa0_clk),
1805	SH_PFC_PIN_GROUP(scifa0_ctrl),
1806	SH_PFC_PIN_GROUP(scifa1_data),
1807	SH_PFC_PIN_GROUP(scifa1_clk),
1808	SH_PFC_PIN_GROUP(scifa1_ctrl),
1809	SH_PFC_PIN_GROUP(scifb0_data),
1810	SH_PFC_PIN_GROUP(scifb0_clk),
1811	SH_PFC_PIN_GROUP(scifb0_ctrl),
1812	SH_PFC_PIN_GROUP(scifb1_data),
1813	SH_PFC_PIN_GROUP(scifb1_clk),
1814	SH_PFC_PIN_GROUP(scifb1_ctrl),
1815	SH_PFC_PIN_GROUP(scifb1_data_b),
1816	SH_PFC_PIN_GROUP(scifb1_clk_b),
1817	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1818	SH_PFC_PIN_GROUP(scifb2_data),
1819	SH_PFC_PIN_GROUP(scifb2_clk),
1820	SH_PFC_PIN_GROUP(scifb2_ctrl),
1821	SH_PFC_PIN_GROUP(scifb2_data_b),
1822	SH_PFC_PIN_GROUP(scifb2_clk_b),
1823	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1824	SH_PFC_PIN_GROUP(scifb3_data),
1825	SH_PFC_PIN_GROUP(scifb3_clk),
1826	SH_PFC_PIN_GROUP(scifb3_ctrl),
1827	SH_PFC_PIN_GROUP(scifb3_data_b),
1828	SH_PFC_PIN_GROUP(scifb3_clk_b),
1829	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1830	BUS_DATA_PIN_GROUP(sdhi0_data, 1),
1831	BUS_DATA_PIN_GROUP(sdhi0_data, 4),
1832	SH_PFC_PIN_GROUP(sdhi0_ctrl),
1833	SH_PFC_PIN_GROUP(sdhi0_cd),
1834	SH_PFC_PIN_GROUP(sdhi0_wp),
1835	BUS_DATA_PIN_GROUP(sdhi1_data, 1),
1836	BUS_DATA_PIN_GROUP(sdhi1_data, 4),
1837	SH_PFC_PIN_GROUP(sdhi1_ctrl),
1838	BUS_DATA_PIN_GROUP(sdhi2_data, 1),
1839	BUS_DATA_PIN_GROUP(sdhi2_data, 4),
1840	SH_PFC_PIN_GROUP(sdhi2_ctrl),
1841};
1842
1843static const char * const irqc_groups[] = {
1844	"irqc_irq0",
1845	"irqc_irq1",
1846	"irqc_irq2",
1847	"irqc_irq3",
1848	"irqc_irq4",
1849	"irqc_irq5",
1850	"irqc_irq6",
1851	"irqc_irq7",
1852	"irqc_irq8",
1853	"irqc_irq9",
1854	"irqc_irq10",
1855	"irqc_irq11",
1856	"irqc_irq12",
1857	"irqc_irq13",
1858	"irqc_irq14",
1859	"irqc_irq15",
1860	"irqc_irq16",
1861	"irqc_irq17",
1862	"irqc_irq18",
1863	"irqc_irq19",
1864	"irqc_irq20",
1865	"irqc_irq21",
1866	"irqc_irq22",
1867	"irqc_irq23",
1868	"irqc_irq24",
1869	"irqc_irq25",
1870	"irqc_irq26",
1871	"irqc_irq27",
1872	"irqc_irq28",
1873	"irqc_irq29",
1874	"irqc_irq30",
1875	"irqc_irq31",
1876	"irqc_irq32",
1877	"irqc_irq33",
1878	"irqc_irq34",
1879	"irqc_irq35",
1880	"irqc_irq36",
1881	"irqc_irq37",
1882	"irqc_irq38",
1883	"irqc_irq39",
1884	"irqc_irq40",
1885	"irqc_irq41",
1886	"irqc_irq42",
1887	"irqc_irq43",
1888	"irqc_irq44",
1889	"irqc_irq45",
1890	"irqc_irq46",
1891	"irqc_irq47",
1892	"irqc_irq48",
1893	"irqc_irq49",
1894	"irqc_irq50",
1895	"irqc_irq51",
1896	"irqc_irq52",
1897	"irqc_irq53",
1898	"irqc_irq54",
1899	"irqc_irq55",
1900	"irqc_irq56",
1901	"irqc_irq57",
1902};
1903
1904static const char * const mmc0_groups[] = {
1905	"mmc0_data1",
1906	"mmc0_data4",
1907	"mmc0_data8",
1908	"mmc0_ctrl",
1909};
1910
1911static const char * const mmc1_groups[] = {
1912	"mmc1_data1",
1913	"mmc1_data4",
1914	"mmc1_data8",
1915	"mmc1_ctrl",
1916};
1917
1918static const char * const scifa0_groups[] = {
1919	"scifa0_data",
1920	"scifa0_clk",
1921	"scifa0_ctrl",
1922};
1923
1924static const char * const scifa1_groups[] = {
1925	"scifa1_data",
1926	"scifa1_clk",
1927	"scifa1_ctrl",
1928};
1929
1930static const char * const scifb0_groups[] = {
1931	"scifb0_data",
1932	"scifb0_clk",
1933	"scifb0_ctrl",
1934};
1935
1936static const char * const scifb1_groups[] = {
1937	"scifb1_data",
1938	"scifb1_clk",
1939	"scifb1_ctrl",
1940	"scifb1_data_b",
1941	"scifb1_clk_b",
1942	"scifb1_ctrl_b",
1943};
1944
1945static const char * const scifb2_groups[] = {
1946	"scifb2_data",
1947	"scifb2_clk",
1948	"scifb2_ctrl",
1949	"scifb2_data_b",
1950	"scifb2_clk_b",
1951	"scifb2_ctrl_b",
1952};
1953
1954static const char * const scifb3_groups[] = {
1955	"scifb3_data",
1956	"scifb3_clk",
1957	"scifb3_ctrl",
1958	"scifb3_data_b",
1959	"scifb3_clk_b",
1960	"scifb3_ctrl_b",
1961};
1962
1963static const char * const sdhi0_groups[] = {
1964	"sdhi0_data1",
1965	"sdhi0_data4",
1966	"sdhi0_ctrl",
1967	"sdhi0_cd",
1968	"sdhi0_wp",
1969};
1970
1971static const char * const sdhi1_groups[] = {
1972	"sdhi1_data1",
1973	"sdhi1_data4",
1974	"sdhi1_ctrl",
1975};
1976
1977static const char * const sdhi2_groups[] = {
1978	"sdhi2_data1",
1979	"sdhi2_data4",
1980	"sdhi2_ctrl",
1981};
1982
1983static const struct sh_pfc_function pinmux_functions[] = {
1984	SH_PFC_FUNCTION(irqc),
1985	SH_PFC_FUNCTION(mmc0),
1986	SH_PFC_FUNCTION(mmc1),
1987	SH_PFC_FUNCTION(scifa0),
1988	SH_PFC_FUNCTION(scifa1),
1989	SH_PFC_FUNCTION(scifb0),
1990	SH_PFC_FUNCTION(scifb1),
1991	SH_PFC_FUNCTION(scifb2),
1992	SH_PFC_FUNCTION(scifb3),
1993	SH_PFC_FUNCTION(sdhi0),
1994	SH_PFC_FUNCTION(sdhi1),
1995	SH_PFC_FUNCTION(sdhi2),
1996};
1997
1998static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1999	PORTCR(0, 0xe6050000),
2000	PORTCR(1, 0xe6050001),
2001	PORTCR(2, 0xe6050002),
2002	PORTCR(3, 0xe6050003),
2003	PORTCR(4, 0xe6050004),
2004	PORTCR(5, 0xe6050005),
2005	PORTCR(6, 0xe6050006),
2006	PORTCR(7, 0xe6050007),
2007	PORTCR(8, 0xe6050008),
2008	PORTCR(9, 0xe6050009),
2009	PORTCR(10, 0xe605000A),
2010	PORTCR(11, 0xe605000B),
2011	PORTCR(12, 0xe605000C),
2012	PORTCR(13, 0xe605000D),
2013	PORTCR(14, 0xe605000E),
2014	PORTCR(15, 0xe605000F),
2015	PORTCR(16, 0xe6050010),
2016	PORTCR(17, 0xe6050011),
2017	PORTCR(18, 0xe6050012),
2018	PORTCR(19, 0xe6050013),
2019	PORTCR(20, 0xe6050014),
2020	PORTCR(21, 0xe6050015),
2021	PORTCR(22, 0xe6050016),
2022	PORTCR(23, 0xe6050017),
2023	PORTCR(24, 0xe6050018),
2024	PORTCR(25, 0xe6050019),
2025	PORTCR(26, 0xe605001A),
2026	PORTCR(27, 0xe605001B),
2027	PORTCR(28, 0xe605001C),
2028	PORTCR(29, 0xe605001D),
2029	PORTCR(30, 0xe605001E),
2030	PORTCR(32, 0xe6051020),
2031	PORTCR(33, 0xe6051021),
2032	PORTCR(34, 0xe6051022),
2033	PORTCR(35, 0xe6051023),
2034	PORTCR(36, 0xe6051024),
2035	PORTCR(37, 0xe6051025),
2036	PORTCR(38, 0xe6051026),
2037	PORTCR(39, 0xe6051027),
2038	PORTCR(40, 0xe6051028),
2039	PORTCR(64, 0xe6050040),
2040	PORTCR(65, 0xe6050041),
2041	PORTCR(66, 0xe6050042),
2042	PORTCR(67, 0xe6050043),
2043	PORTCR(68, 0xe6050044),
2044	PORTCR(69, 0xe6050045),
2045	PORTCR(70, 0xe6050046),
2046	PORTCR(71, 0xe6050047),
2047	PORTCR(72, 0xe6050048),
2048	PORTCR(73, 0xe6050049),
2049	PORTCR(74, 0xe605004A),
2050	PORTCR(75, 0xe605004B),
2051	PORTCR(76, 0xe605004C),
2052	PORTCR(77, 0xe605004D),
2053	PORTCR(78, 0xe605004E),
2054	PORTCR(79, 0xe605004F),
2055	PORTCR(80, 0xe6050050),
2056	PORTCR(81, 0xe6050051),
2057	PORTCR(82, 0xe6050052),
2058	PORTCR(83, 0xe6050053),
2059	PORTCR(84, 0xe6050054),
2060	PORTCR(85, 0xe6050055),
2061	PORTCR(96, 0xe6051060),
2062	PORTCR(97, 0xe6051061),
2063	PORTCR(98, 0xe6051062),
2064	PORTCR(99, 0xe6051063),
2065	PORTCR(100, 0xe6051064),
2066	PORTCR(101, 0xe6051065),
2067	PORTCR(102, 0xe6051066),
2068	PORTCR(103, 0xe6051067),
2069	PORTCR(104, 0xe6051068),
2070	PORTCR(105, 0xe6051069),
2071	PORTCR(106, 0xe605106A),
2072	PORTCR(107, 0xe605106B),
2073	PORTCR(108, 0xe605106C),
2074	PORTCR(109, 0xe605106D),
2075	PORTCR(110, 0xe605106E),
2076	PORTCR(111, 0xe605106F),
2077	PORTCR(112, 0xe6051070),
2078	PORTCR(113, 0xe6051071),
2079	PORTCR(114, 0xe6051072),
2080	PORTCR(115, 0xe6051073),
2081	PORTCR(116, 0xe6051074),
2082	PORTCR(117, 0xe6051075),
2083	PORTCR(118, 0xe6051076),
2084	PORTCR(119, 0xe6051077),
2085	PORTCR(120, 0xe6051078),
2086	PORTCR(121, 0xe6051079),
2087	PORTCR(122, 0xe605107A),
2088	PORTCR(123, 0xe605107B),
2089	PORTCR(124, 0xe605107C),
2090	PORTCR(125, 0xe605107D),
2091	PORTCR(126, 0xe605107E),
2092	PORTCR(128, 0xe6051080),
2093	PORTCR(129, 0xe6051081),
2094	PORTCR(130, 0xe6051082),
2095	PORTCR(131, 0xe6051083),
2096	PORTCR(132, 0xe6051084),
2097	PORTCR(133, 0xe6051085),
2098	PORTCR(134, 0xe6051086),
2099	PORTCR(160, 0xe60520A0),
2100	PORTCR(161, 0xe60520A1),
2101	PORTCR(162, 0xe60520A2),
2102	PORTCR(163, 0xe60520A3),
2103	PORTCR(164, 0xe60520A4),
2104	PORTCR(165, 0xe60520A5),
2105	PORTCR(166, 0xe60520A6),
2106	PORTCR(167, 0xe60520A7),
2107	PORTCR(168, 0xe60520A8),
2108	PORTCR(169, 0xe60520A9),
2109	PORTCR(170, 0xe60520AA),
2110	PORTCR(171, 0xe60520AB),
2111	PORTCR(172, 0xe60520AC),
2112	PORTCR(173, 0xe60520AD),
2113	PORTCR(174, 0xe60520AE),
2114	PORTCR(175, 0xe60520AF),
2115	PORTCR(176, 0xe60520B0),
2116	PORTCR(177, 0xe60520B1),
2117	PORTCR(178, 0xe60520B2),
2118	PORTCR(192, 0xe60520C0),
2119	PORTCR(193, 0xe60520C1),
2120	PORTCR(194, 0xe60520C2),
2121	PORTCR(195, 0xe60520C3),
2122	PORTCR(196, 0xe60520C4),
2123	PORTCR(197, 0xe60520C5),
2124	PORTCR(198, 0xe60520C6),
2125	PORTCR(199, 0xe60520C7),
2126	PORTCR(200, 0xe60520C8),
2127	PORTCR(201, 0xe60520C9),
2128	PORTCR(202, 0xe60520CA),
2129	PORTCR(203, 0xe60520CB),
2130	PORTCR(204, 0xe60520CC),
2131	PORTCR(205, 0xe60520CD),
2132	PORTCR(206, 0xe60520CE),
2133	PORTCR(207, 0xe60520CF),
2134	PORTCR(208, 0xe60520D0),
2135	PORTCR(209, 0xe60520D1),
2136	PORTCR(210, 0xe60520D2),
2137	PORTCR(211, 0xe60520D3),
2138	PORTCR(212, 0xe60520D4),
2139	PORTCR(213, 0xe60520D5),
2140	PORTCR(214, 0xe60520D6),
2141	PORTCR(215, 0xe60520D7),
2142	PORTCR(216, 0xe60520D8),
2143	PORTCR(217, 0xe60520D9),
2144	PORTCR(218, 0xe60520DA),
2145	PORTCR(219, 0xe60520DB),
2146	PORTCR(220, 0xe60520DC),
2147	PORTCR(221, 0xe60520DD),
2148	PORTCR(222, 0xe60520DE),
2149	PORTCR(224, 0xe60520E0),
2150	PORTCR(225, 0xe60520E1),
2151	PORTCR(226, 0xe60520E2),
2152	PORTCR(227, 0xe60520E3),
2153	PORTCR(228, 0xe60520E4),
2154	PORTCR(229, 0xe60520E5),
2155	PORTCR(230, 0xe60520e6),
2156	PORTCR(231, 0xe60520E7),
2157	PORTCR(232, 0xe60520E8),
2158	PORTCR(233, 0xe60520E9),
2159	PORTCR(234, 0xe60520EA),
2160	PORTCR(235, 0xe60520EB),
2161	PORTCR(236, 0xe60520EC),
2162	PORTCR(237, 0xe60520ED),
2163	PORTCR(238, 0xe60520EE),
2164	PORTCR(239, 0xe60520EF),
2165	PORTCR(240, 0xe60520F0),
2166	PORTCR(241, 0xe60520F1),
2167	PORTCR(242, 0xe60520F2),
2168	PORTCR(243, 0xe60520F3),
2169	PORTCR(244, 0xe60520F4),
2170	PORTCR(245, 0xe60520F5),
2171	PORTCR(246, 0xe60520F6),
2172	PORTCR(247, 0xe60520F7),
2173	PORTCR(248, 0xe60520F8),
2174	PORTCR(249, 0xe60520F9),
2175	PORTCR(250, 0xe60520FA),
2176	PORTCR(256, 0xe6052100),
2177	PORTCR(257, 0xe6052101),
2178	PORTCR(258, 0xe6052102),
2179	PORTCR(259, 0xe6052103),
2180	PORTCR(260, 0xe6052104),
2181	PORTCR(261, 0xe6052105),
2182	PORTCR(262, 0xe6052106),
2183	PORTCR(263, 0xe6052107),
2184	PORTCR(264, 0xe6052108),
2185	PORTCR(265, 0xe6052109),
2186	PORTCR(266, 0xe605210A),
2187	PORTCR(267, 0xe605210B),
2188	PORTCR(268, 0xe605210C),
2189	PORTCR(269, 0xe605210D),
2190	PORTCR(270, 0xe605210E),
2191	PORTCR(271, 0xe605210F),
2192	PORTCR(272, 0xe6052110),
2193	PORTCR(273, 0xe6052111),
2194	PORTCR(274, 0xe6052112),
2195	PORTCR(275, 0xe6052113),
2196	PORTCR(276, 0xe6052114),
2197	PORTCR(277, 0xe6052115),
2198	PORTCR(278, 0xe6052116),
2199	PORTCR(279, 0xe6052117),
2200	PORTCR(280, 0xe6052118),
2201	PORTCR(281, 0xe6052119),
2202	PORTCR(282, 0xe605211A),
2203	PORTCR(283, 0xe605211B),
2204	PORTCR(288, 0xe6053120),
2205	PORTCR(289, 0xe6053121),
2206	PORTCR(290, 0xe6053122),
2207	PORTCR(291, 0xe6053123),
2208	PORTCR(292, 0xe6053124),
2209	PORTCR(293, 0xe6053125),
2210	PORTCR(294, 0xe6053126),
2211	PORTCR(295, 0xe6053127),
2212	PORTCR(296, 0xe6053128),
2213	PORTCR(297, 0xe6053129),
2214	PORTCR(298, 0xe605312A),
2215	PORTCR(299, 0xe605312B),
2216	PORTCR(300, 0xe605312C),
2217	PORTCR(301, 0xe605312D),
2218	PORTCR(302, 0xe605312E),
2219	PORTCR(303, 0xe605312F),
2220	PORTCR(304, 0xe6053130),
2221	PORTCR(305, 0xe6053131),
2222	PORTCR(306, 0xe6053132),
2223	PORTCR(307, 0xe6053133),
2224	PORTCR(308, 0xe6053134),
2225	PORTCR(320, 0xe6053140),
2226	PORTCR(321, 0xe6053141),
2227	PORTCR(322, 0xe6053142),
2228	PORTCR(323, 0xe6053143),
2229	PORTCR(324, 0xe6053144),
2230	PORTCR(325, 0xe6053145),
2231	PORTCR(326, 0xe6053146),
2232	PORTCR(327, 0xe6053147),
2233	PORTCR(328, 0xe6053148),
2234	PORTCR(329, 0xe6053149),
2235
2236	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
2237			MSEL1CR_31_0, MSEL1CR_31_1,
2238			0, 0,
2239			0, 0,
2240			0, 0,
2241			MSEL1CR_27_0, MSEL1CR_27_1,
2242			0, 0,
2243			MSEL1CR_25_0, MSEL1CR_25_1,
2244			MSEL1CR_24_0, MSEL1CR_24_1,
2245			0, 0,
2246			MSEL1CR_22_0, MSEL1CR_22_1,
2247			MSEL1CR_21_0, MSEL1CR_21_1,
2248			MSEL1CR_20_0, MSEL1CR_20_1,
2249			MSEL1CR_19_0, MSEL1CR_19_1,
2250			MSEL1CR_18_0, MSEL1CR_18_1,
2251			MSEL1CR_17_0, MSEL1CR_17_1,
2252			MSEL1CR_16_0, MSEL1CR_16_1,
2253			MSEL1CR_15_0, MSEL1CR_15_1,
2254			MSEL1CR_14_0, MSEL1CR_14_1,
2255			MSEL1CR_13_0, MSEL1CR_13_1,
2256			MSEL1CR_12_0, MSEL1CR_12_1,
2257			MSEL1CR_11_0, MSEL1CR_11_1,
2258			MSEL1CR_10_0, MSEL1CR_10_1,
2259			MSEL1CR_09_0, MSEL1CR_09_1,
2260			MSEL1CR_08_0, MSEL1CR_08_1,
2261			MSEL1CR_07_0, MSEL1CR_07_1,
2262			MSEL1CR_06_0, MSEL1CR_06_1,
2263			MSEL1CR_05_0, MSEL1CR_05_1,
2264			MSEL1CR_04_0, MSEL1CR_04_1,
2265			MSEL1CR_03_0, MSEL1CR_03_1,
2266			MSEL1CR_02_0, MSEL1CR_02_1,
2267			MSEL1CR_01_0, MSEL1CR_01_1,
2268			MSEL1CR_00_0, MSEL1CR_00_1,
2269		))
2270	},
2271	{ PINMUX_CFG_REG_VAR("MSEL3CR", 0xe6058020, 32,
2272			     GROUP(1, -2, 1, 1, 1, -2, 1, 1, 1, 1, 1, 1,
2273				   1, 1, 1, -2, 1, 1, 1, 1, -2, 1, -2, 1,
2274				   -1, 1, 1),
2275			     GROUP(
2276			MSEL3CR_31_0, MSEL3CR_31_1,
2277			/* RESERVED [2] */
2278			MSEL3CR_28_0, MSEL3CR_28_1,
2279			MSEL3CR_27_0, MSEL3CR_27_1,
2280			MSEL3CR_26_0, MSEL3CR_26_1,
2281			/* RESERVED [2] */
2282			MSEL3CR_23_0, MSEL3CR_23_1,
2283			MSEL3CR_22_0, MSEL3CR_22_1,
2284			MSEL3CR_21_0, MSEL3CR_21_1,
2285			MSEL3CR_20_0, MSEL3CR_20_1,
2286			MSEL3CR_19_0, MSEL3CR_19_1,
2287			MSEL3CR_18_0, MSEL3CR_18_1,
2288			MSEL3CR_17_0, MSEL3CR_17_1,
2289			MSEL3CR_16_0, MSEL3CR_16_1,
2290			MSEL3CR_15_0, MSEL3CR_15_1,
2291			/* RESERVED [2] */
2292			MSEL3CR_12_0, MSEL3CR_12_1,
2293			MSEL3CR_11_0, MSEL3CR_11_1,
2294			MSEL3CR_10_0, MSEL3CR_10_1,
2295			MSEL3CR_09_0, MSEL3CR_09_1,
2296			/* RESERVED [2] */
2297			MSEL3CR_06_0, MSEL3CR_06_1,
2298			/* RESERVED [2] */
2299			MSEL3CR_03_0, MSEL3CR_03_1,
2300			/* RESERVED [1] */
2301			MSEL3CR_01_0, MSEL3CR_01_1,
2302			MSEL3CR_00_0, MSEL3CR_00_1,
2303			))
2304	},
2305	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
2306			0, 0,
2307			MSEL4CR_30_0, MSEL4CR_30_1,
2308			MSEL4CR_29_0, MSEL4CR_29_1,
2309			MSEL4CR_28_0, MSEL4CR_28_1,
2310			MSEL4CR_27_0, MSEL4CR_27_1,
2311			MSEL4CR_26_0, MSEL4CR_26_1,
2312			MSEL4CR_25_0, MSEL4CR_25_1,
2313			MSEL4CR_24_0, MSEL4CR_24_1,
2314			MSEL4CR_23_0, MSEL4CR_23_1,
2315			MSEL4CR_22_0, MSEL4CR_22_1,
2316			MSEL4CR_21_0, MSEL4CR_21_1,
2317			MSEL4CR_20_0, MSEL4CR_20_1,
2318			MSEL4CR_19_0, MSEL4CR_19_1,
2319			MSEL4CR_18_0, MSEL4CR_18_1,
2320			MSEL4CR_17_0, MSEL4CR_17_1,
2321			MSEL4CR_16_0, MSEL4CR_16_1,
2322			MSEL4CR_15_0, MSEL4CR_15_1,
2323			MSEL4CR_14_0, MSEL4CR_14_1,
2324			MSEL4CR_13_0, MSEL4CR_13_1,
2325			MSEL4CR_12_0, MSEL4CR_12_1,
2326			MSEL4CR_11_0, MSEL4CR_11_1,
2327			MSEL4CR_10_0, MSEL4CR_10_1,
2328			MSEL4CR_09_0, MSEL4CR_09_1,
2329			0, 0,
2330			MSEL4CR_07_0, MSEL4CR_07_1,
2331			0, 0,
2332			0, 0,
2333			MSEL4CR_04_0, MSEL4CR_04_1,
2334			0, 0,
2335			0, 0,
2336			MSEL4CR_01_0, MSEL4CR_01_1,
2337			0, 0,
2338		))
2339	},
2340	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
2341			MSEL5CR_31_0, MSEL5CR_31_1,
2342			MSEL5CR_30_0, MSEL5CR_30_1,
2343			MSEL5CR_29_0, MSEL5CR_29_1,
2344			MSEL5CR_28_0, MSEL5CR_28_1,
2345			MSEL5CR_27_0, MSEL5CR_27_1,
2346			MSEL5CR_26_0, MSEL5CR_26_1,
2347			MSEL5CR_25_0, MSEL5CR_25_1,
2348			MSEL5CR_24_0, MSEL5CR_24_1,
2349			MSEL5CR_23_0, MSEL5CR_23_1,
2350			MSEL5CR_22_0, MSEL5CR_22_1,
2351			MSEL5CR_21_0, MSEL5CR_21_1,
2352			MSEL5CR_20_0, MSEL5CR_20_1,
2353			MSEL5CR_19_0, MSEL5CR_19_1,
2354			MSEL5CR_18_0, MSEL5CR_18_1,
2355			MSEL5CR_17_0, MSEL5CR_17_1,
2356			MSEL5CR_16_0, MSEL5CR_16_1,
2357			MSEL5CR_15_0, MSEL5CR_15_1,
2358			MSEL5CR_14_0, MSEL5CR_14_1,
2359			MSEL5CR_13_0, MSEL5CR_13_1,
2360			MSEL5CR_12_0, MSEL5CR_12_1,
2361			MSEL5CR_11_0, MSEL5CR_11_1,
2362			MSEL5CR_10_0, MSEL5CR_10_1,
2363			MSEL5CR_09_0, MSEL5CR_09_1,
2364			MSEL5CR_08_0, MSEL5CR_08_1,
2365			MSEL5CR_07_0, MSEL5CR_07_1,
2366			MSEL5CR_06_0, MSEL5CR_06_1,
2367			0, 0,
2368			0, 0,
2369			0, 0,
2370			0, 0,
2371			0, 0,
2372			0, 0,
2373		))
2374	},
2375	{ PINMUX_CFG_REG_VAR("MSEL8CR", 0xe6058034, 32,
2376			     GROUP(-15, 1, -14, 1, 1),
2377			     GROUP(
2378			/* RESERVED [15] */
2379			MSEL8CR_16_0, MSEL8CR_16_1,
2380			/* RESERVED [14] */
2381			MSEL8CR_01_0, MSEL8CR_01_1,
2382			MSEL8CR_00_0, MSEL8CR_00_1,
2383		))
2384	},
2385	{ /* sentinel */ }
2386};
2387
2388static const struct pinmux_data_reg pinmux_data_regs[] = {
2389
2390	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
2391			0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2392			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2393			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2394			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2395			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2396			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2397			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2398			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2399		))
2400	},
2401	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
2402			0, 0, 0, 0,
2403			0, 0, 0, 0,
2404			0, 0, 0, 0,
2405			0, 0, 0, 0,
2406			0, 0, 0, 0,
2407			0, 0, 0, PORT40_DATA,
2408			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2409			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2410		))
2411	},
2412	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
2413			0, 0, 0, 0,
2414			0, 0, 0, 0,
2415			0, 0, PORT85_DATA, PORT84_DATA,
2416			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2417			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2418			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2419			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2420			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2421		))
2422	},
2423	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
2424			0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2425			PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2426			PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2427			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2428			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2429			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2430			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2431			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2432		))
2433	},
2434	{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
2435			0, 0, 0, 0,
2436			0, 0, 0, 0,
2437			0, 0, 0, 0,
2438			0, 0, 0, 0,
2439			0, 0, 0, 0,
2440			0, 0, 0, 0,
2441			0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2442			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2443		))
2444	},
2445	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
2446			0, 0, 0, 0,
2447			0, 0, 0, 0,
2448			0, 0, 0, 0,
2449			0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2450			PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2451			PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2452			PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2453			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2454		))
2455	},
2456	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
2457			0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2458			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2459			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2460			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2461			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2462			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2463			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2464			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2465		))
2466	},
2467	{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
2468			0, 0, 0, 0,
2469			0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2470			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2471			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2472			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2473			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2474			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2475			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2476		))
2477	},
2478	{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
2479			0, 0, 0, 0,
2480			PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2481			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2482			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2483			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2484			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2485			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2486			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2487		))
2488	},
2489	{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
2490			0, 0, 0, 0,
2491			0, 0, 0, 0,
2492			0, 0, 0, PORT308_DATA,
2493			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2494			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2495			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2496			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2497			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2498		))
2499	},
2500	{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
2501			0, 0, 0, 0,
2502			0, 0, 0, 0,
2503			0, 0, 0, 0,
2504			0, 0, 0, 0,
2505			0, 0, 0, 0,
2506			0, 0, PORT329_DATA, PORT328_DATA,
2507			PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2508			PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2509		))
2510	},
2511	{ /* sentinel */ }
2512};
2513
2514static const struct pinmux_irq pinmux_irqs[] = {
2515	PINMUX_IRQ(0),		/* IRQ0 */
2516	PINMUX_IRQ(1),		/* IRQ1 */
2517	PINMUX_IRQ(2),		/* IRQ2 */
2518	PINMUX_IRQ(3),		/* IRQ3 */
2519	PINMUX_IRQ(4),		/* IRQ4 */
2520	PINMUX_IRQ(5),		/* IRQ5 */
2521	PINMUX_IRQ(6),		/* IRQ6 */
2522	PINMUX_IRQ(7),		/* IRQ7 */
2523	PINMUX_IRQ(8),		/* IRQ8 */
2524	PINMUX_IRQ(9),		/* IRQ9 */
2525	PINMUX_IRQ(10),		/* IRQ10 */
2526	PINMUX_IRQ(11),		/* IRQ11 */
2527	PINMUX_IRQ(12),		/* IRQ12 */
2528	PINMUX_IRQ(13),		/* IRQ13 */
2529	PINMUX_IRQ(14),		/* IRQ14 */
2530	PINMUX_IRQ(15),		/* IRQ15 */
2531	PINMUX_IRQ(320),	/* IRQ16 */
2532	PINMUX_IRQ(321),	/* IRQ17 */
2533	PINMUX_IRQ(85),		/* IRQ18 */
2534	PINMUX_IRQ(84),		/* IRQ19 */
2535	PINMUX_IRQ(160),	/* IRQ20 */
2536	PINMUX_IRQ(161),	/* IRQ21 */
2537	PINMUX_IRQ(162),	/* IRQ22 */
2538	PINMUX_IRQ(163),	/* IRQ23 */
2539	PINMUX_IRQ(175),	/* IRQ24 */
2540	PINMUX_IRQ(176),	/* IRQ25 */
2541	PINMUX_IRQ(177),	/* IRQ26 */
2542	PINMUX_IRQ(178),	/* IRQ27 */
2543	PINMUX_IRQ(322),	/* IRQ28 */
2544	PINMUX_IRQ(323),	/* IRQ29 */
2545	PINMUX_IRQ(324),	/* IRQ30 */
2546	PINMUX_IRQ(192),	/* IRQ31 */
2547	PINMUX_IRQ(193),	/* IRQ32 */
2548	PINMUX_IRQ(194),	/* IRQ33 */
2549	PINMUX_IRQ(195),	/* IRQ34 */
2550	PINMUX_IRQ(196),	/* IRQ35 */
2551	PINMUX_IRQ(197),	/* IRQ36 */
2552	PINMUX_IRQ(198),	/* IRQ37 */
2553	PINMUX_IRQ(199),	/* IRQ38 */
2554	PINMUX_IRQ(200),	/* IRQ39 */
2555	PINMUX_IRQ(66),		/* IRQ40 */
2556	PINMUX_IRQ(102),	/* IRQ41 */
2557	PINMUX_IRQ(103),	/* IRQ42 */
2558	PINMUX_IRQ(109),	/* IRQ43 */
2559	PINMUX_IRQ(110),	/* IRQ44 */
2560	PINMUX_IRQ(111),	/* IRQ45 */
2561	PINMUX_IRQ(112),	/* IRQ46 */
2562	PINMUX_IRQ(113),	/* IRQ47 */
2563	PINMUX_IRQ(114),	/* IRQ48 */
2564	PINMUX_IRQ(115),	/* IRQ49 */
2565	PINMUX_IRQ(301),	/* IRQ50 */
2566	PINMUX_IRQ(290),	/* IRQ51 */
2567	PINMUX_IRQ(296),	/* IRQ52 */
2568	PINMUX_IRQ(325),	/* IRQ53 */
2569	PINMUX_IRQ(326),	/* IRQ54 */
2570	PINMUX_IRQ(327),	/* IRQ55 */
2571	PINMUX_IRQ(328),	/* IRQ56 */
2572	PINMUX_IRQ(329),	/* IRQ57 */
2573};
2574
2575static const unsigned int r8a73a4_portcr_offsets[] = {
2576	0x00000000, 0x00001000, 0x00000000, 0x00001000,
2577	0x00001000, 0x00002000, 0x00002000, 0x00002000,
2578	0x00002000, 0x00003000, 0x00003000,
2579};
2580
2581static int r8a73a4_pin_to_portcr(unsigned int pin)
2582{
2583	return r8a73a4_portcr_offsets[pin >> 5] + pin;
2584}
2585
2586static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2587	.get_bias = rmobile_pinmux_get_bias,
2588	.set_bias = rmobile_pinmux_set_bias,
2589	.pin_to_portcr = r8a73a4_pin_to_portcr,
2590};
2591
2592const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2593	.name		= "r8a73a4_pfc",
2594	.ops		= &r8a73a4_pfc_ops,
2595
2596	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2597	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2598	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2599
2600	.pins = pinmux_pins,
2601	.nr_pins = ARRAY_SIZE(pinmux_pins),
2602
2603	.groups = pinmux_groups,
2604	.nr_groups = ARRAY_SIZE(pinmux_groups),
2605	.functions = pinmux_functions,
2606	.nr_functions = ARRAY_SIZE(pinmux_functions),
2607
2608	.cfg_regs = pinmux_config_regs,
2609	.data_regs = pinmux_data_regs,
2610
2611	.pinmux_data = pinmux_data,
2612	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
2613
2614	.gpio_irq = pinmux_irqs,
2615	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2616};