pinctrl-spmi-gpio.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
   5 */
   6
   7#include <linux/gpio/driver.h>
   8#include <linux/interrupt.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/of_irq.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14#include <linux/seq_file.h>
  15#include <linux/slab.h>
  16#include <linux/spmi.h>
  17#include <linux/string_choices.h>
  18#include <linux/types.h>
  19
  20#include <linux/pinctrl/pinconf-generic.h>
  21#include <linux/pinctrl/pinconf.h>
  22#include <linux/pinctrl/pinmux.h>
  23
  24#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  25
  26#include "../core.h"
  27#include "../pinctrl-utils.h"
  28
  29#define PMIC_GPIO_ADDRESS_RANGE			0x100
  30
  31/* type and subtype registers base address offsets */
  32#define PMIC_GPIO_REG_TYPE			0x4
  33#define PMIC_GPIO_REG_SUBTYPE			0x5
  34
  35/* GPIO peripheral type and subtype out_values */
  36#define PMIC_GPIO_TYPE				0x10
  37#define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
  38#define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
  39#define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
  40#define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
  41#define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
  42#define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
  43#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2		0x12
  44#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3		0x13
  45#define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK	0x14
  46#define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK	0x15
  47
  48#define PMIC_MPP_REG_RT_STS			0x10
  49#define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
  50
  51/* control register base address offsets */
  52#define PMIC_GPIO_REG_MODE_CTL			0x40
  53#define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
  54#define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
  55#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
  56#define PMIC_GPIO_REG_DIG_IN_CTL		0x43
  57#define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
  58#define PMIC_GPIO_REG_EN_CTL			0x46
  59#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
  60
  61/* PMIC_GPIO_REG_MODE_CTL */
  62#define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
  63#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
  64#define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
  65#define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
  66#define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
  67
  68#define PMIC_GPIO_MODE_DIGITAL_INPUT		0
  69#define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
  70#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
  71#define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
  72#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
  73
  74/* PMIC_GPIO_REG_DIG_VIN_CTL */
  75#define PMIC_GPIO_REG_VIN_SHIFT			0
  76#define PMIC_GPIO_REG_VIN_MASK			0x7
  77
  78/* PMIC_GPIO_REG_DIG_PULL_CTL */
  79#define PMIC_GPIO_REG_PULL_SHIFT		0
  80#define PMIC_GPIO_REG_PULL_MASK			0x7
  81
  82#define PMIC_GPIO_PULL_DOWN			4
  83#define PMIC_GPIO_PULL_DISABLE			5
  84
  85/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
  86#define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
  87#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
  88#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
  89
  90/* PMIC_GPIO_REG_DIG_IN_CTL */
  91#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
  92#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
  93#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
  94
  95/* PMIC_GPIO_REG_DIG_OUT_CTL */
  96#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
  97#define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
  98#define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
  99#define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
 100
 101/*
 102 * Output type - indicates pin should be configured as push-pull,
 103 * open drain or open source.
 104 */
 105#define PMIC_GPIO_OUT_BUF_CMOS			0
 106#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
 107#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
 108
 109#define PMIC_GPIO_OUT_STRENGTH_LOW		1
 110#define PMIC_GPIO_OUT_STRENGTH_HIGH		3
 111
 112/* PMIC_GPIO_REG_EN_CTL */
 113#define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
 114
 115#define PMIC_GPIO_PHYSICAL_OFFSET		1
 116
 117/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
 118#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
 119
 120/* Qualcomm specific pin configurations */
 121#define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
 122#define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
 123#define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
 124#define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
 125#define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
 126
 127/* The index of each function in pmic_gpio_functions[] array */
 128enum pmic_gpio_func_index {
 129	PMIC_GPIO_FUNC_INDEX_NORMAL,
 130	PMIC_GPIO_FUNC_INDEX_PAIRED,
 131	PMIC_GPIO_FUNC_INDEX_FUNC1,
 132	PMIC_GPIO_FUNC_INDEX_FUNC2,
 133	PMIC_GPIO_FUNC_INDEX_FUNC3,
 134	PMIC_GPIO_FUNC_INDEX_FUNC4,
 135	PMIC_GPIO_FUNC_INDEX_DTEST1,
 136	PMIC_GPIO_FUNC_INDEX_DTEST2,
 137	PMIC_GPIO_FUNC_INDEX_DTEST3,
 138	PMIC_GPIO_FUNC_INDEX_DTEST4,
 139};
 140
 141/**
 142 * struct pmic_gpio_pad - keep current GPIO settings
 143 * @base: Address base in SPMI device.
 144 * @is_enabled: Set to false when GPIO should be put in high Z state.
 145 * @out_value: Cached pin output value
 146 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
 147 *	open-drain or open-source mode.
 148 * @output_enabled: Set to true if GPIO output logic is enabled.
 149 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
 150 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
 151 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
 152 * @num_sources: Number of power-sources supported by this GPIO.
 153 * @power_source: Current power-source used.
 154 * @buffer_type: Push-pull, open-drain or open-source.
 155 * @pullup: Constant current which flow trough GPIO output buffer.
 156 * @strength: No, Low, Medium, High
 157 * @function: See pmic_gpio_functions[]
 158 * @atest: the ATEST selection for GPIO analog-pass-through mode
 159 * @dtest_buffer: the DTEST buffer selection for digital input mode.
 160 */
 161struct pmic_gpio_pad {
 162	u16		base;
 163	bool		is_enabled;
 164	bool		out_value;
 165	bool		have_buffer;
 166	bool		output_enabled;
 167	bool		input_enabled;
 168	bool		analog_pass;
 169	bool		lv_mv_type;
 170	unsigned int	num_sources;
 171	unsigned int	power_source;
 172	unsigned int	buffer_type;
 173	unsigned int	pullup;
 174	unsigned int	strength;
 175	unsigned int	function;
 176	unsigned int	atest;
 177	unsigned int	dtest_buffer;
 178};
 179
 180struct pmic_gpio_state {
 181	struct device	*dev;
 182	struct regmap	*map;
 183	struct pinctrl_dev *ctrl;
 184	struct gpio_chip chip;
 185	u8 usid;
 186	u8 pid_base;
 187};
 188
 189static const struct pinconf_generic_params pmic_gpio_bindings[] = {
 190	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
 191	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
 192	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
 193	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
 194	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
 195};
 196
 197#ifdef CONFIG_DEBUG_FS
 198static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
 199	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
 200	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
 201	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
 202	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
 203	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
 204};
 205#endif
 206
 207static const char *const pmic_gpio_groups[] = {
 208	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
 209	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
 210	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
 211	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
 212	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
 213};
 214
 215static const char *const pmic_gpio_functions[] = {
 216	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
 217	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
 218	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
 219	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
 220	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
 221	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
 222	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
 223	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
 224	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
 225	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
 226};
 227
 228static int pmic_gpio_read(struct pmic_gpio_state *state,
 229			  struct pmic_gpio_pad *pad, unsigned int addr)
 230{
 231	unsigned int val;
 232	int ret;
 233
 234	ret = regmap_read(state->map, pad->base + addr, &val);
 235	if (ret < 0)
 236		dev_err(state->dev, "read 0x%x failed\n", addr);
 237	else
 238		ret = val;
 239
 240	return ret;
 241}
 242
 243static int pmic_gpio_write(struct pmic_gpio_state *state,
 244			   struct pmic_gpio_pad *pad, unsigned int addr,
 245			   unsigned int val)
 246{
 247	int ret;
 248
 249	ret = regmap_write(state->map, pad->base + addr, val);
 250	if (ret < 0)
 251		dev_err(state->dev, "write 0x%x failed\n", addr);
 252
 253	return ret;
 254}
 255
 256static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
 257{
 258	/* Every PIN is a group */
 259	return pctldev->desc->npins;
 260}
 261
 262static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
 263					    unsigned pin)
 264{
 265	return pctldev->desc->pins[pin].name;
 266}
 267
 268static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
 269				    const unsigned **pins, unsigned *num_pins)
 270{
 271	*pins = &pctldev->desc->pins[pin].number;
 272	*num_pins = 1;
 273	return 0;
 274}
 275
 276static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
 277	.get_groups_count	= pmic_gpio_get_groups_count,
 278	.get_group_name		= pmic_gpio_get_group_name,
 279	.get_group_pins		= pmic_gpio_get_group_pins,
 280	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
 281	.dt_free_map		= pinctrl_utils_free_map,
 282};
 283
 284static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
 285{
 286	return ARRAY_SIZE(pmic_gpio_functions);
 287}
 288
 289static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
 290					       unsigned function)
 291{
 292	return pmic_gpio_functions[function];
 293}
 294
 295static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
 296					 unsigned function,
 297					 const char *const **groups,
 298					 unsigned *const num_qgroups)
 299{
 300	*groups = pmic_gpio_groups;
 301	*num_qgroups = pctldev->desc->npins;
 302	return 0;
 303}
 304
 305static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 306				unsigned pin)
 307{
 308	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 309	struct pmic_gpio_pad *pad;
 310	unsigned int val;
 311	int ret;
 312
 313	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
 314		pr_err("function: %d is not defined\n", function);
 315		return -EINVAL;
 316	}
 317
 318	pad = pctldev->desc->pins[pin].drv_data;
 319	/*
 320	 * Non-LV/MV subtypes only support 2 special functions,
 321	 * offsetting the dtestx function values by 2
 322	 */
 323	if (!pad->lv_mv_type) {
 324		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
 325				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
 326			pr_err("LV/MV subtype doesn't have func3/func4\n");
 327			return -EINVAL;
 328		}
 329		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
 330			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
 331					PMIC_GPIO_FUNC_INDEX_FUNC3);
 332	}
 333
 334	pad->function = function;
 335
 336	if (pad->analog_pass)
 337		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
 338	else if (pad->output_enabled && pad->input_enabled)
 339		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
 340	else if (pad->output_enabled)
 341		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
 342	else
 343		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
 344
 345	if (pad->lv_mv_type) {
 346		ret = pmic_gpio_write(state, pad,
 347				PMIC_GPIO_REG_MODE_CTL, val);
 348		if (ret < 0)
 349			return ret;
 350
 351		val = pad->atest - 1;
 352		ret = pmic_gpio_write(state, pad,
 353				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
 354		if (ret < 0)
 355			return ret;
 356
 357		val = pad->out_value
 358			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
 359		val |= pad->function
 360			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
 361		ret = pmic_gpio_write(state, pad,
 362			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
 363		if (ret < 0)
 364			return ret;
 365	} else {
 366		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
 367		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 368		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 369
 370		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
 371		if (ret < 0)
 372			return ret;
 373	}
 374
 375	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
 376
 377	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
 378}
 379
 380static const struct pinmux_ops pmic_gpio_pinmux_ops = {
 381	.get_functions_count	= pmic_gpio_get_functions_count,
 382	.get_function_name	= pmic_gpio_get_function_name,
 383	.get_function_groups	= pmic_gpio_get_function_groups,
 384	.set_mux		= pmic_gpio_set_mux,
 385};
 386
 387static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
 388				unsigned int pin, unsigned long *config)
 389{
 390	unsigned param = pinconf_to_config_param(*config);
 391	struct pmic_gpio_pad *pad;
 392	unsigned arg;
 393
 394	pad = pctldev->desc->pins[pin].drv_data;
 395
 396	switch (param) {
 397	case PIN_CONFIG_DRIVE_PUSH_PULL:
 398		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
 399			return -EINVAL;
 400		arg = 1;
 401		break;
 402	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 403		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
 404			return -EINVAL;
 405		arg = 1;
 406		break;
 407	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 408		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
 409			return -EINVAL;
 410		arg = 1;
 411		break;
 412	case PIN_CONFIG_BIAS_PULL_DOWN:
 413		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
 414			return -EINVAL;
 415		arg = 1;
 416		break;
 417	case PIN_CONFIG_BIAS_DISABLE:
 418		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
 419			return -EINVAL;
 420		arg = 1;
 421		break;
 422	case PIN_CONFIG_BIAS_PULL_UP:
 423		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
 424			return -EINVAL;
 425		arg = 1;
 426		break;
 427	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 428		if (pad->is_enabled)
 429			return -EINVAL;
 430		arg = 1;
 431		break;
 432	case PIN_CONFIG_POWER_SOURCE:
 433		arg = pad->power_source;
 434		break;
 435	case PIN_CONFIG_INPUT_ENABLE:
 436		if (!pad->input_enabled)
 437			return -EINVAL;
 438		arg = 1;
 439		break;
 440	case PIN_CONFIG_OUTPUT_ENABLE:
 441		arg = pad->output_enabled;
 442		break;
 443	case PIN_CONFIG_LEVEL:
 444		arg = pad->out_value;
 445		break;
 446	case PMIC_GPIO_CONF_PULL_UP:
 447		arg = pad->pullup;
 448		break;
 449	case PMIC_GPIO_CONF_STRENGTH:
 450		switch (pad->strength) {
 451		case PMIC_GPIO_OUT_STRENGTH_HIGH:
 452			arg = PMIC_GPIO_STRENGTH_HIGH;
 453			break;
 454		case PMIC_GPIO_OUT_STRENGTH_LOW:
 455			arg = PMIC_GPIO_STRENGTH_LOW;
 456			break;
 457		default:
 458			arg = pad->strength;
 459			break;
 460		}
 461		break;
 462	case PMIC_GPIO_CONF_ATEST:
 463		arg = pad->atest;
 464		break;
 465	case PMIC_GPIO_CONF_ANALOG_PASS:
 466		arg = pad->analog_pass;
 467		break;
 468	case PMIC_GPIO_CONF_DTEST_BUFFER:
 469		arg = pad->dtest_buffer;
 470		break;
 471	default:
 472		return -EINVAL;
 473	}
 474
 475	*config = pinconf_to_config_packed(param, arg);
 476	return 0;
 477}
 478
 479static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 480				unsigned long *configs, unsigned nconfs)
 481{
 482	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 483	struct pmic_gpio_pad *pad;
 484	unsigned param, arg;
 485	unsigned int val;
 486	int i, ret;
 487
 488	pad = pctldev->desc->pins[pin].drv_data;
 489
 490	pad->is_enabled = true;
 491	for (i = 0; i < nconfs; i++) {
 492		param = pinconf_to_config_param(configs[i]);
 493		arg = pinconf_to_config_argument(configs[i]);
 494
 495		switch (param) {
 496		case PIN_CONFIG_DRIVE_PUSH_PULL:
 497			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
 498			break;
 499		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 500			if (!pad->have_buffer)
 501				return -EINVAL;
 502			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
 503			break;
 504		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 505			if (!pad->have_buffer)
 506				return -EINVAL;
 507			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
 508			break;
 509		case PIN_CONFIG_BIAS_DISABLE:
 510			pad->pullup = PMIC_GPIO_PULL_DISABLE;
 511			break;
 512		case PIN_CONFIG_BIAS_PULL_UP:
 513			pad->pullup = PMIC_GPIO_PULL_UP_30;
 514			break;
 515		case PIN_CONFIG_BIAS_PULL_DOWN:
 516			if (arg)
 517				pad->pullup = PMIC_GPIO_PULL_DOWN;
 518			else
 519				pad->pullup = PMIC_GPIO_PULL_DISABLE;
 520			break;
 521		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 522			pad->is_enabled = false;
 523			break;
 524		case PIN_CONFIG_POWER_SOURCE:
 525			if (arg >= pad->num_sources)
 526				return -EINVAL;
 527			pad->power_source = arg;
 528			break;
 529		case PIN_CONFIG_INPUT_ENABLE:
 530			pad->input_enabled = arg ? true : false;
 531			break;
 532		case PIN_CONFIG_OUTPUT_ENABLE:
 533			pad->output_enabled = arg ? true : false;
 534			break;
 535		case PIN_CONFIG_LEVEL:
 536			pad->output_enabled = true;
 537			pad->out_value = arg;
 538			break;
 539		case PMIC_GPIO_CONF_PULL_UP:
 540			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
 541				return -EINVAL;
 542			pad->pullup = arg;
 543			break;
 544		case PMIC_GPIO_CONF_STRENGTH:
 545			if (arg > PMIC_GPIO_STRENGTH_LOW)
 546				return -EINVAL;
 547			switch (arg) {
 548			case PMIC_GPIO_STRENGTH_HIGH:
 549				pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
 550				break;
 551			case PMIC_GPIO_STRENGTH_LOW:
 552				pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
 553				break;
 554			default:
 555				pad->strength = arg;
 556				break;
 557			}
 558			break;
 559		case PMIC_GPIO_CONF_ATEST:
 560			if (!pad->lv_mv_type || arg > 4)
 561				return -EINVAL;
 562			pad->atest = arg;
 563			break;
 564		case PMIC_GPIO_CONF_ANALOG_PASS:
 565			if (!pad->lv_mv_type)
 566				return -EINVAL;
 567			pad->analog_pass = true;
 568			break;
 569		case PMIC_GPIO_CONF_DTEST_BUFFER:
 570			if (arg > 4)
 571				return -EINVAL;
 572			pad->dtest_buffer = arg;
 573			break;
 574		default:
 575			return -EINVAL;
 576		}
 577	}
 578
 579	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
 580
 581	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
 582	if (ret < 0)
 583		return ret;
 584
 585	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
 586
 587	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
 588	if (ret < 0)
 589		return ret;
 590
 591	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
 592	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
 593
 594	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
 595	if (ret < 0)
 596		return ret;
 597
 598	if (pad->dtest_buffer == 0) {
 599		val = 0;
 600	} else {
 601		if (pad->lv_mv_type) {
 602			val = pad->dtest_buffer - 1;
 603			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
 604		} else {
 605			val = BIT(pad->dtest_buffer - 1);
 606		}
 607	}
 608	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
 609	if (ret < 0)
 610		return ret;
 611
 612	if (pad->analog_pass)
 613		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
 614	else if (pad->output_enabled && pad->input_enabled)
 615		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
 616	else if (pad->output_enabled)
 617		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
 618	else
 619		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
 620
 621	if (pad->lv_mv_type) {
 622		ret = pmic_gpio_write(state, pad,
 623				PMIC_GPIO_REG_MODE_CTL, val);
 624		if (ret < 0)
 625			return ret;
 626
 627		val = pad->atest - 1;
 628		ret = pmic_gpio_write(state, pad,
 629				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
 630		if (ret < 0)
 631			return ret;
 632
 633		val = pad->out_value
 634			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
 635		val |= pad->function
 636			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
 637		ret = pmic_gpio_write(state, pad,
 638			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
 639		if (ret < 0)
 640			return ret;
 641	} else {
 642		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
 643		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 644		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 645
 646		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
 647		if (ret < 0)
 648			return ret;
 649	}
 650
 651	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
 652
 653	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
 654
 655	return ret;
 656}
 657
 658static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
 659				      struct seq_file *s, unsigned pin)
 660{
 661	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
 662	struct pmic_gpio_pad *pad;
 663	int ret, val, function;
 664
 665	static const char *const biases[] = {
 666		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
 667		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
 668	};
 669	static const char *const buffer_types[] = {
 670		"push-pull", "open-drain", "open-source"
 671	};
 672	static const char *const strengths[] = {
 673		"no", "low", "medium", "high"
 674	};
 675
 676	pad = pctldev->desc->pins[pin].drv_data;
 677
 678	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
 679
 680	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
 681
 682	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
 683		seq_puts(s, " ---");
 684	} else {
 685		if (pad->input_enabled) {
 686			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
 687			if (ret < 0)
 688				return;
 689
 690			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
 691			pad->out_value = ret;
 692		}
 693		/*
 694		 * For the non-LV/MV subtypes only 2 special functions are
 695		 * available, offsetting the dtest function values by 2.
 696		 */
 697		function = pad->function;
 698		if (!pad->lv_mv_type &&
 699				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
 700			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
 701				PMIC_GPIO_FUNC_INDEX_FUNC3;
 702
 703		if (pad->analog_pass)
 704			seq_puts(s, " analog-pass");
 705		else
 706			seq_printf(s, " %-4s",
 707					pad->output_enabled ? "out" : "in");
 708		seq_printf(s, " %-4s", str_high_low(pad->out_value));
 709		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
 710		seq_printf(s, " vin-%d", pad->power_source);
 711		seq_printf(s, " %-27s", biases[pad->pullup]);
 712		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
 713		seq_printf(s, " %-7s", strengths[pad->strength]);
 714		seq_printf(s, " atest-%d", pad->atest);
 715		seq_printf(s, " dtest-%d", pad->dtest_buffer);
 716	}
 717}
 718
 719static const struct pinconf_ops pmic_gpio_pinconf_ops = {
 720	.is_generic			= true,
 721	.pin_config_group_get		= pmic_gpio_config_get,
 722	.pin_config_group_set		= pmic_gpio_config_set,
 723	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
 724};
 725
 726static int pmic_gpio_get_direction(struct gpio_chip *chip, unsigned pin)
 727{
 728	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 729	struct pmic_gpio_pad *pad;
 730
 731	pad = state->ctrl->desc->pins[pin].drv_data;
 732
 733	if (!pad->is_enabled || pad->analog_pass ||
 734	    (!pad->input_enabled && !pad->output_enabled))
 735		return -EINVAL;
 736
 737	/* Make sure the state is aligned on what pmic_gpio_get() returns */
 738	return pad->input_enabled ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
 739}
 740
 741static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 742{
 743	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 744	unsigned long config;
 745
 746	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
 747
 748	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 749}
 750
 751static int pmic_gpio_direction_output(struct gpio_chip *chip,
 752				      unsigned pin, int val)
 753{
 754	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 755	unsigned long config;
 756
 757	config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
 758
 759	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 760}
 761
 762static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
 763{
 764	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 765	struct pmic_gpio_pad *pad;
 766	int ret;
 767
 768	pad = state->ctrl->desc->pins[pin].drv_data;
 769
 770	if (!pad->is_enabled)
 771		return -EINVAL;
 772
 773	if (pad->input_enabled) {
 774		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
 775		if (ret < 0)
 776			return ret;
 777
 778		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
 779	}
 780
 781	return !!pad->out_value;
 782}
 783
 784static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
 785{
 786	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 787	unsigned long config;
 788
 789	config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
 790
 791	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
 792}
 793
 794static int pmic_gpio_of_xlate(struct gpio_chip *chip,
 795			      const struct of_phandle_args *gpio_desc,
 796			      u32 *flags)
 797{
 798	if (chip->of_gpio_n_cells < 2)
 799		return -EINVAL;
 800
 801	if (flags)
 802		*flags = gpio_desc->args[1];
 803
 804	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
 805}
 806
 807static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 808{
 809	struct pmic_gpio_state *state = gpiochip_get_data(chip);
 810	unsigned i;
 811
 812	for (i = 0; i < chip->ngpio; i++) {
 813		pmic_gpio_config_dbg_show(state->ctrl, s, i);
 814		seq_puts(s, "\n");
 815	}
 816}
 817
 818static const struct gpio_chip pmic_gpio_gpio_template = {
 819	.get_direction		= pmic_gpio_get_direction,
 820	.direction_input	= pmic_gpio_direction_input,
 821	.direction_output	= pmic_gpio_direction_output,
 822	.get			= pmic_gpio_get,
 823	.set			= pmic_gpio_set,
 824	.request		= gpiochip_generic_request,
 825	.free			= gpiochip_generic_free,
 826	.of_xlate		= pmic_gpio_of_xlate,
 827	.dbg_show		= pmic_gpio_dbg_show,
 828};
 829
 830static int pmic_gpio_populate(struct pmic_gpio_state *state,
 831			      struct pmic_gpio_pad *pad)
 832{
 833	int type, subtype, val, dir;
 834
 835	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
 836	if (type < 0)
 837		return type;
 838
 839	if (type != PMIC_GPIO_TYPE) {
 840		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
 841			type, pad->base);
 842		return -ENODEV;
 843	}
 844
 845	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
 846	if (subtype < 0)
 847		return subtype;
 848
 849	switch (subtype) {
 850	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
 851		pad->have_buffer = true;
 852		fallthrough;
 853	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
 854		pad->num_sources = 4;
 855		break;
 856	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
 857		pad->have_buffer = true;
 858		fallthrough;
 859	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
 860		pad->num_sources = 8;
 861		break;
 862	case PMIC_GPIO_SUBTYPE_GPIO_LV:
 863		pad->num_sources = 1;
 864		pad->have_buffer = true;
 865		pad->lv_mv_type = true;
 866		break;
 867	case PMIC_GPIO_SUBTYPE_GPIO_MV:
 868		pad->num_sources = 2;
 869		pad->have_buffer = true;
 870		pad->lv_mv_type = true;
 871		break;
 872	case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
 873	case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK:
 874		pad->num_sources = 2;
 875		pad->have_buffer = true;
 876		pad->lv_mv_type = true;
 877		break;
 878	case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
 879	case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK:
 880		pad->num_sources = 3;
 881		pad->have_buffer = true;
 882		pad->lv_mv_type = true;
 883		break;
 884	default:
 885		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
 886		return -ENODEV;
 887	}
 888
 889	if (pad->lv_mv_type) {
 890		val = pmic_gpio_read(state, pad,
 891				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
 892		if (val < 0)
 893			return val;
 894
 895		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
 896		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
 897
 898		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
 899		if (val < 0)
 900			return val;
 901
 902		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
 903	} else {
 904		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
 905		if (val < 0)
 906			return val;
 907
 908		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
 909
 910		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
 911		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
 912		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
 913		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
 914	}
 915
 916	switch (dir) {
 917	case PMIC_GPIO_MODE_DIGITAL_INPUT:
 918		pad->input_enabled = true;
 919		pad->output_enabled = false;
 920		break;
 921	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
 922		pad->input_enabled = false;
 923		pad->output_enabled = true;
 924		break;
 925	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
 926		pad->input_enabled = true;
 927		pad->output_enabled = true;
 928		break;
 929	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
 930		if (!pad->lv_mv_type)
 931			return -ENODEV;
 932		pad->analog_pass = true;
 933		break;
 934	default:
 935		dev_err(state->dev, "unknown GPIO direction\n");
 936		return -ENODEV;
 937	}
 938
 939	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
 940	if (val < 0)
 941		return val;
 942
 943	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
 944	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
 945
 946	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
 947	if (val < 0)
 948		return val;
 949
 950	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
 951	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
 952
 953	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
 954	if (val < 0)
 955		return val;
 956
 957	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
 958		pad->dtest_buffer =
 959			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
 960	else if (!pad->lv_mv_type)
 961		pad->dtest_buffer = ffs(val);
 962	else
 963		pad->dtest_buffer = 0;
 964
 965	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
 966	if (val < 0)
 967		return val;
 968
 969	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
 970	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
 971
 972	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
 973	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
 974
 975	if (pad->lv_mv_type) {
 976		val = pmic_gpio_read(state, pad,
 977				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
 978		if (val < 0)
 979			return val;
 980		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
 981	}
 982
 983	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
 984	pad->is_enabled = true;
 985	return 0;
 986}
 987
 988static int pmic_gpio_domain_translate(struct irq_domain *domain,
 989				      struct irq_fwspec *fwspec,
 990				      unsigned long *hwirq,
 991				      unsigned int *type)
 992{
 993	struct pmic_gpio_state *state = container_of(domain->host_data,
 994						     struct pmic_gpio_state,
 995						     chip);
 996
 997	if (fwspec->param_count != 2 ||
 998	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
 999		return -EINVAL;
1000
1001	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
1002	*type = fwspec->param[1];
1003
1004	return 0;
1005}
1006
1007static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
1008						  unsigned int offset)
1009{
1010	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
1011}
1012
1013static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
1014					   unsigned int child_hwirq,
1015					   unsigned int child_type,
1016					   unsigned int *parent_hwirq,
1017					   unsigned int *parent_type)
1018{
1019	struct pmic_gpio_state *state = gpiochip_get_data(chip);
1020
1021	*parent_hwirq = child_hwirq + state->pid_base;
1022	*parent_type = child_type;
1023
1024	return 0;
1025}
1026
1027static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1028					    union gpio_irq_fwspec *gfwspec,
1029					    unsigned int parent_hwirq,
1030					    unsigned int parent_type)
1031{
1032	struct pmic_gpio_state *state = gpiochip_get_data(chip);
1033	struct irq_fwspec *fwspec = &gfwspec->fwspec;
1034
1035	fwspec->fwnode = chip->irq.parent_domain->fwnode;
1036
1037	fwspec->param_count = 4;
1038	fwspec->param[0] = state->usid;
1039	fwspec->param[1] = parent_hwirq;
1040	/* param[2] must be left as 0 */
1041	fwspec->param[3] = parent_type;
1042
1043	return 0;
1044}
1045
1046static void pmic_gpio_irq_mask(struct irq_data *data)
1047{
1048	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1049
1050	irq_chip_mask_parent(data);
1051	gpiochip_disable_irq(gc, data->hwirq);
1052}
1053
1054static void pmic_gpio_irq_unmask(struct irq_data *data)
1055{
1056	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1057
1058	gpiochip_enable_irq(gc, data->hwirq);
1059	irq_chip_unmask_parent(data);
1060}
1061
1062static const struct irq_chip spmi_gpio_irq_chip = {
1063	.name		= "spmi-gpio",
1064	.irq_ack	= irq_chip_ack_parent,
1065	.irq_mask	= pmic_gpio_irq_mask,
1066	.irq_unmask	= pmic_gpio_irq_unmask,
1067	.irq_set_type	= irq_chip_set_type_parent,
1068	.irq_set_wake	= irq_chip_set_wake_parent,
1069	.flags		= IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
1070	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1071};
1072
1073static int pmic_gpio_probe(struct platform_device *pdev)
1074{
1075	struct irq_domain *parent_domain;
1076	struct device_node *parent_node;
1077	struct device *dev = &pdev->dev;
1078	struct pinctrl_pin_desc *pindesc;
1079	struct pinctrl_desc *pctrldesc;
1080	struct pmic_gpio_pad *pad, *pads;
1081	struct pmic_gpio_state *state;
1082	struct gpio_irq_chip *girq;
1083	const struct spmi_device *parent_spmi_dev;
1084	int ret, npins, i;
1085	u32 reg;
1086
1087	ret = of_property_read_u32(dev->of_node, "reg", &reg);
1088	if (ret < 0) {
1089		dev_err(dev, "missing base address");
1090		return ret;
1091	}
1092
1093	npins = (uintptr_t) device_get_match_data(&pdev->dev);
1094
1095	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1096	if (!state)
1097		return -ENOMEM;
1098
1099	platform_set_drvdata(pdev, state);
1100
1101	state->dev = &pdev->dev;
1102	state->map = dev_get_regmap(dev->parent, NULL);
1103	parent_spmi_dev = to_spmi_device(dev->parent);
1104	state->usid = parent_spmi_dev->usid;
1105	state->pid_base = reg >> 8;
1106
1107	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1108	if (!pindesc)
1109		return -ENOMEM;
1110
1111	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1112	if (!pads)
1113		return -ENOMEM;
1114
1115	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1116	if (!pctrldesc)
1117		return -ENOMEM;
1118
1119	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1120	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1121	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1122	pctrldesc->owner = THIS_MODULE;
1123	pctrldesc->name = dev_name(dev);
1124	pctrldesc->pins = pindesc;
1125	pctrldesc->npins = npins;
1126	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1127	pctrldesc->custom_params = pmic_gpio_bindings;
1128#ifdef CONFIG_DEBUG_FS
1129	pctrldesc->custom_conf_items = pmic_conf_items;
1130#endif
1131
1132	for (i = 0; i < npins; i++, pindesc++) {
1133		pad = &pads[i];
1134		pindesc->drv_data = pad;
1135		pindesc->number = i;
1136		pindesc->name = pmic_gpio_groups[i];
1137
1138		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1139
1140		ret = pmic_gpio_populate(state, pad);
1141		if (ret < 0)
1142			return ret;
1143	}
1144
1145	state->chip = pmic_gpio_gpio_template;
1146	state->chip.parent = dev;
1147	state->chip.base = -1;
1148	state->chip.ngpio = npins;
1149	state->chip.label = dev_name(dev);
1150	state->chip.of_gpio_n_cells = 2;
1151	state->chip.can_sleep = false;
1152
1153	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1154	if (IS_ERR(state->ctrl))
1155		return PTR_ERR(state->ctrl);
1156
1157	parent_node = of_irq_find_parent(state->dev->of_node);
1158	if (!parent_node)
1159		return -ENXIO;
1160
1161	parent_domain = irq_find_host(parent_node);
1162	of_node_put(parent_node);
1163	if (!parent_domain)
1164		return -ENXIO;
1165
1166	girq = &state->chip.irq;
1167	gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
1168	girq->default_type = IRQ_TYPE_NONE;
1169	girq->handler = handle_level_irq;
1170	girq->fwnode = dev_fwnode(state->dev);
1171	girq->parent_domain = parent_domain;
1172	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1173	girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1174	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1175	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1176
1177	ret = gpiochip_add_data(&state->chip, state);
1178	if (ret) {
1179		dev_err(state->dev, "can't add gpio chip\n");
1180		return ret;
1181	}
1182
1183	/*
1184	 * For DeviceTree-supported systems, the gpio core checks the
1185	 * pinctrl's device node for the "gpio-ranges" property.
1186	 * If it is present, it takes care of adding the pin ranges
1187	 * for the driver. In this case the driver can skip ahead.
1188	 *
1189	 * In order to remain compatible with older, existing DeviceTree
1190	 * files which don't set the "gpio-ranges" property or systems that
1191	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1192	 */
1193	if (!of_property_present(dev->of_node, "gpio-ranges")) {
1194		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1195					     npins);
1196		if (ret) {
1197			dev_err(dev, "failed to add pin range\n");
1198			goto err_range;
1199		}
1200	}
1201
1202	return 0;
1203
1204err_range:
1205	gpiochip_remove(&state->chip);
1206	return ret;
1207}
1208
1209static void pmic_gpio_remove(struct platform_device *pdev)
1210{
1211	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1212
1213	gpiochip_remove(&state->chip);
1214}
1215
1216static const struct of_device_id pmic_gpio_of_match[] = {
1217	{ .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1218	/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1219	{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1220	/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1221	{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1222	{ .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1223	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1224	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1225	{ .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1226	{ .compatible = "qcom,pm6450-gpio", .data = (void *) 9 },
1227	{ .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1228	{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1229	{ .compatible = "qcom,pm7550-gpio", .data = (void *) 12 },
1230	{ .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},
1231	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1232	{ .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1233	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1234	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1235	{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1236	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1237	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1238	/* pm8150l has 12 GPIOs with holes on 7 */
1239	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1240	{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1241	{ .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1242	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1243	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1244	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1245	{ .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1246	{ .compatible = "qcom,pm8550-gpio", .data = (void *) 12 },
1247	{ .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 },
1248	{ .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 },
1249	{ .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 },
1250	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1251	/* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */
1252	{ .compatible = "qcom,pm8937-gpio", .data = (void *) 8 },
1253	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1254	/* pm8950 has 8 GPIOs with holes on 3 */
1255	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1256	/* pm8953 has 8 GPIOs with holes on 3 and 6 */
1257	{ .compatible = "qcom,pm8953-gpio", .data = (void *) 8 },
1258	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1259	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1260	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1261	{ .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
1262	{ .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
1263	{ .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
1264	{ .compatible = "qcom,pmh0101-gpio", .data = (void *)18 },
1265	{ .compatible = "qcom,pmh0104-gpio", .data = (void *)8 },
1266	{ .compatible = "qcom,pmh0110-gpio", .data = (void *)14 },
1267	{ .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
1268	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1269	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1270	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1271	{ .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 },
1272	{ .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 },
1273	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1274	{ .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
1275	{ .compatible = "qcom,pmk8850-gpio", .data = (void *)8 },
1276	{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1277	{ .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 },
1278	/* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1279	{ .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1280	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1281	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1282	{ .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 },
1283	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1284	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1285	/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1286	{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1287	{ .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1288	{ .compatible = "qcom,pmx75-gpio", .data = (void *) 16 },
1289	{ .compatible = "qcom,pmxr2230-gpio", .data = (void *) 12 },
1290	{ },
1291};
1292
1293MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1294
1295static struct platform_driver pmic_gpio_driver = {
1296	.driver = {
1297		   .name = "qcom-spmi-gpio",
1298		   .of_match_table = pmic_gpio_of_match,
1299	},
1300	.probe	= pmic_gpio_probe,
1301	.remove = pmic_gpio_remove,
1302};
1303
1304module_platform_driver(pmic_gpio_driver);
1305
1306MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1307MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1308MODULE_ALIAS("platform:qcom-spmi-gpio");
1309MODULE_LICENSE("GPL v2");