pinctrl-sm8250.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/module.h>
   7#include <linux/of.h>
   8#include <linux/platform_device.h>
   9
  10#include "pinctrl-msm.h"
  11
  12static const char * const sm8250_tiles[] = {
  13	"west",
  14	"south",
  15	"north",
  16};
  17
  18enum {
  19	WEST,
  20	SOUTH,
  21	NORTH,
  22};
  23
  24#define REG_SIZE 0x1000
  25#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
  26	{						\
  27		.grp = PINCTRL_PINGROUP("gpio" #id, 	\
  28			gpio##id##_pins, 		\
  29			ARRAY_SIZE(gpio##id##_pins)),	\
  30		.funcs = (int[]){			\
  31			msm_mux_gpio, /* gpio mode */	\
  32			msm_mux_##f1,			\
  33			msm_mux_##f2,			\
  34			msm_mux_##f3,			\
  35			msm_mux_##f4,			\
  36			msm_mux_##f5,			\
  37			msm_mux_##f6,			\
  38			msm_mux_##f7,			\
  39			msm_mux_##f8,			\
  40			msm_mux_##f9			\
  41		},					\
  42		.nfuncs = 10,				\
  43		.ctl_reg = REG_SIZE * id,		\
  44		.io_reg = REG_SIZE * id + 0x4,		\
  45		.intr_cfg_reg = REG_SIZE * id + 0x8,	\
  46		.intr_status_reg = REG_SIZE * id + 0xc,	\
  47		.intr_target_reg = REG_SIZE * id + 0x8,	\
  48		.tile = _tile,				\
  49		.mux_bit = 2,				\
  50		.pull_bit = 0,				\
  51		.drv_bit = 6,				\
  52		.egpio_enable = 12,			\
  53		.egpio_present = 11,			\
  54		.oe_bit = 9,				\
  55		.in_bit = 0,				\
  56		.out_bit = 1,				\
  57		.intr_enable_bit = 0,			\
  58		.intr_status_bit = 0,			\
  59		.intr_target_bit = 5,			\
  60		.intr_target_kpss_val = 3,		\
  61		.intr_raw_status_bit = 4,		\
  62		.intr_polarity_bit = 1,			\
  63		.intr_detection_bit = 2,		\
  64		.intr_detection_width = 2,		\
  65	}
  66
  67#define SDC_PINGROUP(pg_name, ctl, pull, drv)	\
  68	{						\
  69		.grp = PINCTRL_PINGROUP(#pg_name, 	\
  70			pg_name##_pins, 		\
  71			ARRAY_SIZE(pg_name##_pins)),	\
  72		.ctl_reg = ctl,				\
  73		.io_reg = 0,				\
  74		.intr_cfg_reg = 0,			\
  75		.intr_status_reg = 0,			\
  76		.intr_target_reg = 0,			\
  77		.tile = NORTH,				\
  78		.mux_bit = -1,				\
  79		.pull_bit = pull,			\
  80		.drv_bit = drv,				\
  81		.oe_bit = -1,				\
  82		.in_bit = -1,				\
  83		.out_bit = -1,				\
  84		.intr_enable_bit = -1,			\
  85		.intr_status_bit = -1,			\
  86		.intr_target_bit = -1,			\
  87		.intr_raw_status_bit = -1,		\
  88		.intr_polarity_bit = -1,		\
  89		.intr_detection_bit = -1,		\
  90		.intr_detection_width = -1,		\
  91	}
  92
  93#define UFS_RESET(pg_name, offset)				\
  94	{						\
  95		.grp = PINCTRL_PINGROUP(#pg_name, 	\
  96			pg_name##_pins, 		\
  97			ARRAY_SIZE(pg_name##_pins)),	\
  98		.ctl_reg = offset,			\
  99		.io_reg = offset + 0x4,			\
 100		.intr_cfg_reg = 0,			\
 101		.intr_status_reg = 0,			\
 102		.intr_target_reg = 0,			\
 103		.tile = SOUTH,				\
 104		.mux_bit = -1,				\
 105		.pull_bit = 3,				\
 106		.drv_bit = 0,				\
 107		.oe_bit = -1,				\
 108		.in_bit = -1,				\
 109		.out_bit = 0,				\
 110		.intr_enable_bit = -1,			\
 111		.intr_status_bit = -1,			\
 112		.intr_target_bit = -1,			\
 113		.intr_raw_status_bit = -1,		\
 114		.intr_polarity_bit = -1,		\
 115		.intr_detection_bit = -1,		\
 116		.intr_detection_width = -1,		\
 117	}
 118
 119static const struct pinctrl_pin_desc sm8250_pins[] = {
 120	PINCTRL_PIN(0, "GPIO_0"),
 121	PINCTRL_PIN(1, "GPIO_1"),
 122	PINCTRL_PIN(2, "GPIO_2"),
 123	PINCTRL_PIN(3, "GPIO_3"),
 124	PINCTRL_PIN(4, "GPIO_4"),
 125	PINCTRL_PIN(5, "GPIO_5"),
 126	PINCTRL_PIN(6, "GPIO_6"),
 127	PINCTRL_PIN(7, "GPIO_7"),
 128	PINCTRL_PIN(8, "GPIO_8"),
 129	PINCTRL_PIN(9, "GPIO_9"),
 130	PINCTRL_PIN(10, "GPIO_10"),
 131	PINCTRL_PIN(11, "GPIO_11"),
 132	PINCTRL_PIN(12, "GPIO_12"),
 133	PINCTRL_PIN(13, "GPIO_13"),
 134	PINCTRL_PIN(14, "GPIO_14"),
 135	PINCTRL_PIN(15, "GPIO_15"),
 136	PINCTRL_PIN(16, "GPIO_16"),
 137	PINCTRL_PIN(17, "GPIO_17"),
 138	PINCTRL_PIN(18, "GPIO_18"),
 139	PINCTRL_PIN(19, "GPIO_19"),
 140	PINCTRL_PIN(20, "GPIO_20"),
 141	PINCTRL_PIN(21, "GPIO_21"),
 142	PINCTRL_PIN(22, "GPIO_22"),
 143	PINCTRL_PIN(23, "GPIO_23"),
 144	PINCTRL_PIN(24, "GPIO_24"),
 145	PINCTRL_PIN(25, "GPIO_25"),
 146	PINCTRL_PIN(26, "GPIO_26"),
 147	PINCTRL_PIN(27, "GPIO_27"),
 148	PINCTRL_PIN(28, "GPIO_28"),
 149	PINCTRL_PIN(29, "GPIO_29"),
 150	PINCTRL_PIN(30, "GPIO_30"),
 151	PINCTRL_PIN(31, "GPIO_31"),
 152	PINCTRL_PIN(32, "GPIO_32"),
 153	PINCTRL_PIN(33, "GPIO_33"),
 154	PINCTRL_PIN(34, "GPIO_34"),
 155	PINCTRL_PIN(35, "GPIO_35"),
 156	PINCTRL_PIN(36, "GPIO_36"),
 157	PINCTRL_PIN(37, "GPIO_37"),
 158	PINCTRL_PIN(38, "GPIO_38"),
 159	PINCTRL_PIN(39, "GPIO_39"),
 160	PINCTRL_PIN(40, "GPIO_40"),
 161	PINCTRL_PIN(41, "GPIO_41"),
 162	PINCTRL_PIN(42, "GPIO_42"),
 163	PINCTRL_PIN(43, "GPIO_43"),
 164	PINCTRL_PIN(44, "GPIO_44"),
 165	PINCTRL_PIN(45, "GPIO_45"),
 166	PINCTRL_PIN(46, "GPIO_46"),
 167	PINCTRL_PIN(47, "GPIO_47"),
 168	PINCTRL_PIN(48, "GPIO_48"),
 169	PINCTRL_PIN(49, "GPIO_49"),
 170	PINCTRL_PIN(50, "GPIO_50"),
 171	PINCTRL_PIN(51, "GPIO_51"),
 172	PINCTRL_PIN(52, "GPIO_52"),
 173	PINCTRL_PIN(53, "GPIO_53"),
 174	PINCTRL_PIN(54, "GPIO_54"),
 175	PINCTRL_PIN(55, "GPIO_55"),
 176	PINCTRL_PIN(56, "GPIO_56"),
 177	PINCTRL_PIN(57, "GPIO_57"),
 178	PINCTRL_PIN(58, "GPIO_58"),
 179	PINCTRL_PIN(59, "GPIO_59"),
 180	PINCTRL_PIN(60, "GPIO_60"),
 181	PINCTRL_PIN(61, "GPIO_61"),
 182	PINCTRL_PIN(62, "GPIO_62"),
 183	PINCTRL_PIN(63, "GPIO_63"),
 184	PINCTRL_PIN(64, "GPIO_64"),
 185	PINCTRL_PIN(65, "GPIO_65"),
 186	PINCTRL_PIN(66, "GPIO_66"),
 187	PINCTRL_PIN(67, "GPIO_67"),
 188	PINCTRL_PIN(68, "GPIO_68"),
 189	PINCTRL_PIN(69, "GPIO_69"),
 190	PINCTRL_PIN(70, "GPIO_70"),
 191	PINCTRL_PIN(71, "GPIO_71"),
 192	PINCTRL_PIN(72, "GPIO_72"),
 193	PINCTRL_PIN(73, "GPIO_73"),
 194	PINCTRL_PIN(74, "GPIO_74"),
 195	PINCTRL_PIN(75, "GPIO_75"),
 196	PINCTRL_PIN(76, "GPIO_76"),
 197	PINCTRL_PIN(77, "GPIO_77"),
 198	PINCTRL_PIN(78, "GPIO_78"),
 199	PINCTRL_PIN(79, "GPIO_79"),
 200	PINCTRL_PIN(80, "GPIO_80"),
 201	PINCTRL_PIN(81, "GPIO_81"),
 202	PINCTRL_PIN(82, "GPIO_82"),
 203	PINCTRL_PIN(83, "GPIO_83"),
 204	PINCTRL_PIN(84, "GPIO_84"),
 205	PINCTRL_PIN(85, "GPIO_85"),
 206	PINCTRL_PIN(86, "GPIO_86"),
 207	PINCTRL_PIN(87, "GPIO_87"),
 208	PINCTRL_PIN(88, "GPIO_88"),
 209	PINCTRL_PIN(89, "GPIO_89"),
 210	PINCTRL_PIN(90, "GPIO_90"),
 211	PINCTRL_PIN(91, "GPIO_91"),
 212	PINCTRL_PIN(92, "GPIO_92"),
 213	PINCTRL_PIN(93, "GPIO_93"),
 214	PINCTRL_PIN(94, "GPIO_94"),
 215	PINCTRL_PIN(95, "GPIO_95"),
 216	PINCTRL_PIN(96, "GPIO_96"),
 217	PINCTRL_PIN(97, "GPIO_97"),
 218	PINCTRL_PIN(98, "GPIO_98"),
 219	PINCTRL_PIN(99, "GPIO_99"),
 220	PINCTRL_PIN(100, "GPIO_100"),
 221	PINCTRL_PIN(101, "GPIO_101"),
 222	PINCTRL_PIN(102, "GPIO_102"),
 223	PINCTRL_PIN(103, "GPIO_103"),
 224	PINCTRL_PIN(104, "GPIO_104"),
 225	PINCTRL_PIN(105, "GPIO_105"),
 226	PINCTRL_PIN(106, "GPIO_106"),
 227	PINCTRL_PIN(107, "GPIO_107"),
 228	PINCTRL_PIN(108, "GPIO_108"),
 229	PINCTRL_PIN(109, "GPIO_109"),
 230	PINCTRL_PIN(110, "GPIO_110"),
 231	PINCTRL_PIN(111, "GPIO_111"),
 232	PINCTRL_PIN(112, "GPIO_112"),
 233	PINCTRL_PIN(113, "GPIO_113"),
 234	PINCTRL_PIN(114, "GPIO_114"),
 235	PINCTRL_PIN(115, "GPIO_115"),
 236	PINCTRL_PIN(116, "GPIO_116"),
 237	PINCTRL_PIN(117, "GPIO_117"),
 238	PINCTRL_PIN(118, "GPIO_118"),
 239	PINCTRL_PIN(119, "GPIO_119"),
 240	PINCTRL_PIN(120, "GPIO_120"),
 241	PINCTRL_PIN(121, "GPIO_121"),
 242	PINCTRL_PIN(122, "GPIO_122"),
 243	PINCTRL_PIN(123, "GPIO_123"),
 244	PINCTRL_PIN(124, "GPIO_124"),
 245	PINCTRL_PIN(125, "GPIO_125"),
 246	PINCTRL_PIN(126, "GPIO_126"),
 247	PINCTRL_PIN(127, "GPIO_127"),
 248	PINCTRL_PIN(128, "GPIO_128"),
 249	PINCTRL_PIN(129, "GPIO_129"),
 250	PINCTRL_PIN(130, "GPIO_130"),
 251	PINCTRL_PIN(131, "GPIO_131"),
 252	PINCTRL_PIN(132, "GPIO_132"),
 253	PINCTRL_PIN(133, "GPIO_133"),
 254	PINCTRL_PIN(134, "GPIO_134"),
 255	PINCTRL_PIN(135, "GPIO_135"),
 256	PINCTRL_PIN(136, "GPIO_136"),
 257	PINCTRL_PIN(137, "GPIO_137"),
 258	PINCTRL_PIN(138, "GPIO_138"),
 259	PINCTRL_PIN(139, "GPIO_139"),
 260	PINCTRL_PIN(140, "GPIO_140"),
 261	PINCTRL_PIN(141, "GPIO_141"),
 262	PINCTRL_PIN(142, "GPIO_142"),
 263	PINCTRL_PIN(143, "GPIO_143"),
 264	PINCTRL_PIN(144, "GPIO_144"),
 265	PINCTRL_PIN(145, "GPIO_145"),
 266	PINCTRL_PIN(146, "GPIO_146"),
 267	PINCTRL_PIN(147, "GPIO_147"),
 268	PINCTRL_PIN(148, "GPIO_148"),
 269	PINCTRL_PIN(149, "GPIO_149"),
 270	PINCTRL_PIN(150, "GPIO_150"),
 271	PINCTRL_PIN(151, "GPIO_151"),
 272	PINCTRL_PIN(152, "GPIO_152"),
 273	PINCTRL_PIN(153, "GPIO_153"),
 274	PINCTRL_PIN(154, "GPIO_154"),
 275	PINCTRL_PIN(155, "GPIO_155"),
 276	PINCTRL_PIN(156, "GPIO_156"),
 277	PINCTRL_PIN(157, "GPIO_157"),
 278	PINCTRL_PIN(158, "GPIO_158"),
 279	PINCTRL_PIN(159, "GPIO_159"),
 280	PINCTRL_PIN(160, "GPIO_160"),
 281	PINCTRL_PIN(161, "GPIO_161"),
 282	PINCTRL_PIN(162, "GPIO_162"),
 283	PINCTRL_PIN(163, "GPIO_163"),
 284	PINCTRL_PIN(164, "GPIO_164"),
 285	PINCTRL_PIN(165, "GPIO_165"),
 286	PINCTRL_PIN(166, "GPIO_166"),
 287	PINCTRL_PIN(167, "GPIO_167"),
 288	PINCTRL_PIN(168, "GPIO_168"),
 289	PINCTRL_PIN(169, "GPIO_169"),
 290	PINCTRL_PIN(170, "GPIO_170"),
 291	PINCTRL_PIN(171, "GPIO_171"),
 292	PINCTRL_PIN(172, "GPIO_172"),
 293	PINCTRL_PIN(173, "GPIO_173"),
 294	PINCTRL_PIN(174, "GPIO_174"),
 295	PINCTRL_PIN(175, "GPIO_175"),
 296	PINCTRL_PIN(176, "GPIO_176"),
 297	PINCTRL_PIN(177, "GPIO_177"),
 298	PINCTRL_PIN(178, "GPIO_178"),
 299	PINCTRL_PIN(179, "GPIO_179"),
 300	PINCTRL_PIN(180, "SDC2_CLK"),
 301	PINCTRL_PIN(181, "SDC2_CMD"),
 302	PINCTRL_PIN(182, "SDC2_DATA"),
 303	PINCTRL_PIN(183, "UFS_RESET"),
 304};
 305
 306#define DECLARE_MSM_GPIO_PINS(pin) \
 307	static const unsigned int gpio##pin##_pins[] = { pin }
 308DECLARE_MSM_GPIO_PINS(0);
 309DECLARE_MSM_GPIO_PINS(1);
 310DECLARE_MSM_GPIO_PINS(2);
 311DECLARE_MSM_GPIO_PINS(3);
 312DECLARE_MSM_GPIO_PINS(4);
 313DECLARE_MSM_GPIO_PINS(5);
 314DECLARE_MSM_GPIO_PINS(6);
 315DECLARE_MSM_GPIO_PINS(7);
 316DECLARE_MSM_GPIO_PINS(8);
 317DECLARE_MSM_GPIO_PINS(9);
 318DECLARE_MSM_GPIO_PINS(10);
 319DECLARE_MSM_GPIO_PINS(11);
 320DECLARE_MSM_GPIO_PINS(12);
 321DECLARE_MSM_GPIO_PINS(13);
 322DECLARE_MSM_GPIO_PINS(14);
 323DECLARE_MSM_GPIO_PINS(15);
 324DECLARE_MSM_GPIO_PINS(16);
 325DECLARE_MSM_GPIO_PINS(17);
 326DECLARE_MSM_GPIO_PINS(18);
 327DECLARE_MSM_GPIO_PINS(19);
 328DECLARE_MSM_GPIO_PINS(20);
 329DECLARE_MSM_GPIO_PINS(21);
 330DECLARE_MSM_GPIO_PINS(22);
 331DECLARE_MSM_GPIO_PINS(23);
 332DECLARE_MSM_GPIO_PINS(24);
 333DECLARE_MSM_GPIO_PINS(25);
 334DECLARE_MSM_GPIO_PINS(26);
 335DECLARE_MSM_GPIO_PINS(27);
 336DECLARE_MSM_GPIO_PINS(28);
 337DECLARE_MSM_GPIO_PINS(29);
 338DECLARE_MSM_GPIO_PINS(30);
 339DECLARE_MSM_GPIO_PINS(31);
 340DECLARE_MSM_GPIO_PINS(32);
 341DECLARE_MSM_GPIO_PINS(33);
 342DECLARE_MSM_GPIO_PINS(34);
 343DECLARE_MSM_GPIO_PINS(35);
 344DECLARE_MSM_GPIO_PINS(36);
 345DECLARE_MSM_GPIO_PINS(37);
 346DECLARE_MSM_GPIO_PINS(38);
 347DECLARE_MSM_GPIO_PINS(39);
 348DECLARE_MSM_GPIO_PINS(40);
 349DECLARE_MSM_GPIO_PINS(41);
 350DECLARE_MSM_GPIO_PINS(42);
 351DECLARE_MSM_GPIO_PINS(43);
 352DECLARE_MSM_GPIO_PINS(44);
 353DECLARE_MSM_GPIO_PINS(45);
 354DECLARE_MSM_GPIO_PINS(46);
 355DECLARE_MSM_GPIO_PINS(47);
 356DECLARE_MSM_GPIO_PINS(48);
 357DECLARE_MSM_GPIO_PINS(49);
 358DECLARE_MSM_GPIO_PINS(50);
 359DECLARE_MSM_GPIO_PINS(51);
 360DECLARE_MSM_GPIO_PINS(52);
 361DECLARE_MSM_GPIO_PINS(53);
 362DECLARE_MSM_GPIO_PINS(54);
 363DECLARE_MSM_GPIO_PINS(55);
 364DECLARE_MSM_GPIO_PINS(56);
 365DECLARE_MSM_GPIO_PINS(57);
 366DECLARE_MSM_GPIO_PINS(58);
 367DECLARE_MSM_GPIO_PINS(59);
 368DECLARE_MSM_GPIO_PINS(60);
 369DECLARE_MSM_GPIO_PINS(61);
 370DECLARE_MSM_GPIO_PINS(62);
 371DECLARE_MSM_GPIO_PINS(63);
 372DECLARE_MSM_GPIO_PINS(64);
 373DECLARE_MSM_GPIO_PINS(65);
 374DECLARE_MSM_GPIO_PINS(66);
 375DECLARE_MSM_GPIO_PINS(67);
 376DECLARE_MSM_GPIO_PINS(68);
 377DECLARE_MSM_GPIO_PINS(69);
 378DECLARE_MSM_GPIO_PINS(70);
 379DECLARE_MSM_GPIO_PINS(71);
 380DECLARE_MSM_GPIO_PINS(72);
 381DECLARE_MSM_GPIO_PINS(73);
 382DECLARE_MSM_GPIO_PINS(74);
 383DECLARE_MSM_GPIO_PINS(75);
 384DECLARE_MSM_GPIO_PINS(76);
 385DECLARE_MSM_GPIO_PINS(77);
 386DECLARE_MSM_GPIO_PINS(78);
 387DECLARE_MSM_GPIO_PINS(79);
 388DECLARE_MSM_GPIO_PINS(80);
 389DECLARE_MSM_GPIO_PINS(81);
 390DECLARE_MSM_GPIO_PINS(82);
 391DECLARE_MSM_GPIO_PINS(83);
 392DECLARE_MSM_GPIO_PINS(84);
 393DECLARE_MSM_GPIO_PINS(85);
 394DECLARE_MSM_GPIO_PINS(86);
 395DECLARE_MSM_GPIO_PINS(87);
 396DECLARE_MSM_GPIO_PINS(88);
 397DECLARE_MSM_GPIO_PINS(89);
 398DECLARE_MSM_GPIO_PINS(90);
 399DECLARE_MSM_GPIO_PINS(91);
 400DECLARE_MSM_GPIO_PINS(92);
 401DECLARE_MSM_GPIO_PINS(93);
 402DECLARE_MSM_GPIO_PINS(94);
 403DECLARE_MSM_GPIO_PINS(95);
 404DECLARE_MSM_GPIO_PINS(96);
 405DECLARE_MSM_GPIO_PINS(97);
 406DECLARE_MSM_GPIO_PINS(98);
 407DECLARE_MSM_GPIO_PINS(99);
 408DECLARE_MSM_GPIO_PINS(100);
 409DECLARE_MSM_GPIO_PINS(101);
 410DECLARE_MSM_GPIO_PINS(102);
 411DECLARE_MSM_GPIO_PINS(103);
 412DECLARE_MSM_GPIO_PINS(104);
 413DECLARE_MSM_GPIO_PINS(105);
 414DECLARE_MSM_GPIO_PINS(106);
 415DECLARE_MSM_GPIO_PINS(107);
 416DECLARE_MSM_GPIO_PINS(108);
 417DECLARE_MSM_GPIO_PINS(109);
 418DECLARE_MSM_GPIO_PINS(110);
 419DECLARE_MSM_GPIO_PINS(111);
 420DECLARE_MSM_GPIO_PINS(112);
 421DECLARE_MSM_GPIO_PINS(113);
 422DECLARE_MSM_GPIO_PINS(114);
 423DECLARE_MSM_GPIO_PINS(115);
 424DECLARE_MSM_GPIO_PINS(116);
 425DECLARE_MSM_GPIO_PINS(117);
 426DECLARE_MSM_GPIO_PINS(118);
 427DECLARE_MSM_GPIO_PINS(119);
 428DECLARE_MSM_GPIO_PINS(120);
 429DECLARE_MSM_GPIO_PINS(121);
 430DECLARE_MSM_GPIO_PINS(122);
 431DECLARE_MSM_GPIO_PINS(123);
 432DECLARE_MSM_GPIO_PINS(124);
 433DECLARE_MSM_GPIO_PINS(125);
 434DECLARE_MSM_GPIO_PINS(126);
 435DECLARE_MSM_GPIO_PINS(127);
 436DECLARE_MSM_GPIO_PINS(128);
 437DECLARE_MSM_GPIO_PINS(129);
 438DECLARE_MSM_GPIO_PINS(130);
 439DECLARE_MSM_GPIO_PINS(131);
 440DECLARE_MSM_GPIO_PINS(132);
 441DECLARE_MSM_GPIO_PINS(133);
 442DECLARE_MSM_GPIO_PINS(134);
 443DECLARE_MSM_GPIO_PINS(135);
 444DECLARE_MSM_GPIO_PINS(136);
 445DECLARE_MSM_GPIO_PINS(137);
 446DECLARE_MSM_GPIO_PINS(138);
 447DECLARE_MSM_GPIO_PINS(139);
 448DECLARE_MSM_GPIO_PINS(140);
 449DECLARE_MSM_GPIO_PINS(141);
 450DECLARE_MSM_GPIO_PINS(142);
 451DECLARE_MSM_GPIO_PINS(143);
 452DECLARE_MSM_GPIO_PINS(144);
 453DECLARE_MSM_GPIO_PINS(145);
 454DECLARE_MSM_GPIO_PINS(146);
 455DECLARE_MSM_GPIO_PINS(147);
 456DECLARE_MSM_GPIO_PINS(148);
 457DECLARE_MSM_GPIO_PINS(149);
 458DECLARE_MSM_GPIO_PINS(150);
 459DECLARE_MSM_GPIO_PINS(151);
 460DECLARE_MSM_GPIO_PINS(152);
 461DECLARE_MSM_GPIO_PINS(153);
 462DECLARE_MSM_GPIO_PINS(154);
 463DECLARE_MSM_GPIO_PINS(155);
 464DECLARE_MSM_GPIO_PINS(156);
 465DECLARE_MSM_GPIO_PINS(157);
 466DECLARE_MSM_GPIO_PINS(158);
 467DECLARE_MSM_GPIO_PINS(159);
 468DECLARE_MSM_GPIO_PINS(160);
 469DECLARE_MSM_GPIO_PINS(161);
 470DECLARE_MSM_GPIO_PINS(162);
 471DECLARE_MSM_GPIO_PINS(163);
 472DECLARE_MSM_GPIO_PINS(164);
 473DECLARE_MSM_GPIO_PINS(165);
 474DECLARE_MSM_GPIO_PINS(166);
 475DECLARE_MSM_GPIO_PINS(167);
 476DECLARE_MSM_GPIO_PINS(168);
 477DECLARE_MSM_GPIO_PINS(169);
 478DECLARE_MSM_GPIO_PINS(170);
 479DECLARE_MSM_GPIO_PINS(171);
 480DECLARE_MSM_GPIO_PINS(172);
 481DECLARE_MSM_GPIO_PINS(173);
 482DECLARE_MSM_GPIO_PINS(174);
 483DECLARE_MSM_GPIO_PINS(175);
 484DECLARE_MSM_GPIO_PINS(176);
 485DECLARE_MSM_GPIO_PINS(177);
 486DECLARE_MSM_GPIO_PINS(178);
 487DECLARE_MSM_GPIO_PINS(179);
 488
 489static const unsigned int ufs_reset_pins[] = { 180 };
 490static const unsigned int sdc2_clk_pins[] = { 181 };
 491static const unsigned int sdc2_cmd_pins[] = { 182 };
 492static const unsigned int sdc2_data_pins[] = { 183 };
 493
 494enum sm8250_functions {
 495	msm_mux_aoss_cti,
 496	msm_mux_atest,
 497	msm_mux_audio_ref,
 498	msm_mux_cam_mclk,
 499	msm_mux_cci_async,
 500	msm_mux_cci_i2c,
 501	msm_mux_cci_timer0,
 502	msm_mux_cci_timer1,
 503	msm_mux_cci_timer2,
 504	msm_mux_cci_timer3,
 505	msm_mux_cci_timer4,
 506	msm_mux_cri_trng,
 507	msm_mux_cri_trng0,
 508	msm_mux_cri_trng1,
 509	msm_mux_dbg_out,
 510	msm_mux_ddr_bist,
 511	msm_mux_ddr_pxi0,
 512	msm_mux_ddr_pxi1,
 513	msm_mux_ddr_pxi2,
 514	msm_mux_ddr_pxi3,
 515	msm_mux_dp_hot,
 516	msm_mux_egpio,
 517	msm_mux_dp_lcd,
 518	msm_mux_gcc_gp1,
 519	msm_mux_gcc_gp2,
 520	msm_mux_gcc_gp3,
 521	msm_mux_gpio,
 522	msm_mux_ibi_i3c,
 523	msm_mux_jitter_bist,
 524	msm_mux_lpass_slimbus,
 525	msm_mux_mdp_vsync,
 526	msm_mux_mdp_vsync0,
 527	msm_mux_mdp_vsync1,
 528	msm_mux_mdp_vsync2,
 529	msm_mux_mdp_vsync3,
 530	msm_mux_mi2s0_data0,
 531	msm_mux_mi2s0_data1,
 532	msm_mux_mi2s0_sck,
 533	msm_mux_mi2s0_ws,
 534	msm_mux_mi2s1_data0,
 535	msm_mux_mi2s1_data1,
 536	msm_mux_mi2s1_sck,
 537	msm_mux_mi2s1_ws,
 538	msm_mux_mi2s2_data0,
 539	msm_mux_mi2s2_data1,
 540	msm_mux_mi2s2_sck,
 541	msm_mux_mi2s2_ws,
 542	msm_mux_pci_e0,
 543	msm_mux_pci_e1,
 544	msm_mux_pci_e2,
 545	msm_mux_phase_flag,
 546	msm_mux_pll_bist,
 547	msm_mux_pll_bypassnl,
 548	msm_mux_pll_clk,
 549	msm_mux_pll_reset,
 550	msm_mux_pri_mi2s,
 551	msm_mux_prng_rosc,
 552	msm_mux_qdss_cti,
 553	msm_mux_qdss_gpio,
 554	msm_mux_qspi0,
 555	msm_mux_qspi1,
 556	msm_mux_qspi2,
 557	msm_mux_qspi3,
 558	msm_mux_qspi_clk,
 559	msm_mux_qspi_cs,
 560	msm_mux_qup0,
 561	msm_mux_qup1,
 562	msm_mux_qup10,
 563	msm_mux_qup11,
 564	msm_mux_qup12,
 565	msm_mux_qup13,
 566	msm_mux_qup14,
 567	msm_mux_qup15,
 568	msm_mux_qup16,
 569	msm_mux_qup17,
 570	msm_mux_qup18,
 571	msm_mux_qup19,
 572	msm_mux_qup2,
 573	msm_mux_qup3,
 574	msm_mux_qup4,
 575	msm_mux_qup5,
 576	msm_mux_qup6,
 577	msm_mux_qup7,
 578	msm_mux_qup8,
 579	msm_mux_qup9,
 580	msm_mux_qup_l4,
 581	msm_mux_qup_l5,
 582	msm_mux_qup_l6,
 583	msm_mux_sd_write,
 584	msm_mux_sdc40,
 585	msm_mux_sdc41,
 586	msm_mux_sdc42,
 587	msm_mux_sdc43,
 588	msm_mux_sdc4_clk,
 589	msm_mux_sdc4_cmd,
 590	msm_mux_sec_mi2s,
 591	msm_mux_sp_cmu,
 592	msm_mux_tgu_ch0,
 593	msm_mux_tgu_ch1,
 594	msm_mux_tgu_ch2,
 595	msm_mux_tgu_ch3,
 596	msm_mux_tsense_pwm1,
 597	msm_mux_tsense_pwm2,
 598	msm_mux_tsif0_clk,
 599	msm_mux_tsif0_data,
 600	msm_mux_tsif0_en,
 601	msm_mux_tsif0_error,
 602	msm_mux_tsif0_sync,
 603	msm_mux_tsif1_clk,
 604	msm_mux_tsif1_data,
 605	msm_mux_tsif1_en,
 606	msm_mux_tsif1_error,
 607	msm_mux_tsif1_sync,
 608	msm_mux_usb2phy_ac,
 609	msm_mux_usb_phy,
 610	msm_mux_vsense_trigger,
 611	msm_mux__,
 612};
 613
 614static const char * const tsif1_data_groups[] = {
 615	"gpio75",
 616};
 617static const char * const sdc41_groups[] = {
 618	"gpio75",
 619};
 620static const char * const tsif1_sync_groups[] = {
 621	"gpio76",
 622};
 623static const char * const sdc40_groups[] = {
 624	"gpio76",
 625};
 626static const char * const aoss_cti_groups[] = {
 627	"gpio77",
 628};
 629static const char * const phase_flag_groups[] = {
 630	"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
 631	"gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77",
 632	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
 633	"gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118",
 634	"gpio119", "gpio120", "gpio122", "gpio124", "gpio125",
 635};
 636static const char * const sd_write_groups[] = {
 637	"gpio78",
 638};
 639static const char * const pci_e0_groups[] = {
 640	"gpio79", "gpio80",
 641};
 642static const char * const pci_e1_groups[] = {
 643	"gpio82", "gpio83",
 644};
 645static const char * const pci_e2_groups[] = {
 646	"gpio85", "gpio86",
 647};
 648static const char * const tgu_ch0_groups[] = {
 649	"gpio85",
 650};
 651static const char * const atest_groups[] = {
 652	"gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34",
 653	"gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88",
 654	"gpio89",
 655};
 656static const char * const tgu_ch3_groups[] = {
 657	"gpio86",
 658};
 659static const char * const tsif1_error_groups[] = {
 660	"gpio90",
 661};
 662static const char * const tgu_ch1_groups[] = {
 663	"gpio90",
 664};
 665static const char * const tsif0_error_groups[] = {
 666	"gpio91",
 667};
 668static const char * const tgu_ch2_groups[] = {
 669	"gpio91",
 670};
 671static const char * const cam_mclk_groups[] = {
 672	"gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
 673};
 674static const char * const ddr_bist_groups[] = {
 675	"gpio94", "gpio95", "gpio143", "gpio144",
 676};
 677static const char * const pll_bypassnl_groups[] = {
 678	"gpio96",
 679};
 680static const char * const pll_reset_groups[] = {
 681	"gpio97",
 682};
 683static const char * const cci_i2c_groups[] = {
 684	"gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
 685	"gpio107", "gpio108",
 686};
 687static const char * const qdss_gpio_groups[] = {
 688	"gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
 689	"gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
 690	"gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160",
 691	"gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
 692	"gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172",
 693	"gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
 694};
 695static const char * const gcc_gp1_groups[] = {
 696	"gpio106", "gpio136",
 697};
 698static const char * const gcc_gp2_groups[] = {
 699	"gpio107", "gpio137",
 700};
 701static const char * const gcc_gp3_groups[] = {
 702	"gpio108", "gpio138",
 703};
 704static const char * const cci_timer0_groups[] = {
 705	"gpio109",
 706};
 707static const char * const cci_timer1_groups[] = {
 708	"gpio110",
 709};
 710static const char * const cci_timer2_groups[] = {
 711	"gpio111",
 712};
 713static const char * const cci_timer3_groups[] = {
 714	"gpio112",
 715};
 716static const char * const cci_async_groups[] = {
 717	"gpio112", "gpio113", "gpio114",
 718};
 719static const char * const cci_timer4_groups[] = {
 720	"gpio113",
 721};
 722static const char * const qup2_groups[] = {
 723	"gpio115", "gpio116", "gpio117", "gpio118",
 724};
 725static const char * const qup3_groups[] = {
 726	"gpio119", "gpio120", "gpio121", "gpio122",
 727};
 728static const char * const tsense_pwm1_groups[] = {
 729	"gpio123",
 730};
 731static const char * const tsense_pwm2_groups[] = {
 732	"gpio123",
 733};
 734static const char * const qup9_groups[] = {
 735	"gpio125", "gpio126", "gpio127", "gpio128",
 736};
 737static const char * const qup10_groups[] = {
 738	"gpio129", "gpio130", "gpio131", "gpio132",
 739};
 740static const char * const mi2s2_sck_groups[] = {
 741	"gpio133",
 742};
 743static const char * const mi2s2_data0_groups[] = {
 744	"gpio134",
 745};
 746static const char * const mi2s2_ws_groups[] = {
 747	"gpio135",
 748};
 749static const char * const pri_mi2s_groups[] = {
 750	"gpio136",
 751};
 752static const char * const sec_mi2s_groups[] = {
 753	"gpio137",
 754};
 755static const char * const audio_ref_groups[] = {
 756	"gpio137",
 757};
 758static const char * const mi2s2_data1_groups[] = {
 759	"gpio137",
 760};
 761static const char * const mi2s0_sck_groups[] = {
 762	"gpio138",
 763};
 764static const char * const mi2s0_data0_groups[] = {
 765	"gpio139",
 766};
 767static const char * const mi2s0_data1_groups[] = {
 768	"gpio140",
 769};
 770static const char * const mi2s0_ws_groups[] = {
 771	"gpio141",
 772};
 773static const char * const lpass_slimbus_groups[] = {
 774	"gpio142", "gpio143", "gpio144", "gpio145",
 775};
 776static const char * const mi2s1_sck_groups[] = {
 777	"gpio142",
 778};
 779static const char * const mi2s1_data0_groups[] = {
 780	"gpio143",
 781};
 782static const char * const mi2s1_data1_groups[] = {
 783	"gpio144",
 784};
 785static const char * const mi2s1_ws_groups[] = {
 786	"gpio145",
 787};
 788static const char * const cri_trng0_groups[] = {
 789	"gpio159",
 790};
 791static const char * const cri_trng1_groups[] = {
 792	"gpio160",
 793};
 794static const char * const cri_trng_groups[] = {
 795	"gpio161",
 796};
 797static const char * const sp_cmu_groups[] = {
 798	"gpio162",
 799};
 800static const char * const prng_rosc_groups[] = {
 801	"gpio163",
 802};
 803static const char * const qup19_groups[] = {
 804	"gpio0", "gpio1", "gpio2", "gpio3",
 805};
 806static const char * const gpio_groups[] = {
 807	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
 808	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
 809	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
 810	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
 811	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
 812	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
 813	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
 814	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
 815	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
 816	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
 817	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
 818	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
 819	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
 820	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
 821	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
 822	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
 823	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
 824	"gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
 825	"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
 826	"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
 827	"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
 828	"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
 829	"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
 830	"gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
 831	"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
 832	"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
 833	"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
 834	"gpio177", "gpio178", "gpio179",
 835};
 836static const char * const egpio_groups[] = {
 837	"gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
 838	"gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
 839	"gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
 840	"gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
 841	"gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
 842	"gpio176", "gpio177", "gpio178", "gpio179",
 843};
 844static const char * const qdss_cti_groups[] = {
 845	"gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92",
 846	"gpio93",
 847};
 848static const char * const qup1_groups[] = {
 849	"gpio4", "gpio5", "gpio6", "gpio7",
 850};
 851static const char * const ibi_i3c_groups[] = {
 852	"gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40",
 853	"gpio41",
 854};
 855static const char * const qup_l4_groups[] = {
 856	"gpio6", "gpio14", "gpio46", "gpio123",
 857};
 858static const char * const qup_l5_groups[] = {
 859	"gpio7", "gpio15", "gpio47", "gpio124",
 860};
 861static const char * const qup4_groups[] = {
 862	"gpio8", "gpio9", "gpio10", "gpio11",
 863};
 864static const char * const qup5_groups[] = {
 865	"gpio12", "gpio13", "gpio14", "gpio15",
 866};
 867static const char * const qup6_groups[] = {
 868	"gpio16", "gpio17", "gpio18", "gpio19",
 869};
 870static const char * const qup7_groups[] = {
 871	"gpio20", "gpio21", "gpio22", "gpio23",
 872};
 873static const char * const qup8_groups[] = {
 874	"gpio24", "gpio25", "gpio26", "gpio27",
 875};
 876static const char * const qup0_groups[] = {
 877	"gpio28", "gpio29", "gpio30", "gpio31",
 878};
 879static const char * const qup12_groups[] = {
 880	"gpio32", "gpio33", "gpio34", "gpio35",
 881};
 882static const char * const qup13_groups[] = {
 883	"gpio36", "gpio37", "gpio38", "gpio39",
 884};
 885static const char * const qup14_groups[] = {
 886	"gpio40", "gpio41", "gpio42", "gpio43",
 887};
 888static const char * const ddr_pxi3_groups[] = {
 889	"gpio40", "gpio43",
 890};
 891static const char * const ddr_pxi1_groups[] = {
 892	"gpio41", "gpio42",
 893};
 894static const char * const vsense_trigger_groups[] = {
 895	"gpio42",
 896};
 897static const char * const qup15_groups[] = {
 898	"gpio44", "gpio45", "gpio46", "gpio47",
 899};
 900static const char * const dbg_out_groups[] = {
 901	"gpio44",
 902};
 903static const char * const qup16_groups[] = {
 904	"gpio48", "gpio49", "gpio50", "gpio51",
 905};
 906static const char * const qup17_groups[] = {
 907	"gpio52", "gpio53", "gpio54", "gpio55",
 908};
 909static const char * const ddr_pxi0_groups[] = {
 910	"gpio52", "gpio53",
 911};
 912static const char * const jitter_bist_groups[] = {
 913	"gpio54",
 914};
 915static const char * const pll_bist_groups[] = {
 916	"gpio55",
 917};
 918static const char * const ddr_pxi2_groups[] = {
 919	"gpio55", "gpio56",
 920};
 921static const char * const qup18_groups[] = {
 922	"gpio56", "gpio57", "gpio58", "gpio59",
 923};
 924static const char * const qup11_groups[] = {
 925	"gpio60", "gpio61", "gpio62", "gpio63",
 926};
 927static const char * const usb2phy_ac_groups[] = {
 928	"gpio64", "gpio90",
 929};
 930static const char * const qup_l6_groups[] = {
 931	"gpio64", "gpio77", "gpio92", "gpio93",
 932};
 933static const char * const usb_phy_groups[] = {
 934	"gpio65",
 935};
 936static const char * const pll_clk_groups[] = {
 937	"gpio65",
 938};
 939static const char * const mdp_vsync_groups[] = {
 940	"gpio66", "gpio67", "gpio68", "gpio122", "gpio124",
 941};
 942static const char * const dp_lcd_groups[] = {
 943	"gpio67",
 944};
 945static const char * const dp_hot_groups[] = {
 946	"gpio68",
 947};
 948static const char * const qspi_cs_groups[] = {
 949	"gpio69", "gpio75",
 950};
 951static const char * const tsif0_clk_groups[] = {
 952	"gpio69",
 953};
 954static const char * const qspi0_groups[] = {
 955	"gpio70",
 956};
 957static const char * const tsif0_en_groups[] = {
 958	"gpio70",
 959};
 960static const char * const mdp_vsync0_groups[] = {
 961	"gpio70",
 962};
 963static const char * const mdp_vsync1_groups[] = {
 964	"gpio70",
 965};
 966static const char * const mdp_vsync2_groups[] = {
 967	"gpio70",
 968};
 969static const char * const mdp_vsync3_groups[] = {
 970	"gpio70",
 971};
 972static const char * const qspi1_groups[] = {
 973	"gpio71",
 974};
 975static const char * const tsif0_data_groups[] = {
 976	"gpio71",
 977};
 978static const char * const sdc4_cmd_groups[] = {
 979	"gpio71",
 980};
 981static const char * const qspi2_groups[] = {
 982	"gpio72",
 983};
 984static const char * const tsif0_sync_groups[] = {
 985	"gpio72",
 986};
 987static const char * const sdc43_groups[] = {
 988	"gpio72",
 989};
 990static const char * const qspi_clk_groups[] = {
 991	"gpio73",
 992};
 993static const char * const tsif1_clk_groups[] = {
 994	"gpio73",
 995};
 996static const char * const sdc4_clk_groups[] = {
 997	"gpio73",
 998};
 999static const char * const qspi3_groups[] = {
1000	"gpio74",
1001};
1002static const char * const tsif1_en_groups[] = {
1003	"gpio74",
1004};
1005static const char * const sdc42_groups[] = {
1006	"gpio74",
1007};
1008
1009static const struct pinfunction sm8250_functions[] = {
1010	MSM_PIN_FUNCTION(aoss_cti),
1011	MSM_PIN_FUNCTION(atest),
1012	MSM_PIN_FUNCTION(audio_ref),
1013	MSM_PIN_FUNCTION(cam_mclk),
1014	MSM_PIN_FUNCTION(cci_async),
1015	MSM_PIN_FUNCTION(cci_i2c),
1016	MSM_PIN_FUNCTION(cci_timer0),
1017	MSM_PIN_FUNCTION(cci_timer1),
1018	MSM_PIN_FUNCTION(cci_timer2),
1019	MSM_PIN_FUNCTION(cci_timer3),
1020	MSM_PIN_FUNCTION(cci_timer4),
1021	MSM_PIN_FUNCTION(cri_trng),
1022	MSM_PIN_FUNCTION(cri_trng0),
1023	MSM_PIN_FUNCTION(cri_trng1),
1024	MSM_PIN_FUNCTION(dbg_out),
1025	MSM_PIN_FUNCTION(ddr_bist),
1026	MSM_PIN_FUNCTION(ddr_pxi0),
1027	MSM_PIN_FUNCTION(ddr_pxi1),
1028	MSM_PIN_FUNCTION(ddr_pxi2),
1029	MSM_PIN_FUNCTION(ddr_pxi3),
1030	MSM_PIN_FUNCTION(dp_hot),
1031	MSM_PIN_FUNCTION(dp_lcd),
1032	MSM_PIN_FUNCTION(egpio),
1033	MSM_PIN_FUNCTION(gcc_gp1),
1034	MSM_PIN_FUNCTION(gcc_gp2),
1035	MSM_PIN_FUNCTION(gcc_gp3),
1036	MSM_GPIO_PIN_FUNCTION(gpio),
1037	MSM_PIN_FUNCTION(ibi_i3c),
1038	MSM_PIN_FUNCTION(jitter_bist),
1039	MSM_PIN_FUNCTION(lpass_slimbus),
1040	MSM_PIN_FUNCTION(mdp_vsync),
1041	MSM_PIN_FUNCTION(mdp_vsync0),
1042	MSM_PIN_FUNCTION(mdp_vsync1),
1043	MSM_PIN_FUNCTION(mdp_vsync2),
1044	MSM_PIN_FUNCTION(mdp_vsync3),
1045	MSM_PIN_FUNCTION(mi2s0_data0),
1046	MSM_PIN_FUNCTION(mi2s0_data1),
1047	MSM_PIN_FUNCTION(mi2s0_sck),
1048	MSM_PIN_FUNCTION(mi2s0_ws),
1049	MSM_PIN_FUNCTION(mi2s1_data0),
1050	MSM_PIN_FUNCTION(mi2s1_data1),
1051	MSM_PIN_FUNCTION(mi2s1_sck),
1052	MSM_PIN_FUNCTION(mi2s1_ws),
1053	MSM_PIN_FUNCTION(mi2s2_data0),
1054	MSM_PIN_FUNCTION(mi2s2_data1),
1055	MSM_PIN_FUNCTION(mi2s2_sck),
1056	MSM_PIN_FUNCTION(mi2s2_ws),
1057	MSM_PIN_FUNCTION(pci_e0),
1058	MSM_PIN_FUNCTION(pci_e1),
1059	MSM_PIN_FUNCTION(pci_e2),
1060	MSM_PIN_FUNCTION(phase_flag),
1061	MSM_PIN_FUNCTION(pll_bist),
1062	MSM_PIN_FUNCTION(pll_bypassnl),
1063	MSM_PIN_FUNCTION(pll_clk),
1064	MSM_PIN_FUNCTION(pll_reset),
1065	MSM_PIN_FUNCTION(pri_mi2s),
1066	MSM_PIN_FUNCTION(prng_rosc),
1067	MSM_PIN_FUNCTION(qdss_cti),
1068	MSM_PIN_FUNCTION(qdss_gpio),
1069	MSM_PIN_FUNCTION(qspi0),
1070	MSM_PIN_FUNCTION(qspi1),
1071	MSM_PIN_FUNCTION(qspi2),
1072	MSM_PIN_FUNCTION(qspi3),
1073	MSM_PIN_FUNCTION(qspi_clk),
1074	MSM_PIN_FUNCTION(qspi_cs),
1075	MSM_PIN_FUNCTION(qup0),
1076	MSM_PIN_FUNCTION(qup1),
1077	MSM_PIN_FUNCTION(qup10),
1078	MSM_PIN_FUNCTION(qup11),
1079	MSM_PIN_FUNCTION(qup12),
1080	MSM_PIN_FUNCTION(qup13),
1081	MSM_PIN_FUNCTION(qup14),
1082	MSM_PIN_FUNCTION(qup15),
1083	MSM_PIN_FUNCTION(qup16),
1084	MSM_PIN_FUNCTION(qup17),
1085	MSM_PIN_FUNCTION(qup18),
1086	MSM_PIN_FUNCTION(qup19),
1087	MSM_PIN_FUNCTION(qup2),
1088	MSM_PIN_FUNCTION(qup3),
1089	MSM_PIN_FUNCTION(qup4),
1090	MSM_PIN_FUNCTION(qup5),
1091	MSM_PIN_FUNCTION(qup6),
1092	MSM_PIN_FUNCTION(qup7),
1093	MSM_PIN_FUNCTION(qup8),
1094	MSM_PIN_FUNCTION(qup9),
1095	MSM_PIN_FUNCTION(qup_l4),
1096	MSM_PIN_FUNCTION(qup_l5),
1097	MSM_PIN_FUNCTION(qup_l6),
1098	MSM_PIN_FUNCTION(sd_write),
1099	MSM_PIN_FUNCTION(sdc40),
1100	MSM_PIN_FUNCTION(sdc41),
1101	MSM_PIN_FUNCTION(sdc42),
1102	MSM_PIN_FUNCTION(sdc43),
1103	MSM_PIN_FUNCTION(sdc4_clk),
1104	MSM_PIN_FUNCTION(sdc4_cmd),
1105	MSM_PIN_FUNCTION(sec_mi2s),
1106	MSM_PIN_FUNCTION(sp_cmu),
1107	MSM_PIN_FUNCTION(tgu_ch0),
1108	MSM_PIN_FUNCTION(tgu_ch1),
1109	MSM_PIN_FUNCTION(tgu_ch2),
1110	MSM_PIN_FUNCTION(tgu_ch3),
1111	MSM_PIN_FUNCTION(tsense_pwm1),
1112	MSM_PIN_FUNCTION(tsense_pwm2),
1113	MSM_PIN_FUNCTION(tsif0_clk),
1114	MSM_PIN_FUNCTION(tsif0_data),
1115	MSM_PIN_FUNCTION(tsif0_en),
1116	MSM_PIN_FUNCTION(tsif0_error),
1117	MSM_PIN_FUNCTION(tsif0_sync),
1118	MSM_PIN_FUNCTION(tsif1_clk),
1119	MSM_PIN_FUNCTION(tsif1_data),
1120	MSM_PIN_FUNCTION(tsif1_en),
1121	MSM_PIN_FUNCTION(tsif1_error),
1122	MSM_PIN_FUNCTION(tsif1_sync),
1123	MSM_PIN_FUNCTION(usb2phy_ac),
1124	MSM_PIN_FUNCTION(usb_phy),
1125	MSM_PIN_FUNCTION(vsense_trigger),
1126};
1127
1128/* Every pin is maintained as a single group, and missing or non-existing pin
1129 * would be maintained as dummy group to synchronize pin group index with
1130 * pin descriptor registered with pinctrl core.
1131 * Clients would not be able to request these dummy pin groups.
1132 */
1133static const struct msm_pingroup sm8250_groups[] = {
1134	[0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _),
1135	[1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _),
1136	[2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _),
1137	[3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _),
1138	[4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1139	[5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1140	[6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _),
1141	[7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _),
1142	[8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _),
1143	[9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _),
1144	[10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _),
1145	[11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _),
1146	[12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _),
1147	[13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _),
1148	[14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _),
1149	[15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _),
1150	[16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _),
1151	[17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _),
1152	[18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _),
1153	[19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _),
1154	[20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _),
1155	[21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _),
1156	[22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _),
1157	[23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _),
1158	[24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1159	[25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1160	[26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1161	[27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1162	[28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1163	[29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1164	[30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _),
1165	[31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _),
1166	[32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _),
1167	[33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1168	[34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1169	[35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1170	[36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1171	[37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1172	[38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _),
1173	[39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _),
1174	[40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _),
1175	[41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _),
1176	[42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _),
1177	[43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _),
1178	[44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _),
1179	[45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _),
1180	[46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _),
1181	[47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _),
1182	[48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1183	[49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1184	[50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1185	[51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1186	[52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1187	[53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1188	[54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _),
1189	[55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _),
1190	[56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _),
1191	[57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _),
1192	[58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _),
1193	[59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _),
1194	[60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _),
1195	[61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _),
1196	[62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _),
1197	[63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _),
1198	[64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _),
1199	[65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _),
1200	[66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
1201	[67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
1202	[68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _),
1203	[69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _),
1204	[70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _),
1205	[71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _),
1206	[72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _),
1207	[73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _),
1208	[74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _),
1209	[75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _),
1210	[76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _),
1211	[77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _),
1212	[78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _),
1213	[79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1214	[80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1215	[81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1216	[82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1217	[83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1218	[84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1219	[85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _),
1220	[86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _),
1221	[87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _),
1222	[88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _),
1223	[89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _),
1224	[90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _),
1225	[91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _),
1226	[92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1227	[93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1228	[94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1229	[95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1230	[96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _),
1231	[97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _),
1232	[98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1233	[99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1234	[100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1235	[101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1236	[102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1237	[103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1238	[104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1239	[105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1240	[106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _),
1241	[107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1242	[108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1243	[109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _),
1244	[110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _),
1245	[111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _),
1246	[112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _),
1247	[113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _),
1248	[114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _),
1249	[115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1250	[116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1251	[117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1252	[118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1253	[119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1254	[120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1255	[121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _),
1256	[122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _),
1257	[123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1258	[124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _),
1259	[125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _),
1260	[126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _),
1261	[127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _),
1262	[128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _),
1263	[129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _),
1264	[130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _),
1265	[131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _),
1266	[132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _),
1267	[133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _),
1268	[134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _),
1269	[135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _),
1270	[136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1271	[137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _),
1272	[138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _),
1273	[139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _),
1274	[140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _),
1275	[141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _),
1276	[142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _),
1277	[143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _),
1278	[144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _),
1279	[145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _),
1280	[146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, egpio),
1281	[147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, egpio),
1282	[148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, egpio),
1283	[149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, egpio),
1284	[150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, egpio),
1285	[151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, egpio),
1286	[152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, egpio),
1287	[153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, egpio),
1288	[154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, egpio),
1289	[155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, egpio),
1290	[156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, egpio),
1291	[157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, egpio),
1292	[158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, egpio),
1293	[159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, egpio),
1294	[160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, egpio),
1295	[161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, egpio),
1296	[162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, egpio),
1297	[163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, egpio),
1298	[164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1299	[165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1300	[166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1301	[167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1302	[168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1303	[169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1304	[170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1305	[171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1306	[172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1307	[173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1308	[174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1309	[175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1310	[176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1311	[177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio),
1312	[178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, egpio),
1313	[179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, egpio),
1314	[180] = UFS_RESET(ufs_reset, 0xb8000),
1315	[181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
1316	[182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
1317	[183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
1318};
1319
1320static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = {
1321	{ 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 },
1322	{ 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 },
1323	{ 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 73 },
1324	{ 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 },
1325	{ 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 },
1326	{ 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 },
1327	{ 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 },
1328	{ 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 },
1329	{ 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 },
1330	{ 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 },
1331	{ 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 },
1332	{ 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 },
1333	{ 142, 60 }, { 143, 61 }
1334};
1335
1336static const struct msm_pinctrl_soc_data sm8250_pinctrl = {
1337	.pins = sm8250_pins,
1338	.npins = ARRAY_SIZE(sm8250_pins),
1339	.functions = sm8250_functions,
1340	.nfunctions = ARRAY_SIZE(sm8250_functions),
1341	.groups = sm8250_groups,
1342	.ngroups = ARRAY_SIZE(sm8250_groups),
1343	.ngpios = 181,
1344	.tiles = sm8250_tiles,
1345	.ntiles = ARRAY_SIZE(sm8250_tiles),
1346	.wakeirq_map = sm8250_pdc_map,
1347	.nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map),
1348	.egpio_func = 9,
1349};
1350
1351static int sm8250_pinctrl_probe(struct platform_device *pdev)
1352{
1353	return msm_pinctrl_probe(pdev, &sm8250_pinctrl);
1354}
1355
1356static const struct of_device_id sm8250_pinctrl_of_match[] = {
1357	{ .compatible = "qcom,sm8250-pinctrl", },
1358	{ },
1359};
1360
1361static struct platform_driver sm8250_pinctrl_driver = {
1362	.driver = {
1363		.name = "sm8250-pinctrl",
1364		.of_match_table = sm8250_pinctrl_of_match,
1365	},
1366	.probe = sm8250_pinctrl_probe,
1367};
1368
1369static int __init sm8250_pinctrl_init(void)
1370{
1371	return platform_driver_register(&sm8250_pinctrl_driver);
1372}
1373arch_initcall(sm8250_pinctrl_init);
1374
1375static void __exit sm8250_pinctrl_exit(void)
1376{
1377	platform_driver_unregister(&sm8250_pinctrl_driver);
1378}
1379module_exit(sm8250_pinctrl_exit);
1380
1381MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");
1382MODULE_LICENSE("GPL v2");
1383MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);