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pinctrl-qcs615.c
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linux-6.19.14/drivers/pinctrl/qcom/pinctrl-qcs615.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <linux/module.h> 7#include <linux/of.h> 8#include <linux/platform_device.h> 9 10#include "pinctrl-msm.h" 11 12enum { 13 SOUTH, 14 EAST, 15 WEST 16}; 17 18static const char * const qcs615_tiles[] = { 19 [SOUTH] = "south", 20 [EAST] = "east", 21 [WEST] = "west" 22}; 23 24#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 25 { \ 26 .grp = PINCTRL_PINGROUP("gpio" #id, \ 27 gpio##id##_pins, \ 28 ARRAY_SIZE(gpio##id##_pins)), \ 29 .funcs = (int[]){ \ 30 msm_mux_gpio, /* gpio mode */ \ 31 msm_mux_##f1, \ 32 msm_mux_##f2, \ 33 msm_mux_##f3, \ 34 msm_mux_##f4, \ 35 msm_mux_##f5, \ 36 msm_mux_##f6, \ 37 msm_mux_##f7, \ 38 msm_mux_##f8, \ 39 msm_mux_##f9 \ 40 }, \ 41 .nfuncs = 10, \ 42 .ctl_reg = 0x1000 * id, \ 43 .io_reg = 0x1000 * id + 0x4, \ 44 .intr_cfg_reg = 0x1000 * id + 0x8, \ 45 .intr_status_reg = 0x1000 * id + 0xc, \ 46 .intr_target_reg = 0x1000 * id + 0x8, \ 47 .tile = _tile, \ 48 .mux_bit = 2, \ 49 .pull_bit = 0, \ 50 .drv_bit = 6, \ 51 .oe_bit = 9, \ 52 .in_bit = 0, \ 53 .out_bit = 1, \ 54 .intr_enable_bit = 0, \ 55 .intr_status_bit = 0, \ 56 .intr_target_bit = 5, \ 57 .intr_target_kpss_val = 3, \ 58 .intr_raw_status_bit = 4, \ 59 .intr_polarity_bit = 1, \ 60 .intr_detection_bit = 2, \ 61 .intr_detection_width = 2, \ 62 } 63 64#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ 65 { \ 66 .grp = PINCTRL_PINGROUP(#pg_name, \ 67 pg_name##_pins, \ 68 ARRAY_SIZE(pg_name##_pins)), \ 69 .ctl_reg = ctl, \ 70 .io_reg = 0, \ 71 .intr_cfg_reg = 0, \ 72 .intr_status_reg = 0, \ 73 .intr_target_reg = 0, \ 74 .tile = _tile, \ 75 .mux_bit = -1, \ 76 .pull_bit = pull, \ 77 .drv_bit = drv, \ 78 .oe_bit = -1, \ 79 .in_bit = -1, \ 80 .out_bit = -1, \ 81 .intr_enable_bit = -1, \ 82 .intr_status_bit = -1, \ 83 .intr_target_bit = -1, \ 84 .intr_raw_status_bit = -1, \ 85 .intr_polarity_bit = -1, \ 86 .intr_detection_bit = -1, \ 87 .intr_detection_width = -1, \ 88 } 89 90#define UFS_RESET(pg_name, offset) \ 91 { \ 92 .grp = PINCTRL_PINGROUP(#pg_name, \ 93 pg_name##_pins, \ 94 ARRAY_SIZE(pg_name##_pins)), \ 95 .ctl_reg = offset, \ 96 .io_reg = offset + 0x4, \ 97 .intr_cfg_reg = 0, \ 98 .intr_status_reg = 0, \ 99 .intr_target_reg = 0, \ 100 .tile = WEST, \ 101 .mux_bit = -1, \ 102 .pull_bit = 3, \ 103 .drv_bit = 0, \ 104 .oe_bit = -1, \ 105 .in_bit = -1, \ 106 .out_bit = 0, \ 107 .intr_enable_bit = -1, \ 108 .intr_status_bit = -1, \ 109 .intr_target_bit = -1, \ 110 .intr_raw_status_bit = -1, \ 111 .intr_polarity_bit = -1, \ 112 .intr_detection_bit = -1, \ 113 .intr_detection_width = -1, \ 114 } 115 116static const struct pinctrl_pin_desc qcs615_pins[] = { 117 PINCTRL_PIN(0, "GPIO_0"), 118 PINCTRL_PIN(1, "GPIO_1"), 119 PINCTRL_PIN(2, "GPIO_2"), 120 PINCTRL_PIN(3, "GPIO_3"), 121 PINCTRL_PIN(4, "GPIO_4"), 122 PINCTRL_PIN(5, "GPIO_5"), 123 PINCTRL_PIN(6, "GPIO_6"), 124 PINCTRL_PIN(7, "GPIO_7"), 125 PINCTRL_PIN(8, "GPIO_8"), 126 PINCTRL_PIN(9, "GPIO_9"), 127 PINCTRL_PIN(10, "GPIO_10"), 128 PINCTRL_PIN(11, "GPIO_11"), 129 PINCTRL_PIN(12, "GPIO_12"), 130 PINCTRL_PIN(13, "GPIO_13"), 131 PINCTRL_PIN(14, "GPIO_14"), 132 PINCTRL_PIN(15, "GPIO_15"), 133 PINCTRL_PIN(16, "GPIO_16"), 134 PINCTRL_PIN(17, "GPIO_17"), 135 PINCTRL_PIN(18, "GPIO_18"), 136 PINCTRL_PIN(19, "GPIO_19"), 137 PINCTRL_PIN(20, "GPIO_20"), 138 PINCTRL_PIN(21, "GPIO_21"), 139 PINCTRL_PIN(22, "GPIO_22"), 140 PINCTRL_PIN(23, "GPIO_23"), 141 PINCTRL_PIN(24, "GPIO_24"), 142 PINCTRL_PIN(25, "GPIO_25"), 143 PINCTRL_PIN(26, "GPIO_26"), 144 PINCTRL_PIN(27, "GPIO_27"), 145 PINCTRL_PIN(28, "GPIO_28"), 146 PINCTRL_PIN(29, "GPIO_29"), 147 PINCTRL_PIN(30, "GPIO_30"), 148 PINCTRL_PIN(31, "GPIO_31"), 149 PINCTRL_PIN(32, "GPIO_32"), 150 PINCTRL_PIN(33, "GPIO_33"), 151 PINCTRL_PIN(34, "GPIO_34"), 152 PINCTRL_PIN(35, "GPIO_35"), 153 PINCTRL_PIN(36, "GPIO_36"), 154 PINCTRL_PIN(37, "GPIO_37"), 155 PINCTRL_PIN(38, "GPIO_38"), 156 PINCTRL_PIN(39, "GPIO_39"), 157 PINCTRL_PIN(40, "GPIO_40"), 158 PINCTRL_PIN(41, "GPIO_41"), 159 PINCTRL_PIN(42, "GPIO_42"), 160 PINCTRL_PIN(43, "GPIO_43"), 161 PINCTRL_PIN(44, "GPIO_44"), 162 PINCTRL_PIN(45, "GPIO_45"), 163 PINCTRL_PIN(46, "GPIO_46"), 164 PINCTRL_PIN(47, "GPIO_47"), 165 PINCTRL_PIN(48, "GPIO_48"), 166 PINCTRL_PIN(49, "GPIO_49"), 167 PINCTRL_PIN(50, "GPIO_50"), 168 PINCTRL_PIN(51, "GPIO_51"), 169 PINCTRL_PIN(52, "GPIO_52"), 170 PINCTRL_PIN(53, "GPIO_53"), 171 PINCTRL_PIN(54, "GPIO_54"), 172 PINCTRL_PIN(55, "GPIO_55"), 173 PINCTRL_PIN(56, "GPIO_56"), 174 PINCTRL_PIN(57, "GPIO_57"), 175 PINCTRL_PIN(58, "GPIO_58"), 176 PINCTRL_PIN(59, "GPIO_59"), 177 PINCTRL_PIN(60, "GPIO_60"), 178 PINCTRL_PIN(61, "GPIO_61"), 179 PINCTRL_PIN(62, "GPIO_62"), 180 PINCTRL_PIN(63, "GPIO_63"), 181 PINCTRL_PIN(64, "GPIO_64"), 182 PINCTRL_PIN(65, "GPIO_65"), 183 PINCTRL_PIN(66, "GPIO_66"), 184 PINCTRL_PIN(67, "GPIO_67"), 185 PINCTRL_PIN(68, "GPIO_68"), 186 PINCTRL_PIN(69, "GPIO_69"), 187 PINCTRL_PIN(70, "GPIO_70"), 188 PINCTRL_PIN(71, "GPIO_71"), 189 PINCTRL_PIN(72, "GPIO_72"), 190 PINCTRL_PIN(73, "GPIO_73"), 191 PINCTRL_PIN(74, "GPIO_74"), 192 PINCTRL_PIN(75, "GPIO_75"), 193 PINCTRL_PIN(76, "GPIO_76"), 194 PINCTRL_PIN(77, "GPIO_77"), 195 PINCTRL_PIN(78, "GPIO_78"), 196 PINCTRL_PIN(79, "GPIO_79"), 197 PINCTRL_PIN(80, "GPIO_80"), 198 PINCTRL_PIN(81, "GPIO_81"), 199 PINCTRL_PIN(82, "GPIO_82"), 200 PINCTRL_PIN(83, "GPIO_83"), 201 PINCTRL_PIN(84, "GPIO_84"), 202 PINCTRL_PIN(85, "GPIO_85"), 203 PINCTRL_PIN(86, "GPIO_86"), 204 PINCTRL_PIN(87, "GPIO_87"), 205 PINCTRL_PIN(88, "GPIO_88"), 206 PINCTRL_PIN(89, "GPIO_89"), 207 PINCTRL_PIN(90, "GPIO_90"), 208 PINCTRL_PIN(91, "GPIO_91"), 209 PINCTRL_PIN(92, "GPIO_92"), 210 PINCTRL_PIN(93, "GPIO_93"), 211 PINCTRL_PIN(94, "GPIO_94"), 212 PINCTRL_PIN(95, "GPIO_95"), 213 PINCTRL_PIN(96, "GPIO_96"), 214 PINCTRL_PIN(97, "GPIO_97"), 215 PINCTRL_PIN(98, "GPIO_98"), 216 PINCTRL_PIN(99, "GPIO_99"), 217 PINCTRL_PIN(100, "GPIO_100"), 218 PINCTRL_PIN(101, "GPIO_101"), 219 PINCTRL_PIN(102, "GPIO_102"), 220 PINCTRL_PIN(103, "GPIO_103"), 221 PINCTRL_PIN(104, "GPIO_104"), 222 PINCTRL_PIN(105, "GPIO_105"), 223 PINCTRL_PIN(106, "GPIO_106"), 224 PINCTRL_PIN(107, "GPIO_107"), 225 PINCTRL_PIN(108, "GPIO_108"), 226 PINCTRL_PIN(109, "GPIO_109"), 227 PINCTRL_PIN(110, "GPIO_110"), 228 PINCTRL_PIN(111, "GPIO_111"), 229 PINCTRL_PIN(112, "GPIO_112"), 230 PINCTRL_PIN(113, "GPIO_113"), 231 PINCTRL_PIN(114, "GPIO_114"), 232 PINCTRL_PIN(115, "GPIO_115"), 233 PINCTRL_PIN(116, "GPIO_116"), 234 PINCTRL_PIN(117, "GPIO_117"), 235 PINCTRL_PIN(118, "GPIO_118"), 236 PINCTRL_PIN(119, "GPIO_119"), 237 PINCTRL_PIN(120, "GPIO_120"), 238 PINCTRL_PIN(121, "GPIO_121"), 239 PINCTRL_PIN(122, "GPIO_122"), 240 PINCTRL_PIN(123, "UFS_RESET"), 241 PINCTRL_PIN(124, "SDC1_RCLK"), 242 PINCTRL_PIN(125, "SDC1_CLK"), 243 PINCTRL_PIN(126, "SDC1_CMD"), 244 PINCTRL_PIN(127, "SDC1_DATA"), 245 PINCTRL_PIN(128, "SDC2_CLK"), 246 PINCTRL_PIN(129, "SDC2_CMD"), 247 PINCTRL_PIN(130, "SDC2_DATA"), 248}; 249 250#define DECLARE_MSM_GPIO_PINS(pin) \ 251 static const unsigned int gpio##pin##_pins[] = { pin } 252DECLARE_MSM_GPIO_PINS(0); 253DECLARE_MSM_GPIO_PINS(1); 254DECLARE_MSM_GPIO_PINS(2); 255DECLARE_MSM_GPIO_PINS(3); 256DECLARE_MSM_GPIO_PINS(4); 257DECLARE_MSM_GPIO_PINS(5); 258DECLARE_MSM_GPIO_PINS(6); 259DECLARE_MSM_GPIO_PINS(7); 260DECLARE_MSM_GPIO_PINS(8); 261DECLARE_MSM_GPIO_PINS(9); 262DECLARE_MSM_GPIO_PINS(10); 263DECLARE_MSM_GPIO_PINS(11); 264DECLARE_MSM_GPIO_PINS(12); 265DECLARE_MSM_GPIO_PINS(13); 266DECLARE_MSM_GPIO_PINS(14); 267DECLARE_MSM_GPIO_PINS(15); 268DECLARE_MSM_GPIO_PINS(16); 269DECLARE_MSM_GPIO_PINS(17); 270DECLARE_MSM_GPIO_PINS(18); 271DECLARE_MSM_GPIO_PINS(19); 272DECLARE_MSM_GPIO_PINS(20); 273DECLARE_MSM_GPIO_PINS(21); 274DECLARE_MSM_GPIO_PINS(22); 275DECLARE_MSM_GPIO_PINS(23); 276DECLARE_MSM_GPIO_PINS(24); 277DECLARE_MSM_GPIO_PINS(25); 278DECLARE_MSM_GPIO_PINS(26); 279DECLARE_MSM_GPIO_PINS(27); 280DECLARE_MSM_GPIO_PINS(28); 281DECLARE_MSM_GPIO_PINS(29); 282DECLARE_MSM_GPIO_PINS(30); 283DECLARE_MSM_GPIO_PINS(31); 284DECLARE_MSM_GPIO_PINS(32); 285DECLARE_MSM_GPIO_PINS(33); 286DECLARE_MSM_GPIO_PINS(34); 287DECLARE_MSM_GPIO_PINS(35); 288DECLARE_MSM_GPIO_PINS(36); 289DECLARE_MSM_GPIO_PINS(37); 290DECLARE_MSM_GPIO_PINS(38); 291DECLARE_MSM_GPIO_PINS(39); 292DECLARE_MSM_GPIO_PINS(40); 293DECLARE_MSM_GPIO_PINS(41); 294DECLARE_MSM_GPIO_PINS(42); 295DECLARE_MSM_GPIO_PINS(43); 296DECLARE_MSM_GPIO_PINS(44); 297DECLARE_MSM_GPIO_PINS(45); 298DECLARE_MSM_GPIO_PINS(46); 299DECLARE_MSM_GPIO_PINS(47); 300DECLARE_MSM_GPIO_PINS(48); 301DECLARE_MSM_GPIO_PINS(49); 302DECLARE_MSM_GPIO_PINS(50); 303DECLARE_MSM_GPIO_PINS(51); 304DECLARE_MSM_GPIO_PINS(52); 305DECLARE_MSM_GPIO_PINS(53); 306DECLARE_MSM_GPIO_PINS(54); 307DECLARE_MSM_GPIO_PINS(55); 308DECLARE_MSM_GPIO_PINS(56); 309DECLARE_MSM_GPIO_PINS(57); 310DECLARE_MSM_GPIO_PINS(58); 311DECLARE_MSM_GPIO_PINS(59); 312DECLARE_MSM_GPIO_PINS(60); 313DECLARE_MSM_GPIO_PINS(61); 314DECLARE_MSM_GPIO_PINS(62); 315DECLARE_MSM_GPIO_PINS(63); 316DECLARE_MSM_GPIO_PINS(64); 317DECLARE_MSM_GPIO_PINS(65); 318DECLARE_MSM_GPIO_PINS(66); 319DECLARE_MSM_GPIO_PINS(67); 320DECLARE_MSM_GPIO_PINS(68); 321DECLARE_MSM_GPIO_PINS(69); 322DECLARE_MSM_GPIO_PINS(70); 323DECLARE_MSM_GPIO_PINS(71); 324DECLARE_MSM_GPIO_PINS(72); 325DECLARE_MSM_GPIO_PINS(73); 326DECLARE_MSM_GPIO_PINS(74); 327DECLARE_MSM_GPIO_PINS(75); 328DECLARE_MSM_GPIO_PINS(76); 329DECLARE_MSM_GPIO_PINS(77); 330DECLARE_MSM_GPIO_PINS(78); 331DECLARE_MSM_GPIO_PINS(79); 332DECLARE_MSM_GPIO_PINS(80); 333DECLARE_MSM_GPIO_PINS(81); 334DECLARE_MSM_GPIO_PINS(82); 335DECLARE_MSM_GPIO_PINS(83); 336DECLARE_MSM_GPIO_PINS(84); 337DECLARE_MSM_GPIO_PINS(85); 338DECLARE_MSM_GPIO_PINS(86); 339DECLARE_MSM_GPIO_PINS(87); 340DECLARE_MSM_GPIO_PINS(88); 341DECLARE_MSM_GPIO_PINS(89); 342DECLARE_MSM_GPIO_PINS(90); 343DECLARE_MSM_GPIO_PINS(91); 344DECLARE_MSM_GPIO_PINS(92); 345DECLARE_MSM_GPIO_PINS(93); 346DECLARE_MSM_GPIO_PINS(94); 347DECLARE_MSM_GPIO_PINS(95); 348DECLARE_MSM_GPIO_PINS(96); 349DECLARE_MSM_GPIO_PINS(97); 350DECLARE_MSM_GPIO_PINS(98); 351DECLARE_MSM_GPIO_PINS(99); 352DECLARE_MSM_GPIO_PINS(100); 353DECLARE_MSM_GPIO_PINS(101); 354DECLARE_MSM_GPIO_PINS(102); 355DECLARE_MSM_GPIO_PINS(103); 356DECLARE_MSM_GPIO_PINS(104); 357DECLARE_MSM_GPIO_PINS(105); 358DECLARE_MSM_GPIO_PINS(106); 359DECLARE_MSM_GPIO_PINS(107); 360DECLARE_MSM_GPIO_PINS(108); 361DECLARE_MSM_GPIO_PINS(109); 362DECLARE_MSM_GPIO_PINS(110); 363DECLARE_MSM_GPIO_PINS(111); 364DECLARE_MSM_GPIO_PINS(112); 365DECLARE_MSM_GPIO_PINS(113); 366DECLARE_MSM_GPIO_PINS(114); 367DECLARE_MSM_GPIO_PINS(115); 368DECLARE_MSM_GPIO_PINS(116); 369DECLARE_MSM_GPIO_PINS(117); 370DECLARE_MSM_GPIO_PINS(118); 371DECLARE_MSM_GPIO_PINS(119); 372DECLARE_MSM_GPIO_PINS(120); 373DECLARE_MSM_GPIO_PINS(121); 374DECLARE_MSM_GPIO_PINS(122); 375 376static const unsigned int ufs_reset_pins[] = { 123 }; 377static const unsigned int sdc1_rclk_pins[] = { 124 }; 378static const unsigned int sdc1_clk_pins[] = { 125 }; 379static const unsigned int sdc1_cmd_pins[] = { 126 }; 380static const unsigned int sdc1_data_pins[] = { 127 }; 381static const unsigned int sdc2_clk_pins[] = { 128 }; 382static const unsigned int sdc2_cmd_pins[] = { 129 }; 383static const unsigned int sdc2_data_pins[] = { 130 }; 384 385enum qcs615_functions { 386 msm_mux_gpio, 387 msm_mux_adsp_ext, 388 msm_mux_agera_pll, 389 msm_mux_aoss_cti, 390 msm_mux_atest_char, 391 msm_mux_atest_tsens, 392 msm_mux_atest_usb, 393 msm_mux_cam_mclk, 394 msm_mux_cci_async, 395 msm_mux_cci_i2c, 396 msm_mux_cci_timer, 397 msm_mux_copy_gp, 398 msm_mux_copy_phase, 399 msm_mux_cri_trng, 400 msm_mux_dbg_out_clk, 401 msm_mux_ddr_bist, 402 msm_mux_ddr_pxi, 403 msm_mux_dp_hot, 404 msm_mux_edp_hot, 405 msm_mux_edp_lcd, 406 msm_mux_emac_gcc, 407 msm_mux_emac_phy_intr, 408 msm_mux_forced_usb, 409 msm_mux_gcc_gp, 410 msm_mux_gp_pdm, 411 msm_mux_gps_tx, 412 msm_mux_hs0_mi2s, 413 msm_mux_hs1_mi2s, 414 msm_mux_jitter_bist, 415 msm_mux_ldo_en, 416 msm_mux_ldo_update, 417 msm_mux_m_voc, 418 msm_mux_mclk1, 419 msm_mux_mclk2, 420 msm_mux_mdp_vsync, 421 msm_mux_mdp_vsync0_out, 422 msm_mux_mdp_vsync1_out, 423 msm_mux_mdp_vsync2_out, 424 msm_mux_mdp_vsync3_out, 425 msm_mux_mdp_vsync4_out, 426 msm_mux_mdp_vsync5_out, 427 msm_mux_mi2s_1, 428 msm_mux_mss_lte, 429 msm_mux_nav_pps_in, 430 msm_mux_nav_pps_out, 431 msm_mux_pa_indicator_or, 432 msm_mux_pcie_clk_req, 433 msm_mux_pcie_ep_rst, 434 msm_mux_phase_flag, 435 msm_mux_pll_bist, 436 msm_mux_pll_bypassnl, 437 msm_mux_pll_reset_n, 438 msm_mux_prng_rosc, 439 msm_mux_qdss_cti, 440 msm_mux_qdss_gpio, 441 msm_mux_qlink_enable, 442 msm_mux_qlink_request, 443 msm_mux_qspi, 444 msm_mux_qup0, 445 msm_mux_qup1, 446 msm_mux_rgmii, 447 msm_mux_sd_write_protect, 448 msm_mux_sp_cmu, 449 msm_mux_ter_mi2s, 450 msm_mux_tgu_ch, 451 msm_mux_uim1, 452 msm_mux_uim2, 453 msm_mux_usb0_hs, 454 msm_mux_usb1_hs, 455 msm_mux_usb_phy_ps, 456 msm_mux_vfr_1, 457 msm_mux_vsense_trigger_mirnat, 458 msm_mux_wlan, 459 msm_mux_wsa_clk, 460 msm_mux_wsa_data, 461 msm_mux__, 462}; 463 464static const char *const gpio_groups[] = { 465 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", 466 "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", 467 "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", 468 "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", 469 "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 470 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 471 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", 472 "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", 473 "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", 474 "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", 475 "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", 476 "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", 477 "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 478 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 479 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", 480 "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", 481 "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", 482 "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", 483 "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", 484 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", 485 "gpio120", "gpio121", "gpio122", 486}; 487 488static const char *const adsp_ext_groups[] = { 489 "gpio118", 490}; 491 492static const char *const agera_pll_groups[] = { 493 "gpio28", 494}; 495 496static const char *const aoss_cti_groups[] = { 497 "gpio76", 498}; 499 500static const char *const atest_char_groups[] = { 501 "gpio84", "gpio85", "gpio86", "gpio87", 502 "gpio115", "gpio117", "gpio118", "gpio119", 503 "gpio120", "gpio121", 504}; 505 506static const char *const atest_tsens_groups[] = { 507 "gpio7", "gpio29", 508}; 509 510static const char *const atest_usb_groups[] = { 511 "gpio7", "gpio10", "gpio11", "gpio54", 512 "gpio55", "gpio67", "gpio68", "gpio76", 513 "gpio75", "gpio77", 514}; 515 516static const char *const cam_mclk_groups[] = { 517 "gpio28", "gpio29", "gpio30", "gpio31", 518}; 519 520static const char *const cci_async_groups[] = { 521 "gpio26", "gpio41", "gpio42", 522}; 523 524static const char *const cci_i2c_groups[] = { 525 "gpio32", "gpio33", "gpio34", "gpio35", 526}; 527 528static const char *const cci_timer_groups[] = { 529 "gpio37", "gpio38", "gpio39", "gpio41", 530 "gpio42", 531}; 532 533static const char *const copy_gp_groups[] = { 534 "gpio86", 535}; 536 537static const char *const copy_phase_groups[] = { 538 "gpio103", 539}; 540 541static const char *const cri_trng_groups[] = { 542 "gpio60", "gpio61", "gpio62", 543}; 544 545static const char *const dbg_out_clk_groups[] = { 546 "gpio11", 547}; 548 549static const char *const ddr_bist_groups[] = { 550 "gpio7", "gpio8", "gpio9", "gpio10", 551}; 552 553static const char *const ddr_pxi_groups[] = { 554 "gpio6", "gpio7", "gpio10", "gpio11", 555 "gpio12", "gpio13", "gpio54", "gpio55", 556}; 557 558static const char *const dp_hot_groups[] = { 559 "gpio102", "gpio103", "gpio104", 560}; 561 562static const char *const edp_hot_groups[] = { 563 "gpio113", 564}; 565 566static const char *const edp_lcd_groups[] = { 567 "gpio119", 568}; 569 570static const char *const emac_gcc_groups[] = { 571 "gpio101", "gpio102", 572}; 573 574static const char *const emac_phy_intr_groups[] = { 575 "gpio89", 576}; 577 578static const char *const forced_usb_groups[] = { 579 "gpio43", 580}; 581 582static const char *const gcc_gp_groups[] = { 583 "gpio21", "gpio22", "gpio57", "gpio58", 584 "gpio59", "gpio78", 585}; 586 587static const char *const gp_pdm_groups[] = { 588 "gpio8", "gpio54", "gpio63", "gpio66", 589 "gpio79", "gpio95", 590}; 591 592static const char *const gps_tx_groups[] = { 593 "gpio53", "gpio54", "gpio56", "gpio57", 594 "gpio59", "gpio60", 595}; 596 597static const char *const hs0_mi2s_groups[] = { 598 "gpio36", "gpio37", "gpio38", "gpio39", 599}; 600 601static const char *const hs1_mi2s_groups[] = { 602 "gpio24", "gpio25", "gpio26", "gpio27", 603}; 604 605static const char *const jitter_bist_groups[] = { 606 "gpio12", "gpio26", 607}; 608 609static const char *const ldo_en_groups[] = { 610 "gpio97", 611}; 612 613static const char *const ldo_update_groups[] = { 614 "gpio98", 615}; 616 617static const char *const m_voc_groups[] = { 618 "gpio120", 619}; 620 621static const char *const mclk1_groups[] = { 622 "gpio121", 623}; 624 625static const char *const mclk2_groups[] = { 626 "gpio122", 627}; 628 629static const char *const mdp_vsync_groups[] = { 630 "gpio81", "gpio82", "gpio83", "gpio90", 631 "gpio97", "gpio98", 632}; 633 634static const char *const mdp_vsync0_out_groups[] = { 635 "gpio90", 636}; 637 638static const char *const mdp_vsync1_out_groups[] = { 639 "gpio90", 640}; 641 642static const char *const mdp_vsync2_out_groups[] = { 643 "gpio90", 644}; 645 646static const char *const mdp_vsync3_out_groups[] = { 647 "gpio90", 648}; 649 650static const char *const mdp_vsync4_out_groups[] = { 651 "gpio90", 652}; 653 654static const char *const mdp_vsync5_out_groups[] = { 655 "gpio90", 656}; 657 658static const char *const mi2s_1_groups[] = { 659 "gpio108", "gpio109", "gpio110", "gpio111", 660}; 661 662static const char *const mss_lte_groups[] = { 663 "gpio106", "gpio107", 664}; 665 666static const char *const nav_pps_in_groups[] = { 667 "gpio53", "gpio56", "gpio57", "gpio59", 668 "gpio60", 669}; 670 671static const char *const nav_pps_out_groups[] = { 672 "gpio53", "gpio56", "gpio57", "gpio59", 673 "gpio60", 674}; 675 676static const char *const pa_indicator_or_groups[] = { 677 "gpio53", 678}; 679 680static const char *const pcie_clk_req_groups[] = { 681 "gpio90", 682}; 683 684static const char *const pcie_ep_rst_groups[] = { 685 "gpio89", 686}; 687 688static const char *const phase_flag_groups[] = { 689 "gpio10", "gpio18", "gpio19", "gpio20", 690 "gpio23", "gpio24", "gpio25", "gpio38", 691 "gpio40", "gpio41", "gpio42", "gpio43", 692 "gpio44", "gpio45", "gpio53", "gpio54", 693 "gpio55", "gpio67", "gpio68", "gpio75", 694 "gpio76", "gpio77", "gpio78", "gpio79", 695 "gpio80", "gpio82", "gpio84", "gpio92", 696 "gpio116", "gpio117", "gpio118", "gpio119", 697}; 698 699static const char *const pll_bist_groups[] = { 700 "gpio27", 701}; 702 703static const char *const pll_bypassnl_groups[] = { 704 "gpio13", 705}; 706 707static const char *const pll_reset_n_groups[] = { 708 "gpio14", 709}; 710 711static const char *const prng_rosc_groups[] = { 712 "gpio99", "gpio102", 713}; 714 715static const char *const qdss_cti_groups[] = { 716 "gpio83", "gpio96", "gpio97", "gpio98", 717 "gpio103", "gpio104", "gpio112", "gpio113", 718}; 719 720static const char *const qdss_gpio_groups[] = { 721 "gpio0", "gpio1", "gpio2", "gpio3", 722 "gpio6", "gpio7", "gpio8", "gpio9", 723 "gpio14", "gpio15", "gpio20", "gpio21", 724 "gpio28", "gpio29", "gpio30", "gpio31", 725 "gpio32", "gpio33", "gpio34", "gpio35", 726 "gpio44", "gpio45", "gpio46", "gpio47", 727 "gpio81", "gpio82", "gpio92", "gpio93", 728 "gpio94", "gpio95", "gpio108", "gpio109", 729 "gpio117", "gpio118", "gpio119", "gpio120", 730}; 731 732static const char *const qlink_enable_groups[] = { 733 "gpio52", 734}; 735 736static const char *const qlink_request_groups[] = { 737 "gpio51", 738}; 739 740static const char *const qspi_groups[] = { 741 "gpio44", "gpio45", "gpio46", "gpio47", 742 "gpio48", "gpio49", "gpio50", 743}; 744 745static const char *const qup0_groups[] = { 746 "gpio0", "gpio1", "gpio2", "gpio3", 747 "gpio4", "gpio5", "gpio16", "gpio17", 748 "gpio18", "gpio19", 749}; 750 751static const char *const qup1_groups[] = { 752 "gpio6", "gpio7", "gpio8", "gpio9", 753 "gpio10", "gpio11", "gpio12", "gpio13", 754 "gpio14", "gpio15", "gpio20", "gpio21", 755 "gpio22", "gpio23", 756}; 757 758static const char *const rgmii_groups[] = { 759 "gpio81", "gpio82", "gpio83", "gpio91", 760 "gpio92", "gpio93", "gpio94", "gpio95", 761 "gpio96", "gpio97", "gpio102", "gpio103", 762 "gpio112", "gpio113", "gpio114", 763}; 764 765static const char *const sd_write_protect_groups[] = { 766 "gpio24", 767}; 768 769static const char *const sp_cmu_groups[] = { 770 "gpio64", 771}; 772 773static const char *const ter_mi2s_groups[] = { 774 "gpio115", "gpio116", "gpio117", "gpio118", 775}; 776 777static const char *const tgu_ch_groups[] = { 778 "gpio89", "gpio90", "gpio91", "gpio92", 779}; 780 781static const char *const uim1_groups[] = { 782 "gpio77", "gpio78", "gpio79", "gpio80", 783}; 784 785static const char *const uim2_groups[] = { 786 "gpio73", "gpio74", "gpio75", "gpio76", 787}; 788 789static const char *const usb0_hs_groups[] = { 790 "gpio88", 791}; 792 793static const char *const usb1_hs_groups[] = { 794 "gpio89", 795}; 796 797static const char *const usb_phy_ps_groups[] = { 798 "gpio104", 799}; 800 801static const char *const vfr_1_groups[] = { 802 "gpio92", 803}; 804 805static const char *const vsense_trigger_mirnat_groups[] = { 806 "gpio7", 807}; 808 809static const char *const wlan_groups[] = { 810 "gpio16", "gpio17", "gpio47", "gpio48", 811}; 812 813static const char *const wsa_clk_groups[] = { 814 "gpio111", 815}; 816 817static const char *const wsa_data_groups[] = { 818 "gpio110", 819}; 820 821static const struct pinfunction qcs615_functions[] = { 822 MSM_GPIO_PIN_FUNCTION(gpio), 823 MSM_PIN_FUNCTION(adsp_ext), 824 MSM_PIN_FUNCTION(agera_pll), 825 MSM_PIN_FUNCTION(aoss_cti), 826 MSM_PIN_FUNCTION(atest_char), 827 MSM_PIN_FUNCTION(atest_tsens), 828 MSM_PIN_FUNCTION(atest_usb), 829 MSM_PIN_FUNCTION(cam_mclk), 830 MSM_PIN_FUNCTION(cci_async), 831 MSM_PIN_FUNCTION(cci_i2c), 832 MSM_PIN_FUNCTION(cci_timer), 833 MSM_PIN_FUNCTION(copy_gp), 834 MSM_PIN_FUNCTION(copy_phase), 835 MSM_PIN_FUNCTION(cri_trng), 836 MSM_PIN_FUNCTION(dbg_out_clk), 837 MSM_PIN_FUNCTION(ddr_bist), 838 MSM_PIN_FUNCTION(ddr_pxi), 839 MSM_PIN_FUNCTION(dp_hot), 840 MSM_PIN_FUNCTION(edp_hot), 841 MSM_PIN_FUNCTION(edp_lcd), 842 MSM_PIN_FUNCTION(emac_gcc), 843 MSM_PIN_FUNCTION(emac_phy_intr), 844 MSM_PIN_FUNCTION(forced_usb), 845 MSM_PIN_FUNCTION(gcc_gp), 846 MSM_PIN_FUNCTION(gp_pdm), 847 MSM_PIN_FUNCTION(gps_tx), 848 MSM_PIN_FUNCTION(hs0_mi2s), 849 MSM_PIN_FUNCTION(hs1_mi2s), 850 MSM_PIN_FUNCTION(jitter_bist), 851 MSM_PIN_FUNCTION(ldo_en), 852 MSM_PIN_FUNCTION(ldo_update), 853 MSM_PIN_FUNCTION(m_voc), 854 MSM_PIN_FUNCTION(mclk1), 855 MSM_PIN_FUNCTION(mclk2), 856 MSM_PIN_FUNCTION(mdp_vsync), 857 MSM_PIN_FUNCTION(mdp_vsync0_out), 858 MSM_PIN_FUNCTION(mdp_vsync1_out), 859 MSM_PIN_FUNCTION(mdp_vsync2_out), 860 MSM_PIN_FUNCTION(mdp_vsync3_out), 861 MSM_PIN_FUNCTION(mdp_vsync4_out), 862 MSM_PIN_FUNCTION(mdp_vsync5_out), 863 MSM_PIN_FUNCTION(mi2s_1), 864 MSM_PIN_FUNCTION(mss_lte), 865 MSM_PIN_FUNCTION(nav_pps_in), 866 MSM_PIN_FUNCTION(nav_pps_out), 867 MSM_PIN_FUNCTION(pa_indicator_or), 868 MSM_PIN_FUNCTION(pcie_clk_req), 869 MSM_PIN_FUNCTION(pcie_ep_rst), 870 MSM_PIN_FUNCTION(phase_flag), 871 MSM_PIN_FUNCTION(pll_bist), 872 MSM_PIN_FUNCTION(pll_bypassnl), 873 MSM_PIN_FUNCTION(pll_reset_n), 874 MSM_PIN_FUNCTION(prng_rosc), 875 MSM_PIN_FUNCTION(qdss_cti), 876 MSM_PIN_FUNCTION(qdss_gpio), 877 MSM_PIN_FUNCTION(qlink_enable), 878 MSM_PIN_FUNCTION(qlink_request), 879 MSM_PIN_FUNCTION(qspi), 880 MSM_PIN_FUNCTION(qup0), 881 MSM_PIN_FUNCTION(qup1), 882 MSM_PIN_FUNCTION(rgmii), 883 MSM_PIN_FUNCTION(sd_write_protect), 884 MSM_PIN_FUNCTION(sp_cmu), 885 MSM_PIN_FUNCTION(ter_mi2s), 886 MSM_PIN_FUNCTION(tgu_ch), 887 MSM_PIN_FUNCTION(uim1), 888 MSM_PIN_FUNCTION(uim2), 889 MSM_PIN_FUNCTION(usb0_hs), 890 MSM_PIN_FUNCTION(usb1_hs), 891 MSM_PIN_FUNCTION(usb_phy_ps), 892 MSM_PIN_FUNCTION(vfr_1), 893 MSM_PIN_FUNCTION(vsense_trigger_mirnat), 894 MSM_PIN_FUNCTION(wlan), 895 MSM_PIN_FUNCTION(wsa_clk), 896 MSM_PIN_FUNCTION(wsa_data), 897}; 898 899/* Every pin is maintained as a single group, and missing or non-existing pin 900 * would be maintained as dummy group to synchronize pin group index with 901 * pin descriptor registered with pinctrl core. 902 * Clients would not be able to request these dummy pin groups. 903 */ 904static const struct msm_pingroup qcs615_groups[] = { 905 [0] = PINGROUP(0, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), 906 [1] = PINGROUP(1, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), 907 [2] = PINGROUP(2, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), 908 [3] = PINGROUP(3, WEST, qup0, _, qdss_gpio, _, _, _, _, _, _), 909 [4] = PINGROUP(4, WEST, qup0, _, _, _, _, _, _, _, _), 910 [5] = PINGROUP(5, WEST, qup0, _, _, _, _, _, _, _, _), 911 [6] = PINGROUP(6, EAST, qup1, qdss_gpio, ddr_pxi, _, _, _, _, _, _), 912 [7] = PINGROUP(7, EAST, qup1, ddr_bist, qdss_gpio, atest_tsens, 913 vsense_trigger_mirnat, atest_usb, ddr_pxi, _, _), 914 [8] = PINGROUP(8, EAST, qup1, gp_pdm, ddr_bist, qdss_gpio, _, _, _, _, _), 915 [9] = PINGROUP(9, EAST, qup1, ddr_bist, qdss_gpio, _, _, _, _, _, _), 916 [10] = PINGROUP(10, EAST, qup1, ddr_bist, _, phase_flag, atest_usb, ddr_pxi, _, _, _), 917 [11] = PINGROUP(11, EAST, qup1, dbg_out_clk, atest_usb, ddr_pxi, _, _, _, _, _), 918 [12] = PINGROUP(12, EAST, qup1, jitter_bist, ddr_pxi, _, _, _, _, _, _), 919 [13] = PINGROUP(13, EAST, qup1, pll_bypassnl, _, ddr_pxi, _, _, _, _, _), 920 [14] = PINGROUP(14, EAST, qup1, pll_reset_n, _, qdss_gpio, _, _, _, _, _), 921 [15] = PINGROUP(15, EAST, qup1, qdss_gpio, _, _, _, _, _, _, _), 922 [16] = PINGROUP(16, WEST, qup0, _, wlan, _, _, _, _, _, _), 923 [17] = PINGROUP(17, WEST, qup0, _, wlan, _, _, _, _, _, _), 924 [18] = PINGROUP(18, WEST, qup0, _, phase_flag, _, _, _, _, _, _), 925 [19] = PINGROUP(19, WEST, qup0, _, phase_flag, _, _, _, _, _, _), 926 [20] = PINGROUP(20, SOUTH, qup1, _, phase_flag, qdss_gpio, _, _, _, _, _), 927 [21] = PINGROUP(21, SOUTH, qup1, gcc_gp, _, qdss_gpio, _, _, _, _, _), 928 [22] = PINGROUP(22, SOUTH, qup1, gcc_gp, _, _, _, _, _, _, _), 929 [23] = PINGROUP(23, SOUTH, qup1, _, phase_flag, _, _, _, _, _, _), 930 [24] = PINGROUP(24, EAST, hs1_mi2s, sd_write_protect, _, phase_flag, _, _, _, _, _), 931 [25] = PINGROUP(25, EAST, hs1_mi2s, _, phase_flag, _, _, _, _, _, _), 932 [26] = PINGROUP(26, EAST, cci_async, hs1_mi2s, jitter_bist, _, _, _, _, _, _), 933 [27] = PINGROUP(27, EAST, hs1_mi2s, pll_bist, _, _, _, _, _, _, _), 934 [28] = PINGROUP(28, EAST, cam_mclk, agera_pll, qdss_gpio, _, _, _, _, _, _), 935 [29] = PINGROUP(29, EAST, cam_mclk, _, qdss_gpio, atest_tsens, _, _, _, _, _), 936 [30] = PINGROUP(30, EAST, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), 937 [31] = PINGROUP(31, EAST, cam_mclk, _, qdss_gpio, _, _, _, _, _, _), 938 [32] = PINGROUP(32, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), 939 [33] = PINGROUP(33, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), 940 [34] = PINGROUP(34, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), 941 [35] = PINGROUP(35, EAST, cci_i2c, _, qdss_gpio, _, _, _, _, _, _), 942 [36] = PINGROUP(36, EAST, hs0_mi2s, _, _, _, _, _, _, _, _), 943 [37] = PINGROUP(37, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _), 944 [38] = PINGROUP(38, EAST, cci_timer, hs0_mi2s, _, phase_flag, _, _, _, _, _), 945 [39] = PINGROUP(39, EAST, cci_timer, hs0_mi2s, _, _, _, _, _, _, _), 946 [40] = PINGROUP(40, EAST, _, phase_flag, _, _, _, _, _, _, _), 947 [41] = PINGROUP(41, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _), 948 [42] = PINGROUP(42, EAST, cci_async, cci_timer, _, phase_flag, _, _, _, _, _), 949 [43] = PINGROUP(43, SOUTH, _, phase_flag, forced_usb, _, _, _, _, _, _), 950 [44] = PINGROUP(44, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _), 951 [45] = PINGROUP(45, EAST, qspi, _, phase_flag, qdss_gpio, _, _, _, _, _), 952 [46] = PINGROUP(46, EAST, qspi, _, qdss_gpio, _, _, _, _, _, _), 953 [47] = PINGROUP(47, EAST, qspi, _, qdss_gpio, wlan, _, _, _, _, _), 954 [48] = PINGROUP(48, EAST, qspi, _, wlan, _, _, _, _, _, _), 955 [49] = PINGROUP(49, EAST, qspi, _, _, _, _, _, _, _, _), 956 [50] = PINGROUP(50, EAST, qspi, _, _, _, _, _, _, _, _), 957 [51] = PINGROUP(51, SOUTH, qlink_request, _, _, _, _, _, _, _, _), 958 [52] = PINGROUP(52, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), 959 [53] = PINGROUP(53, SOUTH, pa_indicator_or, nav_pps_in, nav_pps_out, gps_tx, _, 960 phase_flag, _, _, _), 961 [54] = PINGROUP(54, SOUTH, _, gps_tx, gp_pdm, _, phase_flag, atest_usb, ddr_pxi, _, _), 962 [55] = PINGROUP(55, SOUTH, _, _, phase_flag, atest_usb, ddr_pxi, _, _, _, _), 963 [56] = PINGROUP(56, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, _, _, _, _, _), 964 [57] = PINGROUP(57, SOUTH, _, nav_pps_in, gps_tx, nav_pps_out, gcc_gp, _, _, _, _), 965 [58] = PINGROUP(58, SOUTH, _, gcc_gp, _, _, _, _, _, _, _), 966 [59] = PINGROUP(59, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, gcc_gp, _, _, _, _), 967 [60] = PINGROUP(60, SOUTH, _, nav_pps_in, nav_pps_out, gps_tx, cri_trng, _, _, _, _), 968 [61] = PINGROUP(61, SOUTH, _, cri_trng, _, _, _, _, _, _, _), 969 [62] = PINGROUP(62, SOUTH, _, cri_trng, _, _, _, _, _, _, _), 970 [63] = PINGROUP(63, SOUTH, _, _, gp_pdm, _, _, _, _, _, _), 971 [64] = PINGROUP(64, SOUTH, _, sp_cmu, _, _, _, _, _, _, _), 972 [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _), 973 [66] = PINGROUP(66, SOUTH, _, gp_pdm, _, _, _, _, _, _, _), 974 [67] = PINGROUP(67, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _), 975 [68] = PINGROUP(68, SOUTH, _, _, _, phase_flag, atest_usb, _, _, _, _), 976 [69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _), 977 [70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _), 978 [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _), 979 [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _), 980 [73] = PINGROUP(73, SOUTH, uim2, _, _, _, _, _, _, _, _), 981 [74] = PINGROUP(74, SOUTH, uim2, _, _, _, _, _, _, _, _), 982 [75] = PINGROUP(75, SOUTH, uim2, _, phase_flag, atest_usb, _, _, _, _, _), 983 [76] = PINGROUP(76, SOUTH, uim2, _, phase_flag, atest_usb, aoss_cti, _, _, _, _), 984 [77] = PINGROUP(77, SOUTH, uim1, _, phase_flag, atest_usb, _, _, _, _, _), 985 [78] = PINGROUP(78, SOUTH, uim1, gcc_gp, _, phase_flag, _, _, _, _, _), 986 [79] = PINGROUP(79, SOUTH, uim1, gp_pdm, _, phase_flag, _, _, _, _, _), 987 [80] = PINGROUP(80, SOUTH, uim1, _, phase_flag, _, _, _, _, _, _), 988 [81] = PINGROUP(81, WEST, rgmii, mdp_vsync, _, qdss_gpio, _, _, _, _, _), 989 [82] = PINGROUP(82, WEST, rgmii, mdp_vsync, _, phase_flag, qdss_gpio, _, _, _, _), 990 [83] = PINGROUP(83, WEST, rgmii, mdp_vsync, _, qdss_cti, _, _, _, _, _), 991 [84] = PINGROUP(84, SOUTH, _, phase_flag, atest_char, _, _, _, _, _, _), 992 [85] = PINGROUP(85, SOUTH, _, atest_char, _, _, _, _, _, _, _), 993 [86] = PINGROUP(86, SOUTH, copy_gp, _, atest_char, _, _, _, _, _, _), 994 [87] = PINGROUP(87, SOUTH, _, atest_char, _, _, _, _, _, _, _), 995 [88] = PINGROUP(88, WEST, _, usb0_hs, _, _, _, _, _, _, _), 996 [89] = PINGROUP(89, WEST, emac_phy_intr, pcie_ep_rst, tgu_ch, usb1_hs, _, _, _, _, _), 997 [90] = PINGROUP(90, WEST, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, 998 mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, mdp_vsync5_out, 999 pcie_clk_req, tgu_ch), 1000 [91] = PINGROUP(91, WEST, rgmii, tgu_ch, _, _, _, _, _, _, _), 1001 [92] = PINGROUP(92, WEST, rgmii, vfr_1, tgu_ch, _, phase_flag, qdss_gpio, _, _, _), 1002 [93] = PINGROUP(93, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _), 1003 [94] = PINGROUP(94, WEST, rgmii, qdss_gpio, _, _, _, _, _, _, _), 1004 [95] = PINGROUP(95, WEST, rgmii, gp_pdm, qdss_gpio, _, _, _, _, _, _), 1005 [96] = PINGROUP(96, WEST, rgmii, qdss_cti, _, _, _, _, _, _, _), 1006 [97] = PINGROUP(97, WEST, rgmii, mdp_vsync, ldo_en, qdss_cti, _, _, _, _, _), 1007 [98] = PINGROUP(98, WEST, mdp_vsync, ldo_update, qdss_cti, _, _, _, _, _, _), 1008 [99] = PINGROUP(99, EAST, prng_rosc, _, _, _, _, _, _, _, _), 1009 [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), 1010 [101] = PINGROUP(101, WEST, emac_gcc, _, _, _, _, _, _, _, _), 1011 [102] = PINGROUP(102, WEST, rgmii, dp_hot, emac_gcc, prng_rosc, _, _, _, _, _), 1012 [103] = PINGROUP(103, WEST, rgmii, dp_hot, copy_phase, qdss_cti, _, _, _, _, _), 1013 [104] = PINGROUP(104, WEST, usb_phy_ps, _, qdss_cti, dp_hot, _, _, _, _, _), 1014 [105] = PINGROUP(105, SOUTH, _, _, _, _, _, _, _, _, _), 1015 [106] = PINGROUP(106, EAST, mss_lte, _, _, _, _, _, _, _, _), 1016 [107] = PINGROUP(107, EAST, mss_lte, _, _, _, _, _, _, _, _), 1017 [108] = PINGROUP(108, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _), 1018 [109] = PINGROUP(109, SOUTH, mi2s_1, _, qdss_gpio, _, _, _, _, _, _), 1019 [110] = PINGROUP(110, SOUTH, wsa_data, mi2s_1, _, _, _, _, _, _, _), 1020 [111] = PINGROUP(111, SOUTH, wsa_clk, mi2s_1, _, _, _, _, _, _, _), 1021 [112] = PINGROUP(112, WEST, rgmii, _, qdss_cti, _, _, _, _, _, _), 1022 [113] = PINGROUP(113, WEST, rgmii, edp_hot, _, qdss_cti, _, _, _, _, _), 1023 [114] = PINGROUP(114, WEST, rgmii, _, _, _, _, _, _, _, _), 1024 [115] = PINGROUP(115, SOUTH, ter_mi2s, atest_char, _, _, _, _, _, _, _), 1025 [116] = PINGROUP(116, SOUTH, ter_mi2s, _, phase_flag, _, _, _, _, _, _), 1026 [117] = PINGROUP(117, SOUTH, ter_mi2s, _, phase_flag, qdss_gpio, atest_char, _, _, _, _), 1027 [118] = PINGROUP(118, SOUTH, ter_mi2s, adsp_ext, _, phase_flag, qdss_gpio, atest_char, 1028 _, _, _), 1029 [119] = PINGROUP(119, SOUTH, edp_lcd, _, phase_flag, qdss_gpio, atest_char, _, _, _, _), 1030 [120] = PINGROUP(120, SOUTH, m_voc, qdss_gpio, atest_char, _, _, _, _, _, _), 1031 [121] = PINGROUP(121, SOUTH, mclk1, atest_char, _, _, _, _, _, _, _), 1032 [122] = PINGROUP(122, SOUTH, mclk2, _, _, _, _, _, _, _, _), 1033 [123] = UFS_RESET(ufs_reset, 0x9f000), 1034 [124] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x9a000, 15, 0), 1035 [125] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x9a000, 13, 6), 1036 [126] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x9a000, 11, 3), 1037 [127] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x9a000, 9, 0), 1038 [128] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x98000, 14, 6), 1039 [129] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x98000, 11, 3), 1040 [130] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x98000, 9, 0), 1041}; 1042 1043static const struct msm_gpio_wakeirq_map qcs615_pdc_map[] = { 1044 { 1, 45 }, { 3, 31 }, { 7, 55 }, { 9, 110 }, { 11, 34 }, 1045 { 13, 33 }, { 14, 35 }, { 17, 46 }, { 19, 48 }, { 21, 83 }, 1046 { 22, 36 }, { 26, 38 }, { 35, 37 }, { 39, 125 }, { 41, 47 }, 1047 { 47, 49 }, { 48, 51 }, { 50, 52 }, { 51, 123 }, { 55, 56 }, 1048 { 56, 57 }, { 57, 58 }, { 60, 60 }, { 71, 54 }, { 80, 73 }, 1049 { 81, 64 }, { 82, 50 }, { 83, 65 }, { 84, 92 }, { 85, 99 }, 1050 { 86, 67 }, { 87, 84 }, { 88, 124 }, { 89, 122 }, { 90, 69 }, 1051 { 92, 88 }, { 93, 75 }, { 94, 91 }, { 95, 72 }, { 96, 82 }, 1052 { 97, 74 }, { 98, 95 }, { 99, 94 }, { 100, 100 }, { 101, 40 }, 1053 { 102, 93 }, { 103, 77 }, { 104, 78 }, { 105, 96 }, { 107, 97 }, 1054 { 108, 111 }, { 112, 112 }, { 113, 113 }, { 117, 85 }, { 118, 102 }, 1055 { 119, 87 }, { 120, 114 }, { 121, 89 }, { 122, 90 }, 1056}; 1057 1058static const struct msm_pinctrl_soc_data qcs615_tlmm = { 1059 .pins = qcs615_pins, 1060 .npins = ARRAY_SIZE(qcs615_pins), 1061 .functions = qcs615_functions, 1062 .nfunctions = ARRAY_SIZE(qcs615_functions), 1063 .groups = qcs615_groups, 1064 .ngroups = ARRAY_SIZE(qcs615_groups), 1065 .ngpios = 124, 1066 .tiles = qcs615_tiles, 1067 .ntiles = ARRAY_SIZE(qcs615_tiles), 1068 .wakeirq_map = qcs615_pdc_map, 1069 .nwakeirq_map = ARRAY_SIZE(qcs615_pdc_map), 1070 .wakeirq_dual_edge_errata = true, 1071}; 1072 1073static const struct of_device_id qcs615_tlmm_of_match[] = { 1074 { 1075 .compatible = "qcom,qcs615-tlmm", 1076 }, 1077 {}, 1078}; 1079 1080static int qcs615_tlmm_probe(struct platform_device *pdev) 1081{ 1082 return msm_pinctrl_probe(pdev, &qcs615_tlmm); 1083} 1084 1085static struct platform_driver qcs615_tlmm_driver = { 1086 .driver = { 1087 .name = "qcs615-tlmm", 1088 .of_match_table = qcs615_tlmm_of_match, 1089 }, 1090 .probe = qcs615_tlmm_probe, 1091}; 1092 1093static int __init qcs615_tlmm_init(void) 1094{ 1095 return platform_driver_register(&qcs615_tlmm_driver); 1096} 1097arch_initcall(qcs615_tlmm_init); 1098 1099static void __exit qcs615_tlmm_exit(void) 1100{ 1101 platform_driver_unregister(&qcs615_tlmm_driver); 1102} 1103module_exit(qcs615_tlmm_exit); 1104 1105MODULE_DESCRIPTION("QTI QCS615 TLMM driver"); 1106MODULE_LICENSE("GPL"); 1107MODULE_DEVICE_TABLE(of, qcs615_tlmm_of_match);
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