pinctrl-msm.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2013, Sony Mobile Communications AB.
   4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   5 */
   6
   7#include <linux/delay.h>
   8#include <linux/err.h>
   9#include <linux/gpio/driver.h>
  10#include <linux/interrupt.h>
  11#include <linux/io.h>
  12#include <linux/log2.h>
  13#include <linux/module.h>
  14#include <linux/of.h>
  15#include <linux/platform_device.h>
  16#include <linux/pm.h>
  17#include <linux/firmware/qcom/qcom_scm.h>
  18#include <linux/reboot.h>
  19#include <linux/seq_file.h>
  20#include <linux/slab.h>
  21#include <linux/spinlock.h>
  22#include <linux/string_choices.h>
  23
  24#include <linux/pinctrl/machine.h>
  25#include <linux/pinctrl/pinconf-generic.h>
  26#include <linux/pinctrl/pinconf.h>
  27#include <linux/pinctrl/pinmux.h>
  28
  29#include <linux/soc/qcom/irq.h>
  30
  31#include "../core.h"
  32#include "../pinconf.h"
  33#include "../pinctrl-utils.h"
  34#include "../pinmux.h"
  35
  36#include "pinctrl-msm.h"
  37
  38#define MAX_NR_GPIO 300
  39#define MAX_NR_TILES 4
  40#define PS_HOLD_OFFSET 0x820
  41
  42/**
  43 * struct msm_pinctrl - state for a pinctrl-msm device
  44 * @dev:            device handle.
  45 * @pctrl:          pinctrl handle.
  46 * @chip:           gpiochip handle.
  47 * @desc:           pin controller descriptor
  48 * @irq:            parent irq for the TLMM irq_chip.
  49 * @intr_target_use_scm: route irq to application cpu using scm calls
  50 * @lock:           Spinlock to protect register resources as well
  51 *                  as msm_pinctrl data structures.
  52 * @enabled_irqs:   Bitmap of currently enabled irqs.
  53 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
  54 *                  detection.
  55 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
  56 * @disabled_for_mux: These IRQs were disabled because we muxed away.
  57 * @ever_gpio:      This bit is set the first time we mux a pin to gpio_func.
  58 * @soc:            Reference to soc_data of platform specific data.
  59 * @regs:           Base addresses for the TLMM tiles.
  60 * @phys_base:      Physical base address
  61 */
  62struct msm_pinctrl {
  63	struct device *dev;
  64	struct pinctrl_dev *pctrl;
  65	struct gpio_chip chip;
  66	struct pinctrl_desc desc;
  67
  68	int irq;
  69
  70	bool intr_target_use_scm;
  71
  72	raw_spinlock_t lock;
  73
  74	DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
  75	DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
  76	DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
  77	DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
  78	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
  79
  80	const struct msm_pinctrl_soc_data *soc;
  81	void __iomem *regs[MAX_NR_TILES];
  82	u32 phys_base[MAX_NR_TILES];
  83};
  84
  85#define MSM_ACCESSOR(name) \
  86static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
  87			    const struct msm_pingroup *g) \
  88{ \
  89	return readl(pctrl->regs[g->tile] + g->name##_reg); \
  90} \
  91static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
  92			      const struct msm_pingroup *g) \
  93{ \
  94	writel(val, pctrl->regs[g->tile] + g->name##_reg); \
  95}
  96
  97MSM_ACCESSOR(ctl)
  98MSM_ACCESSOR(io)
  99MSM_ACCESSOR(intr_cfg)
 100MSM_ACCESSOR(intr_status)
 101MSM_ACCESSOR(intr_target)
 102
 103static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
 104				const struct msm_pingroup *g)
 105{
 106	u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
 107
 108	msm_writel_intr_status(val, pctrl, g);
 109}
 110
 111static int msm_get_groups_count(struct pinctrl_dev *pctldev)
 112{
 113	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 114
 115	return pctrl->soc->ngroups;
 116}
 117
 118static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
 119				      unsigned group)
 120{
 121	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 122
 123	return pctrl->soc->groups[group].grp.name;
 124}
 125
 126static int msm_get_group_pins(struct pinctrl_dev *pctldev,
 127			      unsigned group,
 128			      const unsigned **pins,
 129			      unsigned *num_pins)
 130{
 131	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 132
 133	*pins = pctrl->soc->groups[group].grp.pins;
 134	*num_pins = pctrl->soc->groups[group].grp.npins;
 135	return 0;
 136}
 137
 138static const struct pinctrl_ops msm_pinctrl_ops = {
 139	.get_groups_count	= msm_get_groups_count,
 140	.get_group_name		= msm_get_group_name,
 141	.get_group_pins		= msm_get_group_pins,
 142	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
 143	.dt_free_map		= pinctrl_utils_free_map,
 144};
 145
 146static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
 147{
 148	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 149	struct gpio_chip *chip = &pctrl->chip;
 150
 151	return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
 152}
 153
 154static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 155			      unsigned function,
 156			      unsigned group)
 157{
 158	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 159	struct gpio_chip *gc = &pctrl->chip;
 160	unsigned int irq = irq_find_mapping(gc->irq.domain, group);
 161	struct irq_data *d = irq_get_irq_data(irq);
 162	unsigned int gpio_func = pctrl->soc->gpio_func;
 163	unsigned int egpio_func = pctrl->soc->egpio_func;
 164	const struct msm_pingroup *g;
 165	unsigned long flags;
 166	u32 val, mask;
 167	int i;
 168
 169	g = &pctrl->soc->groups[group];
 170	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
 171
 172	for (i = 0; i < g->nfuncs; i++) {
 173		if (g->funcs[i] == function)
 174			break;
 175	}
 176
 177	if (WARN_ON(i == g->nfuncs))
 178		return -EINVAL;
 179
 180	/*
 181	 * If an GPIO interrupt is setup on this pin then we need special
 182	 * handling.  Specifically interrupt detection logic will still see
 183	 * the pin twiddle even when we're muxed away.
 184	 *
 185	 * When we see a pin with an interrupt setup on it then we'll disable
 186	 * (mask) interrupts on it when we mux away until we mux back.  Note
 187	 * that disable_irq() refcounts and interrupts are disabled as long as
 188	 * at least one disable_irq() has been called.
 189	 */
 190	if (d && i != gpio_func &&
 191	    !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
 192		disable_irq_nosync(irq);
 193
 194	raw_spin_lock_irqsave(&pctrl->lock, flags);
 195
 196	val = msm_readl_ctl(pctrl, g);
 197
 198	/*
 199	 * If this is the first time muxing to GPIO and the direction is
 200	 * output, make sure that we're not going to be glitching the pin
 201	 * by reading the current state of the pin and setting it as the
 202	 * output.
 203	 */
 204	if (i == gpio_func && (val & BIT(g->oe_bit)) &&
 205	    !test_and_set_bit(group, pctrl->ever_gpio)) {
 206		u32 io_val = msm_readl_io(pctrl, g);
 207
 208		if (io_val & BIT(g->in_bit)) {
 209			if (!(io_val & BIT(g->out_bit)))
 210				msm_writel_io(io_val | BIT(g->out_bit), pctrl, g);
 211		} else {
 212			if (io_val & BIT(g->out_bit))
 213				msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g);
 214		}
 215	}
 216
 217	if (egpio_func && i == egpio_func) {
 218		if (val & BIT(g->egpio_present))
 219			val &= ~BIT(g->egpio_enable);
 220	} else {
 221		val &= ~mask;
 222		val |= i << g->mux_bit;
 223		/* Claim ownership of pin if egpio capable */
 224		if (egpio_func && val & BIT(g->egpio_present))
 225			val |= BIT(g->egpio_enable);
 226	}
 227
 228	msm_writel_ctl(val, pctrl, g);
 229
 230	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 231
 232	if (d && i == gpio_func &&
 233	    test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
 234		/*
 235		 * Clear interrupts detected while not GPIO since we only
 236		 * masked things.
 237		 */
 238		if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
 239			irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
 240		else
 241			msm_ack_intr_status(pctrl, g);
 242
 243		enable_irq(irq);
 244	}
 245
 246	return 0;
 247}
 248
 249static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
 250				   struct pinctrl_gpio_range *range,
 251				   unsigned offset)
 252{
 253	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 254	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
 255
 256	/* No funcs? Probably ACPI so can't do anything here */
 257	if (!g->nfuncs)
 258		return 0;
 259
 260	return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
 261}
 262
 263static const struct pinmux_ops msm_pinmux_ops = {
 264	.request		= msm_pinmux_request,
 265	.get_functions_count	= pinmux_generic_get_function_count,
 266	.get_function_name	= pinmux_generic_get_function_name,
 267	.get_function_groups	= pinmux_generic_get_function_groups,
 268	.function_is_gpio	= pinmux_generic_function_is_gpio,
 269	.gpio_request_enable	= msm_pinmux_request_gpio,
 270	.set_mux		= msm_pinmux_set_mux,
 271	.strict			= true,
 272};
 273
 274static int msm_config_reg(struct msm_pinctrl *pctrl,
 275			  const struct msm_pingroup *g,
 276			  unsigned param,
 277			  unsigned *mask,
 278			  unsigned *bit)
 279{
 280	switch (param) {
 281	case PIN_CONFIG_BIAS_DISABLE:
 282	case PIN_CONFIG_BIAS_PULL_DOWN:
 283	case PIN_CONFIG_BIAS_BUS_HOLD:
 284	case PIN_CONFIG_BIAS_PULL_UP:
 285		*bit = g->pull_bit;
 286		*mask = 3;
 287		if (g->i2c_pull_bit)
 288			*mask |= BIT(g->i2c_pull_bit) >> *bit;
 289		break;
 290	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 291		*bit = g->od_bit;
 292		*mask = 1;
 293		break;
 294	case PIN_CONFIG_DRIVE_STRENGTH:
 295		*bit = g->drv_bit;
 296		*mask = 7;
 297		break;
 298	case PIN_CONFIG_LEVEL:
 299	case PIN_CONFIG_INPUT_ENABLE:
 300	case PIN_CONFIG_OUTPUT_ENABLE:
 301		*bit = g->oe_bit;
 302		*mask = 1;
 303		break;
 304	default:
 305		return -ENOTSUPP;
 306	}
 307
 308	return 0;
 309}
 310
 311#define MSM_NO_PULL		0
 312#define MSM_PULL_DOWN		1
 313#define MSM_KEEPER		2
 314#define MSM_PULL_UP_NO_KEEPER	2
 315#define MSM_PULL_UP		3
 316#define MSM_I2C_STRONG_PULL_UP	2200
 317
 318static unsigned msm_regval_to_drive(u32 val)
 319{
 320	return (val + 1) * 2;
 321}
 322
 323static int msm_config_group_get(struct pinctrl_dev *pctldev,
 324				unsigned int group,
 325				unsigned long *config)
 326{
 327	const struct msm_pingroup *g;
 328	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 329	unsigned param = pinconf_to_config_param(*config);
 330	unsigned mask;
 331	unsigned arg;
 332	unsigned bit;
 333	int ret;
 334	u32 val;
 335
 336	/* Pin information can only be requested from valid pin groups */
 337	if (!gpiochip_line_is_valid(&pctrl->chip, group))
 338		return -EINVAL;
 339
 340	g = &pctrl->soc->groups[group];
 341
 342	ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 343	if (ret < 0)
 344		return ret;
 345
 346	val = msm_readl_ctl(pctrl, g);
 347	arg = (val >> bit) & mask;
 348
 349	/* Convert register value to pinconf value */
 350	switch (param) {
 351	case PIN_CONFIG_BIAS_DISABLE:
 352		if (arg != MSM_NO_PULL)
 353			return -EINVAL;
 354		arg = 1;
 355		break;
 356	case PIN_CONFIG_BIAS_PULL_DOWN:
 357		if (arg != MSM_PULL_DOWN)
 358			return -EINVAL;
 359		arg = 1;
 360		break;
 361	case PIN_CONFIG_BIAS_BUS_HOLD:
 362		if (pctrl->soc->pull_no_keeper)
 363			return -ENOTSUPP;
 364
 365		if (arg != MSM_KEEPER)
 366			return -EINVAL;
 367		arg = 1;
 368		break;
 369	case PIN_CONFIG_BIAS_PULL_UP:
 370		if (pctrl->soc->pull_no_keeper)
 371			arg = arg == MSM_PULL_UP_NO_KEEPER;
 372		else if (arg & BIT(g->i2c_pull_bit))
 373			arg = MSM_I2C_STRONG_PULL_UP;
 374		else
 375			arg = arg == MSM_PULL_UP;
 376		if (!arg)
 377			return -EINVAL;
 378		break;
 379	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 380		/* Pin is not open-drain */
 381		if (!arg)
 382			return -EINVAL;
 383		arg = 1;
 384		break;
 385	case PIN_CONFIG_DRIVE_STRENGTH:
 386		arg = msm_regval_to_drive(arg);
 387		break;
 388	case PIN_CONFIG_LEVEL:
 389		/* Pin is not output */
 390		if (!arg)
 391			return -EINVAL;
 392
 393		val = msm_readl_io(pctrl, g);
 394		arg = !!(val & BIT(g->in_bit));
 395		break;
 396	case PIN_CONFIG_OUTPUT_ENABLE:
 397		if (!arg)
 398			return -EINVAL;
 399		break;
 400	default:
 401		return -ENOTSUPP;
 402	}
 403
 404	*config = pinconf_to_config_packed(param, arg);
 405
 406	return 0;
 407}
 408
 409static int msm_config_group_set(struct pinctrl_dev *pctldev,
 410				unsigned group,
 411				unsigned long *configs,
 412				unsigned num_configs)
 413{
 414	const struct msm_pingroup *g;
 415	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 416	unsigned long flags;
 417	unsigned param;
 418	unsigned mask;
 419	unsigned arg;
 420	unsigned bit;
 421	int ret;
 422	u32 val;
 423	int i;
 424
 425	g = &pctrl->soc->groups[group];
 426
 427	for (i = 0; i < num_configs; i++) {
 428		param = pinconf_to_config_param(configs[i]);
 429		arg = pinconf_to_config_argument(configs[i]);
 430
 431		ret = msm_config_reg(pctrl, g, param, &mask, &bit);
 432		if (ret < 0)
 433			return ret;
 434
 435		/* Convert pinconf values to register values */
 436		switch (param) {
 437		case PIN_CONFIG_BIAS_DISABLE:
 438			arg = MSM_NO_PULL;
 439			break;
 440		case PIN_CONFIG_BIAS_PULL_DOWN:
 441			arg = MSM_PULL_DOWN;
 442			break;
 443		case PIN_CONFIG_BIAS_BUS_HOLD:
 444			if (pctrl->soc->pull_no_keeper)
 445				return -ENOTSUPP;
 446
 447			arg = MSM_KEEPER;
 448			break;
 449		case PIN_CONFIG_BIAS_PULL_UP:
 450			if (pctrl->soc->pull_no_keeper)
 451				arg = MSM_PULL_UP_NO_KEEPER;
 452			else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP)
 453				arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP;
 454			else
 455				arg = MSM_PULL_UP;
 456			break;
 457		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 458			arg = 1;
 459			break;
 460		case PIN_CONFIG_DRIVE_STRENGTH:
 461			/* Check for invalid values */
 462			if (arg > 16 || arg < 2 || (arg % 2) != 0)
 463				arg = -1;
 464			else
 465				arg = (arg / 2) - 1;
 466			break;
 467		case PIN_CONFIG_LEVEL:
 468			/* set output value */
 469			raw_spin_lock_irqsave(&pctrl->lock, flags);
 470			val = msm_readl_io(pctrl, g);
 471			if (arg)
 472				val |= BIT(g->out_bit);
 473			else
 474				val &= ~BIT(g->out_bit);
 475			msm_writel_io(val, pctrl, g);
 476			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 477
 478			/* enable output */
 479			arg = 1;
 480			break;
 481		case PIN_CONFIG_INPUT_ENABLE:
 482			/*
 483			 * According to pinctrl documentation this should
 484			 * actually be a no-op.
 485			 *
 486			 * The docs are explicit that "this does not affect
 487			 * the pin's ability to drive output" but what we do
 488			 * here is to modify the output enable bit. Thus, to
 489			 * follow the docs we should remove that.
 490			 *
 491			 * The docs say that we should enable any relevant
 492			 * input buffer, but TLMM there is no input buffer that
 493			 * can be enabled/disabled. It's always on.
 494			 *
 495			 * The points above, explain why this _should_ be a
 496			 * no-op. However, for historical reasons and to
 497			 * support old device trees, we'll violate the docs
 498			 * and still affect the output.
 499			 *
 500			 * It should further be noted that this old historical
 501			 * behavior actually overrides arg to 0. That means
 502			 * that "input-enable" and "input-disable" in a device
 503			 * tree would _both_ disable the output. We'll
 504			 * continue to preserve this behavior as well since
 505			 * we have no other use for this attribute.
 506			 */
 507			arg = 0;
 508			break;
 509		case PIN_CONFIG_OUTPUT_ENABLE:
 510			arg = !!arg;
 511			break;
 512		default:
 513			dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
 514				param);
 515			return -EINVAL;
 516		}
 517
 518		/* Range-check user-supplied value */
 519		if (arg & ~mask) {
 520			dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
 521			return -EINVAL;
 522		}
 523
 524		raw_spin_lock_irqsave(&pctrl->lock, flags);
 525		val = msm_readl_ctl(pctrl, g);
 526		val &= ~(mask << bit);
 527		val |= arg << bit;
 528		msm_writel_ctl(val, pctrl, g);
 529		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 530	}
 531
 532	return 0;
 533}
 534
 535static const struct pinconf_ops msm_pinconf_ops = {
 536	.is_generic		= true,
 537	.pin_config_group_get	= msm_config_group_get,
 538	.pin_config_group_set	= msm_config_group_set,
 539};
 540
 541static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 542{
 543	const struct msm_pingroup *g;
 544	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 545	unsigned long flags;
 546	u32 val;
 547
 548	g = &pctrl->soc->groups[offset];
 549
 550	raw_spin_lock_irqsave(&pctrl->lock, flags);
 551
 552	val = msm_readl_ctl(pctrl, g);
 553	val &= ~BIT(g->oe_bit);
 554	msm_writel_ctl(val, pctrl, g);
 555
 556	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 557
 558	return 0;
 559}
 560
 561static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 562{
 563	const struct msm_pingroup *g;
 564	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 565	unsigned long flags;
 566	u32 val;
 567
 568	g = &pctrl->soc->groups[offset];
 569
 570	raw_spin_lock_irqsave(&pctrl->lock, flags);
 571
 572	val = msm_readl_io(pctrl, g);
 573	if (value)
 574		val |= BIT(g->out_bit);
 575	else
 576		val &= ~BIT(g->out_bit);
 577	msm_writel_io(val, pctrl, g);
 578
 579	val = msm_readl_ctl(pctrl, g);
 580	val |= BIT(g->oe_bit);
 581	msm_writel_ctl(val, pctrl, g);
 582
 583	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 584
 585	return 0;
 586}
 587
 588static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 589{
 590	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 591	const struct msm_pingroup *g;
 592	u32 val;
 593
 594	g = &pctrl->soc->groups[offset];
 595
 596	val = msm_readl_ctl(pctrl, g);
 597
 598	return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
 599				      GPIO_LINE_DIRECTION_IN;
 600}
 601
 602static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
 603{
 604	const struct msm_pingroup *g;
 605	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 606	u32 val;
 607
 608	g = &pctrl->soc->groups[offset];
 609
 610	val = msm_readl_io(pctrl, g);
 611	return !!(val & BIT(g->in_bit));
 612}
 613
 614static int msm_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 615{
 616	const struct msm_pingroup *g;
 617	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 618	unsigned long flags;
 619	u32 val;
 620
 621	g = &pctrl->soc->groups[offset];
 622
 623	raw_spin_lock_irqsave(&pctrl->lock, flags);
 624
 625	val = msm_readl_io(pctrl, g);
 626	if (value)
 627		val |= BIT(g->out_bit);
 628	else
 629		val &= ~BIT(g->out_bit);
 630	msm_writel_io(val, pctrl, g);
 631
 632	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 633
 634	return 0;
 635}
 636
 637#ifdef CONFIG_DEBUG_FS
 638
 639static void msm_gpio_dbg_show_one(struct seq_file *s,
 640				  struct pinctrl_dev *pctldev,
 641				  struct gpio_chip *chip,
 642				  unsigned offset,
 643				  unsigned gpio)
 644{
 645	const struct msm_pingroup *g;
 646	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 647	unsigned func;
 648	int is_out;
 649	int drive;
 650	int pull;
 651	int val;
 652	int egpio_enable;
 653	u32 ctl_reg, io_reg;
 654
 655	static const char * const pulls_keeper[] = {
 656		"no pull",
 657		"pull down",
 658		"keeper",
 659		"pull up"
 660	};
 661
 662	static const char * const pulls_no_keeper[] = {
 663		"no pull",
 664		"pull down",
 665		"pull up",
 666	};
 667
 668	if (!gpiochip_line_is_valid(chip, offset))
 669		return;
 670
 671	g = &pctrl->soc->groups[offset];
 672	ctl_reg = msm_readl_ctl(pctrl, g);
 673	io_reg = msm_readl_io(pctrl, g);
 674
 675	is_out = !!(ctl_reg & BIT(g->oe_bit));
 676	func = (ctl_reg >> g->mux_bit) & 7;
 677	drive = (ctl_reg >> g->drv_bit) & 7;
 678	pull = (ctl_reg >> g->pull_bit) & 3;
 679	egpio_enable = 0;
 680	if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
 681		egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
 682
 683	if (is_out)
 684		val = !!(io_reg & BIT(g->out_bit));
 685	else
 686		val = !!(io_reg & BIT(g->in_bit));
 687
 688	if (egpio_enable) {
 689		seq_printf(s, " %-8s: egpio\n", g->grp.name);
 690		return;
 691	}
 692
 693	seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
 694	seq_printf(s, " %-4s func%d", str_high_low(val), func);
 695	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
 696	if (pctrl->soc->pull_no_keeper)
 697		seq_printf(s, " %s", pulls_no_keeper[pull]);
 698	else
 699		seq_printf(s, " %s", pulls_keeper[pull]);
 700	seq_puts(s, "\n");
 701}
 702
 703static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 704{
 705	unsigned gpio = chip->base;
 706	unsigned i;
 707
 708	for (i = 0; i < chip->ngpio; i++, gpio++)
 709		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
 710}
 711
 712#else
 713#define msm_gpio_dbg_show NULL
 714#endif
 715
 716static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
 717				    unsigned long *valid_mask,
 718				    unsigned int ngpios)
 719{
 720	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 721	int ret;
 722	unsigned int len, i;
 723	const int *reserved = pctrl->soc->reserved_gpios;
 724	u16 *tmp;
 725
 726	/* Remove driver-provided reserved GPIOs from valid_mask */
 727	if (reserved) {
 728		for (i = 0; reserved[i] >= 0; i++) {
 729			if (i >= ngpios || reserved[i] >= ngpios) {
 730				dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
 731				return -EINVAL;
 732			}
 733			clear_bit(reserved[i], valid_mask);
 734		}
 735
 736		return 0;
 737	}
 738
 739	/* The number of GPIOs in the ACPI tables */
 740	len = ret = device_property_count_u16(pctrl->dev, "gpios");
 741	if (ret < 0)
 742		return 0;
 743
 744	if (ret > ngpios)
 745		return -EINVAL;
 746
 747	tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
 748	if (!tmp)
 749		return -ENOMEM;
 750
 751	ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
 752	if (ret < 0) {
 753		dev_err(pctrl->dev, "could not read list of GPIOs\n");
 754		goto out;
 755	}
 756
 757	bitmap_zero(valid_mask, ngpios);
 758	for (i = 0; i < len; i++)
 759		set_bit(tmp[i], valid_mask);
 760
 761out:
 762	kfree(tmp);
 763	return ret;
 764}
 765
 766static const struct gpio_chip msm_gpio_template = {
 767	.direction_input  = msm_gpio_direction_input,
 768	.direction_output = msm_gpio_direction_output,
 769	.get_direction    = msm_gpio_get_direction,
 770	.get              = msm_gpio_get,
 771	.set              = msm_gpio_set,
 772	.request          = gpiochip_generic_request,
 773	.free             = gpiochip_generic_free,
 774	.dbg_show         = msm_gpio_dbg_show,
 775};
 776
 777/* For dual-edge interrupts in software, since some hardware has no
 778 * such support:
 779 *
 780 * At appropriate moments, this function may be called to flip the polarity
 781 * settings of both-edge irq lines to try and catch the next edge.
 782 *
 783 * The attempt is considered successful if:
 784 * - the status bit goes high, indicating that an edge was caught, or
 785 * - the input value of the gpio doesn't change during the attempt.
 786 * If the value changes twice during the process, that would cause the first
 787 * test to fail but would force the second, as two opposite
 788 * transitions would cause a detection no matter the polarity setting.
 789 *
 790 * The do-loop tries to sledge-hammer closed the timing hole between
 791 * the initial value-read and the polarity-write - if the line value changes
 792 * during that window, an interrupt is lost, the new polarity setting is
 793 * incorrect, and the first success test will fail, causing a retry.
 794 *
 795 * Algorithm comes from Google's msmgpio driver.
 796 */
 797static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
 798					  const struct msm_pingroup *g,
 799					  struct irq_data *d)
 800{
 801	int loop_limit = 100;
 802	unsigned val, val2, intstat;
 803	unsigned pol;
 804
 805	do {
 806		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
 807
 808		pol = msm_readl_intr_cfg(pctrl, g);
 809		pol ^= BIT(g->intr_polarity_bit);
 810		msm_writel_intr_cfg(pol, pctrl, g);
 811
 812		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
 813		intstat = msm_readl_intr_status(pctrl, g);
 814		if (intstat || (val == val2))
 815			return;
 816	} while (loop_limit-- > 0);
 817	dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
 818		val, val2);
 819}
 820
 821static void msm_gpio_irq_mask(struct irq_data *d)
 822{
 823	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 824	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 825	const struct msm_pingroup *g;
 826	unsigned long flags;
 827	u32 val;
 828
 829	if (d->parent_data)
 830		irq_chip_mask_parent(d);
 831
 832	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
 833		return;
 834
 835	g = &pctrl->soc->groups[d->hwirq];
 836
 837	raw_spin_lock_irqsave(&pctrl->lock, flags);
 838
 839	val = msm_readl_intr_cfg(pctrl, g);
 840	/*
 841	 * There are two bits that control interrupt forwarding to the CPU. The
 842	 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
 843	 * latched into the interrupt status register when the hardware detects
 844	 * an irq that it's configured for (either edge for edge type or level
 845	 * for level type irq). The 'non-raw' status enable bit causes the
 846	 * hardware to assert the summary interrupt to the CPU if the latched
 847	 * status bit is set. There's a bug though, the edge detection logic
 848	 * seems to have a problem where toggling the RAW_STATUS_EN bit may
 849	 * cause the status bit to latch spuriously when there isn't any edge
 850	 * so we can't touch that bit for edge type irqs and we have to keep
 851	 * the bit set anyway so that edges are latched while the line is masked.
 852	 *
 853	 * To make matters more complicated, leaving the RAW_STATUS_EN bit
 854	 * enabled all the time causes level interrupts to re-latch into the
 855	 * status register because the level is still present on the line after
 856	 * we ack it. We clear the raw status enable bit during mask here and
 857	 * set the bit on unmask so the interrupt can't latch into the hardware
 858	 * while it's masked.
 859	 */
 860	if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
 861		val &= ~BIT(g->intr_raw_status_bit);
 862
 863	val &= ~BIT(g->intr_enable_bit);
 864	msm_writel_intr_cfg(val, pctrl, g);
 865
 866	clear_bit(d->hwirq, pctrl->enabled_irqs);
 867
 868	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 869}
 870
 871static void msm_gpio_irq_unmask(struct irq_data *d)
 872{
 873	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 874	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 875	const struct msm_pingroup *g;
 876	unsigned long flags;
 877	u32 val;
 878
 879	if (d->parent_data)
 880		irq_chip_unmask_parent(d);
 881
 882	if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
 883		return;
 884
 885	g = &pctrl->soc->groups[d->hwirq];
 886
 887	raw_spin_lock_irqsave(&pctrl->lock, flags);
 888
 889	val = msm_readl_intr_cfg(pctrl, g);
 890	val |= BIT(g->intr_raw_status_bit);
 891	val |= BIT(g->intr_enable_bit);
 892	msm_writel_intr_cfg(val, pctrl, g);
 893
 894	set_bit(d->hwirq, pctrl->enabled_irqs);
 895
 896	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 897}
 898
 899static void msm_gpio_irq_enable(struct irq_data *d)
 900{
 901	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 902	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 903
 904	gpiochip_enable_irq(gc, d->hwirq);
 905
 906	if (d->parent_data)
 907		irq_chip_enable_parent(d);
 908
 909	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
 910		msm_gpio_irq_unmask(d);
 911}
 912
 913static void msm_gpio_irq_disable(struct irq_data *d)
 914{
 915	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 916	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 917
 918	if (d->parent_data)
 919		irq_chip_disable_parent(d);
 920
 921	if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
 922		msm_gpio_irq_mask(d);
 923
 924	gpiochip_disable_irq(gc, d->hwirq);
 925}
 926
 927/**
 928 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
 929 * @d: The irq dta.
 930 *
 931 * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
 932 * normally handled by the parent irqchip.  The logic here is slightly
 933 * different due to what's easy to do with our parent, but in principle it's
 934 * the same.
 935 */
 936static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
 937{
 938	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 939	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 940	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
 941	int loop_limit = 100;
 942	unsigned int val;
 943	unsigned int type;
 944
 945	/* Read the value and make a guess about what edge we need to catch */
 946	val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
 947	type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
 948
 949	do {
 950		/* Set the parent to catch the next edge */
 951		irq_chip_set_type_parent(d, type);
 952
 953		/*
 954		 * Possibly the line changed between when we last read "val"
 955		 * (and decided what edge we needed) and when set the edge.
 956		 * If the value didn't change (or changed and then changed
 957		 * back) then we're done.
 958		 */
 959		val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
 960		if (type == IRQ_TYPE_EDGE_RISING) {
 961			if (!val)
 962				return;
 963			type = IRQ_TYPE_EDGE_FALLING;
 964		} else if (type == IRQ_TYPE_EDGE_FALLING) {
 965			if (val)
 966				return;
 967			type = IRQ_TYPE_EDGE_RISING;
 968		}
 969	} while (loop_limit-- > 0);
 970	dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
 971}
 972
 973static void msm_gpio_irq_ack(struct irq_data *d)
 974{
 975	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 976	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
 977	const struct msm_pingroup *g;
 978	unsigned long flags;
 979
 980	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
 981		if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 982			msm_gpio_update_dual_edge_parent(d);
 983		return;
 984	}
 985
 986	g = &pctrl->soc->groups[d->hwirq];
 987
 988	raw_spin_lock_irqsave(&pctrl->lock, flags);
 989
 990	msm_ack_intr_status(pctrl, g);
 991
 992	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
 993		msm_gpio_update_dual_edge_pos(pctrl, g, d);
 994
 995	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 996}
 997
 998static void msm_gpio_irq_eoi(struct irq_data *d)
 999{
1000	d = d->parent_data;
1001
1002	if (d)
1003		d->chip->irq_eoi(d);
1004}
1005
1006static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
1007						       unsigned int type)
1008{
1009	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1010	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1011
1012	return type == IRQ_TYPE_EDGE_BOTH &&
1013	       pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
1014	       test_bit(d->hwirq, pctrl->skip_wake_irqs);
1015}
1016
1017static void msm_gpio_irq_init_valid_mask(struct gpio_chip *gc,
1018					 unsigned long *valid_mask,
1019					 unsigned int ngpios)
1020{
1021	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1022	const struct msm_pingroup *g;
1023	int i;
1024
1025	bitmap_fill(valid_mask, ngpios);
1026
1027	for (i = 0; i < ngpios; i++) {
1028		g = &pctrl->soc->groups[i];
1029
1030		if (g->intr_detection_width != 1 &&
1031		    g->intr_detection_width != 2)
1032			clear_bit(i, valid_mask);
1033	}
1034}
1035
1036static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
1037{
1038	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1039	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1040	const struct msm_pingroup *g;
1041	u32 intr_target_mask = GENMASK(2, 0);
1042	unsigned long flags;
1043	u32 val, oldval;
1044
1045	if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
1046		set_bit(d->hwirq, pctrl->dual_edge_irqs);
1047		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
1048		msm_gpio_update_dual_edge_parent(d);
1049		return 0;
1050	}
1051
1052	if (d->parent_data)
1053		irq_chip_set_type_parent(d, type);
1054
1055	if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
1056		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1057		irq_set_handler_locked(d, handle_fasteoi_irq);
1058		return 0;
1059	}
1060
1061	g = &pctrl->soc->groups[d->hwirq];
1062
1063	raw_spin_lock_irqsave(&pctrl->lock, flags);
1064
1065	/*
1066	 * For hw without possibility of detecting both edges
1067	 */
1068	if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
1069		set_bit(d->hwirq, pctrl->dual_edge_irqs);
1070	else
1071		clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1072
1073	/* Route interrupts to application cpu.
1074	 * With intr_target_use_scm interrupts are routed to
1075	 * application cpu using scm calls.
1076	 */
1077	if (g->intr_target_width)
1078		intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
1079
1080	if (pctrl->intr_target_use_scm) {
1081		u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1082		int ret;
1083
1084		qcom_scm_io_readl(addr, &val);
1085		val &= ~(intr_target_mask << g->intr_target_bit);
1086		val |= g->intr_target_kpss_val << g->intr_target_bit;
1087
1088		ret = qcom_scm_io_writel(addr, val);
1089		if (ret)
1090			dev_err(pctrl->dev,
1091				"Failed routing %lu interrupt to Apps proc",
1092				d->hwirq);
1093	} else {
1094		val = msm_readl_intr_target(pctrl, g);
1095		val &= ~(intr_target_mask << g->intr_target_bit);
1096		val |= g->intr_target_kpss_val << g->intr_target_bit;
1097		msm_writel_intr_target(val, pctrl, g);
1098	}
1099
1100	/* Update configuration for gpio.
1101	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1102	 * internal circuitry of TLMM, toggling the RAW_STATUS
1103	 * could cause the INTR_STATUS to be set for EDGE interrupts.
1104	 */
1105	val = oldval = msm_readl_intr_cfg(pctrl, g);
1106	val |= BIT(g->intr_raw_status_bit);
1107	if (g->intr_detection_width == 2) {
1108		val &= ~(3 << g->intr_detection_bit);
1109		val &= ~(1 << g->intr_polarity_bit);
1110		switch (type) {
1111		case IRQ_TYPE_EDGE_RISING:
1112			val |= 1 << g->intr_detection_bit;
1113			val |= BIT(g->intr_polarity_bit);
1114			break;
1115		case IRQ_TYPE_EDGE_FALLING:
1116			val |= 2 << g->intr_detection_bit;
1117			val |= BIT(g->intr_polarity_bit);
1118			break;
1119		case IRQ_TYPE_EDGE_BOTH:
1120			val |= 3 << g->intr_detection_bit;
1121			val |= BIT(g->intr_polarity_bit);
1122			break;
1123		case IRQ_TYPE_LEVEL_LOW:
1124			break;
1125		case IRQ_TYPE_LEVEL_HIGH:
1126			val |= BIT(g->intr_polarity_bit);
1127			break;
1128		}
1129	} else if (g->intr_detection_width == 1) {
1130		val &= ~(1 << g->intr_detection_bit);
1131		val &= ~(1 << g->intr_polarity_bit);
1132		switch (type) {
1133		case IRQ_TYPE_EDGE_RISING:
1134			val |= BIT(g->intr_detection_bit);
1135			val |= BIT(g->intr_polarity_bit);
1136			break;
1137		case IRQ_TYPE_EDGE_FALLING:
1138			val |= BIT(g->intr_detection_bit);
1139			break;
1140		case IRQ_TYPE_EDGE_BOTH:
1141			val |= BIT(g->intr_detection_bit);
1142			val |= BIT(g->intr_polarity_bit);
1143			break;
1144		case IRQ_TYPE_LEVEL_LOW:
1145			break;
1146		case IRQ_TYPE_LEVEL_HIGH:
1147			val |= BIT(g->intr_polarity_bit);
1148			break;
1149		}
1150	} else {
1151		BUG();
1152	}
1153	msm_writel_intr_cfg(val, pctrl, g);
1154
1155	/*
1156	 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1157	 * Clear the interrupt.  This is safe because we have
1158	 * IRQCHIP_SET_TYPE_MASKED. When changing the interrupt type, we could
1159	 * also still have a non-matching interrupt latched, so clear whenever
1160	 * making changes to the interrupt configuration.
1161	 */
1162	if (val != oldval)
1163		msm_ack_intr_status(pctrl, g);
1164
1165	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1166		msm_gpio_update_dual_edge_pos(pctrl, g, d);
1167
1168	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1169
1170	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1171		irq_set_handler_locked(d, handle_level_irq);
1172	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1173		irq_set_handler_locked(d, handle_edge_irq);
1174
1175	return 0;
1176}
1177
1178static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1179{
1180	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1181	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1182
1183	/*
1184	 * While they may not wake up when the TLMM is powered off,
1185	 * some GPIOs would like to wakeup the system from suspend
1186	 * when TLMM is powered on. To allow that, enable the GPIO
1187	 * summary line to be wakeup capable at GIC.
1188	 */
1189	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1190		return irq_chip_set_wake_parent(d, on);
1191
1192	return irq_set_irq_wake(pctrl->irq, on);
1193}
1194
1195static int msm_gpio_irq_reqres(struct irq_data *d)
1196{
1197	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1198	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1199	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1200	unsigned long flags;
1201	int ret;
1202
1203	if (!try_module_get(gc->owner))
1204		return -ENODEV;
1205
1206	ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1207	if (ret)
1208		goto out;
1209	msm_gpio_direction_input(gc, d->hwirq);
1210
1211	if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1212		dev_err(gc->parent,
1213			"unable to lock HW IRQ %lu for IRQ\n",
1214			d->hwirq);
1215		ret = -EINVAL;
1216		goto out;
1217	}
1218
1219	/*
1220	 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1221	 * only works if disable is not lazy since we only clear any bogus
1222	 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
1223	 */
1224	irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1225
1226	/*
1227	 * If the wakeup_enable bit is present and marked as available for the
1228	 * requested GPIO, it should be enabled when the GPIO is marked as
1229	 * wake irq in order to allow the interrupt event to be transfered to
1230	 * the PDC HW.
1231	 * While the name implies only the wakeup event, it's also required for
1232	 * the interrupt event.
1233	 */
1234	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1235		u32 intr_cfg;
1236
1237		raw_spin_lock_irqsave(&pctrl->lock, flags);
1238
1239		intr_cfg = msm_readl_intr_cfg(pctrl, g);
1240		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1241			intr_cfg |= BIT(g->intr_wakeup_enable_bit);
1242			msm_writel_intr_cfg(intr_cfg, pctrl, g);
1243		}
1244
1245		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1246	}
1247
1248	return 0;
1249out:
1250	module_put(gc->owner);
1251	return ret;
1252}
1253
1254static void msm_gpio_irq_relres(struct irq_data *d)
1255{
1256	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1257	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1258	const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
1259	unsigned long flags;
1260
1261	/* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */
1262	if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) {
1263		u32 intr_cfg;
1264
1265		raw_spin_lock_irqsave(&pctrl->lock, flags);
1266
1267		intr_cfg = msm_readl_intr_cfg(pctrl, g);
1268		if (intr_cfg & BIT(g->intr_wakeup_present_bit)) {
1269			intr_cfg &= ~BIT(g->intr_wakeup_enable_bit);
1270			msm_writel_intr_cfg(intr_cfg, pctrl, g);
1271		}
1272
1273		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1274	}
1275
1276	gpiochip_unlock_as_irq(gc, d->hwirq);
1277	module_put(gc->owner);
1278}
1279
1280static int msm_gpio_irq_set_affinity(struct irq_data *d,
1281				const struct cpumask *dest, bool force)
1282{
1283	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1284	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1285
1286	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1287		return irq_chip_set_affinity_parent(d, dest, force);
1288
1289	return -EINVAL;
1290}
1291
1292static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1293{
1294	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1295	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1296
1297	if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1298		return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1299
1300	return -EINVAL;
1301}
1302
1303static void msm_gpio_irq_handler(struct irq_desc *desc)
1304{
1305	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1306	const struct msm_pingroup *g;
1307	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1308	struct irq_chip *chip = irq_desc_get_chip(desc);
1309	int handled = 0;
1310	u32 val;
1311	int i;
1312
1313	chained_irq_enter(chip, desc);
1314
1315	/*
1316	 * Each pin has it's own IRQ status register, so use
1317	 * enabled_irq bitmap to limit the number of reads.
1318	 */
1319	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1320		g = &pctrl->soc->groups[i];
1321		val = msm_readl_intr_status(pctrl, g);
1322		if (val & BIT(g->intr_status_bit)) {
1323			generic_handle_domain_irq(gc->irq.domain, i);
1324			handled++;
1325		}
1326	}
1327
1328	/* No interrupts were flagged */
1329	if (handled == 0)
1330		handle_bad_irq(desc);
1331
1332	chained_irq_exit(chip, desc);
1333}
1334
1335static int msm_gpio_wakeirq(struct gpio_chip *gc,
1336			    unsigned int child,
1337			    unsigned int child_type,
1338			    unsigned int *parent,
1339			    unsigned int *parent_type)
1340{
1341	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1342	const struct msm_gpio_wakeirq_map *map;
1343	int i;
1344
1345	*parent = GPIO_NO_WAKE_IRQ;
1346	*parent_type = IRQ_TYPE_EDGE_RISING;
1347
1348	for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1349		map = &pctrl->soc->wakeirq_map[i];
1350		if (map->gpio == child) {
1351			*parent = map->wakeirq;
1352			break;
1353		}
1354	}
1355
1356	return 0;
1357}
1358
1359static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1360{
1361	if (pctrl->soc->reserved_gpios)
1362		return true;
1363
1364	return device_property_count_u16(pctrl->dev, "gpios") > 0;
1365}
1366
1367static const struct irq_chip msm_gpio_irq_chip = {
1368	.name			= "msmgpio",
1369	.irq_enable		= msm_gpio_irq_enable,
1370	.irq_disable		= msm_gpio_irq_disable,
1371	.irq_mask		= msm_gpio_irq_mask,
1372	.irq_unmask		= msm_gpio_irq_unmask,
1373	.irq_ack		= msm_gpio_irq_ack,
1374	.irq_eoi		= msm_gpio_irq_eoi,
1375	.irq_set_type		= msm_gpio_irq_set_type,
1376	.irq_set_wake		= msm_gpio_irq_set_wake,
1377	.irq_request_resources	= msm_gpio_irq_reqres,
1378	.irq_release_resources	= msm_gpio_irq_relres,
1379	.irq_set_affinity	= msm_gpio_irq_set_affinity,
1380	.irq_set_vcpu_affinity	= msm_gpio_irq_set_vcpu_affinity,
1381	.flags			= (IRQCHIP_MASK_ON_SUSPEND |
1382				   IRQCHIP_SET_TYPE_MASKED |
1383				   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND |
1384				   IRQCHIP_IMMUTABLE),
1385};
1386
1387static int msm_gpio_init(struct msm_pinctrl *pctrl)
1388{
1389	struct gpio_chip *chip;
1390	struct gpio_irq_chip *girq;
1391	int i, ret;
1392	unsigned gpio, ngpio = pctrl->soc->ngpios;
1393	struct device_node *np;
1394	bool skip;
1395
1396	if (WARN_ON(ngpio > MAX_NR_GPIO))
1397		return -EINVAL;
1398
1399	chip = &pctrl->chip;
1400	chip->base = -1;
1401	chip->ngpio = ngpio;
1402	chip->label = dev_name(pctrl->dev);
1403	chip->parent = pctrl->dev;
1404	chip->owner = THIS_MODULE;
1405	if (msm_gpio_needs_valid_mask(pctrl))
1406		chip->init_valid_mask = msm_gpio_init_valid_mask;
1407
1408	np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1409	if (np) {
1410		chip->irq.parent_domain = irq_find_matching_host(np,
1411						 DOMAIN_BUS_WAKEUP);
1412		of_node_put(np);
1413		if (!chip->irq.parent_domain)
1414			return -EPROBE_DEFER;
1415		chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1416		/*
1417		 * Let's skip handling the GPIOs, if the parent irqchip
1418		 * is handling the direct connect IRQ of the GPIO.
1419		 */
1420		skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1421		for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1422			gpio = pctrl->soc->wakeirq_map[i].gpio;
1423			set_bit(gpio, pctrl->skip_wake_irqs);
1424		}
1425	}
1426
1427	girq = &chip->irq;
1428	gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip);
1429	girq->parent_handler = msm_gpio_irq_handler;
1430	girq->fwnode = dev_fwnode(pctrl->dev);
1431	girq->num_parents = 1;
1432	girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1433				     GFP_KERNEL);
1434	if (!girq->parents)
1435		return -ENOMEM;
1436	girq->default_type = IRQ_TYPE_NONE;
1437	girq->handler = handle_bad_irq;
1438	girq->parents[0] = pctrl->irq;
1439	girq->init_valid_mask = msm_gpio_irq_init_valid_mask;
1440
1441	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1442	if (ret) {
1443		dev_err(pctrl->dev, "Failed register gpiochip\n");
1444		return ret;
1445	}
1446
1447	/*
1448	 * For DeviceTree-supported systems, the gpio core checks the
1449	 * pinctrl's device node for the "gpio-ranges" property.
1450	 * If it is present, it takes care of adding the pin ranges
1451	 * for the driver. In this case the driver can skip ahead.
1452	 *
1453	 * In order to remain compatible with older, existing DeviceTree
1454	 * files which don't set the "gpio-ranges" property or systems that
1455	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1456	 */
1457	if (!of_property_present(pctrl->dev->of_node, "gpio-ranges")) {
1458		ret = gpiochip_add_pin_range(&pctrl->chip,
1459			dev_name(pctrl->dev), 0, 0, chip->ngpio);
1460		if (ret) {
1461			dev_err(pctrl->dev, "Failed to add pin range\n");
1462			return ret;
1463		}
1464	}
1465
1466	return 0;
1467}
1468
1469static int msm_ps_hold_restart(struct sys_off_data *data)
1470{
1471	struct msm_pinctrl *pctrl = data->cb_data;
1472
1473	writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1474	mdelay(1000);
1475	return NOTIFY_DONE;
1476}
1477
1478static struct msm_pinctrl *poweroff_pctrl;
1479
1480static void msm_ps_hold_poweroff(void)
1481{
1482	struct sys_off_data data = {
1483		.cb_data = poweroff_pctrl,
1484	};
1485
1486	msm_ps_hold_restart(&data);
1487}
1488
1489static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1490{
1491	int i;
1492	const struct pinfunction *func = pctrl->soc->functions;
1493
1494	for (i = 0; i < pctrl->soc->nfunctions; i++)
1495		if (!strcmp(func[i].name, "ps_hold")) {
1496			if (devm_register_sys_off_handler(pctrl->dev,
1497							  SYS_OFF_MODE_RESTART,
1498							  128,
1499							  msm_ps_hold_restart,
1500							  pctrl))
1501				dev_err(pctrl->dev,
1502					"failed to setup restart handler.\n");
1503			poweroff_pctrl = pctrl;
1504			pm_power_off = msm_ps_hold_poweroff;
1505			break;
1506		}
1507}
1508
1509static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1510{
1511	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1512
1513	return pinctrl_force_sleep(pctrl->pctrl);
1514}
1515
1516static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1517{
1518	struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1519
1520	return pinctrl_force_default(pctrl->pctrl);
1521}
1522
1523SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1524		  msm_pinctrl_resume);
1525
1526EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1527
1528int msm_pinctrl_probe(struct platform_device *pdev,
1529		      const struct msm_pinctrl_soc_data *soc_data)
1530{
1531	const struct pinfunction *func;
1532	struct msm_pinctrl *pctrl;
1533	struct resource *res;
1534	int ret;
1535	int i;
1536
1537	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1538	if (!pctrl)
1539		return -ENOMEM;
1540
1541	pctrl->dev = &pdev->dev;
1542	pctrl->soc = soc_data;
1543	pctrl->chip = msm_gpio_template;
1544	pctrl->intr_target_use_scm = of_device_is_compatible(
1545					pctrl->dev->of_node,
1546					"qcom,ipq8064-pinctrl");
1547
1548	raw_spin_lock_init(&pctrl->lock);
1549
1550	if (soc_data->tiles) {
1551		for (i = 0; i < soc_data->ntiles; i++) {
1552			res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1553							   soc_data->tiles[i]);
1554			pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1555			if (IS_ERR(pctrl->regs[i]))
1556				return PTR_ERR(pctrl->regs[i]);
1557		}
1558	} else {
1559		pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1560		if (IS_ERR(pctrl->regs[0]))
1561			return PTR_ERR(pctrl->regs[0]);
1562
1563		pctrl->phys_base[0] = res->start;
1564	}
1565
1566	msm_pinctrl_setup_pm_reset(pctrl);
1567
1568	pctrl->irq = platform_get_irq(pdev, 0);
1569	if (pctrl->irq < 0)
1570		return pctrl->irq;
1571
1572	pctrl->desc.owner = THIS_MODULE;
1573	pctrl->desc.pctlops = &msm_pinctrl_ops;
1574	pctrl->desc.pmxops = &msm_pinmux_ops;
1575	pctrl->desc.confops = &msm_pinconf_ops;
1576	pctrl->desc.name = dev_name(&pdev->dev);
1577	pctrl->desc.pins = pctrl->soc->pins;
1578	pctrl->desc.npins = pctrl->soc->npins;
1579
1580	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1581	if (IS_ERR(pctrl->pctrl)) {
1582		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1583		return PTR_ERR(pctrl->pctrl);
1584	}
1585
1586	for (i = 0; i < soc_data->nfunctions; i++) {
1587		func = &soc_data->functions[i];
1588
1589		ret = pinmux_generic_add_pinfunction(pctrl->pctrl, func, NULL);
1590		if (ret < 0)
1591			return ret;
1592	}
1593
1594	ret = msm_gpio_init(pctrl);
1595	if (ret)
1596		return ret;
1597
1598	platform_set_drvdata(pdev, pctrl);
1599
1600	dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1601
1602	return 0;
1603}
1604EXPORT_SYMBOL(msm_pinctrl_probe);
1605
1606MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1607MODULE_LICENSE("GPL v2");