pinctrl-lpass-lpi.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2020 Linaro Ltd.
  5 */
  6
  7#include <linux/bitfield.h>
  8#include <linux/clk.h>
  9#include <linux/gpio/driver.h>
 10#include <linux/module.h>
 11#include <linux/of.h>
 12#include <linux/platform_device.h>
 13#include <linux/seq_file.h>
 14
 15#include <linux/pinctrl/pinconf-generic.h>
 16#include <linux/pinctrl/pinconf.h>
 17#include <linux/pinctrl/pinmux.h>
 18
 19#include "../pinctrl-utils.h"
 20
 21#include "pinctrl-lpass-lpi.h"
 22
 23#define MAX_NR_GPIO		32
 24#define GPIO_FUNC		0
 25#define MAX_LPI_NUM_CLKS	2
 26
 27struct lpi_pinctrl {
 28	struct device *dev;
 29	struct pinctrl_dev *ctrl;
 30	struct gpio_chip chip;
 31	struct pinctrl_desc desc;
 32	char __iomem *tlmm_base;
 33	char __iomem *slew_base;
 34	struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
 35	/* Protects from concurrent register updates */
 36	struct mutex lock;
 37	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
 38	const struct lpi_pinctrl_variant_data *data;
 39};
 40
 41static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
 42			 unsigned int addr)
 43{
 44	u32 pin_offset;
 45
 46	if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
 47		pin_offset = state->data->groups[pin].pin_offset;
 48	else
 49		pin_offset = LPI_TLMM_REG_OFFSET * pin;
 50
 51	return ioread32(state->tlmm_base + pin_offset + addr);
 52}
 53
 54static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
 55			  unsigned int addr, unsigned int val)
 56{
 57	u32 pin_offset;
 58
 59	if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)
 60		pin_offset = state->data->groups[pin].pin_offset;
 61	else
 62		pin_offset = LPI_TLMM_REG_OFFSET * pin;
 63
 64	iowrite32(val, state->tlmm_base + pin_offset + addr);
 65
 66	return 0;
 67}
 68
 69static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
 70	.get_groups_count	= pinctrl_generic_get_group_count,
 71	.get_group_name		= pinctrl_generic_get_group_name,
 72	.get_group_pins		= pinctrl_generic_get_group_pins,
 73	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
 74	.dt_free_map		= pinctrl_utils_free_map,
 75};
 76
 77static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
 78{
 79	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 80
 81	return pctrl->data->nfunctions;
 82}
 83
 84static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
 85					      unsigned int function)
 86{
 87	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 88
 89	return pctrl->data->functions[function].name;
 90}
 91
 92static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
 93					unsigned int function,
 94					const char *const **groups,
 95					unsigned *const num_qgroups)
 96{
 97	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 98
 99	*groups = pctrl->data->functions[function].groups;
100	*num_qgroups = pctrl->data->functions[function].ngroups;
101
102	return 0;
103}
104
105static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
106			    unsigned int group)
107{
108	struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
109	const struct lpi_pingroup *g = &pctrl->data->groups[group];
110	u32 val;
111	int i, pin = g->pin;
112
113	for (i = 0; i < g->nfuncs; i++) {
114		if (g->funcs[i] == function)
115			break;
116	}
117
118	if (WARN_ON(i == g->nfuncs))
119		return -EINVAL;
120
121	mutex_lock(&pctrl->lock);
122	val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
123
124	/*
125	 * If this is the first time muxing to GPIO and the direction is
126	 * output, make sure that we're not going to be glitching the pin
127	 * by reading the current state of the pin and setting it as the
128	 * output.
129	 */
130	if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) &&
131	    !test_and_set_bit(group, pctrl->ever_gpio)) {
132		u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG);
133
134		if (io_val & LPI_GPIO_VALUE_IN_MASK) {
135			if (!(io_val & LPI_GPIO_VALUE_OUT_MASK))
136				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
137					       io_val | LPI_GPIO_VALUE_OUT_MASK);
138		} else {
139			if (io_val & LPI_GPIO_VALUE_OUT_MASK)
140				lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG,
141					       io_val & ~LPI_GPIO_VALUE_OUT_MASK);
142		}
143	}
144
145	u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
146	lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
147	mutex_unlock(&pctrl->lock);
148
149	return 0;
150}
151
152static const struct pinmux_ops lpi_gpio_pinmux_ops = {
153	.get_functions_count	= lpi_gpio_get_functions_count,
154	.get_function_name	= lpi_gpio_get_function_name,
155	.get_function_groups	= lpi_gpio_get_function_groups,
156	.set_mux		= lpi_gpio_set_mux,
157};
158
159static int lpi_config_get(struct pinctrl_dev *pctldev,
160			  unsigned int pin, unsigned long *config)
161{
162	unsigned int param = pinconf_to_config_param(*config);
163	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
164	unsigned int arg = 0;
165	int is_out;
166	int pull;
167	u32 ctl_reg;
168
169	ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
170	is_out = ctl_reg & LPI_GPIO_OE_MASK;
171	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
172
173	switch (param) {
174	case PIN_CONFIG_BIAS_DISABLE:
175		if (pull == LPI_GPIO_BIAS_DISABLE)
176			arg = 1;
177		break;
178	case PIN_CONFIG_BIAS_PULL_DOWN:
179		if (pull == LPI_GPIO_PULL_DOWN)
180			arg = 1;
181		break;
182	case PIN_CONFIG_BIAS_BUS_HOLD:
183		if (pull == LPI_GPIO_KEEPER)
184			arg = 1;
185		break;
186	case PIN_CONFIG_BIAS_PULL_UP:
187		if (pull == LPI_GPIO_PULL_UP)
188			arg = 1;
189		break;
190	case PIN_CONFIG_INPUT_ENABLE:
191	case PIN_CONFIG_LEVEL:
192		if (is_out)
193			arg = 1;
194		break;
195	default:
196		return -EINVAL;
197	}
198
199	*config = pinconf_to_config_packed(param, arg);
200	return 0;
201}
202
203static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
204				    const struct lpi_pingroup *g,
205				    unsigned int group, unsigned int slew)
206{
207	unsigned long sval;
208	void __iomem *reg;
209	int slew_offset;
210
211	if (slew > LPI_SLEW_RATE_MAX) {
212		dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
213			slew, group);
214		return -EINVAL;
215	}
216
217	slew_offset = g->slew_offset;
218	if (slew_offset == LPI_NO_SLEW)
219		return 0;
220
221	if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
222		reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
223	else
224		reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
225
226	mutex_lock(&pctrl->lock);
227
228	sval = ioread32(reg);
229	sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
230	sval |= slew << slew_offset;
231	iowrite32(sval, reg);
232
233	mutex_unlock(&pctrl->lock);
234
235	return 0;
236}
237
238static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
239			  unsigned long *configs, unsigned int nconfs)
240{
241	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
242	unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
243	bool value, output_enabled = false;
244	const struct lpi_pingroup *g;
245	int i, ret;
246	u32 val;
247
248	g = &pctrl->data->groups[group];
249	for (i = 0; i < nconfs; i++) {
250		param = pinconf_to_config_param(configs[i]);
251		arg = pinconf_to_config_argument(configs[i]);
252
253		switch (param) {
254		case PIN_CONFIG_BIAS_DISABLE:
255			pullup = LPI_GPIO_BIAS_DISABLE;
256			break;
257		case PIN_CONFIG_BIAS_PULL_DOWN:
258			pullup = LPI_GPIO_PULL_DOWN;
259			break;
260		case PIN_CONFIG_BIAS_BUS_HOLD:
261			pullup = LPI_GPIO_KEEPER;
262			break;
263		case PIN_CONFIG_BIAS_PULL_UP:
264			pullup = LPI_GPIO_PULL_UP;
265			break;
266		case PIN_CONFIG_INPUT_ENABLE:
267			output_enabled = false;
268			break;
269		case PIN_CONFIG_LEVEL:
270			output_enabled = true;
271			value = arg;
272			break;
273		case PIN_CONFIG_DRIVE_STRENGTH:
274			strength = arg;
275			break;
276		case PIN_CONFIG_SLEW_RATE:
277			ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
278			if (ret)
279				return ret;
280			break;
281		default:
282			return -EINVAL;
283		}
284	}
285
286	/*
287	 * As per Hardware Programming Guide, when configuring pin as output,
288	 * set the pin value before setting output-enable (OE).
289	 */
290	if (output_enabled) {
291		val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
292		lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
293	}
294
295	mutex_lock(&pctrl->lock);
296	val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
297
298	u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
299	u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
300			  LPI_GPIO_OUT_STRENGTH_MASK);
301	u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
302
303	lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
304	mutex_unlock(&pctrl->lock);
305
306	return 0;
307}
308
309static const struct pinconf_ops lpi_gpio_pinconf_ops = {
310	.is_generic			= true,
311	.pin_config_group_get		= lpi_config_get,
312	.pin_config_group_set		= lpi_config_set,
313};
314
315static int lpi_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
316{
317	unsigned long config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, 0);
318	struct lpi_pinctrl *state = gpiochip_get_data(chip);
319	unsigned long arg;
320	int ret;
321
322	ret = lpi_config_get(state->ctrl, pin, &config);
323	if (ret)
324		return ret;
325
326	arg = pinconf_to_config_argument(config);
327
328	return arg ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
329}
330
331static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
332{
333	struct lpi_pinctrl *state = gpiochip_get_data(chip);
334	unsigned long config;
335
336	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
337
338	return lpi_config_set(state->ctrl, pin, &config, 1);
339}
340
341static int lpi_gpio_direction_output(struct gpio_chip *chip,
342				     unsigned int pin, int val)
343{
344	struct lpi_pinctrl *state = gpiochip_get_data(chip);
345	unsigned long config;
346
347	config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
348
349	return lpi_config_set(state->ctrl, pin, &config, 1);
350}
351
352static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
353{
354	struct lpi_pinctrl *state = gpiochip_get_data(chip);
355
356	return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
357		LPI_GPIO_VALUE_IN_MASK;
358}
359
360static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
361{
362	struct lpi_pinctrl *state = gpiochip_get_data(chip);
363	unsigned long config;
364
365	config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
366
367	return lpi_config_set(state->ctrl, pin, &config, 1);
368}
369
370#ifdef CONFIG_DEBUG_FS
371
372static unsigned int lpi_regval_to_drive(u32 val)
373{
374	return (val + 1) * 2;
375}
376
377static void lpi_gpio_dbg_show_one(struct seq_file *s,
378				  struct pinctrl_dev *pctldev,
379				  struct gpio_chip *chip,
380				  unsigned int offset,
381				  unsigned int gpio)
382{
383	struct lpi_pinctrl *state = gpiochip_get_data(chip);
384	struct pinctrl_pin_desc pindesc;
385	unsigned int func;
386	int is_out;
387	int drive;
388	int pull;
389	u32 ctl_reg;
390
391	static const char * const pulls[] = {
392		"no pull",
393		"pull down",
394		"keeper",
395		"pull up"
396	};
397
398	pctldev = pctldev ? : state->ctrl;
399	pindesc = pctldev->desc->pins[offset];
400	ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
401	is_out = ctl_reg & LPI_GPIO_OE_MASK;
402
403	func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
404	drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
405	pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
406
407	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
408	seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
409	seq_printf(s, " %s", pulls[pull]);
410}
411
412static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
413{
414	unsigned int gpio = chip->base;
415	unsigned int i;
416
417	for (i = 0; i < chip->ngpio; i++, gpio++) {
418		lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
419		seq_puts(s, "\n");
420	}
421}
422
423#else
424#define lpi_gpio_dbg_show NULL
425#endif
426
427static const struct gpio_chip lpi_gpio_template = {
428	.get_direction		= lpi_gpio_get_direction,
429	.direction_input	= lpi_gpio_direction_input,
430	.direction_output	= lpi_gpio_direction_output,
431	.get			= lpi_gpio_get,
432	.set			= lpi_gpio_set,
433	.request		= gpiochip_generic_request,
434	.free			= gpiochip_generic_free,
435	.dbg_show		= lpi_gpio_dbg_show,
436};
437
438static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
439{
440	int i, ret;
441
442	for (i = 0; i < pctrl->data->npins; i++) {
443		const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
444
445		ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
446						  (int *)&pin_info->number, 1, NULL);
447		if (ret < 0)
448			goto err_pinctrl;
449	}
450
451	return 0;
452
453err_pinctrl:
454	for (; i > 0; i--)
455		pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
456
457	return ret;
458}
459
460int lpi_pinctrl_probe(struct platform_device *pdev)
461{
462	const struct lpi_pinctrl_variant_data *data;
463	struct device *dev = &pdev->dev;
464	struct lpi_pinctrl *pctrl;
465	int ret;
466
467	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
468	if (!pctrl)
469		return -ENOMEM;
470
471	platform_set_drvdata(pdev, pctrl);
472
473	data = of_device_get_match_data(dev);
474	if (!data)
475		return -EINVAL;
476
477	if (WARN_ON(data->npins > MAX_NR_GPIO))
478		return -EINVAL;
479
480	pctrl->data = data;
481	pctrl->dev = &pdev->dev;
482
483	pctrl->clks[0].id = "core";
484	pctrl->clks[1].id = "audio";
485
486	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
487	if (IS_ERR(pctrl->tlmm_base))
488		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
489				     "TLMM resource not provided\n");
490
491	if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) {
492		pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
493		if (IS_ERR(pctrl->slew_base))
494			return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
495					     "Slew resource not provided\n");
496	}
497
498	ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
499	if (ret)
500		return ret;
501
502	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
503	if (ret)
504		return dev_err_probe(dev, ret, "Can't enable clocks\n");
505
506	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
507	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
508	pctrl->desc.confops = &lpi_gpio_pinconf_ops;
509	pctrl->desc.owner = THIS_MODULE;
510	pctrl->desc.name = dev_name(dev);
511	pctrl->desc.pins = data->pins;
512	pctrl->desc.npins = data->npins;
513	pctrl->chip = lpi_gpio_template;
514	pctrl->chip.parent = dev;
515	pctrl->chip.base = -1;
516	pctrl->chip.ngpio = data->npins;
517	pctrl->chip.label = dev_name(dev);
518	pctrl->chip.can_sleep = true;
519
520	mutex_init(&pctrl->lock);
521
522	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
523	if (IS_ERR(pctrl->ctrl)) {
524		ret = PTR_ERR(pctrl->ctrl);
525		dev_err(dev, "failed to add pin controller\n");
526		goto err_pinctrl;
527	}
528
529	ret = lpi_build_pin_desc_groups(pctrl);
530	if (ret)
531		goto err_pinctrl;
532
533	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
534	if (ret) {
535		dev_err(pctrl->dev, "can't add gpio chip\n");
536		goto err_pinctrl;
537	}
538
539	return 0;
540
541err_pinctrl:
542	mutex_destroy(&pctrl->lock);
543	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
544
545	return ret;
546}
547EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
548
549void lpi_pinctrl_remove(struct platform_device *pdev)
550{
551	struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
552	int i;
553
554	mutex_destroy(&pctrl->lock);
555	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
556
557	for (i = 0; i < pctrl->data->npins; i++)
558		pinctrl_generic_remove_group(pctrl->ctrl, i);
559}
560EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
561
562MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
563MODULE_LICENSE("GPL");