pinctrl-pxa2xx.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Marvell PXA2xx family pin control
  4 *
  5 * Copyright (C) 2015 Robert Jarzmik
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/io.h>
 10#include <linux/of.h>
 11#include <linux/of_address.h>
 12#include <linux/module.h>
 13#include <linux/pinctrl/machine.h>
 14#include <linux/pinctrl/pinconf.h>
 15#include <linux/pinctrl/pinconf-generic.h>
 16#include <linux/pinctrl/pinmux.h>
 17#include <linux/pinctrl/pinctrl.h>
 18#include <linux/platform_device.h>
 19#include <linux/slab.h>
 20
 21#include "../pinctrl-utils.h"
 22#include "pinctrl-pxa2xx.h"
 23
 24static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 25{
 26	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 27
 28	return pctl->ngroups;
 29}
 30
 31static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 32					       unsigned tgroup)
 33{
 34	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 35	struct pingroup *group = pctl->groups + tgroup;
 36
 37	return group->name;
 38}
 39
 40static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 41				       unsigned tgroup,
 42				       const unsigned **pins,
 43				       unsigned *num_pins)
 44{
 45	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 46	struct pingroup *group = pctl->groups + tgroup;
 47
 48	*pins = group->pins;
 49	*num_pins = group->npins;
 50
 51	return 0;
 52}
 53
 54static const struct pinctrl_ops pxa2xx_pctl_ops = {
 55#ifdef CONFIG_OF
 56	.dt_node_to_map		= pinconf_generic_dt_node_to_map_all,
 57	.dt_free_map		= pinctrl_utils_free_map,
 58#endif
 59	.get_groups_count	= pxa2xx_pctrl_get_groups_count,
 60	.get_group_name		= pxa2xx_pctrl_get_group_name,
 61	.get_group_pins		= pxa2xx_pctrl_get_group_pins,
 62};
 63
 64static struct pxa_desc_function *
 65pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name,
 66		       const char *func_name)
 67{
 68	int i;
 69	struct pxa_desc_function *df;
 70
 71	for (i = 0; i < pctl->npins; i++) {
 72		const struct pxa_desc_pin *pin = pctl->ppins + i;
 73
 74		if (!strcmp(pin->pin.name, pin_name))
 75			for (df = pin->functions; df->name; df++)
 76				if (!strcmp(df->name, func_name))
 77					return df;
 78	}
 79
 80	return NULL;
 81}
 82
 83static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 84					 struct pinctrl_gpio_range *range,
 85					 unsigned pin,
 86					 bool input)
 87{
 88	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 89	unsigned long flags;
 90	uint32_t val;
 91	void __iomem *gpdr;
 92
 93	gpdr = pctl->base_gpdr[pin / 32];
 94	dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n",
 95		pin, !input);
 96
 97	spin_lock_irqsave(&pctl->lock, flags);
 98
 99	val = readl_relaxed(gpdr);
100	val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32));
101	writel_relaxed(val, gpdr);
102
103	spin_unlock_irqrestore(&pctl->lock, flags);
104
105	return 0;
106}
107
108static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
109					    unsigned function)
110{
111	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
112	struct pinfunction *pf = pctl->functions + function;
113
114	return pf->name;
115}
116
117static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev)
118{
119	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
120
121	return pctl->nfuncs;
122}
123
124static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
125				      unsigned function,
126				      const char * const **groups,
127				      unsigned * const num_groups)
128{
129	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
130	struct pinfunction *pf = pctl->functions + function;
131
132	*groups = pf->groups;
133	*num_groups = pf->ngroups;
134
135	return 0;
136}
137
138static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function,
139			      unsigned tgroup)
140{
141	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
142	struct pingroup *g = pctl->groups + tgroup;
143	unsigned int pin = g->pins[0];
144	struct pxa_desc_function *df;
145	unsigned long flags;
146	void __iomem *gafr, *gpdr;
147	int shift;
148	u32 val;
149
150	df = pxa_desc_by_func_group(pctl, g->name, (pctl->functions + function)->name);
151	if (!df)
152		return -EINVAL;
153
154	gafr = pctl->base_gafr[pin / 16];
155	gpdr = pctl->base_gpdr[pin / 32];
156	shift = (pin % 16) << 1;
157	dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n",
158		pin, df->muxval >> 1, df->muxval & 0x1);
159
160	spin_lock_irqsave(&pctl->lock, flags);
161
162	val = readl_relaxed(gafr);
163	val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift);
164	writel_relaxed(val, gafr);
165
166	val = readl_relaxed(gpdr);
167	val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0);
168	writel_relaxed(val, gpdr);
169
170	spin_unlock_irqrestore(&pctl->lock, flags);
171
172	return 0;
173}
174static const struct pinmux_ops pxa2xx_pinmux_ops = {
175	.get_functions_count = pxa2xx_get_functions_count,
176	.get_function_name = pxa2xx_pmx_get_func_name,
177	.get_function_groups = pxa2xx_pmx_get_func_groups,
178	.set_mux = pxa2xx_pmx_set_mux,
179	.gpio_set_direction = pxa2xx_pmx_gpio_set_direction,
180};
181
182static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev,
183				  unsigned group,
184				  unsigned long *config)
185{
186	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
187	struct pingroup *g = pctl->groups + group;
188	unsigned int pin = g->pins[0];
189	unsigned long flags;
190	void __iomem *pgsr = pctl->base_pgsr[pin / 32];
191	u32 val;
192
193	spin_lock_irqsave(&pctl->lock, flags);
194	val = readl_relaxed(pgsr) & BIT(pin % 32);
195	*config = val ? PIN_CONFIG_MODE_LOW_POWER : 0;
196	spin_unlock_irqrestore(&pctl->lock, flags);
197
198	dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
199		pin, !!val);
200	return 0;
201}
202
203static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev,
204				  unsigned group,
205				  unsigned long *configs,
206				  unsigned num_configs)
207{
208	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
209	struct pingroup *g = pctl->groups + group;
210	unsigned int pin = g->pins[0];
211	unsigned long flags;
212	void __iomem *pgsr = pctl->base_pgsr[pin / 32];
213	int i, is_set = 0;
214	u32 val;
215
216	for (i = 0; i < num_configs; i++) {
217		switch (pinconf_to_config_param(configs[i])) {
218		case PIN_CONFIG_MODE_LOW_POWER:
219			is_set = pinconf_to_config_argument(configs[i]);
220			break;
221		default:
222			return -EINVAL;
223		}
224	}
225
226	dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n",
227		pin, is_set);
228
229	spin_lock_irqsave(&pctl->lock, flags);
230	val = readl_relaxed(pgsr);
231	val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0);
232	writel_relaxed(val, pgsr);
233	spin_unlock_irqrestore(&pctl->lock, flags);
234
235	return 0;
236}
237
238static const struct pinconf_ops pxa2xx_pconf_ops = {
239	.pin_config_group_get	= pxa2xx_pconf_group_get,
240	.pin_config_group_set	= pxa2xx_pconf_group_set,
241	.is_generic		= true,
242};
243
244static struct pinctrl_desc pxa2xx_pinctrl_desc = {
245	.confops	= &pxa2xx_pconf_ops,
246	.pctlops	= &pxa2xx_pctl_ops,
247	.pmxops		= &pxa2xx_pinmux_ops,
248};
249
250static const struct pinfunction *pxa2xx_find_function(struct pxa_pinctrl *pctl,
251						      const char *fname,
252						      const struct pinfunction *functions)
253{
254	const struct pinfunction *func;
255
256	for (func = functions; func->name; func++)
257		if (!strcmp(fname, func->name))
258			return func;
259
260	return NULL;
261}
262
263static int pxa2xx_build_functions(struct pxa_pinctrl *pctl)
264{
265	struct pinfunction *functions;
266	int i;
267	struct pxa_desc_function *df;
268
269	/*
270	 * Each pin can have at most 6 alternate functions, and 2 gpio functions
271	 * which are common to each pin. As there are more than 2 pins without
272	 * alternate function, 6 * npins is an absolute high limit of the number
273	 * of functions.
274	 */
275	functions = devm_kcalloc(pctl->dev, pctl->npins * 6,
276				 sizeof(*functions), GFP_KERNEL);
277	if (!functions)
278		return -ENOMEM;
279
280	for (i = 0; i < pctl->npins; i++)
281		for (df = pctl->ppins[i].functions; df->name; df++)
282			if (!pxa2xx_find_function(pctl, df->name, functions))
283				(functions + pctl->nfuncs++)->name = df->name;
284	pctl->functions = devm_kmemdup_array(pctl->dev, functions, pctl->nfuncs,
285					     sizeof(*functions), GFP_KERNEL);
286	if (!pctl->functions)
287		return -ENOMEM;
288
289	devm_kfree(pctl->dev, functions);
290	return 0;
291}
292
293static int pxa2xx_build_groups(struct pxa_pinctrl *pctl)
294{
295	int i, j, ngroups;
296	struct pxa_desc_function *df;
297	struct pinfunction *func;
298	const char **gtmp;
299
300	gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp),
301				  GFP_KERNEL);
302	if (!gtmp)
303		return -ENOMEM;
304
305	for (i = 0; i < pctl->nfuncs; i++) {
306		ngroups = 0;
307		for (j = 0; j < pctl->npins; j++)
308			for (df = pctl->ppins[j].functions; df->name;
309			     df++)
310				if (!strcmp(pctl->functions[i].name,
311					    df->name))
312					gtmp[ngroups++] = (char *)
313						pctl->ppins[j].pin.name;
314		func = pctl->functions + i;
315		func->ngroups = ngroups;
316		func->groups = devm_kmemdup_array(pctl->dev, gtmp, ngroups,
317						  sizeof(*gtmp), GFP_KERNEL);
318		if (!func->groups)
319			return -ENOMEM;
320	}
321
322	devm_kfree(pctl->dev, gtmp);
323	return 0;
324}
325
326static int pxa2xx_build_state(struct pxa_pinctrl *pctl,
327			      const struct pxa_desc_pin *ppins, int npins)
328{
329	struct pinctrl_pin_desc *pins;
330	struct pingroup *group;
331	int ret, i;
332
333	pctl->npins = npins;
334	pctl->ppins = ppins;
335	pctl->ngroups = npins;
336
337	pctl->desc.npins = npins;
338	pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL);
339	if (!pins)
340		return -ENOMEM;
341
342	pctl->desc.pins = pins;
343	for (i = 0; i < npins; i++)
344		pins[i] = ppins[i].pin;
345
346	pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups,
347					  sizeof(*pctl->groups), GFP_KERNEL);
348	if (!pctl->groups)
349		return -ENOMEM;
350
351	for (i = 0; i < npins; i++) {
352		group = pctl->groups + i;
353		group->name = ppins[i].pin.name;
354		group->pins = &ppins[i].pin.number;
355		group->npins = 1;
356	}
357
358	ret = pxa2xx_build_functions(pctl);
359	if (ret)
360		return ret;
361
362	ret = pxa2xx_build_groups(pctl);
363	if (ret)
364		return ret;
365
366	return 0;
367}
368
369int pxa2xx_pinctrl_init(struct platform_device *pdev,
370			const struct pxa_desc_pin *ppins, int npins,
371			void __iomem *base_gafr[], void __iomem *base_gpdr[],
372			void __iomem *base_pgsr[])
373{
374	struct pxa_pinctrl *pctl;
375	int ret, i, maxpin = 0;
376
377	for (i = 0; i < npins; i++)
378		maxpin = max_t(int, ppins[i].pin.number, maxpin);
379
380	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
381	if (!pctl)
382		return -ENOMEM;
383	pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16),
384				       sizeof(*pctl->base_gafr), GFP_KERNEL);
385	pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
386				       sizeof(*pctl->base_gpdr), GFP_KERNEL);
387	pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
388				       sizeof(*pctl->base_pgsr), GFP_KERNEL);
389	if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr)
390		return -ENOMEM;
391
392	platform_set_drvdata(pdev, pctl);
393	spin_lock_init(&pctl->lock);
394
395	pctl->dev = &pdev->dev;
396	pctl->desc = pxa2xx_pinctrl_desc;
397	pctl->desc.name = dev_name(&pdev->dev);
398	pctl->desc.owner = THIS_MODULE;
399
400	for (i = 0; i < roundup(maxpin, 16); i += 16)
401		pctl->base_gafr[i / 16] = base_gafr[i / 16];
402	for (i = 0; i < roundup(maxpin, 32); i += 32) {
403		pctl->base_gpdr[i / 32] = base_gpdr[i / 32];
404		pctl->base_pgsr[i / 32] = base_pgsr[i / 32];
405	}
406
407	ret = pxa2xx_build_state(pctl, ppins, npins);
408	if (ret)
409		return ret;
410
411	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->desc, pctl);
412	if (IS_ERR(pctl->pctl_dev)) {
413		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
414		return PTR_ERR(pctl->pctl_dev);
415	}
416
417	dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n");
418
419	return 0;
420}
421EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
422
423MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
424MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver");
425MODULE_LICENSE("GPL v2");