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pinctrl-zynq.c
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linux-6.19.14/drivers/pinctrl/pinctrl-zynq.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Zynq pin controller 4 * 5 * Copyright (C) 2014 Xilinx 6 * 7 * Sören Brinkmann <soren.brinkmann@xilinx.com> 8 */ 9#include <linux/io.h> 10#include <linux/mfd/syscon.h> 11#include <linux/module.h> 12#include <linux/init.h> 13#include <linux/of.h> 14#include <linux/platform_device.h> 15#include <linux/pinctrl/pinctrl.h> 16#include <linux/pinctrl/pinmux.h> 17#include <linux/pinctrl/pinconf.h> 18#include <linux/pinctrl/pinconf-generic.h> 19#include <linux/regmap.h> 20#include "pinctrl-utils.h" 21#include "core.h" 22 23#define ZYNQ_NUM_MIOS 54 24 25#define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c 26#define ZYNQ_PCTRL_MIO_MST_TRI1 0x110 27 28#define ZYNQ_PINMUX_MUX_SHIFT 1 29#define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT) 30 31/** 32 * struct zynq_pinctrl - driver data 33 * @pctrl: Pinctrl device 34 * @syscon: Syscon regmap 35 * @pctrl_offset: Offset for pinctrl into the @syscon space 36 * @groups: Pingroups 37 * @ngroups: Number of @groups 38 * @funcs: Pinmux functions 39 * @nfuncs: Number of @funcs 40 */ 41struct zynq_pinctrl { 42 struct pinctrl_dev *pctrl; 43 struct regmap *syscon; 44 u32 pctrl_offset; 45 const struct zynq_pctrl_group *groups; 46 unsigned int ngroups; 47 const struct zynq_pinmux_function *funcs; 48 unsigned int nfuncs; 49}; 50 51struct zynq_pctrl_group { 52 const char *name; 53 const unsigned int *pins; 54 const unsigned int npins; 55}; 56 57/** 58 * struct zynq_pinmux_function - a pinmux function 59 * @name: Name of the pinmux function. 60 * @groups: List of pingroups for this function. 61 * @ngroups: Number of entries in @groups. 62 * @mux_val: Selector for this function 63 * @mux: Offset of function specific mux 64 * @mux_mask: Mask for function specific selector 65 * @mux_shift: Shift for function specific selector 66 */ 67struct zynq_pinmux_function { 68 const char *name; 69 const char * const *groups; 70 unsigned int ngroups; 71 unsigned int mux_val; 72 u32 mux; 73 u32 mux_mask; 74 u8 mux_shift; 75}; 76 77enum zynq_pinmux_functions { 78 ZYNQ_PMUX_can0, 79 ZYNQ_PMUX_can1, 80 ZYNQ_PMUX_ethernet0, 81 ZYNQ_PMUX_ethernet1, 82 ZYNQ_PMUX_gpio0, 83 ZYNQ_PMUX_i2c0, 84 ZYNQ_PMUX_i2c1, 85 ZYNQ_PMUX_mdio0, 86 ZYNQ_PMUX_mdio1, 87 ZYNQ_PMUX_qspi0, 88 ZYNQ_PMUX_qspi1, 89 ZYNQ_PMUX_qspi_fbclk, 90 ZYNQ_PMUX_qspi_cs1, 91 ZYNQ_PMUX_spi0, 92 ZYNQ_PMUX_spi1, 93 ZYNQ_PMUX_spi0_ss, 94 ZYNQ_PMUX_spi1_ss, 95 ZYNQ_PMUX_sdio0, 96 ZYNQ_PMUX_sdio0_pc, 97 ZYNQ_PMUX_sdio0_cd, 98 ZYNQ_PMUX_sdio0_wp, 99 ZYNQ_PMUX_sdio1, 100 ZYNQ_PMUX_sdio1_pc, 101 ZYNQ_PMUX_sdio1_cd, 102 ZYNQ_PMUX_sdio1_wp, 103 ZYNQ_PMUX_smc0_nor, 104 ZYNQ_PMUX_smc0_nor_cs1, 105 ZYNQ_PMUX_smc0_nor_addr25, 106 ZYNQ_PMUX_smc0_nand, 107 ZYNQ_PMUX_ttc0, 108 ZYNQ_PMUX_ttc1, 109 ZYNQ_PMUX_uart0, 110 ZYNQ_PMUX_uart1, 111 ZYNQ_PMUX_usb0, 112 ZYNQ_PMUX_usb1, 113 ZYNQ_PMUX_swdt0, 114 ZYNQ_PMUX_MAX_FUNC 115}; 116 117static const struct pinctrl_pin_desc zynq_pins[] = { 118 PINCTRL_PIN(0, "MIO0"), 119 PINCTRL_PIN(1, "MIO1"), 120 PINCTRL_PIN(2, "MIO2"), 121 PINCTRL_PIN(3, "MIO3"), 122 PINCTRL_PIN(4, "MIO4"), 123 PINCTRL_PIN(5, "MIO5"), 124 PINCTRL_PIN(6, "MIO6"), 125 PINCTRL_PIN(7, "MIO7"), 126 PINCTRL_PIN(8, "MIO8"), 127 PINCTRL_PIN(9, "MIO9"), 128 PINCTRL_PIN(10, "MIO10"), 129 PINCTRL_PIN(11, "MIO11"), 130 PINCTRL_PIN(12, "MIO12"), 131 PINCTRL_PIN(13, "MIO13"), 132 PINCTRL_PIN(14, "MIO14"), 133 PINCTRL_PIN(15, "MIO15"), 134 PINCTRL_PIN(16, "MIO16"), 135 PINCTRL_PIN(17, "MIO17"), 136 PINCTRL_PIN(18, "MIO18"), 137 PINCTRL_PIN(19, "MIO19"), 138 PINCTRL_PIN(20, "MIO20"), 139 PINCTRL_PIN(21, "MIO21"), 140 PINCTRL_PIN(22, "MIO22"), 141 PINCTRL_PIN(23, "MIO23"), 142 PINCTRL_PIN(24, "MIO24"), 143 PINCTRL_PIN(25, "MIO25"), 144 PINCTRL_PIN(26, "MIO26"), 145 PINCTRL_PIN(27, "MIO27"), 146 PINCTRL_PIN(28, "MIO28"), 147 PINCTRL_PIN(29, "MIO29"), 148 PINCTRL_PIN(30, "MIO30"), 149 PINCTRL_PIN(31, "MIO31"), 150 PINCTRL_PIN(32, "MIO32"), 151 PINCTRL_PIN(33, "MIO33"), 152 PINCTRL_PIN(34, "MIO34"), 153 PINCTRL_PIN(35, "MIO35"), 154 PINCTRL_PIN(36, "MIO36"), 155 PINCTRL_PIN(37, "MIO37"), 156 PINCTRL_PIN(38, "MIO38"), 157 PINCTRL_PIN(39, "MIO39"), 158 PINCTRL_PIN(40, "MIO40"), 159 PINCTRL_PIN(41, "MIO41"), 160 PINCTRL_PIN(42, "MIO42"), 161 PINCTRL_PIN(43, "MIO43"), 162 PINCTRL_PIN(44, "MIO44"), 163 PINCTRL_PIN(45, "MIO45"), 164 PINCTRL_PIN(46, "MIO46"), 165 PINCTRL_PIN(47, "MIO47"), 166 PINCTRL_PIN(48, "MIO48"), 167 PINCTRL_PIN(49, "MIO49"), 168 PINCTRL_PIN(50, "MIO50"), 169 PINCTRL_PIN(51, "MIO51"), 170 PINCTRL_PIN(52, "MIO52"), 171 PINCTRL_PIN(53, "MIO53"), 172 PINCTRL_PIN(54, "EMIO_SD0_WP"), 173 PINCTRL_PIN(55, "EMIO_SD0_CD"), 174 PINCTRL_PIN(56, "EMIO_SD1_WP"), 175 PINCTRL_PIN(57, "EMIO_SD1_CD"), 176}; 177 178/* pin groups */ 179static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 180 24, 25, 26, 27}; 181static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 182 36, 37, 38, 39}; 183static const unsigned int mdio0_0_pins[] = {52, 53}; 184static const unsigned int mdio1_0_pins[] = {52, 53}; 185static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6}; 186 187static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13}; 188static const unsigned int qspi_cs1_pins[] = {0}; 189static const unsigned int qspi_fbclk_pins[] = {8}; 190static const unsigned int spi0_0_pins[] = {16, 17, 21}; 191static const unsigned int spi0_0_ss0_pins[] = {18}; 192static const unsigned int spi0_0_ss1_pins[] = {19}; 193static const unsigned int spi0_0_ss2_pins[] = {20,}; 194static const unsigned int spi0_1_pins[] = {28, 29, 33}; 195static const unsigned int spi0_1_ss0_pins[] = {30}; 196static const unsigned int spi0_1_ss1_pins[] = {31}; 197static const unsigned int spi0_1_ss2_pins[] = {32}; 198static const unsigned int spi0_2_pins[] = {40, 41, 45}; 199static const unsigned int spi0_2_ss0_pins[] = {42}; 200static const unsigned int spi0_2_ss1_pins[] = {43}; 201static const unsigned int spi0_2_ss2_pins[] = {44}; 202static const unsigned int spi1_0_pins[] = {10, 11, 12}; 203static const unsigned int spi1_0_ss0_pins[] = {13}; 204static const unsigned int spi1_0_ss1_pins[] = {14}; 205static const unsigned int spi1_0_ss2_pins[] = {15}; 206static const unsigned int spi1_1_pins[] = {22, 23, 24}; 207static const unsigned int spi1_1_ss0_pins[] = {25}; 208static const unsigned int spi1_1_ss1_pins[] = {26}; 209static const unsigned int spi1_1_ss2_pins[] = {27}; 210static const unsigned int spi1_2_pins[] = {34, 35, 36}; 211static const unsigned int spi1_2_ss0_pins[] = {37}; 212static const unsigned int spi1_2_ss1_pins[] = {38}; 213static const unsigned int spi1_2_ss2_pins[] = {39}; 214static const unsigned int spi1_3_pins[] = {46, 47, 48, 49}; 215static const unsigned int spi1_3_ss0_pins[] = {49}; 216static const unsigned int spi1_3_ss1_pins[] = {50}; 217static const unsigned int spi1_3_ss2_pins[] = {51}; 218 219static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21}; 220static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33}; 221static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45}; 222static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15}; 223static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27}; 224static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39}; 225static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51}; 226static const unsigned int sdio0_emio_wp_pins[] = {54}; 227static const unsigned int sdio0_emio_cd_pins[] = {55}; 228static const unsigned int sdio1_emio_wp_pins[] = {56}; 229static const unsigned int sdio1_emio_cd_pins[] = {57}; 230static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 231 15, 16, 17, 18, 19, 20, 21, 22, 23, 232 24, 25, 26, 27, 28, 29, 30, 31, 32, 233 33, 34, 35, 36, 37, 38, 39}; 234static const unsigned int smc0_nor_cs1_pins[] = {1}; 235static const unsigned int smc0_nor_addr25_pins[] = {1}; 236static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 237 12, 13, 14, 16, 17, 18, 19, 20, 238 21, 22, 23}; 239static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7, 240 8, 9, 10, 11, 12, 13, 14}; 241/* Note: CAN MIO clock inputs are modeled in the clock framework */ 242static const unsigned int can0_0_pins[] = {10, 11}; 243static const unsigned int can0_1_pins[] = {14, 15}; 244static const unsigned int can0_2_pins[] = {18, 19}; 245static const unsigned int can0_3_pins[] = {22, 23}; 246static const unsigned int can0_4_pins[] = {26, 27}; 247static const unsigned int can0_5_pins[] = {30, 31}; 248static const unsigned int can0_6_pins[] = {34, 35}; 249static const unsigned int can0_7_pins[] = {38, 39}; 250static const unsigned int can0_8_pins[] = {42, 43}; 251static const unsigned int can0_9_pins[] = {46, 47}; 252static const unsigned int can0_10_pins[] = {50, 51}; 253static const unsigned int can1_0_pins[] = {8, 9}; 254static const unsigned int can1_1_pins[] = {12, 13}; 255static const unsigned int can1_2_pins[] = {16, 17}; 256static const unsigned int can1_3_pins[] = {20, 21}; 257static const unsigned int can1_4_pins[] = {24, 25}; 258static const unsigned int can1_5_pins[] = {28, 29}; 259static const unsigned int can1_6_pins[] = {32, 33}; 260static const unsigned int can1_7_pins[] = {36, 37}; 261static const unsigned int can1_8_pins[] = {40, 41}; 262static const unsigned int can1_9_pins[] = {44, 45}; 263static const unsigned int can1_10_pins[] = {48, 49}; 264static const unsigned int can1_11_pins[] = {52, 53}; 265static const unsigned int uart0_0_pins[] = {10, 11}; 266static const unsigned int uart0_1_pins[] = {14, 15}; 267static const unsigned int uart0_2_pins[] = {18, 19}; 268static const unsigned int uart0_3_pins[] = {22, 23}; 269static const unsigned int uart0_4_pins[] = {26, 27}; 270static const unsigned int uart0_5_pins[] = {30, 31}; 271static const unsigned int uart0_6_pins[] = {34, 35}; 272static const unsigned int uart0_7_pins[] = {38, 39}; 273static const unsigned int uart0_8_pins[] = {42, 43}; 274static const unsigned int uart0_9_pins[] = {46, 47}; 275static const unsigned int uart0_10_pins[] = {50, 51}; 276static const unsigned int uart1_0_pins[] = {8, 9}; 277static const unsigned int uart1_1_pins[] = {12, 13}; 278static const unsigned int uart1_2_pins[] = {16, 17}; 279static const unsigned int uart1_3_pins[] = {20, 21}; 280static const unsigned int uart1_4_pins[] = {24, 25}; 281static const unsigned int uart1_5_pins[] = {28, 29}; 282static const unsigned int uart1_6_pins[] = {32, 33}; 283static const unsigned int uart1_7_pins[] = {36, 37}; 284static const unsigned int uart1_8_pins[] = {40, 41}; 285static const unsigned int uart1_9_pins[] = {44, 45}; 286static const unsigned int uart1_10_pins[] = {48, 49}; 287static const unsigned int uart1_11_pins[] = {52, 53}; 288static const unsigned int i2c0_0_pins[] = {10, 11}; 289static const unsigned int i2c0_1_pins[] = {14, 15}; 290static const unsigned int i2c0_2_pins[] = {18, 19}; 291static const unsigned int i2c0_3_pins[] = {22, 23}; 292static const unsigned int i2c0_4_pins[] = {26, 27}; 293static const unsigned int i2c0_5_pins[] = {30, 31}; 294static const unsigned int i2c0_6_pins[] = {34, 35}; 295static const unsigned int i2c0_7_pins[] = {38, 39}; 296static const unsigned int i2c0_8_pins[] = {42, 43}; 297static const unsigned int i2c0_9_pins[] = {46, 47}; 298static const unsigned int i2c0_10_pins[] = {50, 51}; 299static const unsigned int i2c1_0_pins[] = {12, 13}; 300static const unsigned int i2c1_1_pins[] = {16, 17}; 301static const unsigned int i2c1_2_pins[] = {20, 21}; 302static const unsigned int i2c1_3_pins[] = {24, 25}; 303static const unsigned int i2c1_4_pins[] = {28, 29}; 304static const unsigned int i2c1_5_pins[] = {32, 33}; 305static const unsigned int i2c1_6_pins[] = {36, 37}; 306static const unsigned int i2c1_7_pins[] = {40, 41}; 307static const unsigned int i2c1_8_pins[] = {44, 45}; 308static const unsigned int i2c1_9_pins[] = {48, 49}; 309static const unsigned int i2c1_10_pins[] = {52, 53}; 310static const unsigned int ttc0_0_pins[] = {18, 19}; 311static const unsigned int ttc0_1_pins[] = {30, 31}; 312static const unsigned int ttc0_2_pins[] = {42, 43}; 313static const unsigned int ttc1_0_pins[] = {16, 17}; 314static const unsigned int ttc1_1_pins[] = {28, 29}; 315static const unsigned int ttc1_2_pins[] = {40, 41}; 316static const unsigned int swdt0_0_pins[] = {14, 15}; 317static const unsigned int swdt0_1_pins[] = {26, 27}; 318static const unsigned int swdt0_2_pins[] = {38, 39}; 319static const unsigned int swdt0_3_pins[] = {50, 51}; 320static const unsigned int swdt0_4_pins[] = {52, 53}; 321static const unsigned int gpio0_0_pins[] = {0}; 322static const unsigned int gpio0_1_pins[] = {1}; 323static const unsigned int gpio0_2_pins[] = {2}; 324static const unsigned int gpio0_3_pins[] = {3}; 325static const unsigned int gpio0_4_pins[] = {4}; 326static const unsigned int gpio0_5_pins[] = {5}; 327static const unsigned int gpio0_6_pins[] = {6}; 328static const unsigned int gpio0_7_pins[] = {7}; 329static const unsigned int gpio0_8_pins[] = {8}; 330static const unsigned int gpio0_9_pins[] = {9}; 331static const unsigned int gpio0_10_pins[] = {10}; 332static const unsigned int gpio0_11_pins[] = {11}; 333static const unsigned int gpio0_12_pins[] = {12}; 334static const unsigned int gpio0_13_pins[] = {13}; 335static const unsigned int gpio0_14_pins[] = {14}; 336static const unsigned int gpio0_15_pins[] = {15}; 337static const unsigned int gpio0_16_pins[] = {16}; 338static const unsigned int gpio0_17_pins[] = {17}; 339static const unsigned int gpio0_18_pins[] = {18}; 340static const unsigned int gpio0_19_pins[] = {19}; 341static const unsigned int gpio0_20_pins[] = {20}; 342static const unsigned int gpio0_21_pins[] = {21}; 343static const unsigned int gpio0_22_pins[] = {22}; 344static const unsigned int gpio0_23_pins[] = {23}; 345static const unsigned int gpio0_24_pins[] = {24}; 346static const unsigned int gpio0_25_pins[] = {25}; 347static const unsigned int gpio0_26_pins[] = {26}; 348static const unsigned int gpio0_27_pins[] = {27}; 349static const unsigned int gpio0_28_pins[] = {28}; 350static const unsigned int gpio0_29_pins[] = {29}; 351static const unsigned int gpio0_30_pins[] = {30}; 352static const unsigned int gpio0_31_pins[] = {31}; 353static const unsigned int gpio0_32_pins[] = {32}; 354static const unsigned int gpio0_33_pins[] = {33}; 355static const unsigned int gpio0_34_pins[] = {34}; 356static const unsigned int gpio0_35_pins[] = {35}; 357static const unsigned int gpio0_36_pins[] = {36}; 358static const unsigned int gpio0_37_pins[] = {37}; 359static const unsigned int gpio0_38_pins[] = {38}; 360static const unsigned int gpio0_39_pins[] = {39}; 361static const unsigned int gpio0_40_pins[] = {40}; 362static const unsigned int gpio0_41_pins[] = {41}; 363static const unsigned int gpio0_42_pins[] = {42}; 364static const unsigned int gpio0_43_pins[] = {43}; 365static const unsigned int gpio0_44_pins[] = {44}; 366static const unsigned int gpio0_45_pins[] = {45}; 367static const unsigned int gpio0_46_pins[] = {46}; 368static const unsigned int gpio0_47_pins[] = {47}; 369static const unsigned int gpio0_48_pins[] = {48}; 370static const unsigned int gpio0_49_pins[] = {49}; 371static const unsigned int gpio0_50_pins[] = {50}; 372static const unsigned int gpio0_51_pins[] = {51}; 373static const unsigned int gpio0_52_pins[] = {52}; 374static const unsigned int gpio0_53_pins[] = {53}; 375static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36, 376 37, 38, 39}; 377static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 378 49, 50, 51}; 379 380#define DEFINE_ZYNQ_PINCTRL_GRP(nm) \ 381 { \ 382 .name = #nm "_grp", \ 383 .pins = nm ## _pins, \ 384 .npins = ARRAY_SIZE(nm ## _pins), \ 385 } 386 387static const struct zynq_pctrl_group zynq_pctrl_groups[] = { 388 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0), 389 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0), 390 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0), 391 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0), 392 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0), 393 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0), 394 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk), 395 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1), 396 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0), 397 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0), 398 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1), 399 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2), 400 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1), 401 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0), 402 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1), 403 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2), 404 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2), 405 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0), 406 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1), 407 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2), 408 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0), 409 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0), 410 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1), 411 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2), 412 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1), 413 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0), 414 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1), 415 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2), 416 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2), 417 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0), 418 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1), 419 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2), 420 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3), 421 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0), 422 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1), 423 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2), 424 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0), 425 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1), 426 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2), 427 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0), 428 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1), 429 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2), 430 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3), 431 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp), 432 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd), 433 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp), 434 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd), 435 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor), 436 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1), 437 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25), 438 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand), 439 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8), 440 DEFINE_ZYNQ_PINCTRL_GRP(can0_0), 441 DEFINE_ZYNQ_PINCTRL_GRP(can0_1), 442 DEFINE_ZYNQ_PINCTRL_GRP(can0_2), 443 DEFINE_ZYNQ_PINCTRL_GRP(can0_3), 444 DEFINE_ZYNQ_PINCTRL_GRP(can0_4), 445 DEFINE_ZYNQ_PINCTRL_GRP(can0_5), 446 DEFINE_ZYNQ_PINCTRL_GRP(can0_6), 447 DEFINE_ZYNQ_PINCTRL_GRP(can0_7), 448 DEFINE_ZYNQ_PINCTRL_GRP(can0_8), 449 DEFINE_ZYNQ_PINCTRL_GRP(can0_9), 450 DEFINE_ZYNQ_PINCTRL_GRP(can0_10), 451 DEFINE_ZYNQ_PINCTRL_GRP(can1_0), 452 DEFINE_ZYNQ_PINCTRL_GRP(can1_1), 453 DEFINE_ZYNQ_PINCTRL_GRP(can1_2), 454 DEFINE_ZYNQ_PINCTRL_GRP(can1_3), 455 DEFINE_ZYNQ_PINCTRL_GRP(can1_4), 456 DEFINE_ZYNQ_PINCTRL_GRP(can1_5), 457 DEFINE_ZYNQ_PINCTRL_GRP(can1_6), 458 DEFINE_ZYNQ_PINCTRL_GRP(can1_7), 459 DEFINE_ZYNQ_PINCTRL_GRP(can1_8), 460 DEFINE_ZYNQ_PINCTRL_GRP(can1_9), 461 DEFINE_ZYNQ_PINCTRL_GRP(can1_10), 462 DEFINE_ZYNQ_PINCTRL_GRP(can1_11), 463 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0), 464 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1), 465 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2), 466 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3), 467 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4), 468 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5), 469 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6), 470 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7), 471 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8), 472 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9), 473 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10), 474 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0), 475 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1), 476 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2), 477 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3), 478 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4), 479 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5), 480 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6), 481 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7), 482 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8), 483 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9), 484 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10), 485 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11), 486 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0), 487 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1), 488 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2), 489 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3), 490 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4), 491 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5), 492 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6), 493 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7), 494 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8), 495 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9), 496 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10), 497 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0), 498 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1), 499 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2), 500 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3), 501 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4), 502 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5), 503 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6), 504 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7), 505 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8), 506 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9), 507 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10), 508 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0), 509 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1), 510 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2), 511 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0), 512 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1), 513 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2), 514 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0), 515 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1), 516 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2), 517 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3), 518 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4), 519 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0), 520 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1), 521 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2), 522 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3), 523 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4), 524 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5), 525 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6), 526 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7), 527 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8), 528 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9), 529 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10), 530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11), 531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12), 532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13), 533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14), 534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15), 535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16), 536 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17), 537 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18), 538 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19), 539 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20), 540 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21), 541 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22), 542 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23), 543 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24), 544 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25), 545 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26), 546 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27), 547 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28), 548 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29), 549 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30), 550 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31), 551 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32), 552 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33), 553 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34), 554 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35), 555 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36), 556 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37), 557 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38), 558 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39), 559 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40), 560 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41), 561 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42), 562 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43), 563 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44), 564 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45), 565 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46), 566 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47), 567 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48), 568 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49), 569 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50), 570 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51), 571 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52), 572 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53), 573 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0), 574 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0), 575}; 576 577/* function groups */ 578static const char * const ethernet0_groups[] = {"ethernet0_0_grp"}; 579static const char * const ethernet1_groups[] = {"ethernet1_0_grp"}; 580static const char * const usb0_groups[] = {"usb0_0_grp"}; 581static const char * const usb1_groups[] = {"usb1_0_grp"}; 582static const char * const mdio0_groups[] = {"mdio0_0_grp"}; 583static const char * const mdio1_groups[] = {"mdio1_0_grp"}; 584static const char * const qspi0_groups[] = {"qspi0_0_grp"}; 585static const char * const qspi1_groups[] = {"qspi1_0_grp"}; 586static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"}; 587static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"}; 588static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp", 589 "spi0_2_grp"}; 590static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp", 591 "spi1_2_grp", "spi1_3_grp"}; 592static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp", 593 "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp", 594 "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp", 595 "spi0_2_ss1_grp", "spi0_2_ss2_grp"}; 596static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp", 597 "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp", 598 "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp", 599 "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp", 600 "spi1_3_ss1_grp", "spi1_3_ss2_grp"}; 601static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp", 602 "sdio0_2_grp"}; 603static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp", 604 "sdio1_2_grp", "sdio1_3_grp"}; 605static const char * const sdio0_pc_groups[] = {"gpio0_0_grp", 606 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 607 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", 608 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 609 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 610 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 611 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 612 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 613 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 614 "gpio0_50_grp", "gpio0_52_grp"}; 615static const char * const sdio1_pc_groups[] = {"gpio0_1_grp", 616 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", 617 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 618 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 619 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 620 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 621 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 622 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 623 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 624 "gpio0_51_grp", "gpio0_53_grp"}; 625static const char * const sdio0_cd_groups[] = {"gpio0_0_grp", 626 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 627 "gpio0_10_grp", "gpio0_12_grp", 628 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 629 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 630 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 631 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 632 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 633 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 634 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 635 "gpio0_3_grp", "gpio0_5_grp", 636 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 637 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 638 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 639 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 640 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 641 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 642 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 643 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"}; 644static const char * const sdio0_wp_groups[] = {"gpio0_0_grp", 645 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 646 "gpio0_10_grp", "gpio0_12_grp", 647 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 648 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 649 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 650 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 651 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 652 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 653 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 654 "gpio0_3_grp", "gpio0_5_grp", 655 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 656 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 657 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 658 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 659 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 660 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 661 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 662 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"}; 663static const char * const sdio1_cd_groups[] = {"gpio0_0_grp", 664 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 665 "gpio0_10_grp", "gpio0_12_grp", 666 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 667 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 668 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 669 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 670 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 671 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 672 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 673 "gpio0_3_grp", "gpio0_5_grp", 674 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 675 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 676 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 677 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 678 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 679 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 680 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 681 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"}; 682static const char * const sdio1_wp_groups[] = {"gpio0_0_grp", 683 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 684 "gpio0_10_grp", "gpio0_12_grp", 685 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 686 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 687 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 688 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 689 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 690 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 691 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 692 "gpio0_3_grp", "gpio0_5_grp", 693 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 694 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 695 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 696 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 697 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 698 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 699 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 700 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"}; 701static const char * const smc0_nor_groups[] = {"smc0_nor_grp"}; 702static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; 703static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; 704static const char * const smc0_nand_groups[] = {"smc0_nand_grp", 705 "smc0_nand8_grp"}; 706static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", 707 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", 708 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", 709 "can0_10_grp"}; 710static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp", 711 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp", 712 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp", 713 "can1_10_grp", "can1_11_grp"}; 714static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp", 715 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp", 716 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp", 717 "uart0_10_grp"}; 718static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp", 719 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp", 720 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp", 721 "uart1_10_grp", "uart1_11_grp"}; 722static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp", 723 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp", 724 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp", 725 "i2c0_10_grp"}; 726static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp", 727 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp", 728 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp", 729 "i2c1_10_grp"}; 730static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp", 731 "ttc0_2_grp"}; 732static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp", 733 "ttc1_2_grp"}; 734static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp", 735 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"}; 736static const char * const gpio0_groups[] = {"gpio0_0_grp", 737 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp", 738 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp", 739 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp", 740 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp", 741 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp", 742 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp", 743 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp", 744 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp", 745 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp", 746 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp", 747 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp", 748 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp", 749 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp", 750 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp", 751 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp", 752 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 753 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 754 "gpio0_51_grp", "gpio0_53_grp"}; 755 756#define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \ 757 [ZYNQ_PMUX_##fname] = { \ 758 .name = #fname, \ 759 .groups = fname##_groups, \ 760 .ngroups = ARRAY_SIZE(fname##_groups), \ 761 .mux_val = mval, \ 762 } 763 764#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\ 765 [ZYNQ_PMUX_##fname] = { \ 766 .name = #fname, \ 767 .groups = fname##_groups, \ 768 .ngroups = ARRAY_SIZE(fname##_groups), \ 769 .mux_val = mval, \ 770 .mux = offset, \ 771 .mux_mask = mask, \ 772 .mux_shift = shift, \ 773 } 774 775#define ZYNQ_SDIO_WP_SHIFT 0 776#define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT) 777#define ZYNQ_SDIO_CD_SHIFT 16 778#define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT) 779 780static const struct zynq_pinmux_function zynq_pmux_functions[] = { 781 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1), 782 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1), 783 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2), 784 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2), 785 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40), 786 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50), 787 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1), 788 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1), 789 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1), 790 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1), 791 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50), 792 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), 793 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50), 794 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50), 795 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), 796 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), 797 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, 798 ZYNQ_SDIO_WP_SHIFT), 799 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK, 800 ZYNQ_SDIO_CD_SHIFT), 801 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), 802 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), 803 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK, 804 ZYNQ_SDIO_WP_SHIFT), 805 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK, 806 ZYNQ_SDIO_CD_SHIFT), 807 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), 808 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8), 809 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4), 810 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8), 811 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10), 812 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10), 813 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70), 814 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70), 815 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20), 816 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20), 817 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60), 818 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60), 819 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30), 820 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0), 821}; 822 823 824/* pinctrl */ 825static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 826{ 827 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 828 829 return pctrl->ngroups; 830} 831 832static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev, 833 unsigned int selector) 834{ 835 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 836 837 return pctrl->groups[selector].name; 838} 839 840static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 841 unsigned int selector, 842 const unsigned int **pins, 843 unsigned int *num_pins) 844{ 845 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 846 847 *pins = pctrl->groups[selector].pins; 848 *num_pins = pctrl->groups[selector].npins; 849 850 return 0; 851} 852 853static const struct pinctrl_ops zynq_pctrl_ops = { 854 .get_groups_count = zynq_pctrl_get_groups_count, 855 .get_group_name = zynq_pctrl_get_group_name, 856 .get_group_pins = zynq_pctrl_get_group_pins, 857 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 858 .dt_free_map = pinctrl_utils_free_map, 859}; 860 861/* pinmux */ 862static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev) 863{ 864 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 865 866 return pctrl->nfuncs; 867} 868 869static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev, 870 unsigned int selector) 871{ 872 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 873 874 return pctrl->funcs[selector].name; 875} 876 877static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev, 878 unsigned int selector, 879 const char * const **groups, 880 unsigned * const num_groups) 881{ 882 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 883 884 *groups = pctrl->funcs[selector].groups; 885 *num_groups = pctrl->funcs[selector].ngroups; 886 return 0; 887} 888 889static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev, 890 unsigned int function, 891 unsigned int group) 892{ 893 int i, ret; 894 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 895 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group]; 896 const struct zynq_pinmux_function *func = &pctrl->funcs[function]; 897 898 /* 899 * SD WP & CD are special. They have dedicated registers 900 * to mux them in 901 */ 902 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp || 903 function == ZYNQ_PMUX_sdio1_cd || 904 function == ZYNQ_PMUX_sdio1_wp) { 905 u32 reg; 906 907 ret = regmap_read(pctrl->syscon, 908 pctrl->pctrl_offset + func->mux, ®); 909 if (ret) 910 return ret; 911 912 reg &= ~func->mux_mask; 913 reg |= pgrp->pins[0] << func->mux_shift; 914 ret = regmap_write(pctrl->syscon, 915 pctrl->pctrl_offset + func->mux, reg); 916 if (ret) 917 return ret; 918 } else { 919 for (i = 0; i < pgrp->npins; i++) { 920 unsigned int pin = pgrp->pins[i]; 921 u32 reg, addr = pctrl->pctrl_offset + (4 * pin); 922 923 ret = regmap_read(pctrl->syscon, addr, ®); 924 if (ret) 925 return ret; 926 927 reg &= ~ZYNQ_PINMUX_MUX_MASK; 928 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; 929 ret = regmap_write(pctrl->syscon, addr, reg); 930 if (ret) 931 return ret; 932 } 933 } 934 935 return 0; 936} 937 938static const struct pinmux_ops zynq_pinmux_ops = { 939 .get_functions_count = zynq_pmux_get_functions_count, 940 .get_function_name = zynq_pmux_get_function_name, 941 .get_function_groups = zynq_pmux_get_function_groups, 942 .set_mux = zynq_pinmux_set_mux, 943}; 944 945/* pinconfig */ 946#define ZYNQ_PINCONF_TRISTATE BIT(0) 947#define ZYNQ_PINCONF_SPEED BIT(8) 948#define ZYNQ_PINCONF_PULLUP BIT(12) 949#define ZYNQ_PINCONF_DISABLE_RECVR BIT(13) 950 951#define ZYNQ_PINCONF_IOTYPE_SHIFT 9 952#define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT) 953 954enum zynq_io_standards { 955 zynq_iostd_min, 956 zynq_iostd_lvcmos18, 957 zynq_iostd_lvcmos25, 958 zynq_iostd_lvcmos33, 959 zynq_iostd_hstl, 960 zynq_iostd_max 961}; 962 963/* 964 * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to 965 * this parameter (on a custom format) tells the driver which alternative 966 * IO standard to use. 967 */ 968#define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1) 969 970static const struct pinconf_generic_params zynq_dt_params[] = { 971 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18}, 972}; 973 974#ifdef CONFIG_DEBUG_FS 975static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] 976 = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true), 977}; 978#endif 979 980static unsigned int zynq_pinconf_iostd_get(u32 reg) 981{ 982 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT; 983} 984 985static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev, 986 unsigned int pin, 987 unsigned long *config) 988{ 989 u32 reg; 990 int ret; 991 unsigned int arg = 0; 992 unsigned int param = pinconf_to_config_param(*config); 993 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 994 995 if (pin >= ZYNQ_NUM_MIOS) 996 return -ENOTSUPP; 997 998 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); 999 if (ret) 1000 return -EIO; 1001 1002 switch (param) { 1003 case PIN_CONFIG_BIAS_PULL_UP: 1004 if (!(reg & ZYNQ_PINCONF_PULLUP)) 1005 return -EINVAL; 1006 arg = 1; 1007 break; 1008 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 1009 if (!(reg & ZYNQ_PINCONF_TRISTATE)) 1010 return -EINVAL; 1011 arg = 1; 1012 break; 1013 case PIN_CONFIG_BIAS_DISABLE: 1014 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE) 1015 return -EINVAL; 1016 break; 1017 case PIN_CONFIG_SLEW_RATE: 1018 arg = !!(reg & ZYNQ_PINCONF_SPEED); 1019 break; 1020 case PIN_CONFIG_MODE_LOW_POWER: 1021 { 1022 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); 1023 1024 if (iostd != zynq_iostd_hstl) 1025 return -EINVAL; 1026 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR)) 1027 return -EINVAL; 1028 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR); 1029 break; 1030 } 1031 case PIN_CONFIG_IOSTANDARD: 1032 case PIN_CONFIG_POWER_SOURCE: 1033 arg = zynq_pinconf_iostd_get(reg); 1034 break; 1035 default: 1036 return -ENOTSUPP; 1037 } 1038 1039 *config = pinconf_to_config_packed(param, arg); 1040 return 0; 1041} 1042 1043static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, 1044 unsigned int pin, 1045 unsigned long *configs, 1046 unsigned int num_configs) 1047{ 1048 int i, ret; 1049 u32 reg; 1050 u32 pullup = 0; 1051 u32 tristate = 0; 1052 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1053 1054 if (pin >= ZYNQ_NUM_MIOS) 1055 return -ENOTSUPP; 1056 1057 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); 1058 if (ret) 1059 return -EIO; 1060 1061 for (i = 0; i < num_configs; i++) { 1062 unsigned int param = pinconf_to_config_param(configs[i]); 1063 unsigned int arg = pinconf_to_config_argument(configs[i]); 1064 1065 switch (param) { 1066 case PIN_CONFIG_BIAS_PULL_UP: 1067 pullup = ZYNQ_PINCONF_PULLUP; 1068 break; 1069 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 1070 tristate = ZYNQ_PINCONF_TRISTATE; 1071 break; 1072 case PIN_CONFIG_BIAS_DISABLE: 1073 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); 1074 break; 1075 case PIN_CONFIG_SLEW_RATE: 1076 if (arg) 1077 reg |= ZYNQ_PINCONF_SPEED; 1078 else 1079 reg &= ~ZYNQ_PINCONF_SPEED; 1080 1081 break; 1082 case PIN_CONFIG_IOSTANDARD: 1083 case PIN_CONFIG_POWER_SOURCE: 1084 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { 1085 dev_warn(pctldev->dev, 1086 "unsupported IO standard '%u'\n", 1087 param); 1088 break; 1089 } 1090 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; 1091 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; 1092 break; 1093 case PIN_CONFIG_MODE_LOW_POWER: 1094 if (arg) 1095 reg |= ZYNQ_PINCONF_DISABLE_RECVR; 1096 else 1097 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; 1098 1099 break; 1100 default: 1101 dev_warn(pctldev->dev, 1102 "unsupported configuration parameter '%u'\n", 1103 param); 1104 continue; 1105 } 1106 } 1107 1108 if (tristate || pullup) { 1109 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); 1110 reg |= tristate | pullup; 1111 } 1112 1113 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg); 1114 if (ret) 1115 return -EIO; 1116 1117 return 0; 1118} 1119 1120static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev, 1121 unsigned int selector, 1122 unsigned long *configs, 1123 unsigned int num_configs) 1124{ 1125 int i, ret; 1126 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1127 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector]; 1128 1129 for (i = 0; i < pgrp->npins; i++) { 1130 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs, 1131 num_configs); 1132 if (ret) 1133 return ret; 1134 } 1135 1136 return 0; 1137} 1138 1139static const struct pinconf_ops zynq_pinconf_ops = { 1140 .is_generic = true, 1141 .pin_config_get = zynq_pinconf_cfg_get, 1142 .pin_config_set = zynq_pinconf_cfg_set, 1143 .pin_config_group_set = zynq_pinconf_group_set, 1144}; 1145 1146static const struct pinctrl_desc zynq_desc = { 1147 .name = "zynq_pinctrl", 1148 .pins = zynq_pins, 1149 .npins = ARRAY_SIZE(zynq_pins), 1150 .pctlops = &zynq_pctrl_ops, 1151 .pmxops = &zynq_pinmux_ops, 1152 .confops = &zynq_pinconf_ops, 1153 .num_custom_params = ARRAY_SIZE(zynq_dt_params), 1154 .custom_params = zynq_dt_params, 1155#ifdef CONFIG_DEBUG_FS 1156 .custom_conf_items = zynq_conf_items, 1157#endif 1158 .owner = THIS_MODULE, 1159}; 1160 1161static int zynq_pinctrl_probe(struct platform_device *pdev) 1162 1163{ 1164 struct resource *res; 1165 struct zynq_pinctrl *pctrl; 1166 1167 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1168 if (!pctrl) 1169 return -ENOMEM; 1170 1171 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1172 "syscon"); 1173 if (IS_ERR(pctrl->syscon)) { 1174 dev_err(&pdev->dev, "unable to get syscon\n"); 1175 return PTR_ERR(pctrl->syscon); 1176 } 1177 1178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1179 if (!res) { 1180 dev_err(&pdev->dev, "missing IO resource\n"); 1181 return -ENODEV; 1182 } 1183 pctrl->pctrl_offset = res->start; 1184 1185 pctrl->groups = zynq_pctrl_groups; 1186 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups); 1187 pctrl->funcs = zynq_pmux_functions; 1188 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions); 1189 1190 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl); 1191 if (IS_ERR(pctrl->pctrl)) 1192 return PTR_ERR(pctrl->pctrl); 1193 1194 platform_set_drvdata(pdev, pctrl); 1195 1196 dev_info(&pdev->dev, "zynq pinctrl initialized\n"); 1197 1198 return 0; 1199} 1200 1201static const struct of_device_id zynq_pinctrl_of_match[] = { 1202 { .compatible = "xlnx,pinctrl-zynq" }, 1203 { } 1204}; 1205MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match); 1206 1207static struct platform_driver zynq_pinctrl_driver = { 1208 .driver = { 1209 .name = "zynq-pinctrl", 1210 .of_match_table = zynq_pinctrl_of_match, 1211 }, 1212 .probe = zynq_pinctrl_probe, 1213}; 1214 1215module_platform_driver(zynq_pinctrl_driver);
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