pinctrl-stmfx.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
  4 *
  5 * Copyright (C) 2019 STMicroelectronics
  6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
  7 */
  8#include <linux/gpio/driver.h>
  9#include <linux/interrupt.h>
 10#include <linux/mfd/stmfx.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/seq_file.h>
 14#include <linux/string_choices.h>
 15
 16#include <linux/pinctrl/pinconf.h>
 17#include <linux/pinctrl/pinmux.h>
 18
 19#include "core.h"
 20#include "pinctrl-utils.h"
 21
 22/* GPIOs expander */
 23/* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
 24#define STMFX_REG_GPIO_STATE		STMFX_REG_GPIO_STATE1 /* R */
 25/* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
 26#define STMFX_REG_GPIO_DIR		STMFX_REG_GPIO_DIR1 /* RW */
 27/* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
 28#define STMFX_REG_GPIO_TYPE		STMFX_REG_GPIO_TYPE1 /* RW */
 29/* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
 30#define STMFX_REG_GPIO_PUPD		STMFX_REG_GPIO_PUPD1 /* RW */
 31/* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
 32#define STMFX_REG_GPO_SET		STMFX_REG_GPO_SET1 /* RW */
 33/* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
 34#define STMFX_REG_GPO_CLR		STMFX_REG_GPO_CLR1 /* RW */
 35/* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
 36#define STMFX_REG_IRQ_GPI_SRC		STMFX_REG_IRQ_GPI_SRC1 /* RW */
 37/* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
 38#define STMFX_REG_IRQ_GPI_EVT		STMFX_REG_IRQ_GPI_EVT1 /* RW */
 39/* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
 40#define STMFX_REG_IRQ_GPI_TYPE		STMFX_REG_IRQ_GPI_TYPE1 /* RW */
 41/* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
 42#define STMFX_REG_IRQ_GPI_PENDING	STMFX_REG_IRQ_GPI_PENDING1 /* R */
 43/* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
 44#define STMFX_REG_IRQ_GPI_ACK		STMFX_REG_IRQ_GPI_ACK1 /* RW */
 45
 46#define NR_GPIO_REGS			3
 47#define NR_GPIOS_PER_REG		8
 48#define get_reg(offset)			((offset) / NR_GPIOS_PER_REG)
 49#define get_shift(offset)		((offset) % NR_GPIOS_PER_REG)
 50#define get_mask(offset)		(BIT(get_shift(offset)))
 51
 52/*
 53 * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
 54 * Pins availability is managed thanks to gpio-ranges property.
 55 */
 56static const struct pinctrl_pin_desc stmfx_pins[] = {
 57	PINCTRL_PIN(0, "gpio0"),
 58	PINCTRL_PIN(1, "gpio1"),
 59	PINCTRL_PIN(2, "gpio2"),
 60	PINCTRL_PIN(3, "gpio3"),
 61	PINCTRL_PIN(4, "gpio4"),
 62	PINCTRL_PIN(5, "gpio5"),
 63	PINCTRL_PIN(6, "gpio6"),
 64	PINCTRL_PIN(7, "gpio7"),
 65	PINCTRL_PIN(8, "gpio8"),
 66	PINCTRL_PIN(9, "gpio9"),
 67	PINCTRL_PIN(10, "gpio10"),
 68	PINCTRL_PIN(11, "gpio11"),
 69	PINCTRL_PIN(12, "gpio12"),
 70	PINCTRL_PIN(13, "gpio13"),
 71	PINCTRL_PIN(14, "gpio14"),
 72	PINCTRL_PIN(15, "gpio15"),
 73	PINCTRL_PIN(16, "agpio0"),
 74	PINCTRL_PIN(17, "agpio1"),
 75	PINCTRL_PIN(18, "agpio2"),
 76	PINCTRL_PIN(19, "agpio3"),
 77	PINCTRL_PIN(20, "agpio4"),
 78	PINCTRL_PIN(21, "agpio5"),
 79	PINCTRL_PIN(22, "agpio6"),
 80	PINCTRL_PIN(23, "agpio7"),
 81};
 82
 83struct stmfx_pinctrl {
 84	struct device *dev;
 85	struct stmfx *stmfx;
 86	struct pinctrl_dev *pctl_dev;
 87	struct pinctrl_desc pctl_desc;
 88	struct gpio_chip gpio_chip;
 89	struct mutex lock; /* IRQ bus lock */
 90	unsigned long gpio_valid_mask;
 91	/* Cache of IRQ_GPI_* registers for bus_lock */
 92	u8 irq_gpi_src[NR_GPIO_REGS];
 93	u8 irq_gpi_type[NR_GPIO_REGS];
 94	u8 irq_gpi_evt[NR_GPIO_REGS];
 95	u8 irq_toggle_edge[NR_GPIO_REGS];
 96#ifdef CONFIG_PM
 97	/* Backup of GPIO_* registers for suspend/resume */
 98	u8 bkp_gpio_state[NR_GPIO_REGS];
 99	u8 bkp_gpio_dir[NR_GPIO_REGS];
100	u8 bkp_gpio_type[NR_GPIO_REGS];
101	u8 bkp_gpio_pupd[NR_GPIO_REGS];
102#endif
103};
104
105static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
106{
107	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
108	u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
109	u32 mask = get_mask(offset);
110	u32 value;
111	int ret;
112
113	ret = regmap_read(pctl->stmfx->map, reg, &value);
114
115	return ret ? ret : !!(value & mask);
116}
117
118static int stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
119{
120	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
121	u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
122	u32 mask = get_mask(offset);
123
124	return regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
125				 mask, mask);
126}
127
128static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
129{
130	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
131	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
132	u32 mask = get_mask(offset);
133	u32 val;
134	int ret;
135
136	ret = regmap_read(pctl->stmfx->map, reg, &val);
137	/*
138	 * On stmfx, gpio pins direction is (0)input, (1)output.
139	 */
140	if (ret)
141		return ret;
142
143	if (val & mask)
144		return GPIO_LINE_DIRECTION_OUT;
145
146	return GPIO_LINE_DIRECTION_IN;
147}
148
149static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
150{
151	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
152	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
153	u32 mask = get_mask(offset);
154
155	return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
156}
157
158static int stmfx_gpio_direction_output(struct gpio_chip *gc,
159				       unsigned int offset, int value)
160{
161	struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
162	u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
163	u32 mask = get_mask(offset);
164	int ret;
165
166	ret = stmfx_gpio_set(gc, offset, value);
167	if (ret)
168		return ret;
169
170	return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
171}
172
173static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
174				  unsigned int offset)
175{
176	u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
177	u32 pupd, mask = get_mask(offset);
178	int ret;
179
180	ret = regmap_read(pctl->stmfx->map, reg, &pupd);
181	if (ret)
182		return ret;
183
184	return !!(pupd & mask);
185}
186
187static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
188				  unsigned int offset, u32 pupd)
189{
190	u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
191	u32 mask = get_mask(offset);
192
193	return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
194}
195
196static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
197				  unsigned int offset)
198{
199	u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
200	u32 type, mask = get_mask(offset);
201	int ret;
202
203	ret = regmap_read(pctl->stmfx->map, reg, &type);
204	if (ret)
205		return ret;
206
207	return !!(type & mask);
208}
209
210static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
211				  unsigned int offset, u32 type)
212{
213	u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
214	u32 mask = get_mask(offset);
215
216	return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
217}
218
219static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
220			     unsigned int pin, unsigned long *config)
221{
222	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
223	u32 param = pinconf_to_config_param(*config);
224	struct pinctrl_gpio_range *range;
225	u32 arg = 0;
226	int ret, dir, type, pupd;
227
228	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
229	if (!range)
230		return -EINVAL;
231
232	dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
233	if (dir < 0)
234		return dir;
235
236	/*
237	 * Currently the gpiolib IN is 1 and OUT is 0 but let's not count
238	 * on it just to be on the safe side also in the future :)
239	 */
240	dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
241
242	type = stmfx_pinconf_get_type(pctl, pin);
243	if (type < 0)
244		return type;
245	pupd = stmfx_pinconf_get_pupd(pctl, pin);
246	if (pupd < 0)
247		return pupd;
248
249	switch (param) {
250	case PIN_CONFIG_BIAS_DISABLE:
251		if ((!dir && (!type || !pupd)) || (dir && !type))
252			arg = 1;
253		break;
254	case PIN_CONFIG_BIAS_PULL_DOWN:
255		if (dir && type && !pupd)
256			arg = 1;
257		break;
258	case PIN_CONFIG_BIAS_PULL_UP:
259		if (type && pupd)
260			arg = 1;
261		break;
262	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
263		if ((!dir && type) || (dir && !type))
264			arg = 1;
265		break;
266	case PIN_CONFIG_DRIVE_PUSH_PULL:
267		if ((!dir && !type) || (dir && type))
268			arg = 1;
269		break;
270	case PIN_CONFIG_LEVEL:
271		if (dir)
272			return -EINVAL;
273
274		ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
275		if (ret < 0)
276			return ret;
277
278		arg = ret;
279		break;
280	default:
281		return -ENOTSUPP;
282	}
283
284	*config = pinconf_to_config_packed(param, arg);
285
286	return 0;
287}
288
289static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
290			     unsigned long *configs, unsigned int num_configs)
291{
292	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
293	struct pinctrl_gpio_range *range;
294	enum pin_config_param param;
295	u32 arg;
296	int i, ret;
297
298	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
299	if (!range) {
300		dev_err(pctldev->dev, "pin %d is not available\n", pin);
301		return -EINVAL;
302	}
303
304	for (i = 0; i < num_configs; i++) {
305		param = pinconf_to_config_param(configs[i]);
306		arg = pinconf_to_config_argument(configs[i]);
307
308		switch (param) {
309		case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
310		case PIN_CONFIG_BIAS_DISABLE:
311		case PIN_CONFIG_DRIVE_PUSH_PULL:
312			ret = stmfx_pinconf_set_type(pctl, pin, 0);
313			if (ret)
314				return ret;
315			break;
316		case PIN_CONFIG_BIAS_PULL_DOWN:
317			ret = stmfx_pinconf_set_type(pctl, pin, 1);
318			if (ret)
319				return ret;
320			ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
321			if (ret)
322				return ret;
323			break;
324		case PIN_CONFIG_BIAS_PULL_UP:
325			ret = stmfx_pinconf_set_type(pctl, pin, 1);
326			if (ret)
327				return ret;
328			ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
329			if (ret)
330				return ret;
331			break;
332		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
333			ret = stmfx_pinconf_set_type(pctl, pin, 1);
334			if (ret)
335				return ret;
336			break;
337		case PIN_CONFIG_LEVEL:
338			ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
339							  pin, arg);
340			if (ret)
341				return ret;
342			break;
343		default:
344			return -ENOTSUPP;
345		}
346	}
347
348	return 0;
349}
350
351static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
352				   struct seq_file *s, unsigned int offset)
353{
354	struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
355	struct pinctrl_gpio_range *range;
356	int dir, type, pupd, val;
357
358	range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
359	if (!range)
360		return;
361
362	dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
363	if (dir < 0)
364		return;
365	type = stmfx_pinconf_get_type(pctl, offset);
366	if (type < 0)
367		return;
368	pupd = stmfx_pinconf_get_pupd(pctl, offset);
369	if (pupd < 0)
370		return;
371	val = stmfx_gpio_get(&pctl->gpio_chip, offset);
372	if (val < 0)
373		return;
374
375	if (dir == GPIO_LINE_DIRECTION_OUT) {
376		seq_printf(s, "output %s ", str_high_low(val));
377		if (type)
378			seq_printf(s, "open drain %s internal pull-up ",
379				   pupd ? "with" : "without");
380		else
381			seq_puts(s, "push pull no pull ");
382	} else {
383		seq_printf(s, "input %s ", str_high_low(val));
384		if (type)
385			seq_printf(s, "with internal pull-%s ",
386				   str_up_down(pupd));
387		else
388			seq_printf(s, "%s ", pupd ? "floating" : "analog");
389	}
390}
391
392static const struct pinconf_ops stmfx_pinconf_ops = {
393	.pin_config_get		= stmfx_pinconf_get,
394	.pin_config_set		= stmfx_pinconf_set,
395	.pin_config_dbg_show	= stmfx_pinconf_dbg_show,
396};
397
398static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
399{
400	return 0;
401}
402
403static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
404						unsigned int selector)
405{
406	return NULL;
407}
408
409static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
410					unsigned int selector,
411					const unsigned int **pins,
412					unsigned int *num_pins)
413{
414	return -ENOTSUPP;
415}
416
417static const struct pinctrl_ops stmfx_pinctrl_ops = {
418	.get_groups_count = stmfx_pinctrl_get_groups_count,
419	.get_group_name = stmfx_pinctrl_get_group_name,
420	.get_group_pins = stmfx_pinctrl_get_group_pins,
421	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
422	.dt_free_map = pinctrl_utils_free_map,
423};
424
425static void stmfx_pinctrl_irq_mask(struct irq_data *data)
426{
427	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
428	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
429	u32 reg = get_reg(data->hwirq);
430	u32 mask = get_mask(data->hwirq);
431
432	pctl->irq_gpi_src[reg] &= ~mask;
433	gpiochip_disable_irq(gpio_chip, irqd_to_hwirq(data));
434}
435
436static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
437{
438	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
439	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
440	u32 reg = get_reg(data->hwirq);
441	u32 mask = get_mask(data->hwirq);
442
443	gpiochip_enable_irq(gpio_chip, irqd_to_hwirq(data));
444	pctl->irq_gpi_src[reg] |= mask;
445}
446
447static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
448{
449	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
450	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
451	u32 reg = get_reg(data->hwirq);
452	u32 mask = get_mask(data->hwirq);
453
454	if (type == IRQ_TYPE_NONE)
455		return -EINVAL;
456
457	if (type & IRQ_TYPE_EDGE_BOTH) {
458		pctl->irq_gpi_evt[reg] |= mask;
459		irq_set_handler_locked(data, handle_edge_irq);
460	} else {
461		pctl->irq_gpi_evt[reg] &= ~mask;
462		irq_set_handler_locked(data, handle_level_irq);
463	}
464
465	if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
466		pctl->irq_gpi_type[reg] |= mask;
467	else
468		pctl->irq_gpi_type[reg] &= ~mask;
469
470	/*
471	 * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
472	 * GPIO value to set the right edge trigger. But in atomic context
473	 * here we can't access registers over I2C. That's why (type &
474	 * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
475	 */
476
477	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
478		pctl->irq_toggle_edge[reg] |= mask;
479	else
480		pctl->irq_toggle_edge[reg] &= mask;
481
482	return 0;
483}
484
485static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
486{
487	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
488	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
489
490	mutex_lock(&pctl->lock);
491}
492
493static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
494{
495	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
496	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
497	u32 reg = get_reg(data->hwirq);
498	u32 mask = get_mask(data->hwirq);
499
500	/*
501	 * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
502	 * (this couldn't be done in .irq_set_type because of atomic context)
503	 * to set the right irq trigger type.
504	 */
505	if (pctl->irq_toggle_edge[reg] & mask) {
506		if (stmfx_gpio_get(gpio_chip, data->hwirq))
507			pctl->irq_gpi_type[reg] &= ~mask;
508		else
509			pctl->irq_gpi_type[reg] |= mask;
510	}
511
512	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
513			  pctl->irq_gpi_evt, NR_GPIO_REGS);
514	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
515			  pctl->irq_gpi_type, NR_GPIO_REGS);
516	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
517			  pctl->irq_gpi_src, NR_GPIO_REGS);
518
519	mutex_unlock(&pctl->lock);
520}
521
522static int stmfx_gpio_irq_request_resources(struct irq_data *data)
523{
524	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
525	int ret;
526
527	ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
528	if (ret)
529		return ret;
530
531	return gpiochip_reqres_irq(gpio_chip, data->hwirq);
532}
533
534static void stmfx_gpio_irq_release_resources(struct irq_data *data)
535{
536	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
537
538	return gpiochip_relres_irq(gpio_chip, data->hwirq);
539}
540
541static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
542					     unsigned int offset)
543{
544	u32 reg = get_reg(offset);
545	u32 mask = get_mask(offset);
546	int val;
547
548	if (!(pctl->irq_toggle_edge[reg] & mask))
549		return;
550
551	val = stmfx_gpio_get(&pctl->gpio_chip, offset);
552	if (val < 0)
553		return;
554
555	if (val) {
556		pctl->irq_gpi_type[reg] &= mask;
557		regmap_write_bits(pctl->stmfx->map,
558				  STMFX_REG_IRQ_GPI_TYPE + reg,
559				  mask, 0);
560
561	} else {
562		pctl->irq_gpi_type[reg] |= mask;
563		regmap_write_bits(pctl->stmfx->map,
564				  STMFX_REG_IRQ_GPI_TYPE + reg,
565				  mask, mask);
566	}
567}
568
569static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
570{
571	struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
572	struct gpio_chip *gc = &pctl->gpio_chip;
573	u8 pending[NR_GPIO_REGS];
574	u8 src[NR_GPIO_REGS] = {0, 0, 0};
575	unsigned long n, status;
576	int i, ret;
577
578	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
579			       &pending, NR_GPIO_REGS);
580	if (ret)
581		return IRQ_NONE;
582
583	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
584			  src, NR_GPIO_REGS);
585
586	BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
587	for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
588		status |= (unsigned long)pending[i] << (i * 8);
589	for_each_set_bit(n, &status, gc->ngpio) {
590		handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
591		stmfx_pinctrl_irq_toggle_trigger(pctl, n);
592	}
593
594	regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
595			  pctl->irq_gpi_src, NR_GPIO_REGS);
596
597	return IRQ_HANDLED;
598}
599
600static void stmfx_pinctrl_irq_print_chip(struct irq_data *d, struct seq_file *p)
601{
602	struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(d);
603	struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
604
605	seq_puts(p, dev_name(pctl->dev));
606}
607
608static const struct irq_chip stmfx_pinctrl_irq_chip = {
609	.irq_mask = stmfx_pinctrl_irq_mask,
610	.irq_unmask = stmfx_pinctrl_irq_unmask,
611	.irq_set_type = stmfx_pinctrl_irq_set_type,
612	.irq_bus_lock = stmfx_pinctrl_irq_bus_lock,
613	.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock,
614	.irq_request_resources = stmfx_gpio_irq_request_resources,
615	.irq_release_resources = stmfx_gpio_irq_release_resources,
616	.irq_print_chip = stmfx_pinctrl_irq_print_chip,
617	.flags = IRQCHIP_IMMUTABLE,
618};
619
620static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
621{
622	struct pinctrl_gpio_range *gpio_range;
623	struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
624	u32 func = STMFX_FUNC_GPIO;
625
626	pctl->gpio_valid_mask = GENMASK(15, 0);
627
628	gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
629	if (gpio_range) {
630		func |= STMFX_FUNC_ALTGPIO_LOW;
631		pctl->gpio_valid_mask |= GENMASK(19, 16);
632	}
633
634	gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
635	if (gpio_range) {
636		func |= STMFX_FUNC_ALTGPIO_HIGH;
637		pctl->gpio_valid_mask |= GENMASK(23, 20);
638	}
639
640	return stmfx_function_enable(pctl->stmfx, func);
641}
642
643static int stmfx_pinctrl_probe(struct platform_device *pdev)
644{
645	struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
646	struct device_node *np = pdev->dev.of_node;
647	struct stmfx_pinctrl *pctl;
648	struct gpio_irq_chip *girq;
649	int irq, ret;
650
651	pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
652	if (!pctl)
653		return -ENOMEM;
654
655	platform_set_drvdata(pdev, pctl);
656
657	pctl->dev = &pdev->dev;
658	pctl->stmfx = stmfx;
659
660	if (!of_property_present(np, "gpio-ranges")) {
661		dev_err(pctl->dev, "missing required gpio-ranges property\n");
662		return -EINVAL;
663	}
664
665	irq = platform_get_irq(pdev, 0);
666	if (irq < 0)
667		return irq;
668
669	mutex_init(&pctl->lock);
670
671	/* Register pin controller */
672	pctl->pctl_desc.name = "stmfx-pinctrl";
673	pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
674	pctl->pctl_desc.confops = &stmfx_pinconf_ops;
675	pctl->pctl_desc.pins = stmfx_pins;
676	pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
677	pctl->pctl_desc.owner = THIS_MODULE;
678	pctl->pctl_desc.link_consumers = true;
679
680	ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
681					     pctl, &pctl->pctl_dev);
682	if (ret) {
683		dev_err(pctl->dev, "pinctrl registration failed\n");
684		return ret;
685	}
686
687	ret = pinctrl_enable(pctl->pctl_dev);
688	if (ret) {
689		dev_err(pctl->dev, "pinctrl enable failed\n");
690		return ret;
691	}
692
693	/* Register gpio controller */
694	pctl->gpio_chip.label = "stmfx-gpio";
695	pctl->gpio_chip.parent = pctl->dev;
696	pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
697	pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
698	pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
699	pctl->gpio_chip.get = stmfx_gpio_get;
700	pctl->gpio_chip.set = stmfx_gpio_set;
701	pctl->gpio_chip.set_config = gpiochip_generic_config;
702	pctl->gpio_chip.base = -1;
703	pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
704	pctl->gpio_chip.can_sleep = true;
705
706	girq = &pctl->gpio_chip.irq;
707	gpio_irq_chip_set_chip(girq, &stmfx_pinctrl_irq_chip);
708	/* This will let us handle the parent IRQ in the driver */
709	girq->parent_handler = NULL;
710	girq->num_parents = 0;
711	girq->parents = NULL;
712	girq->default_type = IRQ_TYPE_NONE;
713	girq->handler = handle_bad_irq;
714	girq->threaded = true;
715
716	ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
717	if (ret) {
718		dev_err(pctl->dev, "gpio_chip registration failed\n");
719		return ret;
720	}
721
722	ret = stmfx_pinctrl_gpio_function_enable(pctl);
723	if (ret)
724		return ret;
725
726	ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
727					stmfx_pinctrl_irq_thread_fn,
728					IRQF_ONESHOT,
729					dev_name(pctl->dev), pctl);
730	if (ret) {
731		dev_err(pctl->dev, "cannot request irq%d\n", irq);
732		return ret;
733	}
734
735	dev_info(pctl->dev,
736		 "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
737
738	return 0;
739}
740
741static void stmfx_pinctrl_remove(struct platform_device *pdev)
742{
743	struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
744	int ret;
745
746	ret = stmfx_function_disable(stmfx,
747				     STMFX_FUNC_GPIO |
748				     STMFX_FUNC_ALTGPIO_LOW |
749				     STMFX_FUNC_ALTGPIO_HIGH);
750	if (ret)
751		dev_err(&pdev->dev, "Failed to disable pins (%pe)\n",
752			ERR_PTR(ret));
753}
754
755#ifdef CONFIG_PM_SLEEP
756static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
757{
758	int ret;
759
760	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
761			       &pctl->bkp_gpio_state, NR_GPIO_REGS);
762	if (ret)
763		return ret;
764	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
765			       &pctl->bkp_gpio_dir, NR_GPIO_REGS);
766	if (ret)
767		return ret;
768	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
769			       &pctl->bkp_gpio_type, NR_GPIO_REGS);
770	if (ret)
771		return ret;
772	ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
773			       &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
774	if (ret)
775		return ret;
776
777	return 0;
778}
779
780static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
781{
782	int ret;
783
784	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
785				pctl->bkp_gpio_dir, NR_GPIO_REGS);
786	if (ret)
787		return ret;
788	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
789				pctl->bkp_gpio_type, NR_GPIO_REGS);
790	if (ret)
791		return ret;
792	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
793				pctl->bkp_gpio_pupd, NR_GPIO_REGS);
794	if (ret)
795		return ret;
796	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
797				pctl->bkp_gpio_state, NR_GPIO_REGS);
798	if (ret)
799		return ret;
800	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
801				pctl->irq_gpi_evt, NR_GPIO_REGS);
802	if (ret)
803		return ret;
804	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
805				pctl->irq_gpi_type, NR_GPIO_REGS);
806	if (ret)
807		return ret;
808	ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
809				pctl->irq_gpi_src, NR_GPIO_REGS);
810	if (ret)
811		return ret;
812
813	return 0;
814}
815
816static int stmfx_pinctrl_suspend(struct device *dev)
817{
818	struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
819	int ret;
820
821	ret = stmfx_pinctrl_backup_regs(pctl);
822	if (ret) {
823		dev_err(pctl->dev, "registers backup failure\n");
824		return ret;
825	}
826
827	return 0;
828}
829
830static int stmfx_pinctrl_resume(struct device *dev)
831{
832	struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
833	int ret;
834
835	ret = stmfx_pinctrl_restore_regs(pctl);
836	if (ret) {
837		dev_err(pctl->dev, "registers restoration failure\n");
838		return ret;
839	}
840
841	return 0;
842}
843#endif
844
845static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
846			 stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
847
848static const struct of_device_id stmfx_pinctrl_of_match[] = {
849	{ .compatible = "st,stmfx-0300-pinctrl", },
850	{},
851};
852MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
853
854static struct platform_driver stmfx_pinctrl_driver = {
855	.driver = {
856		.name = "stmfx-pinctrl",
857		.of_match_table = stmfx_pinctrl_of_match,
858		.pm = &stmfx_pinctrl_dev_pm_ops,
859	},
860	.probe = stmfx_pinctrl_probe,
861	.remove = stmfx_pinctrl_remove,
862};
863module_platform_driver(stmfx_pinctrl_driver);
864
865MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
866MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
867MODULE_LICENSE("GPL v2");