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pinctrl-st.c
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linux-6.19.14/drivers/pinctrl/pinctrl-st.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 STMicroelectronics (R&D) Limited. 4 * Authors: 5 * Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 */ 7 8#include <linux/err.h> 9#include <linux/gpio/driver.h> 10#include <linux/init.h> 11#include <linux/io.h> 12#include <linux/mfd/syscon.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/of_irq.h> 17#include <linux/platform_device.h> 18#include <linux/regmap.h> 19#include <linux/seq_file.h> 20#include <linux/slab.h> 21#include <linux/string_helpers.h> 22 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/pinconf.h> 25#include <linux/pinctrl/pinctrl.h> 26#include <linux/pinctrl/pinmux.h> 27 28#include "core.h" 29 30/* PIO Block registers */ 31/* PIO output */ 32#define REG_PIO_POUT 0x00 33/* Set bits of POUT */ 34#define REG_PIO_SET_POUT 0x04 35/* Clear bits of POUT */ 36#define REG_PIO_CLR_POUT 0x08 37/* PIO input */ 38#define REG_PIO_PIN 0x10 39/* PIO configuration */ 40#define REG_PIO_PC(n) (0x20 + (n) * 0x10) 41/* Set bits of PC[2:0] */ 42#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10) 43/* Clear bits of PC[2:0] */ 44#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10) 45/* PIO input comparison */ 46#define REG_PIO_PCOMP 0x50 47/* Set bits of PCOMP */ 48#define REG_PIO_SET_PCOMP 0x54 49/* Clear bits of PCOMP */ 50#define REG_PIO_CLR_PCOMP 0x58 51/* PIO input comparison mask */ 52#define REG_PIO_PMASK 0x60 53/* Set bits of PMASK */ 54#define REG_PIO_SET_PMASK 0x64 55/* Clear bits of PMASK */ 56#define REG_PIO_CLR_PMASK 0x68 57 58#define ST_GPIO_DIRECTION_BIDIR 0x1 59#define ST_GPIO_DIRECTION_OUT 0x2 60#define ST_GPIO_DIRECTION_IN 0x4 61 62/* 63 * Packed style retime configuration. 64 * There are two registers cfg0 and cfg1 in this style for each bank. 65 * Each field in this register is 8 bit corresponding to 8 pins in the bank. 66 */ 67#define RT_P_CFGS_PER_BANK 2 68#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) 69#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) 70#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) 71#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) 72#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) 73#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) 74#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) 75 76/* 77 * Dedicated style retime Configuration register 78 * each register is dedicated per pin. 79 */ 80#define RT_D_CFGS_PER_BANK 8 81#define RT_D_CFG_CLK_SHIFT 0 82#define RT_D_CFG_CLK_MASK (0x3 << 0) 83#define RT_D_CFG_CLKNOTDATA_SHIFT 2 84#define RT_D_CFG_CLKNOTDATA_MASK BIT(2) 85#define RT_D_CFG_DELAY_SHIFT 3 86#define RT_D_CFG_DELAY_MASK (0xf << 3) 87#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7 88#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7) 89#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8 90#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8) 91#define RT_D_CFG_INVERTCLK_SHIFT 9 92#define RT_D_CFG_INVERTCLK_MASK BIT(9) 93#define RT_D_CFG_RETIME_SHIFT 10 94#define RT_D_CFG_RETIME_MASK BIT(10) 95 96/* 97 * Pinconf is represented in an opaque unsigned long variable. 98 * Below is the bit allocation details for each possible configuration. 99 * All the bit fields can be encapsulated into four variables 100 * (direction, retime-type, retime-clk, retime-delay) 101 * 102 * +----------------+ 103 *[31:28]| reserved-3 | 104 * +----------------+------------- 105 *[27] | oe | | 106 * +----------------+ v 107 *[26] | pu | [Direction ] 108 * +----------------+ ^ 109 *[25] | od | | 110 * +----------------+------------- 111 *[24] | reserved-2 | 112 * +----------------+------------- 113 *[23] | retime | | 114 * +----------------+ | 115 *[22] | retime-invclk | | 116 * +----------------+ v 117 *[21] |retime-clknotdat| [Retime-type ] 118 * +----------------+ ^ 119 *[20] | retime-de | | 120 * +----------------+------------- 121 *[19:18]| retime-clk |------>[Retime-Clk ] 122 * +----------------+ 123 *[17:16]| reserved-1 | 124 * +----------------+ 125 *[15..0]| retime-delay |------>[Retime Delay] 126 * +----------------+ 127 */ 128 129#define ST_PINCONF_UNPACK(conf, param)\ 130 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \ 131 & ST_PINCONF_ ##param ##_MASK) 132 133#define ST_PINCONF_PACK(conf, val, param) (conf |=\ 134 ((val & ST_PINCONF_ ##param ##_MASK) << \ 135 ST_PINCONF_ ##param ##_SHIFT)) 136 137/* Output enable */ 138#define ST_PINCONF_OE_MASK 0x1 139#define ST_PINCONF_OE_SHIFT 27 140#define ST_PINCONF_OE BIT(27) 141#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 142#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE) 143 144/* Pull Up */ 145#define ST_PINCONF_PU_MASK 0x1 146#define ST_PINCONF_PU_SHIFT 26 147#define ST_PINCONF_PU BIT(26) 148#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU) 149#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU) 150 151/* Open Drain */ 152#define ST_PINCONF_OD_MASK 0x1 153#define ST_PINCONF_OD_SHIFT 25 154#define ST_PINCONF_OD BIT(25) 155#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD) 156#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD) 157 158#define ST_PINCONF_RT_MASK 0x1 159#define ST_PINCONF_RT_SHIFT 23 160#define ST_PINCONF_RT BIT(23) 161#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT) 162#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT) 163 164#define ST_PINCONF_RT_INVERTCLK_MASK 0x1 165#define ST_PINCONF_RT_INVERTCLK_SHIFT 22 166#define ST_PINCONF_RT_INVERTCLK BIT(22) 167#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \ 168 ST_PINCONF_UNPACK(conf, RT_INVERTCLK) 169#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \ 170 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK) 171 172#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1 173#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21 174#define ST_PINCONF_RT_CLKNOTDATA BIT(21) 175#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \ 176 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA) 177#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \ 178 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA) 179 180#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1 181#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20 182#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20) 183#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \ 184 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE) 185#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \ 186 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE) 187 188#define ST_PINCONF_RT_CLK_MASK 0x3 189#define ST_PINCONF_RT_CLK_SHIFT 18 190#define ST_PINCONF_RT_CLK BIT(18) 191#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK) 192#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK) 193 194/* RETIME_DELAY in Pico Secs */ 195#define ST_PINCONF_RT_DELAY_MASK 0xffff 196#define ST_PINCONF_RT_DELAY_SHIFT 0 197#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY) 198#define ST_PINCONF_PACK_RT_DELAY(conf, val) \ 199 ST_PINCONF_PACK(conf, val, RT_DELAY) 200 201#define ST_GPIO_PINS_PER_BANK (8) 202#define OF_GPIO_ARGS_MIN (4) 203#define OF_RT_ARGS_MIN (2) 204 205#define gpio_range_to_bank(chip) \ 206 container_of(chip, struct st_gpio_bank, range) 207 208#define pc_to_bank(pc) \ 209 container_of(pc, struct st_gpio_bank, pc) 210 211enum st_retime_style { 212 st_retime_style_none, 213 st_retime_style_packed, 214 st_retime_style_dedicated, 215}; 216 217struct st_retime_dedicated { 218 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK]; 219}; 220 221struct st_retime_packed { 222 struct regmap_field *clk1notclk0; 223 struct regmap_field *delay_0; 224 struct regmap_field *delay_1; 225 struct regmap_field *invertclk; 226 struct regmap_field *retime; 227 struct regmap_field *clknotdata; 228 struct regmap_field *double_edge; 229}; 230 231struct st_pio_control { 232 u32 rt_pin_mask; 233 struct regmap_field *alt, *oe, *pu, *od; 234 /* retiming */ 235 union { 236 struct st_retime_packed rt_p; 237 struct st_retime_dedicated rt_d; 238 } rt; 239}; 240 241struct st_pctl_data { 242 const enum st_retime_style rt_style; 243 const unsigned int *input_delays; 244 const int ninput_delays; 245 const unsigned int *output_delays; 246 const int noutput_delays; 247 /* register offset information */ 248 const int alt, oe, pu, od, rt; 249}; 250 251struct st_pinconf { 252 int pin; 253 const char *name; 254 unsigned long config; 255 int altfunc; 256}; 257 258struct st_pmx_func { 259 const char *name; 260 const char **groups; 261 unsigned ngroups; 262}; 263 264struct st_pctl_group { 265 const char *name; 266 unsigned int *pins; 267 unsigned npins; 268 struct st_pinconf *pin_conf; 269}; 270 271/* 272 * Edge triggers are not supported at hardware level, it is supported by 273 * software by exploiting the level trigger support in hardware. 274 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration 275 * of each gpio pin in a GPIO bank. 276 * 277 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of 278 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank. 279 * 280 * bit allocation per pin is: 281 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31] 282 * -------------------------------------------------------- 283 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 | 284 * -------------------------------------------------------- 285 * 286 * A pin can have one of following the values in its edge configuration field. 287 * 288 * ------- ---------------------------- 289 * [0-3] - Description 290 * ------- ---------------------------- 291 * 0000 - No edge IRQ. 292 * 0001 - Falling edge IRQ. 293 * 0010 - Rising edge IRQ. 294 * 0011 - Rising and Falling edge IRQ. 295 * ------- ---------------------------- 296 */ 297 298#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4 299#define ST_IRQ_EDGE_MASK 0xf 300#define ST_IRQ_EDGE_FALLING BIT(0) 301#define ST_IRQ_EDGE_RISING BIT(1) 302#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1)) 303 304#define ST_IRQ_RISING_EDGE_CONF(pin) \ 305 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 306 307#define ST_IRQ_FALLING_EDGE_CONF(pin) \ 308 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 309 310#define ST_IRQ_BOTH_EDGE_CONF(pin) \ 311 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)) 312 313#define ST_IRQ_EDGE_CONF(conf, pin) \ 314 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK) 315 316struct st_gpio_bank { 317 struct gpio_chip gpio_chip; 318 struct pinctrl_gpio_range range; 319 void __iomem *base; 320 struct st_pio_control pc; 321 unsigned long irq_edge_conf; 322 spinlock_t lock; 323}; 324 325struct st_pinctrl { 326 struct device *dev; 327 struct pinctrl_dev *pctl; 328 struct st_gpio_bank *banks; 329 int nbanks; 330 struct st_pmx_func *functions; 331 int nfunctions; 332 struct st_pctl_group *groups; 333 int ngroups; 334 struct regmap *regmap; 335 const struct st_pctl_data *data; 336 void __iomem *irqmux_base; 337}; 338 339/* SOC specific data */ 340 341static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250, 342 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 }; 343 344static const struct st_pctl_data stih407_data = { 345 .rt_style = st_retime_style_dedicated, 346 .input_delays = stih407_delays, 347 .ninput_delays = ARRAY_SIZE(stih407_delays), 348 .output_delays = stih407_delays, 349 .noutput_delays = ARRAY_SIZE(stih407_delays), 350 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100, 351}; 352 353static const struct st_pctl_data stih407_flashdata = { 354 .rt_style = st_retime_style_none, 355 .input_delays = stih407_delays, 356 .ninput_delays = ARRAY_SIZE(stih407_delays), 357 .output_delays = stih407_delays, 358 .noutput_delays = ARRAY_SIZE(stih407_delays), 359 .alt = 0, 360 .oe = -1, /* Not Available */ 361 .pu = -1, /* Not Available */ 362 .od = 60, 363 .rt = 100, 364}; 365 366static struct st_pio_control *st_get_pio_control( 367 struct pinctrl_dev *pctldev, int pin) 368{ 369 struct pinctrl_gpio_range *range = 370 pinctrl_find_gpio_range_from_pin(pctldev, pin); 371 struct st_gpio_bank *bank = gpio_range_to_bank(range); 372 373 return &bank->pc; 374} 375 376/* Low level functions.. */ 377static inline int st_gpio_pin(int gpio) 378{ 379 return gpio%ST_GPIO_PINS_PER_BANK; 380} 381 382static void st_pinconf_set_config(struct st_pio_control *pc, 383 int pin, unsigned long config) 384{ 385 struct regmap_field *output_enable = pc->oe; 386 struct regmap_field *pull_up = pc->pu; 387 struct regmap_field *open_drain = pc->od; 388 unsigned int oe_value, pu_value, od_value; 389 unsigned long mask = BIT(pin); 390 391 if (output_enable) { 392 regmap_field_read(output_enable, &oe_value); 393 oe_value &= ~mask; 394 if (config & ST_PINCONF_OE) 395 oe_value |= mask; 396 regmap_field_write(output_enable, oe_value); 397 } 398 399 if (pull_up) { 400 regmap_field_read(pull_up, &pu_value); 401 pu_value &= ~mask; 402 if (config & ST_PINCONF_PU) 403 pu_value |= mask; 404 regmap_field_write(pull_up, pu_value); 405 } 406 407 if (open_drain) { 408 regmap_field_read(open_drain, &od_value); 409 od_value &= ~mask; 410 if (config & ST_PINCONF_OD) 411 od_value |= mask; 412 regmap_field_write(open_drain, od_value); 413 } 414} 415 416static void st_pctl_set_function(struct st_pio_control *pc, 417 int pin_id, int function) 418{ 419 struct regmap_field *alt = pc->alt; 420 unsigned int val; 421 int pin = st_gpio_pin(pin_id); 422 int offset = pin * 4; 423 424 if (!alt) 425 return; 426 427 regmap_field_read(alt, &val); 428 val &= ~(0xf << offset); 429 val |= function << offset; 430 regmap_field_write(alt, val); 431} 432 433static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin) 434{ 435 struct regmap_field *alt = pc->alt; 436 unsigned int val; 437 int offset = pin * 4; 438 439 if (!alt) 440 return 0; 441 442 regmap_field_read(alt, &val); 443 444 return (val >> offset) & 0xf; 445} 446 447static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 448 const struct st_pctl_data *data, unsigned long config) 449{ 450 const unsigned int *delay_times; 451 int num_delay_times, i, closest_index = -1; 452 unsigned int closest_divergence = UINT_MAX; 453 454 if (ST_PINCONF_UNPACK_OE(config)) { 455 delay_times = data->output_delays; 456 num_delay_times = data->noutput_delays; 457 } else { 458 delay_times = data->input_delays; 459 num_delay_times = data->ninput_delays; 460 } 461 462 for (i = 0; i < num_delay_times; i++) { 463 unsigned int divergence = abs(delay - delay_times[i]); 464 465 if (divergence == 0) 466 return i; 467 468 if (divergence < closest_divergence) { 469 closest_divergence = divergence; 470 closest_index = i; 471 } 472 } 473 474 pr_warn("Attempt to set delay %d, closest available %d\n", 475 delay, delay_times[closest_index]); 476 477 return closest_index; 478} 479 480static unsigned long st_pinconf_bit_to_delay(unsigned int index, 481 const struct st_pctl_data *data, unsigned long output) 482{ 483 const unsigned int *delay_times; 484 int num_delay_times; 485 486 if (output) { 487 delay_times = data->output_delays; 488 num_delay_times = data->noutput_delays; 489 } else { 490 delay_times = data->input_delays; 491 num_delay_times = data->ninput_delays; 492 } 493 494 if (index < num_delay_times) { 495 return delay_times[index]; 496 } else { 497 pr_warn("Delay not found in/out delay list\n"); 498 return 0; 499 } 500} 501 502static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field, 503 int enable, int pin) 504{ 505 unsigned int val = 0; 506 507 regmap_field_read(field, &val); 508 if (enable) 509 val |= BIT(pin); 510 else 511 val &= ~BIT(pin); 512 regmap_field_write(field, val); 513} 514 515static void st_pinconf_set_retime_packed(struct st_pinctrl *info, 516 struct st_pio_control *pc, unsigned long config, int pin) 517{ 518 const struct st_pctl_data *data = info->data; 519 struct st_retime_packed *rt_p = &pc->rt.rt_p; 520 unsigned int delay; 521 522 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0, 523 ST_PINCONF_UNPACK_RT_CLK(config), pin); 524 525 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata, 526 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin); 527 528 st_regmap_field_bit_set_clear_pin(rt_p->double_edge, 529 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin); 530 531 st_regmap_field_bit_set_clear_pin(rt_p->invertclk, 532 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin); 533 534 st_regmap_field_bit_set_clear_pin(rt_p->retime, 535 ST_PINCONF_UNPACK_RT(config), pin); 536 537 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config), 538 data, config); 539 /* 2 bit delay, lsb */ 540 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin); 541 /* 2 bit delay, msb */ 542 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin); 543} 544 545static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info, 546 struct st_pio_control *pc, unsigned long config, int pin) 547{ 548 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1; 549 int clk = ST_PINCONF_UNPACK_RT_CLK(config); 550 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config); 551 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config); 552 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config); 553 int retime = ST_PINCONF_UNPACK_RT(config); 554 555 unsigned long delay = st_pinconf_delay_to_bit( 556 ST_PINCONF_UNPACK_RT_DELAY(config), 557 info->data, config); 558 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 559 560 unsigned long retime_config = 561 ((clk) << RT_D_CFG_CLK_SHIFT) | 562 ((delay) << RT_D_CFG_DELAY_SHIFT) | 563 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) | 564 ((retime) << RT_D_CFG_RETIME_SHIFT) | 565 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) | 566 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) | 567 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT); 568 569 regmap_field_write(rt_d->rt[pin], retime_config); 570} 571 572static void st_pinconf_get_direction(struct st_pio_control *pc, 573 int pin, unsigned long *config) 574{ 575 unsigned int oe_value, pu_value, od_value; 576 577 if (pc->oe) { 578 regmap_field_read(pc->oe, &oe_value); 579 if (oe_value & BIT(pin)) 580 ST_PINCONF_PACK_OE(*config); 581 } 582 583 if (pc->pu) { 584 regmap_field_read(pc->pu, &pu_value); 585 if (pu_value & BIT(pin)) 586 ST_PINCONF_PACK_PU(*config); 587 } 588 589 if (pc->od) { 590 regmap_field_read(pc->od, &od_value); 591 if (od_value & BIT(pin)) 592 ST_PINCONF_PACK_OD(*config); 593 } 594} 595 596static int st_pinconf_get_retime_packed(struct st_pinctrl *info, 597 struct st_pio_control *pc, int pin, unsigned long *config) 598{ 599 const struct st_pctl_data *data = info->data; 600 struct st_retime_packed *rt_p = &pc->rt.rt_p; 601 unsigned int delay_bits, delay, delay0, delay1, val; 602 int output = ST_PINCONF_UNPACK_OE(*config); 603 604 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin))) 605 ST_PINCONF_PACK_RT(*config); 606 607 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin))) 608 ST_PINCONF_PACK_RT_CLK(*config, 1); 609 610 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin))) 611 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 612 613 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin))) 614 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 615 616 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin))) 617 ST_PINCONF_PACK_RT_INVERTCLK(*config); 618 619 regmap_field_read(rt_p->delay_0, &delay0); 620 regmap_field_read(rt_p->delay_1, &delay1); 621 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) | 622 (((delay0 & BIT(pin)) ? 1 : 0)); 623 delay = st_pinconf_bit_to_delay(delay_bits, data, output); 624 ST_PINCONF_PACK_RT_DELAY(*config, delay); 625 626 return 0; 627} 628 629static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info, 630 struct st_pio_control *pc, int pin, unsigned long *config) 631{ 632 unsigned int value; 633 unsigned long delay_bits, delay, rt_clk; 634 int output = ST_PINCONF_UNPACK_OE(*config); 635 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 636 637 regmap_field_read(rt_d->rt[pin], &value); 638 639 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT; 640 ST_PINCONF_PACK_RT_CLK(*config, rt_clk); 641 642 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT; 643 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output); 644 ST_PINCONF_PACK_RT_DELAY(*config, delay); 645 646 if (value & RT_D_CFG_CLKNOTDATA_MASK) 647 ST_PINCONF_PACK_RT_CLKNOTDATA(*config); 648 649 if (value & RT_D_CFG_DOUBLE_EDGE_MASK) 650 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config); 651 652 if (value & RT_D_CFG_INVERTCLK_MASK) 653 ST_PINCONF_PACK_RT_INVERTCLK(*config); 654 655 if (value & RT_D_CFG_RETIME_MASK) 656 ST_PINCONF_PACK_RT(*config); 657 658 return 0; 659} 660 661/* GPIO related functions */ 662 663static inline void __st_gpio_set(struct st_gpio_bank *bank, 664 unsigned offset, int value) 665{ 666 if (value) 667 writel(BIT(offset), bank->base + REG_PIO_SET_POUT); 668 else 669 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT); 670} 671 672static void st_gpio_direction(struct st_gpio_bank *bank, 673 unsigned int gpio, unsigned int direction) 674{ 675 int offset = st_gpio_pin(gpio); 676 int i = 0; 677 /** 678 * There are three configuration registers (PIOn_PC0, PIOn_PC1 679 * and PIOn_PC2) for each port. These are used to configure the 680 * PIO port pins. Each pin can be configured as an input, output, 681 * bidirectional, or alternative function pin. Three bits, one bit 682 * from each of the three registers, configure the corresponding bit of 683 * the port. Valid bit settings is: 684 * 685 * PC2 PC1 PC0 Direction. 686 * 0 0 0 [Input Weak pull-up] 687 * 0 0 or 1 1 [Bidirection] 688 * 0 1 0 [Output] 689 * 1 0 0 [Input] 690 * 691 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits 692 * individually. 693 */ 694 for (i = 0; i <= 2; i++) { 695 if (direction & BIT(i)) 696 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i)); 697 else 698 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i)); 699 } 700} 701 702static int st_gpio_get(struct gpio_chip *chip, unsigned offset) 703{ 704 struct st_gpio_bank *bank = gpiochip_get_data(chip); 705 706 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset)); 707} 708 709static int st_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 710{ 711 struct st_gpio_bank *bank = gpiochip_get_data(chip); 712 __st_gpio_set(bank, offset, value); 713 714 return 0; 715} 716 717static int st_gpio_direction_output(struct gpio_chip *chip, 718 unsigned offset, int value) 719{ 720 struct st_gpio_bank *bank = gpiochip_get_data(chip); 721 722 __st_gpio_set(bank, offset, value); 723 724 return pinctrl_gpio_direction_output(chip, offset); 725} 726 727static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 728{ 729 struct st_gpio_bank *bank = gpiochip_get_data(chip); 730 struct st_pio_control pc = bank->pc; 731 unsigned long config; 732 unsigned int direction = 0; 733 unsigned int function; 734 unsigned int value; 735 int i = 0; 736 737 /* Alternate function direction is handled by Pinctrl */ 738 function = st_pctl_get_pin_function(&pc, offset); 739 if (function) { 740 st_pinconf_get_direction(&pc, offset, &config); 741 if (ST_PINCONF_UNPACK_OE(config)) 742 return GPIO_LINE_DIRECTION_OUT; 743 744 return GPIO_LINE_DIRECTION_IN; 745 } 746 747 /* 748 * GPIO direction is handled differently 749 * - See st_gpio_direction() above for an explanation 750 */ 751 for (i = 0; i <= 2; i++) { 752 value = readl(bank->base + REG_PIO_PC(i)); 753 direction |= ((value >> offset) & 0x1) << i; 754 } 755 756 if (direction == ST_GPIO_DIRECTION_IN) 757 return GPIO_LINE_DIRECTION_IN; 758 759 return GPIO_LINE_DIRECTION_OUT; 760} 761 762/* Pinctrl Groups */ 763static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev) 764{ 765 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 766 767 return info->ngroups; 768} 769 770static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev, 771 unsigned selector) 772{ 773 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 774 775 return info->groups[selector].name; 776} 777 778static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev, 779 unsigned selector, const unsigned **pins, unsigned *npins) 780{ 781 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 782 783 if (selector >= info->ngroups) 784 return -EINVAL; 785 786 *pins = info->groups[selector].pins; 787 *npins = info->groups[selector].npins; 788 789 return 0; 790} 791 792static inline const struct st_pctl_group *st_pctl_find_group_by_name( 793 const struct st_pinctrl *info, const char *name) 794{ 795 int i; 796 797 for (i = 0; i < info->ngroups; i++) { 798 if (!strcmp(info->groups[i].name, name)) 799 return &info->groups[i]; 800 } 801 802 return NULL; 803} 804 805static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, 806 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps) 807{ 808 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 809 const struct st_pctl_group *grp; 810 struct device *dev = info->dev; 811 struct pinctrl_map *new_map; 812 struct device_node *parent; 813 int map_num, i; 814 815 grp = st_pctl_find_group_by_name(info, np->name); 816 if (!grp) { 817 dev_err(dev, "unable to find group for node %pOFn\n", np); 818 return -EINVAL; 819 } 820 821 map_num = grp->npins + 1; 822 new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL); 823 if (!new_map) 824 return -ENOMEM; 825 826 parent = of_get_parent(np); 827 if (!parent) { 828 devm_kfree(dev, new_map); 829 return -EINVAL; 830 } 831 832 *map = new_map; 833 *num_maps = map_num; 834 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 835 new_map[0].data.mux.function = parent->name; 836 new_map[0].data.mux.group = np->name; 837 of_node_put(parent); 838 839 /* create config map per pin */ 840 new_map++; 841 for (i = 0; i < grp->npins; i++) { 842 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 843 new_map[i].data.configs.group_or_pin = 844 pin_get_name(pctldev, grp->pins[i]); 845 new_map[i].data.configs.configs = &grp->pin_conf[i].config; 846 new_map[i].data.configs.num_configs = 1; 847 } 848 dev_info(dev, "maps: function %s group %s num %d\n", 849 (*map)->data.mux.function, grp->name, map_num); 850 851 return 0; 852} 853 854static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev, 855 struct pinctrl_map *map, unsigned num_maps) 856{ 857} 858 859static const struct pinctrl_ops st_pctlops = { 860 .get_groups_count = st_pctl_get_groups_count, 861 .get_group_pins = st_pctl_get_group_pins, 862 .get_group_name = st_pctl_get_group_name, 863 .dt_node_to_map = st_pctl_dt_node_to_map, 864 .dt_free_map = st_pctl_dt_free_map, 865}; 866 867/* Pinmux */ 868static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 869{ 870 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 871 872 return info->nfunctions; 873} 874 875static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev, 876 unsigned selector) 877{ 878 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 879 880 return info->functions[selector].name; 881} 882 883static int st_pmx_get_groups(struct pinctrl_dev *pctldev, 884 unsigned selector, const char * const **grps, unsigned * const ngrps) 885{ 886 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 887 *grps = info->functions[selector].groups; 888 *ngrps = info->functions[selector].ngroups; 889 890 return 0; 891} 892 893static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 894 unsigned group) 895{ 896 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 897 struct st_pinconf *conf = info->groups[group].pin_conf; 898 struct st_pio_control *pc; 899 int i; 900 901 for (i = 0; i < info->groups[group].npins; i++) { 902 pc = st_get_pio_control(pctldev, conf[i].pin); 903 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc); 904 } 905 906 return 0; 907} 908 909static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev, 910 struct pinctrl_gpio_range *range, unsigned gpio, 911 bool input) 912{ 913 struct st_gpio_bank *bank = gpio_range_to_bank(range); 914 /* 915 * When a PIO bank is used in its primary function mode (altfunc = 0) 916 * Output Enable (OE), Open Drain(OD), and Pull Up (PU) 917 * for the primary PIO functions are driven by the related PIO block 918 */ 919 st_pctl_set_function(&bank->pc, gpio, 0); 920 st_gpio_direction(bank, gpio, input ? 921 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT); 922 923 return 0; 924} 925 926static const struct pinmux_ops st_pmxops = { 927 .get_functions_count = st_pmx_get_funcs_count, 928 .get_function_name = st_pmx_get_fname, 929 .get_function_groups = st_pmx_get_groups, 930 .set_mux = st_pmx_set_mux, 931 .gpio_set_direction = st_pmx_set_gpio_direction, 932 .strict = true, 933}; 934 935/* Pinconf */ 936static void st_pinconf_get_retime(struct st_pinctrl *info, 937 struct st_pio_control *pc, int pin, unsigned long *config) 938{ 939 if (info->data->rt_style == st_retime_style_packed) 940 st_pinconf_get_retime_packed(info, pc, pin, config); 941 else if (info->data->rt_style == st_retime_style_dedicated) 942 if ((BIT(pin) & pc->rt_pin_mask)) 943 st_pinconf_get_retime_dedicated(info, pc, 944 pin, config); 945} 946 947static void st_pinconf_set_retime(struct st_pinctrl *info, 948 struct st_pio_control *pc, int pin, unsigned long config) 949{ 950 if (info->data->rt_style == st_retime_style_packed) 951 st_pinconf_set_retime_packed(info, pc, config, pin); 952 else if (info->data->rt_style == st_retime_style_dedicated) 953 if ((BIT(pin) & pc->rt_pin_mask)) 954 st_pinconf_set_retime_dedicated(info, pc, 955 config, pin); 956} 957 958static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id, 959 unsigned long *configs, unsigned num_configs) 960{ 961 int pin = st_gpio_pin(pin_id); 962 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 963 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 964 int i; 965 966 for (i = 0; i < num_configs; i++) { 967 st_pinconf_set_config(pc, pin, configs[i]); 968 st_pinconf_set_retime(info, pc, pin, configs[i]); 969 } /* for each config */ 970 971 return 0; 972} 973 974static int st_pinconf_get(struct pinctrl_dev *pctldev, 975 unsigned pin_id, unsigned long *config) 976{ 977 int pin = st_gpio_pin(pin_id); 978 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 979 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id); 980 981 *config = 0; 982 st_pinconf_get_direction(pc, pin, config); 983 st_pinconf_get_retime(info, pc, pin, config); 984 985 return 0; 986} 987 988static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 989 struct seq_file *s, unsigned pin_id) 990{ 991 struct st_pio_control *pc; 992 unsigned long config; 993 unsigned int function; 994 int offset = st_gpio_pin(pin_id); 995 char f[16]; 996 int oe; 997 998 mutex_unlock(&pctldev->mutex); 999 pc = st_get_pio_control(pctldev, pin_id); 1000 st_pinconf_get(pctldev, pin_id, &config); 1001 mutex_lock(&pctldev->mutex); 1002 1003 function = st_pctl_get_pin_function(pc, offset); 1004 if (function) 1005 snprintf(f, 10, "Alt Fn %u", function); 1006 else 1007 snprintf(f, 5, "GPIO"); 1008 1009 oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset); 1010 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n" 1011 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1012 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1013 (oe == GPIO_LINE_DIRECTION_OUT), 1014 ST_PINCONF_UNPACK_PU(config), 1015 ST_PINCONF_UNPACK_OD(config), 1016 f, 1017 ST_PINCONF_UNPACK_RT(config), 1018 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1019 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1020 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), 1021 ST_PINCONF_UNPACK_RT_CLK(config), 1022 ST_PINCONF_UNPACK_RT_DELAY(config)); 1023} 1024 1025static const struct pinconf_ops st_confops = { 1026 .pin_config_get = st_pinconf_get, 1027 .pin_config_set = st_pinconf_set, 1028 .pin_config_dbg_show = st_pinconf_dbg_show, 1029}; 1030 1031static void st_pctl_dt_child_count(struct st_pinctrl *info, 1032 struct device_node *np) 1033{ 1034 struct device_node *child; 1035 for_each_child_of_node(np, child) { 1036 if (of_property_read_bool(child, "gpio-controller")) { 1037 info->nbanks++; 1038 } else { 1039 info->nfunctions++; 1040 info->ngroups += of_get_child_count(child); 1041 } 1042 } 1043} 1044 1045static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info, 1046 int bank, struct st_pio_control *pc) 1047{ 1048 struct device *dev = info->dev; 1049 struct regmap *rm = info->regmap; 1050 const struct st_pctl_data *data = info->data; 1051 /* 2 registers per bank */ 1052 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; 1053 struct st_retime_packed *rt_p = &pc->rt.rt_p; 1054 /* cfg0 */ 1055 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); 1056 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); 1057 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); 1058 /* cfg1 */ 1059 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); 1060 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); 1061 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); 1062 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); 1063 1064 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0); 1065 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0); 1066 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1); 1067 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk); 1068 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime); 1069 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata); 1070 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge); 1071 1072 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) || 1073 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) || 1074 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) || 1075 IS_ERR(rt_p->double_edge)) 1076 return -EINVAL; 1077 1078 return 0; 1079} 1080 1081static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info, 1082 int bank, struct st_pio_control *pc) 1083{ 1084 struct device *dev = info->dev; 1085 struct regmap *rm = info->regmap; 1086 const struct st_pctl_data *data = info->data; 1087 /* 8 registers per bank */ 1088 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; 1089 struct st_retime_dedicated *rt_d = &pc->rt.rt_d; 1090 unsigned int j; 1091 u32 pin_mask = pc->rt_pin_mask; 1092 1093 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) { 1094 if (BIT(j) & pin_mask) { 1095 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); 1096 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); 1097 if (IS_ERR(rt_d->rt[j])) 1098 return -EINVAL; 1099 reg_offset += 4; 1100 } 1101 } 1102 return 0; 1103} 1104 1105static int st_pctl_dt_setup_retime(struct st_pinctrl *info, 1106 int bank, struct st_pio_control *pc) 1107{ 1108 const struct st_pctl_data *data = info->data; 1109 if (data->rt_style == st_retime_style_packed) 1110 return st_pctl_dt_setup_retime_packed(info, bank, pc); 1111 else if (data->rt_style == st_retime_style_dedicated) 1112 return st_pctl_dt_setup_retime_dedicated(info, bank, pc); 1113 1114 return -EINVAL; 1115} 1116 1117 1118static struct regmap_field *st_pc_get_value(struct device *dev, 1119 struct regmap *regmap, int bank, 1120 int data, int lsb, int msb) 1121{ 1122 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); 1123 1124 if (data < 0) 1125 return NULL; 1126 1127 return devm_regmap_field_alloc(dev, regmap, reg); 1128} 1129 1130static void st_parse_syscfgs(struct st_pinctrl *info, int bank, 1131 struct device_node *np) 1132{ 1133 const struct st_pctl_data *data = info->data; 1134 /** 1135 * For a given shared register like OE/PU/OD, there are 8 bits per bank 1136 * 0:7 belongs to bank0, 8:15 belongs to bank1 ... 1137 * So each register is shared across 4 banks. 1138 */ 1139 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK; 1140 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1; 1141 struct st_pio_control *pc = &info->banks[bank].pc; 1142 struct device *dev = info->dev; 1143 struct regmap *regmap = info->regmap; 1144 1145 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31); 1146 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb); 1147 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb); 1148 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb); 1149 1150 /* retime avaiable for all pins by default */ 1151 pc->rt_pin_mask = 0xff; 1152 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask); 1153 st_pctl_dt_setup_retime(info, bank, pc); 1154 1155 return; 1156} 1157 1158static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, 1159 phandle bank, unsigned int offset) 1160{ 1161 struct device_node *np; 1162 struct gpio_chip *chip; 1163 int retval = -EINVAL; 1164 int i; 1165 1166 np = of_find_node_by_phandle(bank); 1167 if (!np) 1168 return -EINVAL; 1169 1170 for (i = 0; i < info->nbanks; i++) { 1171 chip = &info->banks[i].gpio_chip; 1172 if (chip->fwnode == of_fwnode_handle(np)) { 1173 if (offset < chip->ngpio) 1174 retval = chip->base + offset; 1175 break; 1176 } 1177 } 1178 1179 of_node_put(np); 1180 return retval; 1181} 1182 1183/* 1184 * Each pin is represented in of the below forms. 1185 * <bank offset mux direction rt_type rt_delay rt_clk> 1186 */ 1187static int st_pctl_dt_parse_groups(struct device_node *np, 1188 struct st_pctl_group *grp, struct st_pinctrl *info, int idx) 1189{ 1190 /* bank pad direction val altfunction */ 1191 const __be32 *list; 1192 struct property *pp; 1193 struct device *dev = info->dev; 1194 struct st_pinconf *conf; 1195 struct device_node *pins __free(device_node) = NULL; 1196 phandle bank; 1197 unsigned int offset; 1198 int i = 0, npins = 0, nr_props; 1199 1200 pins = of_get_child_by_name(np, "st,pins"); 1201 if (!pins) 1202 return -ENODATA; 1203 1204 for_each_property_of_node(pins, pp) { 1205 /* Skip those we do not want to proceed */ 1206 if (!strcmp(pp->name, "name")) 1207 continue; 1208 1209 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) { 1210 npins++; 1211 } else { 1212 pr_warn("Invalid st,pins in %pOFn node\n", np); 1213 return -EINVAL; 1214 } 1215 } 1216 1217 grp->npins = npins; 1218 grp->name = np->name; 1219 grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL); 1220 grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL); 1221 1222 if (!grp->pins || !grp->pin_conf) 1223 return -ENOMEM; 1224 1225 /* <bank offset mux direction rt_type rt_delay rt_clk> */ 1226 for_each_property_of_node(pins, pp) { 1227 if (!strcmp(pp->name, "name")) 1228 continue; 1229 nr_props = pp->length/sizeof(u32); 1230 list = pp->value; 1231 conf = &grp->pin_conf[i]; 1232 1233 /* bank & offset */ 1234 bank = be32_to_cpup(list++); 1235 offset = be32_to_cpup(list++); 1236 conf->pin = st_pctl_dt_calculate_pin(info, bank, offset); 1237 conf->name = pp->name; 1238 grp->pins[i] = conf->pin; 1239 /* mux */ 1240 conf->altfunc = be32_to_cpup(list++); 1241 conf->config = 0; 1242 /* direction */ 1243 conf->config |= be32_to_cpup(list++); 1244 /* rt_type rt_delay rt_clk */ 1245 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) { 1246 /* rt_type */ 1247 conf->config |= be32_to_cpup(list++); 1248 /* rt_delay */ 1249 conf->config |= be32_to_cpup(list++); 1250 /* rt_clk */ 1251 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) 1252 conf->config |= be32_to_cpup(list++); 1253 } 1254 i++; 1255 } 1256 1257 return 0; 1258} 1259 1260static int st_pctl_parse_functions(struct device_node *np, 1261 struct st_pinctrl *info, u32 index, int *grp_index) 1262{ 1263 struct device *dev = info->dev; 1264 struct st_pmx_func *func; 1265 struct st_pctl_group *grp; 1266 int ret, i; 1267 1268 func = &info->functions[index]; 1269 func->name = np->name; 1270 func->ngroups = of_get_child_count(np); 1271 if (func->ngroups == 0) 1272 return dev_err_probe(dev, -EINVAL, "No groups defined\n"); 1273 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 1274 if (!func->groups) 1275 return -ENOMEM; 1276 1277 i = 0; 1278 for_each_child_of_node_scoped(np, child) { 1279 func->groups[i] = child->name; 1280 grp = &info->groups[*grp_index]; 1281 *grp_index += 1; 1282 ret = st_pctl_dt_parse_groups(child, grp, info, i++); 1283 if (ret) 1284 return ret; 1285 } 1286 dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); 1287 1288 return 0; 1289} 1290 1291static void st_gpio_irq_mask(struct irq_data *d) 1292{ 1293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1294 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1295 1296 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); 1297 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 1298} 1299 1300static void st_gpio_irq_unmask(struct irq_data *d) 1301{ 1302 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1303 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1304 1305 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 1306 writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); 1307} 1308 1309static int st_gpio_irq_request_resources(struct irq_data *d) 1310{ 1311 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1312 1313 pinctrl_gpio_direction_input(gc, d->hwirq); 1314 1315 return gpiochip_reqres_irq(gc, d->hwirq); 1316} 1317 1318static void st_gpio_irq_release_resources(struct irq_data *d) 1319{ 1320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1321 1322 gpiochip_relres_irq(gc, d->hwirq); 1323} 1324 1325static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) 1326{ 1327 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1328 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1329 unsigned long flags; 1330 int comp, pin = d->hwirq; 1331 u32 val; 1332 u32 pin_edge_conf = 0; 1333 1334 switch (type) { 1335 case IRQ_TYPE_LEVEL_HIGH: 1336 comp = 0; 1337 break; 1338 case IRQ_TYPE_EDGE_FALLING: 1339 comp = 0; 1340 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin); 1341 break; 1342 case IRQ_TYPE_LEVEL_LOW: 1343 comp = 1; 1344 break; 1345 case IRQ_TYPE_EDGE_RISING: 1346 comp = 1; 1347 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin); 1348 break; 1349 case IRQ_TYPE_EDGE_BOTH: 1350 comp = st_gpio_get(&bank->gpio_chip, pin); 1351 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin); 1352 break; 1353 default: 1354 return -EINVAL; 1355 } 1356 1357 spin_lock_irqsave(&bank->lock, flags); 1358 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << ( 1359 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN)); 1360 bank->irq_edge_conf |= pin_edge_conf; 1361 spin_unlock_irqrestore(&bank->lock, flags); 1362 1363 val = readl(bank->base + REG_PIO_PCOMP); 1364 val &= ~BIT(pin); 1365 val |= (comp << pin); 1366 writel(val, bank->base + REG_PIO_PCOMP); 1367 1368 return 0; 1369} 1370 1371/* 1372 * As edge triggers are not supported at hardware level, it is supported by 1373 * software by exploiting the level trigger support in hardware. 1374 * 1375 * Steps for detection raising edge interrupt in software. 1376 * 1377 * Step 1: CONFIGURE pin to detect level LOW interrupts. 1378 * 1379 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler, 1380 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt. 1381 * IGNORE calling the actual interrupt handler for the pin at this stage. 1382 * 1383 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler 1384 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then 1385 * DISPATCH the interrupt to the interrupt handler of the pin. 1386 * 1387 * step-1 ________ __________ 1388 * | | step - 3 1389 * | | 1390 * step -2 |_____| 1391 * 1392 * falling edge is also detected int the same way. 1393 * 1394 */ 1395static void __gpio_irq_handler(struct st_gpio_bank *bank) 1396{ 1397 unsigned long port_in, port_mask, port_comp, active_irqs; 1398 unsigned long bank_edge_mask, flags; 1399 int n, val, ecfg; 1400 1401 spin_lock_irqsave(&bank->lock, flags); 1402 bank_edge_mask = bank->irq_edge_conf; 1403 spin_unlock_irqrestore(&bank->lock, flags); 1404 1405 for (;;) { 1406 port_in = readl(bank->base + REG_PIO_PIN); 1407 port_comp = readl(bank->base + REG_PIO_PCOMP); 1408 port_mask = readl(bank->base + REG_PIO_PMASK); 1409 1410 active_irqs = (port_in ^ port_comp) & port_mask; 1411 1412 if (active_irqs == 0) 1413 break; 1414 1415 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) { 1416 /* check if we are detecting fake edges ... */ 1417 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n); 1418 1419 if (ecfg) { 1420 /* edge detection. */ 1421 val = st_gpio_get(&bank->gpio_chip, n); 1422 1423 writel(BIT(n), 1424 val ? bank->base + REG_PIO_SET_PCOMP : 1425 bank->base + REG_PIO_CLR_PCOMP); 1426 1427 if (ecfg != ST_IRQ_EDGE_BOTH && 1428 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val)) 1429 continue; 1430 } 1431 1432 generic_handle_domain_irq(bank->gpio_chip.irq.domain, n); 1433 } 1434 } 1435} 1436 1437static void st_gpio_irq_handler(struct irq_desc *desc) 1438{ 1439 /* interrupt dedicated per bank */ 1440 struct irq_chip *chip = irq_desc_get_chip(desc); 1441 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1442 struct st_gpio_bank *bank = gpiochip_get_data(gc); 1443 1444 chained_irq_enter(chip, desc); 1445 __gpio_irq_handler(bank); 1446 chained_irq_exit(chip, desc); 1447} 1448 1449static void st_gpio_irqmux_handler(struct irq_desc *desc) 1450{ 1451 struct irq_chip *chip = irq_desc_get_chip(desc); 1452 struct st_pinctrl *info = irq_desc_get_handler_data(desc); 1453 unsigned long status; 1454 int n; 1455 1456 chained_irq_enter(chip, desc); 1457 1458 status = readl(info->irqmux_base); 1459 1460 for_each_set_bit(n, &status, info->nbanks) 1461 __gpio_irq_handler(&info->banks[n]); 1462 1463 chained_irq_exit(chip, desc); 1464} 1465 1466static const struct gpio_chip st_gpio_template = { 1467 .request = gpiochip_generic_request, 1468 .free = gpiochip_generic_free, 1469 .get = st_gpio_get, 1470 .set = st_gpio_set, 1471 .direction_input = pinctrl_gpio_direction_input, 1472 .direction_output = st_gpio_direction_output, 1473 .get_direction = st_gpio_get_direction, 1474 .ngpio = ST_GPIO_PINS_PER_BANK, 1475}; 1476 1477static const struct irq_chip st_gpio_irqchip = { 1478 .name = "GPIO", 1479 .irq_request_resources = st_gpio_irq_request_resources, 1480 .irq_release_resources = st_gpio_irq_release_resources, 1481 .irq_disable = st_gpio_irq_mask, 1482 .irq_mask = st_gpio_irq_mask, 1483 .irq_unmask = st_gpio_irq_unmask, 1484 .irq_set_type = st_gpio_irq_set_type, 1485 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1486}; 1487 1488static int st_gpiolib_register_bank(struct st_pinctrl *info, 1489 int bank_nr, struct device_node *np) 1490{ 1491 struct st_gpio_bank *bank = &info->banks[bank_nr]; 1492 struct pinctrl_gpio_range *range = &bank->range; 1493 struct device *dev = info->dev; 1494 int bank_num = of_alias_get_id(np, "gpio"); 1495 struct resource res, irq_res; 1496 int err; 1497 1498 if (of_address_to_resource(np, 0, &res)) 1499 return -ENODEV; 1500 1501 bank->base = devm_ioremap_resource(dev, &res); 1502 if (IS_ERR(bank->base)) 1503 return PTR_ERR(bank->base); 1504 1505 bank->gpio_chip = st_gpio_template; 1506 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; 1507 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; 1508 bank->gpio_chip.fwnode = of_fwnode_handle(np); 1509 bank->gpio_chip.parent = dev; 1510 spin_lock_init(&bank->lock); 1511 1512 of_property_read_string(np, "st,bank-name", &range->name); 1513 bank->gpio_chip.label = range->name; 1514 1515 range->id = bank_num; 1516 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK; 1517 range->npins = bank->gpio_chip.ngpio; 1518 range->gc = &bank->gpio_chip; 1519 1520 /** 1521 * GPIO bank can have one of the two possible types of 1522 * interrupt-wirings. 1523 * 1524 * First type is via irqmux, single interrupt is used by multiple 1525 * gpio banks. This reduces number of overall interrupts numbers 1526 * required. All these banks belong to a single pincontroller. 1527 * _________ 1528 * | |----> [gpio-bank (n) ] 1529 * | |----> [gpio-bank (n + 1)] 1530 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] 1531 * | |----> [gpio-bank (... )] 1532 * |_________|----> [gpio-bank (n + 7)] 1533 * 1534 * Second type has a dedicated interrupt per each gpio bank. 1535 * 1536 * [irqN]----> [gpio-bank (n)] 1537 */ 1538 1539 if (of_irq_to_resource(np, 0, &irq_res) > 0) { 1540 struct gpio_irq_chip *girq; 1541 int gpio_irq = irq_res.start; 1542 1543 /* This is not a valid IRQ */ 1544 if (gpio_irq <= 0) { 1545 dev_err(dev, "invalid IRQ for %pOF bank\n", np); 1546 goto skip_irq; 1547 } 1548 /* We need to have a mux as well */ 1549 if (!info->irqmux_base) { 1550 dev_err(dev, "no irqmux for %pOF bank\n", np); 1551 goto skip_irq; 1552 } 1553 1554 girq = &bank->gpio_chip.irq; 1555 gpio_irq_chip_set_chip(girq, &st_gpio_irqchip); 1556 girq->parent_handler = st_gpio_irq_handler; 1557 girq->num_parents = 1; 1558 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 1559 GFP_KERNEL); 1560 if (!girq->parents) 1561 return -ENOMEM; 1562 girq->parents[0] = gpio_irq; 1563 girq->default_type = IRQ_TYPE_NONE; 1564 girq->handler = handle_simple_irq; 1565 } 1566 1567skip_irq: 1568 err = gpiochip_add_data(&bank->gpio_chip, bank); 1569 if (err) 1570 return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num); 1571 dev_info(dev, "%s bank added.\n", range->name); 1572 1573 return 0; 1574} 1575 1576static const struct of_device_id st_pctl_of_match[] = { 1577 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data}, 1578 { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data}, 1579 { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data}, 1580 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata}, 1581 { /* sentinel */ } 1582}; 1583 1584static int st_pctl_probe_dt(struct platform_device *pdev, 1585 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info) 1586{ 1587 struct device *dev = &pdev->dev; 1588 int ret = 0; 1589 int i = 0, j = 0, k = 0, bank; 1590 struct pinctrl_pin_desc *pdesc; 1591 struct device_node *np = dev->of_node; 1592 int grp_index = 0; 1593 int irq = 0; 1594 1595 st_pctl_dt_child_count(info, np); 1596 if (!info->nbanks) 1597 return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n"); 1598 1599 dev_info(dev, "nbanks = %d\n", info->nbanks); 1600 dev_info(dev, "nfunctions = %d\n", info->nfunctions); 1601 dev_info(dev, "ngroups = %d\n", info->ngroups); 1602 1603 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 1604 1605 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 1606 1607 info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL); 1608 1609 if (!info->functions || !info->groups || !info->banks) 1610 return -ENOMEM; 1611 1612 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1613 if (IS_ERR(info->regmap)) 1614 return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n"); 1615 info->data = of_match_node(st_pctl_of_match, np)->data; 1616 1617 irq = platform_get_irq(pdev, 0); 1618 1619 if (irq > 0) { 1620 info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux"); 1621 if (IS_ERR(info->irqmux_base)) 1622 return PTR_ERR(info->irqmux_base); 1623 1624 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler, 1625 info); 1626 } 1627 1628 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK; 1629 pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL); 1630 if (!pdesc) 1631 return -ENOMEM; 1632 1633 pctl_desc->pins = pdesc; 1634 1635 bank = 0; 1636 for_each_child_of_node_scoped(np, child) { 1637 if (of_property_read_bool(child, "gpio-controller")) { 1638 const char *bank_name = NULL; 1639 char **pin_names; 1640 1641 ret = st_gpiolib_register_bank(info, bank, child); 1642 if (ret) 1643 return ret; 1644 1645 k = info->banks[bank].range.pin_base; 1646 bank_name = info->banks[bank].range.name; 1647 1648 pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK); 1649 if (IS_ERR(pin_names)) 1650 return PTR_ERR(pin_names); 1651 1652 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { 1653 pdesc->number = k; 1654 pdesc->name = pin_names[j]; 1655 pdesc++; 1656 } 1657 st_parse_syscfgs(info, bank, child); 1658 bank++; 1659 } else { 1660 ret = st_pctl_parse_functions(child, info, 1661 i++, &grp_index); 1662 if (ret) { 1663 dev_err(dev, "No functions found.\n"); 1664 return ret; 1665 } 1666 } 1667 } 1668 1669 return 0; 1670} 1671 1672static int st_pctl_probe(struct platform_device *pdev) 1673{ 1674 struct device *dev = &pdev->dev; 1675 struct st_pinctrl *info; 1676 struct pinctrl_desc *pctl_desc; 1677 int ret, i; 1678 1679 if (!dev->of_node) { 1680 dev_err(dev, "device node not found.\n"); 1681 return -EINVAL; 1682 } 1683 1684 pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL); 1685 if (!pctl_desc) 1686 return -ENOMEM; 1687 1688 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1689 if (!info) 1690 return -ENOMEM; 1691 1692 info->dev = dev; 1693 platform_set_drvdata(pdev, info); 1694 ret = st_pctl_probe_dt(pdev, pctl_desc, info); 1695 if (ret) 1696 return ret; 1697 1698 pctl_desc->owner = THIS_MODULE; 1699 pctl_desc->pctlops = &st_pctlops; 1700 pctl_desc->pmxops = &st_pmxops; 1701 pctl_desc->confops = &st_confops; 1702 pctl_desc->name = dev_name(dev); 1703 1704 info->pctl = devm_pinctrl_register(dev, pctl_desc, info); 1705 if (IS_ERR(info->pctl)) 1706 return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n"); 1707 1708 for (i = 0; i < info->nbanks; i++) 1709 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range); 1710 1711 return 0; 1712} 1713 1714static struct platform_driver st_pctl_driver = { 1715 .driver = { 1716 .name = "st-pinctrl", 1717 .of_match_table = st_pctl_of_match, 1718 }, 1719 .probe = st_pctl_probe, 1720}; 1721 1722static int __init st_pctl_init(void) 1723{ 1724 return platform_driver_register(&st_pctl_driver); 1725} 1726arch_initcall(st_pctl_init);
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