pinctrl-single.c

   1/*
   2 * Generic device tree based pinctrl driver for one register per pin
   3 * type pinmux controllers
   4 *
   5 * Copyright (C) 2012 Texas Instruments, Inc.
   6 *
   7 * This file is licensed under the terms of the GNU General Public
   8 * License version 2. This program is licensed "as is" without any
   9 * warranty of any kind, whether express or implied.
  10 */
  11
  12#include <linux/init.h>
  13#include <linux/module.h>
  14#include <linux/io.h>
  15#include <linux/platform_device.h>
  16#include <linux/slab.h>
  17#include <linux/err.h>
  18#include <linux/list.h>
  19#include <linux/interrupt.h>
  20#include <linux/irqchip/chained_irq.h>
  21#include <linux/of.h>
  22#include <linux/of_irq.h>
  23#include <linux/seq_file.h>
  24
  25#include <linux/pinctrl/pinconf-generic.h>
  26#include <linux/pinctrl/pinconf.h>
  27#include <linux/pinctrl/pinctrl.h>
  28#include <linux/pinctrl/pinmux.h>
  29
  30#include <linux/platform_data/pinctrl-single.h>
  31
  32#include "core.h"
  33#include "devicetree.h"
  34#include "pinconf.h"
  35#include "pinmux.h"
  36
  37#define DRIVER_NAME			"pinctrl-single"
  38#define PCS_OFF_DISABLED		~0U
  39
  40/**
  41 * struct pcs_func_vals - mux function register offset and value pair
  42 * @reg:	register virtual address
  43 * @val:	register value
  44 * @mask:	mask
  45 */
  46struct pcs_func_vals {
  47	void __iomem *reg;
  48	unsigned val;
  49	unsigned mask;
  50};
  51
  52/**
  53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  54 * and value, enable, disable, mask
  55 * @param:	config parameter
  56 * @val:	user input bits in the pinconf register
  57 * @enable:	enable bits in the pinconf register
  58 * @disable:	disable bits in the pinconf register
  59 * @mask:	mask bits in the register value
  60 */
  61struct pcs_conf_vals {
  62	enum pin_config_param param;
  63	unsigned val;
  64	unsigned enable;
  65	unsigned disable;
  66	unsigned mask;
  67};
  68
  69/**
  70 * struct pcs_conf_type - pinconf property name, pinconf param pair
  71 * @name:	property name in DTS file
  72 * @param:	config parameter
  73 */
  74struct pcs_conf_type {
  75	const char *name;
  76	enum pin_config_param param;
  77};
  78
  79/**
  80 * struct pcs_function - pinctrl function
  81 * @name:	pinctrl function name
  82 * @vals:	register and vals array
  83 * @nvals:	number of entries in vals array
  84 * @conf:	array of pin configurations
  85 * @nconfs:	number of pin configurations available
  86 * @node:	list node
  87 */
  88struct pcs_function {
  89	const char *name;
  90	struct pcs_func_vals *vals;
  91	unsigned nvals;
  92	struct pcs_conf_vals *conf;
  93	int nconfs;
  94	struct list_head node;
  95};
  96
  97/**
  98 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
  99 * @offset:	offset base of pins
 100 * @npins:	number pins with the same mux value of gpio function
 101 * @gpiofunc:	mux value of gpio function
 102 * @node:	list node
 103 */
 104struct pcs_gpiofunc_range {
 105	unsigned offset;
 106	unsigned npins;
 107	unsigned gpiofunc;
 108	struct list_head node;
 109};
 110
 111/**
 112 * struct pcs_data - wrapper for data needed by pinctrl framework
 113 * @pa:		pindesc array
 114 * @cur:	index to current element
 115 *
 116 * REVISIT: We should be able to drop this eventually by adding
 117 * support for registering pins individually in the pinctrl
 118 * framework for those drivers that don't need a static array.
 119 */
 120struct pcs_data {
 121	struct pinctrl_pin_desc *pa;
 122	int cur;
 123};
 124
 125/**
 126 * struct pcs_soc_data - SoC specific settings
 127 * @flags:	initial SoC specific PCS_FEAT_xxx values
 128 * @irq:	optional interrupt for the controller
 129 * @irq_enable_mask:	optional SoC specific interrupt enable mask
 130 * @irq_status_mask:	optional SoC specific interrupt status mask
 131 * @rearm:	optional SoC specific wake-up rearm function
 132 */
 133struct pcs_soc_data {
 134	unsigned flags;
 135	int irq;
 136	unsigned irq_enable_mask;
 137	unsigned irq_status_mask;
 138	void (*rearm)(void);
 139};
 140
 141/**
 142 * struct pcs_device - pinctrl device instance
 143 * @res:	resources
 144 * @base:	virtual address of the controller
 145 * @saved_vals: saved values for the controller
 146 * @size:	size of the ioremapped area
 147 * @dev:	device entry
 148 * @np:		device tree node
 149 * @pctl:	pin controller device
 150 * @flags:	mask of PCS_FEAT_xxx values
 151 * @missing_nr_pinctrl_cells: for legacy binding, may go away
 152 * @socdata:	soc specific data
 153 * @lock:	spinlock for register access
 154 * @mutex:	mutex protecting the lists
 155 * @width:	bits per mux register
 156 * @fmask:	function register mask
 157 * @fshift:	function register shift
 158 * @foff:	value to turn mux off
 159 * @fmax:	max number of functions in fmask
 160 * @bits_per_mux: number of bits per mux
 161 * @bits_per_pin: number of bits per pin
 162 * @pins:	physical pins on the SoC
 163 * @gpiofuncs:	list of gpio functions
 164 * @irqs:	list of interrupt registers
 165 * @chip:	chip container for this instance
 166 * @domain:	IRQ domain for this instance
 167 * @desc:	pin controller descriptor
 168 * @read:	register read function to use
 169 * @write:	register write function to use
 170 */
 171struct pcs_device {
 172	struct resource *res;
 173	void __iomem *base;
 174	void *saved_vals;
 175	unsigned size;
 176	struct device *dev;
 177	struct device_node *np;
 178	struct pinctrl_dev *pctl;
 179	unsigned flags;
 180#define PCS_CONTEXT_LOSS_OFF	(1 << 3)
 181#define PCS_QUIRK_SHARED_IRQ	(1 << 2)
 182#define PCS_FEAT_IRQ		(1 << 1)
 183#define PCS_FEAT_PINCONF	(1 << 0)
 184	struct property *missing_nr_pinctrl_cells;
 185	struct pcs_soc_data socdata;
 186	raw_spinlock_t lock;
 187	struct mutex mutex;
 188	unsigned width;
 189	unsigned fmask;
 190	unsigned fshift;
 191	unsigned foff;
 192	unsigned fmax;
 193	bool bits_per_mux;
 194	unsigned bits_per_pin;
 195	struct pcs_data pins;
 196	struct list_head gpiofuncs;
 197	struct list_head irqs;
 198	struct irq_chip chip;
 199	struct irq_domain *domain;
 200	struct pinctrl_desc desc;
 201	unsigned (*read)(void __iomem *reg);
 202	void (*write)(unsigned val, void __iomem *reg);
 203};
 204
 205#define PCS_QUIRK_HAS_SHARED_IRQ	(pcs->flags & PCS_QUIRK_SHARED_IRQ)
 206#define PCS_HAS_IRQ		(pcs->flags & PCS_FEAT_IRQ)
 207#define PCS_HAS_PINCONF		(pcs->flags & PCS_FEAT_PINCONF)
 208
 209static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 210			   unsigned long *config);
 211static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 212			   unsigned long *configs, unsigned num_configs);
 213
 214static enum pin_config_param pcs_bias[] = {
 215	PIN_CONFIG_BIAS_PULL_DOWN,
 216	PIN_CONFIG_BIAS_PULL_UP,
 217};
 218
 219/*
 220 * This lock class tells lockdep that irqchip core that this single
 221 * pinctrl can be in a different category than its parents, so it won't
 222 * report false recursion.
 223 */
 224static struct lock_class_key pcs_lock_class;
 225
 226/* Class for the IRQ request mutex */
 227static struct lock_class_key pcs_request_class;
 228
 229/*
 230 * REVISIT: Reads and writes could eventually use regmap or something
 231 * generic. But at least on omaps, some mux registers are performance
 232 * critical as they may need to be remuxed every time before and after
 233 * idle. Adding tests for register access width for every read and
 234 * write like regmap is doing is not desired, and caching the registers
 235 * does not help in this case.
 236 */
 237
 238static unsigned int pcs_readb(void __iomem *reg)
 239{
 240	return readb(reg);
 241}
 242
 243static unsigned int pcs_readw(void __iomem *reg)
 244{
 245	return readw(reg);
 246}
 247
 248static unsigned int pcs_readl(void __iomem *reg)
 249{
 250	return readl(reg);
 251}
 252
 253static void pcs_writeb(unsigned int val, void __iomem *reg)
 254{
 255	writeb(val, reg);
 256}
 257
 258static void pcs_writew(unsigned int val, void __iomem *reg)
 259{
 260	writew(val, reg);
 261}
 262
 263static void pcs_writel(unsigned int val, void __iomem *reg)
 264{
 265	writel(val, reg);
 266}
 267
 268static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
 269					   unsigned int pin)
 270{
 271	unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
 272
 273	if (pcs->bits_per_mux) {
 274		unsigned int pin_offset_bytes;
 275
 276		pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 277		return (pin_offset_bytes / mux_bytes) * mux_bytes;
 278	}
 279
 280	return pin * mux_bytes;
 281}
 282
 283static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
 284					  unsigned int pin)
 285{
 286	return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
 287}
 288
 289static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 290					struct seq_file *s,
 291					unsigned pin)
 292{
 293	struct pcs_device *pcs;
 294	unsigned int val;
 295	unsigned long offset;
 296	size_t pa;
 297
 298	pcs = pinctrl_dev_get_drvdata(pctldev);
 299
 300	offset = pcs_pin_reg_offset_get(pcs, pin);
 301	val = pcs->read(pcs->base + offset);
 302
 303	if (pcs->bits_per_mux)
 304		val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
 305
 306	pa = pcs->res->start + offset;
 307
 308	seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 309}
 310
 311static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 312				struct pinctrl_map *map, unsigned num_maps)
 313{
 314	struct pcs_device *pcs;
 315
 316	pcs = pinctrl_dev_get_drvdata(pctldev);
 317	devm_kfree(pcs->dev, map);
 318}
 319
 320static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 321				struct device_node *np_config,
 322				struct pinctrl_map **map, unsigned *num_maps);
 323
 324static const struct pinctrl_ops pcs_pinctrl_ops = {
 325	.get_groups_count = pinctrl_generic_get_group_count,
 326	.get_group_name = pinctrl_generic_get_group_name,
 327	.get_group_pins = pinctrl_generic_get_group_pins,
 328	.pin_dbg_show = pcs_pin_dbg_show,
 329	.dt_node_to_map = pcs_dt_node_to_map,
 330	.dt_free_map = pcs_dt_free_map,
 331};
 332
 333static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 334			    struct pcs_function **func)
 335{
 336	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 337	struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 338	const struct pinctrl_setting_mux *setting;
 339	const struct function_desc *function;
 340	unsigned fselector;
 341
 342	/* If pin is not described in DTS & enabled, mux_setting is NULL. */
 343	setting = pdesc->mux_setting;
 344	if (!setting)
 345		return -ENOTSUPP;
 346	fselector = setting->func;
 347	function = pinmux_generic_get_function(pctldev, fselector);
 348	if (!function)
 349		return -EINVAL;
 350	*func = function->data;
 351	if (!(*func)) {
 352		dev_err(pcs->dev, "%s could not find function%i\n",
 353			__func__, fselector);
 354		return -ENOTSUPP;
 355	}
 356	return 0;
 357}
 358
 359static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 360	unsigned group)
 361{
 362	struct pcs_device *pcs;
 363	const struct function_desc *function;
 364	struct pcs_function *func;
 365	int i;
 366
 367	pcs = pinctrl_dev_get_drvdata(pctldev);
 368	/* If function mask is null, needn't enable it. */
 369	if (!pcs->fmask)
 370		return 0;
 371	function = pinmux_generic_get_function(pctldev, fselector);
 372	if (!function)
 373		return -EINVAL;
 374	func = function->data;
 375	if (!func)
 376		return -EINVAL;
 377
 378	dev_dbg(pcs->dev, "enabling %s function%i\n",
 379		func->name, fselector);
 380
 381	for (i = 0; i < func->nvals; i++) {
 382		struct pcs_func_vals *vals;
 383		unsigned long flags;
 384		unsigned val, mask;
 385
 386		vals = &func->vals[i];
 387		raw_spin_lock_irqsave(&pcs->lock, flags);
 388		val = pcs->read(vals->reg);
 389
 390		if (pcs->bits_per_mux)
 391			mask = vals->mask;
 392		else
 393			mask = pcs->fmask;
 394
 395		val &= ~mask;
 396		val |= (vals->val & mask);
 397		pcs->write(val, vals->reg);
 398		raw_spin_unlock_irqrestore(&pcs->lock, flags);
 399	}
 400
 401	return 0;
 402}
 403
 404static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 405			    struct pinctrl_gpio_range *range, unsigned pin)
 406{
 407	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 408	struct pcs_gpiofunc_range *frange = NULL;
 409	struct list_head *pos, *tmp;
 410	unsigned data;
 411
 412	/* If function mask is null, return directly. */
 413	if (!pcs->fmask)
 414		return -ENOTSUPP;
 415
 416	list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 417		u32 offset;
 418
 419		frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 420		if (pin >= frange->offset + frange->npins
 421			|| pin < frange->offset)
 422			continue;
 423
 424		offset = pcs_pin_reg_offset_get(pcs, pin);
 425
 426		if (pcs->bits_per_mux) {
 427			int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
 428
 429			data = pcs->read(pcs->base + offset);
 430			data &= ~(pcs->fmask << pin_shift);
 431			data |= frange->gpiofunc << pin_shift;
 432			pcs->write(data, pcs->base + offset);
 433		} else {
 434			data = pcs->read(pcs->base + offset);
 435			data &= ~pcs->fmask;
 436			data |= frange->gpiofunc;
 437			pcs->write(data, pcs->base + offset);
 438		}
 439		break;
 440	}
 441	return 0;
 442}
 443
 444static const struct pinmux_ops pcs_pinmux_ops = {
 445	.get_functions_count = pinmux_generic_get_function_count,
 446	.get_function_name = pinmux_generic_get_function_name,
 447	.get_function_groups = pinmux_generic_get_function_groups,
 448	.set_mux = pcs_set_mux,
 449	.gpio_request_enable = pcs_request_gpio,
 450};
 451
 452/* Clear BIAS value */
 453static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 454{
 455	unsigned long config;
 456	int i;
 457	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 458		config = pinconf_to_config_packed(pcs_bias[i], 0);
 459		pcs_pinconf_set(pctldev, pin, &config, 1);
 460	}
 461}
 462
 463/*
 464 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 465 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 466 */
 467static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 468{
 469	unsigned long config;
 470	int i;
 471
 472	for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 473		config = pinconf_to_config_packed(pcs_bias[i], 0);
 474		if (!pcs_pinconf_get(pctldev, pin, &config))
 475			goto out;
 476	}
 477	return true;
 478out:
 479	return false;
 480}
 481
 482static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 483				unsigned pin, unsigned long *config)
 484{
 485	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 486	struct pcs_function *func;
 487	enum pin_config_param param;
 488	unsigned offset = 0, data = 0, i, j;
 489	int ret;
 490
 491	ret = pcs_get_function(pctldev, pin, &func);
 492	if (ret)
 493		return ret;
 494
 495	for (i = 0; i < func->nconfs; i++) {
 496		param = pinconf_to_config_param(*config);
 497		if (param == PIN_CONFIG_BIAS_DISABLE) {
 498			if (pcs_pinconf_bias_disable(pctldev, pin)) {
 499				*config = 0;
 500				return 0;
 501			} else {
 502				return -ENOTSUPP;
 503			}
 504		} else if (param != func->conf[i].param) {
 505			continue;
 506		}
 507
 508		offset = pin * (pcs->width / BITS_PER_BYTE);
 509		data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 510		switch (func->conf[i].param) {
 511		/* 4 parameters */
 512		case PIN_CONFIG_BIAS_PULL_DOWN:
 513		case PIN_CONFIG_BIAS_PULL_UP:
 514		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 515			if ((data != func->conf[i].enable) ||
 516			    (data == func->conf[i].disable))
 517				return -ENOTSUPP;
 518			*config = 0;
 519			break;
 520		/* 2 parameters */
 521		case PIN_CONFIG_INPUT_SCHMITT:
 522			for (j = 0; j < func->nconfs; j++) {
 523				switch (func->conf[j].param) {
 524				case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 525					if (data != func->conf[j].enable)
 526						return -ENOTSUPP;
 527					break;
 528				default:
 529					break;
 530				}
 531			}
 532			*config = data;
 533			break;
 534		case PIN_CONFIG_DRIVE_STRENGTH:
 535		case PIN_CONFIG_SLEW_RATE:
 536		case PIN_CONFIG_MODE_LOW_POWER:
 537		case PIN_CONFIG_INPUT_ENABLE:
 538		default:
 539			*config = data;
 540			break;
 541		}
 542		return 0;
 543	}
 544	return -ENOTSUPP;
 545}
 546
 547static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 548				unsigned pin, unsigned long *configs,
 549				unsigned num_configs)
 550{
 551	struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 552	struct pcs_function *func;
 553	unsigned offset = 0, shift = 0, i, data;
 554	u32 arg;
 555	int j, ret;
 556	enum pin_config_param param;
 557
 558	ret = pcs_get_function(pctldev, pin, &func);
 559	if (ret)
 560		return ret;
 561
 562	for (j = 0; j < num_configs; j++) {
 563		param = pinconf_to_config_param(configs[j]);
 564
 565		/* BIAS_DISABLE has no entry in the func->conf table */
 566		if (param == PIN_CONFIG_BIAS_DISABLE) {
 567			/* This just disables all bias entries */
 568			pcs_pinconf_clear_bias(pctldev, pin);
 569			continue;
 570		}
 571
 572		for (i = 0; i < func->nconfs; i++) {
 573			if (param != func->conf[i].param)
 574				continue;
 575
 576			offset = pin * (pcs->width / BITS_PER_BYTE);
 577			data = pcs->read(pcs->base + offset);
 578			arg = pinconf_to_config_argument(configs[j]);
 579			switch (param) {
 580			/* 2 parameters */
 581			case PIN_CONFIG_INPUT_SCHMITT:
 582			case PIN_CONFIG_DRIVE_STRENGTH:
 583			case PIN_CONFIG_SLEW_RATE:
 584			case PIN_CONFIG_MODE_LOW_POWER:
 585			case PIN_CONFIG_INPUT_ENABLE:
 586				shift = ffs(func->conf[i].mask) - 1;
 587				data &= ~func->conf[i].mask;
 588				data |= (arg << shift) & func->conf[i].mask;
 589				break;
 590			/* 4 parameters */
 591			case PIN_CONFIG_BIAS_PULL_DOWN:
 592			case PIN_CONFIG_BIAS_PULL_UP:
 593				if (arg) {
 594					pcs_pinconf_clear_bias(pctldev, pin);
 595					data = pcs->read(pcs->base + offset);
 596				}
 597				fallthrough;
 598			case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 599				data &= ~func->conf[i].mask;
 600				if (arg)
 601					data |= func->conf[i].enable;
 602				else
 603					data |= func->conf[i].disable;
 604				break;
 605			default:
 606				return -ENOTSUPP;
 607			}
 608			pcs->write(data, pcs->base + offset);
 609
 610			break;
 611		}
 612		if (i >= func->nconfs)
 613			return -ENOTSUPP;
 614	} /* for each config */
 615
 616	return 0;
 617}
 618
 619static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 620				unsigned group, unsigned long *config)
 621{
 622	const unsigned *pins;
 623	unsigned npins, old = 0;
 624	int i, ret;
 625
 626	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 627	if (ret)
 628		return ret;
 629	for (i = 0; i < npins; i++) {
 630		if (pcs_pinconf_get(pctldev, pins[i], config))
 631			return -ENOTSUPP;
 632		/* configs do not match between two pins */
 633		if (i && (old != *config))
 634			return -ENOTSUPP;
 635		old = *config;
 636	}
 637	return 0;
 638}
 639
 640static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 641				unsigned group, unsigned long *configs,
 642				unsigned num_configs)
 643{
 644	const unsigned *pins;
 645	unsigned npins;
 646	int i, ret;
 647
 648	ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 649	if (ret)
 650		return ret;
 651	for (i = 0; i < npins; i++) {
 652		if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 653			return -ENOTSUPP;
 654	}
 655	return 0;
 656}
 657
 658static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 659				struct seq_file *s, unsigned pin)
 660{
 661}
 662
 663static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 664				struct seq_file *s, unsigned selector)
 665{
 666}
 667
 668static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 669					struct seq_file *s,
 670					unsigned long config)
 671{
 672	pinconf_generic_dump_config(pctldev, s, config);
 673}
 674
 675static const struct pinconf_ops pcs_pinconf_ops = {
 676	.pin_config_get = pcs_pinconf_get,
 677	.pin_config_set = pcs_pinconf_set,
 678	.pin_config_group_get = pcs_pinconf_group_get,
 679	.pin_config_group_set = pcs_pinconf_group_set,
 680	.pin_config_dbg_show = pcs_pinconf_dbg_show,
 681	.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 682	.pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 683	.is_generic = true,
 684};
 685
 686/**
 687 * pcs_add_pin() - add a pin to the static per controller pin array
 688 * @pcs: pcs driver instance
 689 * @offset: register offset from base
 690 */
 691static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
 692{
 693	struct pcs_soc_data *pcs_soc = &pcs->socdata;
 694	struct pinctrl_pin_desc *pin;
 695	int i;
 696
 697	i = pcs->pins.cur;
 698	if (i >= pcs->desc.npins) {
 699		dev_err(pcs->dev, "too many pins, max %i\n",
 700			pcs->desc.npins);
 701		return -ENOMEM;
 702	}
 703
 704	if (pcs_soc->irq_enable_mask) {
 705		unsigned val;
 706
 707		val = pcs->read(pcs->base + offset);
 708		if (val & pcs_soc->irq_enable_mask) {
 709			dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 710				(unsigned long)pcs->res->start + offset, val);
 711			val &= ~pcs_soc->irq_enable_mask;
 712			pcs->write(val, pcs->base + offset);
 713		}
 714	}
 715
 716	pin = &pcs->pins.pa[i];
 717	pin->number = i;
 718	pcs->pins.cur++;
 719
 720	return i;
 721}
 722
 723/**
 724 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 725 * @pcs: pcs driver instance
 726 *
 727 * In case of errors, resources are freed in pcs_free_resources.
 728 *
 729 * If your hardware needs holes in the address space, then just set
 730 * up multiple driver instances.
 731 */
 732static int pcs_allocate_pin_table(struct pcs_device *pcs)
 733{
 734	int mux_bytes, nr_pins, i;
 735
 736	mux_bytes = pcs->width / BITS_PER_BYTE;
 737
 738	if (pcs->bits_per_mux && pcs->fmask) {
 739		pcs->bits_per_pin = fls(pcs->fmask);
 740		nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 741	} else {
 742		nr_pins = pcs->size / mux_bytes;
 743	}
 744
 745	dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 746	pcs->pins.pa = devm_kcalloc(pcs->dev,
 747				nr_pins, sizeof(*pcs->pins.pa),
 748				GFP_KERNEL);
 749	if (!pcs->pins.pa)
 750		return -ENOMEM;
 751
 752	pcs->desc.pins = pcs->pins.pa;
 753	pcs->desc.npins = nr_pins;
 754
 755	for (i = 0; i < pcs->desc.npins; i++) {
 756		unsigned offset;
 757		int res;
 758
 759		offset = pcs_pin_reg_offset_get(pcs, i);
 760		res = pcs_add_pin(pcs, offset);
 761		if (res < 0) {
 762			dev_err(pcs->dev, "error adding pins: %i\n", res);
 763			return res;
 764		}
 765	}
 766
 767	return 0;
 768}
 769
 770/**
 771 * pcs_add_function() - adds a new function to the function list
 772 * @pcs: pcs driver instance
 773 * @fcn: new function allocated
 774 * @name: name of the function
 775 * @vals: array of mux register value pairs used by the function
 776 * @nvals: number of mux register value pairs
 777 * @pgnames: array of pingroup names for the function
 778 * @npgnames: number of pingroup names
 779 *
 780 * Caller must take care of locking.
 781 */
 782static int pcs_add_function(struct pcs_device *pcs,
 783			    struct pcs_function **fcn,
 784			    const char *name,
 785			    struct pcs_func_vals *vals,
 786			    unsigned int nvals,
 787			    const char **pgnames,
 788			    unsigned int npgnames)
 789{
 790	struct pcs_function *function;
 791	int selector;
 792
 793	function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 794	if (!function)
 795		return -ENOMEM;
 796
 797	function->vals = vals;
 798	function->nvals = nvals;
 799	function->name = name;
 800
 801	selector = pinmux_generic_add_function(pcs->pctl, name,
 802					       pgnames, npgnames,
 803					       function);
 804	if (selector < 0) {
 805		devm_kfree(pcs->dev, function);
 806		*fcn = NULL;
 807	} else {
 808		*fcn = function;
 809	}
 810
 811	return selector;
 812}
 813
 814/**
 815 * pcs_get_pin_by_offset() - get a pin index based on the register offset
 816 * @pcs: pcs driver instance
 817 * @offset: register offset from the base
 818 *
 819 * Note that this is OK as long as the pins are in a static array.
 820 */
 821static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 822{
 823	unsigned index;
 824
 825	if (offset >= pcs->size) {
 826		dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 827			offset, pcs->size);
 828		return -EINVAL;
 829	}
 830
 831	if (pcs->bits_per_mux)
 832		index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 833	else
 834		index = offset / (pcs->width / BITS_PER_BYTE);
 835
 836	return index;
 837}
 838
 839/*
 840 * check whether data matches enable bits or disable bits
 841 * Return value: 1 for matching enable bits, 0 for matching disable bits,
 842 *               and negative value for matching failure.
 843 */
 844static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 845{
 846	int ret = -EINVAL;
 847
 848	if (data == enable)
 849		ret = 1;
 850	else if (data == disable)
 851		ret = 0;
 852	return ret;
 853}
 854
 855static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 856		       unsigned value, unsigned enable, unsigned disable,
 857		       unsigned mask)
 858{
 859	(*conf)->param = param;
 860	(*conf)->val = value;
 861	(*conf)->enable = enable;
 862	(*conf)->disable = disable;
 863	(*conf)->mask = mask;
 864	(*conf)++;
 865}
 866
 867static void add_setting(unsigned long **setting, enum pin_config_param param,
 868			unsigned arg)
 869{
 870	**setting = pinconf_to_config_packed(param, arg);
 871	(*setting)++;
 872}
 873
 874/* add pinconf setting with 2 parameters */
 875static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 876			  const char *name, enum pin_config_param param,
 877			  struct pcs_conf_vals **conf, unsigned long **settings)
 878{
 879	unsigned value[2], shift;
 880	int ret;
 881
 882	ret = of_property_read_u32_array(np, name, value, 2);
 883	if (ret)
 884		return;
 885	/* set value & mask */
 886	value[0] &= value[1];
 887	shift = ffs(value[1]) - 1;
 888	/* skip enable & disable */
 889	add_config(conf, param, value[0], 0, 0, value[1]);
 890	add_setting(settings, param, value[0] >> shift);
 891}
 892
 893/* add pinconf setting with 4 parameters */
 894static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 895			  const char *name, enum pin_config_param param,
 896			  struct pcs_conf_vals **conf, unsigned long **settings)
 897{
 898	unsigned value[4];
 899	int ret;
 900
 901	/* value to set, enable, disable, mask */
 902	ret = of_property_read_u32_array(np, name, value, 4);
 903	if (ret)
 904		return;
 905	if (!value[3]) {
 906		dev_err(pcs->dev, "mask field of the property can't be 0\n");
 907		return;
 908	}
 909	value[0] &= value[3];
 910	value[1] &= value[3];
 911	value[2] &= value[3];
 912	ret = pcs_config_match(value[0], value[1], value[2]);
 913	if (ret < 0)
 914		dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 915	add_config(conf, param, value[0], value[1], value[2], value[3]);
 916	add_setting(settings, param, ret);
 917}
 918
 919static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 920			     struct pcs_function *func,
 921			     struct pinctrl_map **map)
 922
 923{
 924	struct pinctrl_map *m = *map;
 925	int i = 0, nconfs = 0;
 926	unsigned long *settings = NULL, *s = NULL;
 927	struct pcs_conf_vals *conf = NULL;
 928	static const struct pcs_conf_type prop2[] = {
 929		{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 930		{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 931		{ "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, },
 932		{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 933		{ "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
 934	};
 935	static const struct pcs_conf_type prop4[] = {
 936		{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 937		{ "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 938		{ "pinctrl-single,input-schmitt-enable",
 939			PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 940	};
 941
 942	/* If pinconf isn't supported, don't parse properties in below. */
 943	if (!PCS_HAS_PINCONF)
 944		return -ENOTSUPP;
 945
 946	/* cacluate how much properties are supported in current node */
 947	for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 948		if (of_property_present(np, prop2[i].name))
 949			nconfs++;
 950	}
 951	for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 952		if (of_property_present(np, prop4[i].name))
 953			nconfs++;
 954	}
 955	if (!nconfs)
 956		return -ENOTSUPP;
 957
 958	func->conf = devm_kcalloc(pcs->dev,
 959				  nconfs, sizeof(struct pcs_conf_vals),
 960				  GFP_KERNEL);
 961	if (!func->conf)
 962		return -ENOMEM;
 963	func->nconfs = nconfs;
 964	conf = &(func->conf[0]);
 965	m++;
 966	settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 967				GFP_KERNEL);
 968	if (!settings)
 969		return -ENOMEM;
 970	s = &settings[0];
 971
 972	for (i = 0; i < ARRAY_SIZE(prop2); i++)
 973		pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 974			      &conf, &s);
 975	for (i = 0; i < ARRAY_SIZE(prop4); i++)
 976		pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 977			      &conf, &s);
 978	m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 979	m->data.configs.group_or_pin = np->name;
 980	m->data.configs.configs = settings;
 981	m->data.configs.num_configs = nconfs;
 982	return 0;
 983}
 984
 985/**
 986 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
 987 * @pcs: pinctrl driver instance
 988 * @np: device node of the mux entry
 989 * @map: map entry
 990 * @num_maps: number of map
 991 * @pgnames: pingroup names
 992 *
 993 * Note that this binding currently supports only sets of one register + value.
 994 *
 995 * Also note that this driver tries to avoid understanding pin and function
 996 * names because of the extra bloat they would cause especially in the case of
 997 * a large number of pins. This driver just sets what is specified for the board
 998 * in the .dts file. Further user space debugging tools can be developed to
 999 * decipher the pin and function names using debugfs.
1000 *
1001 * If you are concerned about the boot time, set up the static pins in
1002 * the bootloader, and only set up selected pins as device tree entries.
1003 */
1004static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1005						struct device_node *np,
1006						struct pinctrl_map **map,
1007						unsigned *num_maps,
1008						const char **pgnames)
1009{
1010	const char *name = "pinctrl-single,pins";
1011	struct pcs_func_vals *vals;
1012	int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1013	struct pcs_function *function = NULL;
1014
1015	rows = pinctrl_count_index_with_args(np, name);
1016	if (rows <= 0) {
1017		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1018		return -EINVAL;
1019	}
1020
1021	vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1022	if (!vals)
1023		return -ENOMEM;
1024
1025	pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1026	if (!pins)
1027		goto free_vals;
1028
1029	for (i = 0; i < rows; i++) {
1030		struct of_phandle_args pinctrl_spec;
1031		unsigned int offset;
1032		int pin;
1033
1034		res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1035		if (res)
1036			return res;
1037
1038		if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1039			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1040				pinctrl_spec.args_count);
1041			break;
1042		}
1043
1044		offset = pinctrl_spec.args[0];
1045		vals[found].reg = pcs->base + offset;
1046
1047		switch (pinctrl_spec.args_count) {
1048		case 2:
1049			vals[found].val = pinctrl_spec.args[1];
1050			break;
1051		case 3:
1052			vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1053			break;
1054		}
1055
1056		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1057			pinctrl_spec.np, offset, vals[found].val);
1058
1059		pin = pcs_get_pin_by_offset(pcs, offset);
1060		if (pin < 0) {
1061			dev_err(pcs->dev,
1062				"could not add functions for %pOFn %ux\n",
1063				np, offset);
1064			break;
1065		}
1066		pins[found++] = pin;
1067	}
1068
1069	pgnames[0] = np->name;
1070	mutex_lock(&pcs->mutex);
1071	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1072				pgnames, 1);
1073	if (fsel < 0) {
1074		res = fsel;
1075		goto free_pins;
1076	}
1077
1078	gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1079	if (gsel < 0) {
1080		res = gsel;
1081		goto free_function;
1082	}
1083
1084	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1085	(*map)->data.mux.group = np->name;
1086	(*map)->data.mux.function = np->name;
1087
1088	if (PCS_HAS_PINCONF && function) {
1089		res = pcs_parse_pinconf(pcs, np, function, map);
1090		if (res == 0)
1091			*num_maps = 2;
1092		else if (res == -ENOTSUPP)
1093			*num_maps = 1;
1094		else
1095			goto free_pingroups;
1096	} else {
1097		*num_maps = 1;
1098	}
1099	mutex_unlock(&pcs->mutex);
1100
1101	return 0;
1102
1103free_pingroups:
1104	pinctrl_generic_remove_group(pcs->pctl, gsel);
1105	*num_maps = 1;
1106free_function:
1107	pinmux_generic_remove_function(pcs->pctl, fsel);
1108free_pins:
1109	mutex_unlock(&pcs->mutex);
1110	devm_kfree(pcs->dev, pins);
1111
1112free_vals:
1113	devm_kfree(pcs->dev, vals);
1114
1115	return res;
1116}
1117
1118static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1119						struct device_node *np,
1120						struct pinctrl_map **map,
1121						unsigned *num_maps,
1122						const char **pgnames)
1123{
1124	const char *name = "pinctrl-single,bits";
1125	struct pcs_func_vals *vals;
1126	int rows, *pins, found = 0, res = -ENOMEM, i, fsel;
1127	int npins_in_row;
1128	struct pcs_function *function = NULL;
1129
1130	rows = pinctrl_count_index_with_args(np, name);
1131	if (rows <= 0) {
1132		dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1133		return -EINVAL;
1134	}
1135
1136	if (PCS_HAS_PINCONF) {
1137		dev_err(pcs->dev, "pinconf not supported\n");
1138		return -ENOTSUPP;
1139	}
1140
1141	npins_in_row = pcs->width / pcs->bits_per_pin;
1142
1143	vals = devm_kzalloc(pcs->dev,
1144			    array3_size(rows, npins_in_row, sizeof(*vals)),
1145			    GFP_KERNEL);
1146	if (!vals)
1147		return -ENOMEM;
1148
1149	pins = devm_kzalloc(pcs->dev,
1150			    array3_size(rows, npins_in_row, sizeof(*pins)),
1151			    GFP_KERNEL);
1152	if (!pins)
1153		goto free_vals;
1154
1155	for (i = 0; i < rows; i++) {
1156		struct of_phandle_args pinctrl_spec;
1157		unsigned offset, val;
1158		unsigned mask, bit_pos, val_pos, mask_pos, submask;
1159		unsigned pin_num_from_lsb;
1160		int pin;
1161
1162		res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1163		if (res)
1164			return res;
1165
1166		if (pinctrl_spec.args_count < 3) {
1167			dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1168				pinctrl_spec.args_count);
1169			break;
1170		}
1171
1172		/* Index plus two value cells */
1173		offset = pinctrl_spec.args[0];
1174		val = pinctrl_spec.args[1];
1175		mask = pinctrl_spec.args[2];
1176
1177		dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1178			pinctrl_spec.np, offset, val, mask);
1179
1180		/* Parse pins in each row from LSB */
1181		while (mask) {
1182			bit_pos = __ffs(mask);
1183			pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1184			mask_pos = ((pcs->fmask) << bit_pos);
1185			val_pos = val & mask_pos;
1186			submask = mask & mask_pos;
1187
1188			if ((mask & mask_pos) == 0) {
1189				dev_err(pcs->dev,
1190					"Invalid mask for %pOFn at 0x%x\n",
1191					np, offset);
1192				break;
1193			}
1194
1195			mask &= ~mask_pos;
1196
1197			if (submask != mask_pos) {
1198				dev_warn(pcs->dev,
1199						"Invalid submask 0x%x for %pOFn at 0x%x\n",
1200						submask, np, offset);
1201				continue;
1202			}
1203
1204			vals[found].mask = submask;
1205			vals[found].reg = pcs->base + offset;
1206			vals[found].val = val_pos;
1207
1208			pin = pcs_get_pin_by_offset(pcs, offset);
1209			if (pin < 0) {
1210				dev_err(pcs->dev,
1211					"could not add functions for %pOFn %ux\n",
1212					np, offset);
1213				break;
1214			}
1215			pins[found++] = pin + pin_num_from_lsb;
1216		}
1217	}
1218
1219	pgnames[0] = np->name;
1220	mutex_lock(&pcs->mutex);
1221	fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1222				pgnames, 1);
1223	if (fsel < 0) {
1224		res = fsel;
1225		goto free_pins;
1226	}
1227
1228	res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1229	if (res < 0)
1230		goto free_function;
1231
1232	(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1233	(*map)->data.mux.group = np->name;
1234	(*map)->data.mux.function = np->name;
1235
1236	*num_maps = 1;
1237	mutex_unlock(&pcs->mutex);
1238
1239	return 0;
1240
1241free_function:
1242	pinmux_generic_remove_function(pcs->pctl, fsel);
1243free_pins:
1244	mutex_unlock(&pcs->mutex);
1245	devm_kfree(pcs->dev, pins);
1246
1247free_vals:
1248	devm_kfree(pcs->dev, vals);
1249
1250	return res;
1251}
1252/**
1253 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1254 * @pctldev: pinctrl instance
1255 * @np_config: device tree pinmux entry
1256 * @map: array of map entries
1257 * @num_maps: number of maps
1258 */
1259static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1260				struct device_node *np_config,
1261				struct pinctrl_map **map, unsigned *num_maps)
1262{
1263	struct pcs_device *pcs;
1264	const char **pgnames;
1265	int ret;
1266
1267	pcs = pinctrl_dev_get_drvdata(pctldev);
1268
1269	/* create 2 maps. One is for pinmux, and the other is for pinconf. */
1270	*map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1271	if (!*map)
1272		return -ENOMEM;
1273
1274	*num_maps = 0;
1275
1276	pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1277	if (!pgnames) {
1278		ret = -ENOMEM;
1279		goto free_map;
1280	}
1281
1282	if (pcs->bits_per_mux) {
1283		ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1284				num_maps, pgnames);
1285		if (ret < 0) {
1286			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1287				np_config);
1288			goto free_pgnames;
1289		}
1290	} else {
1291		ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1292				num_maps, pgnames);
1293		if (ret < 0) {
1294			dev_err(pcs->dev, "no pins entries for %pOFn\n",
1295				np_config);
1296			goto free_pgnames;
1297		}
1298	}
1299
1300	return 0;
1301
1302free_pgnames:
1303	devm_kfree(pcs->dev, pgnames);
1304free_map:
1305	devm_kfree(pcs->dev, *map);
1306
1307	return ret;
1308}
1309
1310/**
1311 * pcs_irq_free() - free interrupt
1312 * @pcs: pcs driver instance
1313 */
1314static void pcs_irq_free(struct pcs_device *pcs)
1315{
1316	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1317
1318	if (pcs_soc->irq < 0)
1319		return;
1320
1321	if (pcs->domain)
1322		irq_domain_remove(pcs->domain);
1323
1324	if (PCS_QUIRK_HAS_SHARED_IRQ)
1325		free_irq(pcs_soc->irq, pcs_soc);
1326	else
1327		irq_set_chained_handler(pcs_soc->irq, NULL);
1328}
1329
1330/**
1331 * pcs_free_resources() - free memory used by this driver
1332 * @pcs: pcs driver instance
1333 */
1334static void pcs_free_resources(struct pcs_device *pcs)
1335{
1336	pcs_irq_free(pcs);
1337
1338#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1339	if (pcs->missing_nr_pinctrl_cells)
1340		of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1341#endif
1342}
1343
1344static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1345{
1346	const char *propname = "pinctrl-single,gpio-range";
1347	const char *cellname = "#pinctrl-single,gpio-range-cells";
1348	struct of_phandle_args gpiospec;
1349	struct pcs_gpiofunc_range *range;
1350	int ret, i;
1351
1352	for (i = 0; ; i++) {
1353		ret = of_parse_phandle_with_args(node, propname, cellname,
1354						 i, &gpiospec);
1355		/* Do not treat it as error. Only treat it as end condition. */
1356		if (ret) {
1357			ret = 0;
1358			break;
1359		}
1360		range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1361		if (!range) {
1362			of_node_put(gpiospec.np);
1363			ret = -ENOMEM;
1364			break;
1365		}
1366		range->offset = gpiospec.args[0];
1367		range->npins = gpiospec.args[1];
1368		range->gpiofunc = gpiospec.args[2];
1369		mutex_lock(&pcs->mutex);
1370		list_add_tail(&range->node, &pcs->gpiofuncs);
1371		mutex_unlock(&pcs->mutex);
1372		of_node_put(gpiospec.np);
1373	}
1374	return ret;
1375}
1376
1377/**
1378 * struct pcs_interrupt
1379 * @reg:	virtual address of interrupt register
1380 * @hwirq:	hardware irq number
1381 * @irq:	virtual irq number
1382 * @node:	list node
1383 */
1384struct pcs_interrupt {
1385	void __iomem *reg;
1386	irq_hw_number_t hwirq;
1387	unsigned int irq;
1388	struct list_head node;
1389};
1390
1391/**
1392 * pcs_irq_set() - enables or disables an interrupt
1393 * @pcs_soc: SoC specific settings
1394 * @irq: interrupt
1395 * @enable: enable or disable the interrupt
1396 *
1397 * Note that this currently assumes one interrupt per pinctrl
1398 * register that is typically used for wake-up events.
1399 */
1400static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1401			       int irq, const bool enable)
1402{
1403	struct pcs_device *pcs;
1404	struct list_head *pos;
1405	unsigned mask;
1406
1407	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1408	list_for_each(pos, &pcs->irqs) {
1409		struct pcs_interrupt *pcswi;
1410		unsigned soc_mask;
1411
1412		pcswi = list_entry(pos, struct pcs_interrupt, node);
1413		if (irq != pcswi->irq)
1414			continue;
1415
1416		soc_mask = pcs_soc->irq_enable_mask;
1417		raw_spin_lock(&pcs->lock);
1418		mask = pcs->read(pcswi->reg);
1419		if (enable)
1420			mask |= soc_mask;
1421		else
1422			mask &= ~soc_mask;
1423		pcs->write(mask, pcswi->reg);
1424
1425		/* flush posted write */
1426		mask = pcs->read(pcswi->reg);
1427		raw_spin_unlock(&pcs->lock);
1428	}
1429
1430	if (pcs_soc->rearm)
1431		pcs_soc->rearm();
1432}
1433
1434/**
1435 * pcs_irq_mask() - mask pinctrl interrupt
1436 * @d: interrupt data
1437 */
1438static void pcs_irq_mask(struct irq_data *d)
1439{
1440	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1441
1442	pcs_irq_set(pcs_soc, d->irq, false);
1443}
1444
1445/**
1446 * pcs_irq_unmask() - unmask pinctrl interrupt
1447 * @d: interrupt data
1448 */
1449static void pcs_irq_unmask(struct irq_data *d)
1450{
1451	struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1452
1453	pcs_irq_set(pcs_soc, d->irq, true);
1454}
1455
1456/**
1457 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1458 * @d: interrupt data
1459 * @state: wake-up state
1460 *
1461 * Note that this should be called only for suspend and resume.
1462 * For runtime PM, the wake-up events should be enabled by default.
1463 */
1464static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1465{
1466	if (state)
1467		pcs_irq_unmask(d);
1468	else
1469		pcs_irq_mask(d);
1470
1471	return 0;
1472}
1473
1474/**
1475 * pcs_irq_handle() - common interrupt handler
1476 * @pcs_soc: SoC specific settings
1477 *
1478 * Note that this currently assumes we have one interrupt bit per
1479 * mux register. This interrupt is typically used for wake-up events.
1480 * For more complex interrupts different handlers can be specified.
1481 */
1482static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1483{
1484	struct pcs_device *pcs;
1485	struct list_head *pos;
1486	int count = 0;
1487
1488	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1489	list_for_each(pos, &pcs->irqs) {
1490		struct pcs_interrupt *pcswi;
1491		unsigned mask;
1492
1493		pcswi = list_entry(pos, struct pcs_interrupt, node);
1494		raw_spin_lock(&pcs->lock);
1495		mask = pcs->read(pcswi->reg);
1496		raw_spin_unlock(&pcs->lock);
1497		if (mask & pcs_soc->irq_status_mask) {
1498			generic_handle_domain_irq(pcs->domain,
1499						  pcswi->hwirq);
1500			count++;
1501		}
1502	}
1503
1504	return count;
1505}
1506
1507/**
1508 * pcs_irq_handler() - handler for the shared interrupt case
1509 * @irq: interrupt
1510 * @d: data
1511 *
1512 * Use this for cases where multiple instances of
1513 * pinctrl-single share a single interrupt like on omaps.
1514 */
1515static irqreturn_t pcs_irq_handler(int irq, void *d)
1516{
1517	struct pcs_soc_data *pcs_soc = d;
1518
1519	return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1520}
1521
1522/**
1523 * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case
1524 * @desc: interrupt descriptor
1525 *
1526 * Use this if you have a separate interrupt for each
1527 * pinctrl-single instance.
1528 */
1529static void pcs_irq_chain_handler(struct irq_desc *desc)
1530{
1531	struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1532	struct irq_chip *chip;
1533
1534	chip = irq_desc_get_chip(desc);
1535	chained_irq_enter(chip, desc);
1536	pcs_irq_handle(pcs_soc);
1537	/* REVISIT: export and add handle_bad_irq(irq, desc)? */
1538	chained_irq_exit(chip, desc);
1539}
1540
1541static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1542			     irq_hw_number_t hwirq)
1543{
1544	struct pcs_soc_data *pcs_soc = d->host_data;
1545	struct pcs_device *pcs;
1546	struct pcs_interrupt *pcswi;
1547
1548	pcs = container_of(pcs_soc, struct pcs_device, socdata);
1549	pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1550	if (!pcswi)
1551		return -ENOMEM;
1552
1553	pcswi->reg = pcs->base + hwirq;
1554	pcswi->hwirq = hwirq;
1555	pcswi->irq = irq;
1556
1557	mutex_lock(&pcs->mutex);
1558	list_add_tail(&pcswi->node, &pcs->irqs);
1559	mutex_unlock(&pcs->mutex);
1560
1561	irq_set_chip_data(irq, pcs_soc);
1562	irq_set_chip_and_handler(irq, &pcs->chip,
1563				 handle_level_irq);
1564	irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1565	irq_set_noprobe(irq);
1566
1567	return 0;
1568}
1569
1570static const struct irq_domain_ops pcs_irqdomain_ops = {
1571	.map = pcs_irqdomain_map,
1572	.xlate = irq_domain_xlate_onecell,
1573};
1574
1575/**
1576 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1577 * @pcs: pcs driver instance
1578 * @np: device node pointer
1579 */
1580static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1581					struct device_node *np)
1582{
1583	struct pcs_soc_data *pcs_soc = &pcs->socdata;
1584	const char *name = "pinctrl";
1585	int num_irqs;
1586
1587	if (!pcs_soc->irq_enable_mask ||
1588	    !pcs_soc->irq_status_mask) {
1589		pcs_soc->irq = -1;
1590		return -EINVAL;
1591	}
1592
1593	INIT_LIST_HEAD(&pcs->irqs);
1594	pcs->chip.name = name;
1595	pcs->chip.irq_ack = pcs_irq_mask;
1596	pcs->chip.irq_mask = pcs_irq_mask;
1597	pcs->chip.irq_unmask = pcs_irq_unmask;
1598	pcs->chip.irq_set_wake = pcs_irq_set_wake;
1599
1600	if (PCS_QUIRK_HAS_SHARED_IRQ) {
1601		int res;
1602
1603		res = request_irq(pcs_soc->irq, pcs_irq_handler,
1604				  IRQF_SHARED | IRQF_NO_SUSPEND |
1605				  IRQF_NO_THREAD,
1606				  name, pcs_soc);
1607		if (res) {
1608			pcs_soc->irq = -1;
1609			return res;
1610		}
1611	} else {
1612		irq_set_chained_handler_and_data(pcs_soc->irq,
1613						 pcs_irq_chain_handler,
1614						 pcs_soc);
1615	}
1616
1617	/*
1618	 * We can use the register offset as the hardirq
1619	 * number as irq_domain_create_simple maps them lazily.
1620	 * This way we can easily support more than one
1621	 * interrupt per function if needed.
1622	 */
1623	num_irqs = pcs->size;
1624
1625	pcs->domain = irq_domain_create_simple(of_fwnode_handle(np),
1626					       num_irqs, 0,
1627					       &pcs_irqdomain_ops,
1628					       pcs_soc);
1629	if (!pcs->domain) {
1630		irq_set_chained_handler(pcs_soc->irq, NULL);
1631		return -EINVAL;
1632	}
1633
1634	return 0;
1635}
1636
1637static int pcs_save_context(struct pcs_device *pcs)
1638{
1639	int i, mux_bytes;
1640	u64 *regsl;
1641	u32 *regsw;
1642	u16 *regshw;
1643
1644	mux_bytes = pcs->width / BITS_PER_BYTE;
1645
1646	if (!pcs->saved_vals) {
1647		pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1648		if (!pcs->saved_vals)
1649			return -ENOMEM;
1650	}
1651
1652	switch (pcs->width) {
1653	case 64:
1654		regsl = pcs->saved_vals;
1655		for (i = 0; i < pcs->size; i += mux_bytes)
1656			*regsl++ = pcs->read(pcs->base + i);
1657		break;
1658	case 32:
1659		regsw = pcs->saved_vals;
1660		for (i = 0; i < pcs->size; i += mux_bytes)
1661			*regsw++ = pcs->read(pcs->base + i);
1662		break;
1663	case 16:
1664		regshw = pcs->saved_vals;
1665		for (i = 0; i < pcs->size; i += mux_bytes)
1666			*regshw++ = pcs->read(pcs->base + i);
1667		break;
1668	}
1669
1670	return 0;
1671}
1672
1673static void pcs_restore_context(struct pcs_device *pcs)
1674{
1675	int i, mux_bytes;
1676	u64 *regsl;
1677	u32 *regsw;
1678	u16 *regshw;
1679
1680	mux_bytes = pcs->width / BITS_PER_BYTE;
1681
1682	switch (pcs->width) {
1683	case 64:
1684		regsl = pcs->saved_vals;
1685		for (i = 0; i < pcs->size; i += mux_bytes)
1686			pcs->write(*regsl++, pcs->base + i);
1687		break;
1688	case 32:
1689		regsw = pcs->saved_vals;
1690		for (i = 0; i < pcs->size; i += mux_bytes)
1691			pcs->write(*regsw++, pcs->base + i);
1692		break;
1693	case 16:
1694		regshw = pcs->saved_vals;
1695		for (i = 0; i < pcs->size; i += mux_bytes)
1696			pcs->write(*regshw++, pcs->base + i);
1697		break;
1698	}
1699}
1700
1701static int pinctrl_single_suspend_noirq(struct device *dev)
1702{
1703	struct pcs_device *pcs = dev_get_drvdata(dev);
1704
1705	if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1706		int ret;
1707
1708		ret = pcs_save_context(pcs);
1709		if (ret < 0)
1710			return ret;
1711	}
1712
1713	return pinctrl_force_sleep(pcs->pctl);
1714}
1715
1716static int pinctrl_single_resume_noirq(struct device *dev)
1717{
1718	struct pcs_device *pcs = dev_get_drvdata(dev);
1719
1720	if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1721		pcs_restore_context(pcs);
1722
1723	return pinctrl_force_default(pcs->pctl);
1724}
1725
1726static DEFINE_NOIRQ_DEV_PM_OPS(pinctrl_single_pm_ops,
1727			       pinctrl_single_suspend_noirq,
1728			       pinctrl_single_resume_noirq);
1729
1730/**
1731 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1732 * @pcs: pinctrl driver instance
1733 * @np: device tree node
1734 * @cells: number of cells
1735 *
1736 * Handle legacy binding with no #pinctrl-cells. This should be
1737 * always two pinctrl-single,bit-per-mux and one for others.
1738 * At some point we may want to consider removing this.
1739 */
1740static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1741					   struct device_node *np,
1742					   int cells)
1743{
1744	struct property *p;
1745	const char *name = "#pinctrl-cells";
1746	int error;
1747	u32 val;
1748
1749	error = of_property_read_u32(np, name, &val);
1750	if (!error)
1751		return 0;
1752
1753	dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1754		 name, cells);
1755
1756	p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1757	if (!p)
1758		return -ENOMEM;
1759
1760	p->length = sizeof(__be32);
1761	p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1762	if (!p->value)
1763		return -ENOMEM;
1764	*(__be32 *)p->value = cpu_to_be32(cells);
1765
1766	p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1767	if (!p->name)
1768		return -ENOMEM;
1769
1770	pcs->missing_nr_pinctrl_cells = p;
1771
1772#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1773	error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1774#endif
1775
1776	return error;
1777}
1778
1779static int pcs_probe(struct platform_device *pdev)
1780{
1781	struct device_node *np = pdev->dev.of_node;
1782	struct pcs_pdata *pdata;
1783	struct resource *res;
1784	struct pcs_device *pcs;
1785	const struct pcs_soc_data *soc;
1786	int ret;
1787
1788	soc = of_device_get_match_data(&pdev->dev);
1789	if (WARN_ON(!soc))
1790		return -EINVAL;
1791
1792	pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1793	if (!pcs)
1794		return -ENOMEM;
1795
1796	pcs->dev = &pdev->dev;
1797	pcs->np = np;
1798	raw_spin_lock_init(&pcs->lock);
1799	mutex_init(&pcs->mutex);
1800	INIT_LIST_HEAD(&pcs->gpiofuncs);
1801	pcs->flags = soc->flags;
1802	memcpy(&pcs->socdata, soc, sizeof(*soc));
1803
1804	ret = of_property_read_u32(np, "pinctrl-single,register-width",
1805				   &pcs->width);
1806	if (ret) {
1807		dev_err(pcs->dev, "register width not specified\n");
1808
1809		return ret;
1810	}
1811
1812	ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1813				   &pcs->fmask);
1814	if (!ret) {
1815		pcs->fshift = __ffs(pcs->fmask);
1816		pcs->fmax = pcs->fmask >> pcs->fshift;
1817	} else {
1818		/* If mask property doesn't exist, function mux is invalid. */
1819		pcs->fmask = 0;
1820		pcs->fshift = 0;
1821		pcs->fmax = 0;
1822	}
1823
1824	ret = of_property_read_u32(np, "pinctrl-single,function-off",
1825					&pcs->foff);
1826	if (ret)
1827		pcs->foff = PCS_OFF_DISABLED;
1828
1829	pcs->bits_per_mux = of_property_read_bool(np,
1830						  "pinctrl-single,bit-per-mux");
1831	ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1832					      pcs->bits_per_mux ? 2 : 1);
1833	if (ret) {
1834		dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1835
1836		return ret;
1837	}
1838
1839	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1840	if (!res) {
1841		dev_err(pcs->dev, "could not get resource\n");
1842		return -ENODEV;
1843	}
1844
1845	pcs->res = devm_request_mem_region(pcs->dev, res->start,
1846			resource_size(res), DRIVER_NAME);
1847	if (!pcs->res) {
1848		dev_err(pcs->dev, "could not get mem_region\n");
1849		return -EBUSY;
1850	}
1851
1852	pcs->size = resource_size(pcs->res);
1853	pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1854	if (!pcs->base) {
1855		dev_err(pcs->dev, "could not ioremap\n");
1856		return -ENODEV;
1857	}
1858
1859	platform_set_drvdata(pdev, pcs);
1860
1861	switch (pcs->width) {
1862	case 8:
1863		pcs->read = pcs_readb;
1864		pcs->write = pcs_writeb;
1865		break;
1866	case 16:
1867		pcs->read = pcs_readw;
1868		pcs->write = pcs_writew;
1869		break;
1870	case 32:
1871		pcs->read = pcs_readl;
1872		pcs->write = pcs_writel;
1873		break;
1874	default:
1875		break;
1876	}
1877
1878	pcs->desc.name = DRIVER_NAME;
1879	pcs->desc.pctlops = &pcs_pinctrl_ops;
1880	pcs->desc.pmxops = &pcs_pinmux_ops;
1881	if (PCS_HAS_PINCONF)
1882		pcs->desc.confops = &pcs_pinconf_ops;
1883	pcs->desc.owner = THIS_MODULE;
1884
1885	ret = pcs_allocate_pin_table(pcs);
1886	if (ret < 0)
1887		goto free;
1888
1889	ret = devm_pinctrl_register_and_init(pcs->dev, &pcs->desc, pcs, &pcs->pctl);
1890	if (ret) {
1891		dev_err(pcs->dev, "could not register single pinctrl driver\n");
1892		goto free;
1893	}
1894
1895	ret = pcs_add_gpio_func(np, pcs);
1896	if (ret < 0)
1897		goto free;
1898
1899	pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1900	if (pcs->socdata.irq)
1901		pcs->flags |= PCS_FEAT_IRQ;
1902
1903	/* We still need auxdata for some omaps for PRM interrupts */
1904	pdata = dev_get_platdata(&pdev->dev);
1905	if (pdata) {
1906		if (pdata->rearm)
1907			pcs->socdata.rearm = pdata->rearm;
1908		if (pdata->irq) {
1909			pcs->socdata.irq = pdata->irq;
1910			pcs->flags |= PCS_FEAT_IRQ;
1911		}
1912	}
1913
1914	if (PCS_HAS_IRQ) {
1915		ret = pcs_irq_init_chained_handler(pcs, np);
1916		if (ret < 0)
1917			dev_warn(pcs->dev, "initialized with no interrupts\n");
1918	}
1919
1920	dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1921
1922	ret = pinctrl_enable(pcs->pctl);
1923	if (ret)
1924		goto free;
1925
1926	return 0;
1927free:
1928	pcs_free_resources(pcs);
1929
1930	return ret;
1931}
1932
1933static void pcs_remove(struct platform_device *pdev)
1934{
1935	struct pcs_device *pcs = platform_get_drvdata(pdev);
1936
1937	pcs_free_resources(pcs);
1938}
1939
1940static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1941	.flags = PCS_QUIRK_SHARED_IRQ,
1942	.irq_enable_mask = (1 << 14),	/* OMAP_WAKEUP_EN */
1943	.irq_status_mask = (1 << 15),	/* OMAP_WAKEUP_EVENT */
1944};
1945
1946static const struct pcs_soc_data pinctrl_single_dra7 = {
1947	.irq_enable_mask = (1 << 24),	/* WAKEUPENABLE */
1948	.irq_status_mask = (1 << 25),	/* WAKEUPEVENT */
1949};
1950
1951static const struct pcs_soc_data pinctrl_single_am437x = {
1952	.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1953	.irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1954	.irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1955};
1956
1957static const struct pcs_soc_data pinctrl_single_am654 = {
1958	.flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1959	.irq_enable_mask = (1 << 29),   /* WKUP_EN */
1960	.irq_status_mask = (1 << 30),   /* WKUP_EVT */
1961};
1962
1963static const struct pcs_soc_data pinctrl_single_j7200 = {
1964	.flags = PCS_CONTEXT_LOSS_OFF,
1965};
1966
1967static const struct pcs_soc_data pinctrl_single = {
1968};
1969
1970static const struct pcs_soc_data pinconf_single = {
1971	.flags = PCS_FEAT_PINCONF,
1972};
1973
1974static const struct of_device_id pcs_of_match[] = {
1975	{ .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single },
1976	{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1977	{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
1978	{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1979	{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1980	{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1981	{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1982	{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
1983	{ .compatible = "pinctrl-single", .data = &pinctrl_single },
1984	{ .compatible = "pinconf-single", .data = &pinconf_single },
1985	{ },
1986};
1987MODULE_DEVICE_TABLE(of, pcs_of_match);
1988
1989static struct platform_driver pcs_driver = {
1990	.probe		= pcs_probe,
1991	.remove		= pcs_remove,
1992	.driver = {
1993		.name		= DRIVER_NAME,
1994		.of_match_table	= pcs_of_match,
1995		.pm = pm_sleep_ptr(&pinctrl_single_pm_ops),
1996	},
1997};
1998
1999module_platform_driver(pcs_driver);
2000
2001MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2002MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2003MODULE_LICENSE("GPL v2");