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pinctrl-rockchip.c
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linux-6.19.14/drivers/pinctrl/pinctrl-rockchip.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Pinctrl driver for Rockchip SoCs 4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18#include <linux/init.h> 19#include <linux/module.h> 20#include <linux/platform_device.h> 21#include <linux/io.h> 22#include <linux/bitops.h> 23#include <linux/gpio/driver.h> 24#include <linux/of.h> 25#include <linux/of_platform.h> 26#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/pinconf.h> 28#include <linux/pinctrl/pinctrl.h> 29#include <linux/pinctrl/pinmux.h> 30#include <linux/pinctrl/pinconf-generic.h> 31#include <linux/irqchip/chained_irq.h> 32#include <linux/clk.h> 33#include <linux/regmap.h> 34#include <linux/mfd/syscon.h> 35#include <linux/string_helpers.h> 36 37#include <dt-bindings/pinctrl/rockchip.h> 38 39#include "core.h" 40#include "pinconf.h" 41#include "pinctrl-rockchip.h" 42 43/* 44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword 45 * register 31:16 area. 46 */ 47#define WRITE_MASK_VAL(h, l, v) \ 48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) 49 50/* 51 * Encode variants of iomux registers into a type variable 52 */ 53#define IOMUX_GPIO_ONLY BIT(0) 54#define IOMUX_WIDTH_4BIT BIT(1) 55#define IOMUX_SOURCE_PMU BIT(2) 56#define IOMUX_UNROUTED BIT(3) 57#define IOMUX_WIDTH_3BIT BIT(4) 58#define IOMUX_WIDTH_2BIT BIT(5) 59#define IOMUX_L_SOURCE_PMU BIT(6) 60 61#define PIN_BANK(id, pins, label) \ 62 { \ 63 .bank_num = id, \ 64 .nr_pins = pins, \ 65 .name = label, \ 66 .iomux = { \ 67 { .offset = -1 }, \ 68 { .offset = -1 }, \ 69 { .offset = -1 }, \ 70 { .offset = -1 }, \ 71 }, \ 72 } 73 74#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 75 { \ 76 .bank_num = id, \ 77 .nr_pins = pins, \ 78 .name = label, \ 79 .iomux = { \ 80 { .type = iom0, .offset = -1 }, \ 81 { .type = iom1, .offset = -1 }, \ 82 { .type = iom2, .offset = -1 }, \ 83 { .type = iom3, .offset = -1 }, \ 84 }, \ 85 } 86 87#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \ 88 iom1, iom2, iom3, \ 89 offset0, offset1, \ 90 offset2, offset3, pull0, \ 91 pull1, pull2, pull3) \ 92 { \ 93 .bank_num = id, \ 94 .nr_pins = pins, \ 95 .name = label, \ 96 .iomux = { \ 97 { .type = iom0, .offset = offset0 }, \ 98 { .type = iom1, .offset = offset1 }, \ 99 { .type = iom2, .offset = offset2 }, \ 100 { .type = iom3, .offset = offset3 }, \ 101 }, \ 102 .pull_type[0] = pull0, \ 103 .pull_type[1] = pull1, \ 104 .pull_type[2] = pull2, \ 105 .pull_type[3] = pull3, \ 106 } 107 108#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \ 109 iom1, iom2, iom3, \ 110 offset0, offset1, \ 111 offset2, offset3, drv0, \ 112 drv1, drv2, drv3) \ 113 { \ 114 .bank_num = id, \ 115 .nr_pins = pins, \ 116 .name = label, \ 117 .iomux = { \ 118 { .type = iom0, .offset = offset0 }, \ 119 { .type = iom1, .offset = offset1 }, \ 120 { .type = iom2, .offset = offset2 }, \ 121 { .type = iom3, .offset = offset3 }, \ 122 }, \ 123 .drv = { \ 124 { .drv_type = drv0, .offset = -1 }, \ 125 { .drv_type = drv1, .offset = -1 }, \ 126 { .drv_type = drv2, .offset = -1 }, \ 127 { .drv_type = drv3, .offset = -1 }, \ 128 }, \ 129 } 130 131#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 132 { \ 133 .bank_num = id, \ 134 .nr_pins = pins, \ 135 .name = label, \ 136 .iomux = { \ 137 { .offset = -1 }, \ 138 { .offset = -1 }, \ 139 { .offset = -1 }, \ 140 { .offset = -1 }, \ 141 }, \ 142 .drv = { \ 143 { .drv_type = type0, .offset = -1 }, \ 144 { .drv_type = type1, .offset = -1 }, \ 145 { .drv_type = type2, .offset = -1 }, \ 146 { .drv_type = type3, .offset = -1 }, \ 147 }, \ 148 } 149 150#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \ 151 iom2, iom3, pull0, pull1, \ 152 pull2, pull3) \ 153 { \ 154 .bank_num = id, \ 155 .nr_pins = pins, \ 156 .name = label, \ 157 .iomux = { \ 158 { .type = iom0, .offset = -1 }, \ 159 { .type = iom1, .offset = -1 }, \ 160 { .type = iom2, .offset = -1 }, \ 161 { .type = iom3, .offset = -1 }, \ 162 }, \ 163 .pull_type[0] = pull0, \ 164 .pull_type[1] = pull1, \ 165 .pull_type[2] = pull2, \ 166 .pull_type[3] = pull3, \ 167 } 168 169#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 170 drv2, drv3, pull0, pull1, \ 171 pull2, pull3) \ 172 { \ 173 .bank_num = id, \ 174 .nr_pins = pins, \ 175 .name = label, \ 176 .iomux = { \ 177 { .offset = -1 }, \ 178 { .offset = -1 }, \ 179 { .offset = -1 }, \ 180 { .offset = -1 }, \ 181 }, \ 182 .drv = { \ 183 { .drv_type = drv0, .offset = -1 }, \ 184 { .drv_type = drv1, .offset = -1 }, \ 185 { .drv_type = drv2, .offset = -1 }, \ 186 { .drv_type = drv3, .offset = -1 }, \ 187 }, \ 188 .pull_type[0] = pull0, \ 189 .pull_type[1] = pull1, \ 190 .pull_type[2] = pull2, \ 191 .pull_type[3] = pull3, \ 192 } 193 194#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ 195 iom3, offset0, offset1, offset2, \ 196 offset3) \ 197 { \ 198 .bank_num = id, \ 199 .nr_pins = pins, \ 200 .name = label, \ 201 .iomux = { \ 202 { .type = iom0, .offset = offset0 }, \ 203 { .type = iom1, .offset = offset1 }, \ 204 { .type = iom2, .offset = offset2 }, \ 205 { .type = iom3, .offset = offset3 }, \ 206 }, \ 207 } 208 209#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 210 iom2, iom3, drv0, drv1, drv2, \ 211 drv3, offset0, offset1, \ 212 offset2, offset3) \ 213 { \ 214 .bank_num = id, \ 215 .nr_pins = pins, \ 216 .name = label, \ 217 .iomux = { \ 218 { .type = iom0, .offset = -1 }, \ 219 { .type = iom1, .offset = -1 }, \ 220 { .type = iom2, .offset = -1 }, \ 221 { .type = iom3, .offset = -1 }, \ 222 }, \ 223 .drv = { \ 224 { .drv_type = drv0, .offset = offset0 }, \ 225 { .drv_type = drv1, .offset = offset1 }, \ 226 { .drv_type = drv2, .offset = offset2 }, \ 227 { .drv_type = drv3, .offset = offset3 }, \ 228 }, \ 229 } 230 231#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 232 label, iom0, iom1, iom2, \ 233 iom3, drv0, drv1, drv2, \ 234 drv3, offset0, offset1, \ 235 offset2, offset3, pull0, \ 236 pull1, pull2, pull3) \ 237 { \ 238 .bank_num = id, \ 239 .nr_pins = pins, \ 240 .name = label, \ 241 .iomux = { \ 242 { .type = iom0, .offset = -1 }, \ 243 { .type = iom1, .offset = -1 }, \ 244 { .type = iom2, .offset = -1 }, \ 245 { .type = iom3, .offset = -1 }, \ 246 }, \ 247 .drv = { \ 248 { .drv_type = drv0, .offset = offset0 }, \ 249 { .drv_type = drv1, .offset = offset1 }, \ 250 { .drv_type = drv2, .offset = offset2 }, \ 251 { .drv_type = drv3, .offset = offset3 }, \ 252 }, \ 253 .pull_type[0] = pull0, \ 254 .pull_type[1] = pull1, \ 255 .pull_type[2] = pull2, \ 256 .pull_type[3] = pull3, \ 257 } 258 259#define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \ 260 label, iom0, iom1, \ 261 iom2, iom3, offset0, \ 262 offset1, offset2, \ 263 offset3, drv0, drv1, \ 264 drv2, drv3, pull0, \ 265 pull1, pull2, pull3) \ 266 { \ 267 .bank_num = id, \ 268 .nr_pins = pins, \ 269 .name = label, \ 270 .iomux = { \ 271 { .type = iom0, .offset = offset0 }, \ 272 { .type = iom1, .offset = offset1 }, \ 273 { .type = iom2, .offset = offset2 }, \ 274 { .type = iom3, .offset = offset3 }, \ 275 }, \ 276 .drv = { \ 277 { .drv_type = drv0, .offset = -1 }, \ 278 { .drv_type = drv1, .offset = -1 }, \ 279 { .drv_type = drv2, .offset = -1 }, \ 280 { .drv_type = drv3, .offset = -1 }, \ 281 }, \ 282 .pull_type[0] = pull0, \ 283 .pull_type[1] = pull1, \ 284 .pull_type[2] = pull2, \ 285 .pull_type[3] = pull3, \ 286 } 287 288#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ 289 { \ 290 .bank_num = ID, \ 291 .pin = PIN, \ 292 .func = FUNC, \ 293 .route_offset = REG, \ 294 .route_val = VAL, \ 295 .route_location = FLAG, \ 296 } 297 298#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \ 299 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME) 300 301#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \ 302 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF) 303 304#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ 305 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) 306 307#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \ 308 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P) 309 310static struct regmap_config rockchip_regmap_config = { 311 .reg_bits = 32, 312 .val_bits = 32, 313 .reg_stride = 4, 314}; 315 316static inline const struct rockchip_pin_group *pinctrl_name_to_group( 317 const struct rockchip_pinctrl *info, 318 const char *name) 319{ 320 int i; 321 322 for (i = 0; i < info->ngroups; i++) { 323 if (!strcmp(info->groups[i].name, name)) 324 return &info->groups[i]; 325 } 326 327 return NULL; 328} 329 330/* 331 * given a pin number that is local to a pin controller, find out the pin bank 332 * and the register base of the pin bank. 333 */ 334static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 335 unsigned pin) 336{ 337 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 338 339 while (pin >= (b->pin_base + b->nr_pins)) 340 b++; 341 342 return b; 343} 344 345static struct rockchip_pin_bank *bank_num_to_bank( 346 struct rockchip_pinctrl *info, 347 unsigned num) 348{ 349 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 350 int i; 351 352 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 353 if (b->bank_num == num) 354 return b; 355 } 356 357 return ERR_PTR(-EINVAL); 358} 359 360/* 361 * Pinctrl_ops handling 362 */ 363 364static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 365{ 366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 367 368 return info->ngroups; 369} 370 371static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 372 unsigned selector) 373{ 374 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 375 376 return info->groups[selector].name; 377} 378 379static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 380 unsigned selector, const unsigned **pins, 381 unsigned *npins) 382{ 383 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 384 385 if (selector >= info->ngroups) 386 return -EINVAL; 387 388 *pins = info->groups[selector].pins; 389 *npins = info->groups[selector].npins; 390 391 return 0; 392} 393 394static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 395 struct device_node *np, 396 struct pinctrl_map **map, unsigned *num_maps) 397{ 398 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 399 const struct rockchip_pin_group *grp; 400 struct device *dev = info->dev; 401 struct pinctrl_map *new_map; 402 struct device_node *parent; 403 int map_num = 1; 404 int i; 405 406 /* 407 * first find the group of this node and check if we need to create 408 * config maps for pins 409 */ 410 grp = pinctrl_name_to_group(info, np->name); 411 if (!grp) { 412 dev_err(dev, "unable to find group for node %pOFn\n", np); 413 return -EINVAL; 414 } 415 416 map_num += grp->npins; 417 418 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 419 if (!new_map) 420 return -ENOMEM; 421 422 *map = new_map; 423 *num_maps = map_num; 424 425 /* create mux map */ 426 parent = of_get_parent(np); 427 if (!parent) { 428 kfree(new_map); 429 return -EINVAL; 430 } 431 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 432 new_map[0].data.mux.function = parent->name; 433 new_map[0].data.mux.group = np->name; 434 of_node_put(parent); 435 436 /* create config map */ 437 new_map++; 438 for (i = 0; i < grp->npins; i++) { 439 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 440 new_map[i].data.configs.group_or_pin = 441 pin_get_name(pctldev, grp->pins[i]); 442 new_map[i].data.configs.configs = grp->data[i].configs; 443 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 444 } 445 446 dev_dbg(dev, "maps: function %s group %s num %d\n", 447 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 448 449 return 0; 450} 451 452static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 453 struct pinctrl_map *map, unsigned num_maps) 454{ 455 kfree(map); 456} 457 458static const struct pinctrl_ops rockchip_pctrl_ops = { 459 .get_groups_count = rockchip_get_groups_count, 460 .get_group_name = rockchip_get_group_name, 461 .get_group_pins = rockchip_get_group_pins, 462 .dt_node_to_map = rockchip_dt_node_to_map, 463 .dt_free_map = rockchip_dt_free_map, 464}; 465 466/* 467 * Hardware access 468 */ 469 470static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 471 { 472 .num = 1, 473 .pin = 0, 474 .reg = 0x418, 475 .bit = 0, 476 .mask = 0x3 477 }, { 478 .num = 1, 479 .pin = 1, 480 .reg = 0x418, 481 .bit = 2, 482 .mask = 0x3 483 }, { 484 .num = 1, 485 .pin = 2, 486 .reg = 0x418, 487 .bit = 4, 488 .mask = 0x3 489 }, { 490 .num = 1, 491 .pin = 3, 492 .reg = 0x418, 493 .bit = 6, 494 .mask = 0x3 495 }, { 496 .num = 1, 497 .pin = 4, 498 .reg = 0x418, 499 .bit = 8, 500 .mask = 0x3 501 }, { 502 .num = 1, 503 .pin = 5, 504 .reg = 0x418, 505 .bit = 10, 506 .mask = 0x3 507 }, { 508 .num = 1, 509 .pin = 6, 510 .reg = 0x418, 511 .bit = 12, 512 .mask = 0x3 513 }, { 514 .num = 1, 515 .pin = 7, 516 .reg = 0x418, 517 .bit = 14, 518 .mask = 0x3 519 }, { 520 .num = 1, 521 .pin = 8, 522 .reg = 0x41c, 523 .bit = 0, 524 .mask = 0x3 525 }, { 526 .num = 1, 527 .pin = 9, 528 .reg = 0x41c, 529 .bit = 2, 530 .mask = 0x3 531 }, 532}; 533 534static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { 535 { 536 .num = 0, 537 .pin = 20, 538 .reg = 0x10000, 539 .bit = 0, 540 .mask = 0xf 541 }, 542 { 543 .num = 0, 544 .pin = 21, 545 .reg = 0x10000, 546 .bit = 4, 547 .mask = 0xf 548 }, 549 { 550 .num = 0, 551 .pin = 22, 552 .reg = 0x10000, 553 .bit = 8, 554 .mask = 0xf 555 }, 556 { 557 .num = 0, 558 .pin = 23, 559 .reg = 0x10000, 560 .bit = 12, 561 .mask = 0xf 562 }, 563}; 564 565static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 566 { 567 .num = 2, 568 .pin = 20, 569 .reg = 0xe8, 570 .bit = 0, 571 .mask = 0x7 572 }, { 573 .num = 2, 574 .pin = 21, 575 .reg = 0xe8, 576 .bit = 4, 577 .mask = 0x7 578 }, { 579 .num = 2, 580 .pin = 22, 581 .reg = 0xe8, 582 .bit = 8, 583 .mask = 0x7 584 }, { 585 .num = 2, 586 .pin = 23, 587 .reg = 0xe8, 588 .bit = 12, 589 .mask = 0x7 590 }, { 591 .num = 2, 592 .pin = 24, 593 .reg = 0xd4, 594 .bit = 12, 595 .mask = 0x7 596 }, 597}; 598 599static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 600 { 601 /* gpio1b6_sel */ 602 .num = 1, 603 .pin = 14, 604 .reg = 0x28, 605 .bit = 12, 606 .mask = 0xf 607 }, { 608 /* gpio1b7_sel */ 609 .num = 1, 610 .pin = 15, 611 .reg = 0x2c, 612 .bit = 0, 613 .mask = 0x3 614 }, { 615 /* gpio1c2_sel */ 616 .num = 1, 617 .pin = 18, 618 .reg = 0x30, 619 .bit = 4, 620 .mask = 0xf 621 }, { 622 /* gpio1c3_sel */ 623 .num = 1, 624 .pin = 19, 625 .reg = 0x30, 626 .bit = 8, 627 .mask = 0xf 628 }, { 629 /* gpio1c4_sel */ 630 .num = 1, 631 .pin = 20, 632 .reg = 0x30, 633 .bit = 12, 634 .mask = 0xf 635 }, { 636 /* gpio1c5_sel */ 637 .num = 1, 638 .pin = 21, 639 .reg = 0x34, 640 .bit = 0, 641 .mask = 0xf 642 }, { 643 /* gpio1c6_sel */ 644 .num = 1, 645 .pin = 22, 646 .reg = 0x34, 647 .bit = 4, 648 .mask = 0xf 649 }, { 650 /* gpio1c7_sel */ 651 .num = 1, 652 .pin = 23, 653 .reg = 0x34, 654 .bit = 8, 655 .mask = 0xf 656 }, { 657 /* gpio2a2_sel */ 658 .num = 2, 659 .pin = 2, 660 .reg = 0x40, 661 .bit = 4, 662 .mask = 0x3 663 }, { 664 /* gpio2a3_sel */ 665 .num = 2, 666 .pin = 3, 667 .reg = 0x40, 668 .bit = 6, 669 .mask = 0x3 670 }, { 671 /* gpio2c0_sel */ 672 .num = 2, 673 .pin = 16, 674 .reg = 0x50, 675 .bit = 0, 676 .mask = 0x3 677 }, { 678 /* gpio3b2_sel */ 679 .num = 3, 680 .pin = 10, 681 .reg = 0x68, 682 .bit = 4, 683 .mask = 0x3 684 }, { 685 /* gpio3b3_sel */ 686 .num = 3, 687 .pin = 11, 688 .reg = 0x68, 689 .bit = 6, 690 .mask = 0x3 691 }, { 692 /* gpio3b4_sel */ 693 .num = 3, 694 .pin = 12, 695 .reg = 0x68, 696 .bit = 8, 697 .mask = 0xf 698 }, { 699 /* gpio3b5_sel */ 700 .num = 3, 701 .pin = 13, 702 .reg = 0x68, 703 .bit = 12, 704 .mask = 0xf 705 }, 706}; 707 708static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 709 { 710 /* gpio2_b7_sel */ 711 .num = 2, 712 .pin = 15, 713 .reg = 0x28, 714 .bit = 0, 715 .mask = 0x7 716 }, { 717 /* gpio2_c7_sel */ 718 .num = 2, 719 .pin = 23, 720 .reg = 0x30, 721 .bit = 14, 722 .mask = 0x3 723 }, { 724 /* gpio3_b1_sel */ 725 .num = 3, 726 .pin = 9, 727 .reg = 0x44, 728 .bit = 2, 729 .mask = 0x3 730 }, { 731 /* gpio3_b2_sel */ 732 .num = 3, 733 .pin = 10, 734 .reg = 0x44, 735 .bit = 4, 736 .mask = 0x3 737 }, { 738 /* gpio3_b3_sel */ 739 .num = 3, 740 .pin = 11, 741 .reg = 0x44, 742 .bit = 6, 743 .mask = 0x3 744 }, { 745 /* gpio3_b4_sel */ 746 .num = 3, 747 .pin = 12, 748 .reg = 0x44, 749 .bit = 8, 750 .mask = 0x3 751 }, { 752 /* gpio3_b5_sel */ 753 .num = 3, 754 .pin = 13, 755 .reg = 0x44, 756 .bit = 10, 757 .mask = 0x3 758 }, { 759 /* gpio3_b6_sel */ 760 .num = 3, 761 .pin = 14, 762 .reg = 0x44, 763 .bit = 12, 764 .mask = 0x3 765 }, { 766 /* gpio3_b7_sel */ 767 .num = 3, 768 .pin = 15, 769 .reg = 0x44, 770 .bit = 14, 771 .mask = 0x3 772 }, 773}; 774 775static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 776 int *reg, u8 *bit, int *mask) 777{ 778 struct rockchip_pinctrl *info = bank->drvdata; 779 struct rockchip_pin_ctrl *ctrl = info->ctrl; 780 struct rockchip_mux_recalced_data *data; 781 int i; 782 783 for (i = 0; i < ctrl->niomux_recalced; i++) { 784 data = &ctrl->iomux_recalced[i]; 785 if (data->num == bank->bank_num && 786 data->pin == pin) 787 break; 788 } 789 790 if (i >= ctrl->niomux_recalced) 791 return; 792 793 *reg = data->reg; 794 *mask = data->mask; 795 *bit = data->bit; 796} 797 798static struct rockchip_mux_route_data px30_mux_route_data[] = { 799 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */ 800 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */ 801 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */ 802 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */ 803 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */ 804 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */ 805 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */ 806 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */ 807 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */ 808 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */ 809 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */ 810 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */ 811 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */ 812 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */ 813 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */ 814 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */ 815 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */ 816 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */ 817 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */ 818 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */ 819 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */ 820 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */ 821 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */ 822 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */ 823 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */ 824 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */ 825 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */ 826 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */ 827 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */ 828 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */ 829 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */ 830 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */ 831 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */ 832 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */ 833 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */ 834 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */ 835 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */ 836 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */ 837 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */ 838 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */ 839 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */ 840 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */ 841 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */ 842 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */ 843 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */ 844 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */ 845 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */ 846 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */ 847}; 848 849static struct rockchip_mux_route_data rv1126_mux_route_data[] = { 850 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ 851 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ 852 853 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ 854 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ 855 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ 856 857 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ 858 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ 859 860 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ 861 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ 862 863 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ 864 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ 865 866 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ 867 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ 868 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ 869 870 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ 871 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ 872 873 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ 874 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ 875 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ 876 877 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ 878 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ 879 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ 880 881 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ 882 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ 883 884 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ 885 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ 886 887 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */ 888 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */ 889 890 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */ 891 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */ 892 893 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */ 894 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */ 895 896 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ 897 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ 898 899 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ 900 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ 901 902 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ 903 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ 904 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ 905 906 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ 907 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ 908 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ 909 910 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ 911 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ 912 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ 913 914 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */ 915 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */ 916 917 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */ 918 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */ 919 920 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */ 921 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */ 922 923 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ 924 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ 925 926 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */ 927 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */ 928 929 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */ 930 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */ 931 932 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */ 933 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */ 934 935 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ 936 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ 937 938 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ 939 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ 940 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ 941 942 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ 943 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ 944}; 945 946static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 947 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */ 948 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */ 949 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */ 950 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */ 951 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */ 952 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */ 953 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */ 954}; 955 956static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 957 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */ 958 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */ 959}; 960 961static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 962 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */ 963 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */ 964 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */ 965 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */ 966 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */ 967 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */ 968 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */ 969 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */ 970 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */ 971 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */ 972 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */ 973 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */ 974 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */ 975 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */ 976 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */ 977 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */ 978 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */ 979 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */ 980}; 981 982static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 983 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */ 984 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */ 985}; 986 987static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 988 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */ 989 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */ 990 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */ 991 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */ 992 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */ 993 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */ 994 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */ 995 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */ 996 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */ 997 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */ 998 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */ 999 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */ 1000 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */ 1001}; 1002 1003static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1004 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */ 1005 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */ 1006 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */ 1007 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */ 1008 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */ 1009 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */ 1010 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */ 1011 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */ 1012 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */ 1013 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */ 1014 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */ 1015 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */ 1016}; 1017 1018static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1019 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */ 1020 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */ 1021 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */ 1022 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */ 1023 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */ 1024}; 1025 1026static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 1027 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */ 1028 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */ 1029 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */ 1030 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ 1031 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ 1032 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ 1033 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ 1034 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ 1035 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ 1036 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ 1037 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ 1038 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ 1039 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ 1040 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ 1041 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ 1042 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ 1043 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ 1044 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ 1045 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ 1046 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ 1047 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ 1048 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ 1049 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */ 1050 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */ 1051 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */ 1052 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */ 1053 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */ 1054 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */ 1055 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */ 1056 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */ 1057 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */ 1058 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */ 1059 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */ 1060 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */ 1061 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */ 1062 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */ 1063 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */ 1064 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */ 1065 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */ 1066 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */ 1067 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */ 1068 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ 1069 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ 1070 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ 1071 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ 1072 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ 1073 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ 1074 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ 1075 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */ 1076 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */ 1077 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ 1078 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ 1079 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ 1080 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ 1081 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ 1082 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ 1083 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ 1084 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ 1085 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */ 1086 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */ 1087 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */ 1088 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */ 1089 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */ 1090 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */ 1091 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */ 1092 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */ 1093 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */ 1094 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */ 1095 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */ 1096 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */ 1097 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */ 1098 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */ 1099 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */ 1100 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */ 1101 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */ 1102 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */ 1103 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */ 1104 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */ 1105 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */ 1106 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1107 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */ 1108 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1109 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ 1110 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ 1111 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ 1112 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ 1113 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ 1114 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ 1115 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ 1116 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ 1117 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ 1118 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ 1119 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ 1120}; 1121 1122static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1123 int mux, u32 *loc, u32 *reg, u32 *value) 1124{ 1125 struct rockchip_pinctrl *info = bank->drvdata; 1126 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1127 struct rockchip_mux_route_data *data; 1128 int i; 1129 1130 for (i = 0; i < ctrl->niomux_routes; i++) { 1131 data = &ctrl->iomux_routes[i]; 1132 if ((data->bank_num == bank->bank_num) && 1133 (data->pin == pin) && (data->func == mux)) 1134 break; 1135 } 1136 1137 if (i >= ctrl->niomux_routes) 1138 return false; 1139 1140 *loc = data->route_location; 1141 *reg = data->route_offset; 1142 *value = data->route_val; 1143 1144 return true; 1145} 1146 1147static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1148{ 1149 struct rockchip_pinctrl *info = bank->drvdata; 1150 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1151 int iomux_num = (pin / 8); 1152 struct regmap *regmap; 1153 unsigned int val; 1154 int reg, ret, mask, mux_type; 1155 u8 bit; 1156 1157 if (iomux_num > 3) 1158 return -EINVAL; 1159 1160 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1161 dev_err(info->dev, "pin %d is unrouted\n", pin); 1162 return -EINVAL; 1163 } 1164 1165 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1166 return RK_FUNC_GPIO; 1167 1168 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1169 regmap = info->regmap_pmu; 1170 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1171 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1172 else 1173 regmap = info->regmap_base; 1174 1175 if (ctrl->type == RK3506) { 1176 if (bank->bank_num == 1) 1177 regmap = info->regmap_ioc1; 1178 else if (bank->bank_num == 4) 1179 return 0; 1180 } 1181 1182 /* get basic quadrupel of mux registers and the correct reg inside */ 1183 mux_type = bank->iomux[iomux_num].type; 1184 reg = bank->iomux[iomux_num].offset; 1185 if (mux_type & IOMUX_WIDTH_4BIT) { 1186 if ((pin % 8) >= 4) 1187 reg += 0x4; 1188 bit = (pin % 4) * 4; 1189 mask = 0xf; 1190 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1191 if ((pin % 8) >= 5) 1192 reg += 0x4; 1193 bit = (pin % 8 % 5) * 3; 1194 mask = 0x7; 1195 } else { 1196 bit = (pin % 8) * 2; 1197 mask = 0x3; 1198 } 1199 1200 if (bank->recalced_mask & BIT(pin)) 1201 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1202 1203 if (ctrl->type == RK3576) { 1204 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) 1205 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ 1206 } 1207 1208 if (ctrl->type == RK3588) { 1209 if (bank->bank_num == 0) { 1210 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1211 u32 reg0 = 0; 1212 1213 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1214 ret = regmap_read(regmap, reg0, &val); 1215 if (ret) 1216 return ret; 1217 1218 if (!(val & BIT(8))) 1219 return ((val >> bit) & mask); 1220 1221 reg = reg + 0x8000; /* BUS_IOC_BASE */ 1222 regmap = info->regmap_base; 1223 } 1224 } else if (bank->bank_num > 0) { 1225 reg += 0x8000; /* BUS_IOC_BASE */ 1226 } 1227 } 1228 1229 ret = regmap_read(regmap, reg, &val); 1230 if (ret) 1231 return ret; 1232 1233 return ((val >> bit) & mask); 1234} 1235 1236static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1237 int pin, int mux) 1238{ 1239 struct rockchip_pinctrl *info = bank->drvdata; 1240 struct device *dev = info->dev; 1241 int iomux_num = (pin / 8); 1242 1243 if (iomux_num > 3) 1244 return -EINVAL; 1245 1246 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1247 dev_err(dev, "pin %d is unrouted\n", pin); 1248 return -EINVAL; 1249 } 1250 1251 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1252 if (mux != RK_FUNC_GPIO) { 1253 dev_err(dev, "pin %d only supports a gpio mux\n", pin); 1254 return -ENOTSUPP; 1255 } 1256 } 1257 1258 return 0; 1259} 1260 1261/* 1262 * Set a new mux function for a pin. 1263 * 1264 * The register is divided into the upper and lower 16 bit. When changing 1265 * a value, the previous register value is not read and changed. Instead 1266 * it seems the changed bits are marked in the upper 16 bit, while the 1267 * changed value gets set in the same offset in the lower 16 bit. 1268 * All pin settings seem to be 2 bit wide in both the upper and lower 1269 * parts. 1270 * @bank: pin bank to change 1271 * @pin: pin to change 1272 * @mux: new mux function to set 1273 */ 1274static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1275{ 1276 struct rockchip_pinctrl *info = bank->drvdata; 1277 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1278 struct device *dev = info->dev; 1279 int iomux_num = (pin / 8); 1280 struct regmap *regmap; 1281 int reg, ret, mask, mux_type; 1282 u8 bit; 1283 u32 data, rmask, route_location, route_reg, route_val; 1284 1285 ret = rockchip_verify_mux(bank, pin, mux); 1286 if (ret < 0) 1287 return ret; 1288 1289 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1290 return 0; 1291 1292 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1293 1294 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1295 regmap = info->regmap_pmu; 1296 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) 1297 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base; 1298 else 1299 regmap = info->regmap_base; 1300 1301 if (ctrl->type == RK3506) { 1302 if (bank->bank_num == 1) 1303 regmap = info->regmap_ioc1; 1304 else if (bank->bank_num == 4) 1305 return 0; 1306 } 1307 1308 /* get basic quadrupel of mux registers and the correct reg inside */ 1309 mux_type = bank->iomux[iomux_num].type; 1310 reg = bank->iomux[iomux_num].offset; 1311 if (mux_type & IOMUX_WIDTH_4BIT) { 1312 if ((pin % 8) >= 4) 1313 reg += 0x4; 1314 bit = (pin % 4) * 4; 1315 mask = 0xf; 1316 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1317 if ((pin % 8) >= 5) 1318 reg += 0x4; 1319 bit = (pin % 8 % 5) * 3; 1320 mask = 0x7; 1321 } else { 1322 bit = (pin % 8) * 2; 1323 mask = 0x3; 1324 } 1325 1326 if (bank->recalced_mask & BIT(pin)) 1327 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1328 1329 if (ctrl->type == RK3576) { 1330 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7)) 1331 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */ 1332 } 1333 1334 if (ctrl->type == RK3588) { 1335 if (bank->bank_num == 0) { 1336 if ((pin >= RK_PB4) && (pin <= RK_PD7)) { 1337 if (mux < 8) { 1338 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1339 data = (mask << (bit + 16)); 1340 rmask = data | (data >> 16); 1341 data |= (mux & mask) << bit; 1342 ret = regmap_update_bits(regmap, reg, rmask, data); 1343 } else { 1344 u32 reg0 = 0; 1345 1346 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */ 1347 data = (mask << (bit + 16)); 1348 rmask = data | (data >> 16); 1349 data |= 8 << bit; 1350 ret = regmap_update_bits(regmap, reg0, rmask, data); 1351 1352 reg0 = reg + 0x8000; /* BUS_IOC_BASE */ 1353 data = (mask << (bit + 16)); 1354 rmask = data | (data >> 16); 1355 data |= mux << bit; 1356 regmap = info->regmap_base; 1357 ret |= regmap_update_bits(regmap, reg0, rmask, data); 1358 } 1359 } else { 1360 data = (mask << (bit + 16)); 1361 rmask = data | (data >> 16); 1362 data |= (mux & mask) << bit; 1363 ret = regmap_update_bits(regmap, reg, rmask, data); 1364 } 1365 return ret; 1366 } else if (bank->bank_num > 0) { 1367 reg += 0x8000; /* BUS_IOC_BASE */ 1368 } 1369 } 1370 1371 if (mux > mask) 1372 return -EINVAL; 1373 1374 if (bank->route_mask & BIT(pin)) { 1375 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1376 &route_reg, &route_val)) { 1377 struct regmap *route_regmap = regmap; 1378 1379 /* handle special locations */ 1380 switch (route_location) { 1381 case ROCKCHIP_ROUTE_PMU: 1382 route_regmap = info->regmap_pmu; 1383 break; 1384 case ROCKCHIP_ROUTE_GRF: 1385 route_regmap = info->regmap_base; 1386 break; 1387 } 1388 1389 ret = regmap_write(route_regmap, route_reg, route_val); 1390 if (ret) 1391 return ret; 1392 } 1393 } 1394 1395 data = (mask << (bit + 16)); 1396 rmask = data | (data >> 16); 1397 data |= (mux & mask) << bit; 1398 ret = regmap_update_bits(regmap, reg, rmask, data); 1399 1400 return ret; 1401} 1402 1403#define PX30_PULL_PMU_OFFSET 0x10 1404#define PX30_PULL_GRF_OFFSET 0x60 1405#define PX30_PULL_BITS_PER_PIN 2 1406#define PX30_PULL_PINS_PER_REG 8 1407#define PX30_PULL_BANK_STRIDE 16 1408 1409static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1410 int pin_num, struct regmap **regmap, 1411 int *reg, u8 *bit) 1412{ 1413 struct rockchip_pinctrl *info = bank->drvdata; 1414 1415 /* The first 32 pins of the first bank are located in PMU */ 1416 if (bank->bank_num == 0) { 1417 *regmap = info->regmap_pmu; 1418 *reg = PX30_PULL_PMU_OFFSET; 1419 } else { 1420 *regmap = info->regmap_base; 1421 *reg = PX30_PULL_GRF_OFFSET; 1422 1423 /* correct the offset, as we're starting with the 2nd bank */ 1424 *reg -= 0x10; 1425 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1426 } 1427 1428 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1429 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1430 *bit *= PX30_PULL_BITS_PER_PIN; 1431 1432 return 0; 1433} 1434 1435#define PX30_DRV_PMU_OFFSET 0x20 1436#define PX30_DRV_GRF_OFFSET 0xf0 1437#define PX30_DRV_BITS_PER_PIN 2 1438#define PX30_DRV_PINS_PER_REG 8 1439#define PX30_DRV_BANK_STRIDE 16 1440 1441static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1442 int pin_num, struct regmap **regmap, 1443 int *reg, u8 *bit) 1444{ 1445 struct rockchip_pinctrl *info = bank->drvdata; 1446 1447 /* The first 32 pins of the first bank are located in PMU */ 1448 if (bank->bank_num == 0) { 1449 *regmap = info->regmap_pmu; 1450 *reg = PX30_DRV_PMU_OFFSET; 1451 } else { 1452 *regmap = info->regmap_base; 1453 *reg = PX30_DRV_GRF_OFFSET; 1454 1455 /* correct the offset, as we're starting with the 2nd bank */ 1456 *reg -= 0x10; 1457 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1458 } 1459 1460 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1461 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1462 *bit *= PX30_DRV_BITS_PER_PIN; 1463 1464 return 0; 1465} 1466 1467#define PX30_SCHMITT_PMU_OFFSET 0x38 1468#define PX30_SCHMITT_GRF_OFFSET 0xc0 1469#define PX30_SCHMITT_PINS_PER_PMU_REG 16 1470#define PX30_SCHMITT_BANK_STRIDE 16 1471#define PX30_SCHMITT_PINS_PER_GRF_REG 8 1472 1473static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1474 int pin_num, 1475 struct regmap **regmap, 1476 int *reg, u8 *bit) 1477{ 1478 struct rockchip_pinctrl *info = bank->drvdata; 1479 int pins_per_reg; 1480 1481 if (bank->bank_num == 0) { 1482 *regmap = info->regmap_pmu; 1483 *reg = PX30_SCHMITT_PMU_OFFSET; 1484 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1485 } else { 1486 *regmap = info->regmap_base; 1487 *reg = PX30_SCHMITT_GRF_OFFSET; 1488 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1489 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1490 } 1491 1492 *reg += ((pin_num / pins_per_reg) * 4); 1493 *bit = pin_num % pins_per_reg; 1494 1495 return 0; 1496} 1497 1498#define RV1108_PULL_PMU_OFFSET 0x10 1499#define RV1108_PULL_OFFSET 0x110 1500#define RV1108_PULL_PINS_PER_REG 8 1501#define RV1108_PULL_BITS_PER_PIN 2 1502#define RV1108_PULL_BANK_STRIDE 16 1503 1504static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1505 int pin_num, struct regmap **regmap, 1506 int *reg, u8 *bit) 1507{ 1508 struct rockchip_pinctrl *info = bank->drvdata; 1509 1510 /* The first 24 pins of the first bank are located in PMU */ 1511 if (bank->bank_num == 0) { 1512 *regmap = info->regmap_pmu; 1513 *reg = RV1108_PULL_PMU_OFFSET; 1514 } else { 1515 *reg = RV1108_PULL_OFFSET; 1516 *regmap = info->regmap_base; 1517 /* correct the offset, as we're starting with the 2nd bank */ 1518 *reg -= 0x10; 1519 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1520 } 1521 1522 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1523 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1524 *bit *= RV1108_PULL_BITS_PER_PIN; 1525 1526 return 0; 1527} 1528 1529#define RV1108_DRV_PMU_OFFSET 0x20 1530#define RV1108_DRV_GRF_OFFSET 0x210 1531#define RV1108_DRV_BITS_PER_PIN 2 1532#define RV1108_DRV_PINS_PER_REG 8 1533#define RV1108_DRV_BANK_STRIDE 16 1534 1535static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1536 int pin_num, struct regmap **regmap, 1537 int *reg, u8 *bit) 1538{ 1539 struct rockchip_pinctrl *info = bank->drvdata; 1540 1541 /* The first 24 pins of the first bank are located in PMU */ 1542 if (bank->bank_num == 0) { 1543 *regmap = info->regmap_pmu; 1544 *reg = RV1108_DRV_PMU_OFFSET; 1545 } else { 1546 *regmap = info->regmap_base; 1547 *reg = RV1108_DRV_GRF_OFFSET; 1548 1549 /* correct the offset, as we're starting with the 2nd bank */ 1550 *reg -= 0x10; 1551 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1552 } 1553 1554 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1555 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1556 *bit *= RV1108_DRV_BITS_PER_PIN; 1557 1558 return 0; 1559} 1560 1561#define RV1108_SCHMITT_PMU_OFFSET 0x30 1562#define RV1108_SCHMITT_GRF_OFFSET 0x388 1563#define RV1108_SCHMITT_BANK_STRIDE 8 1564#define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1565#define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1566 1567static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1568 int pin_num, 1569 struct regmap **regmap, 1570 int *reg, u8 *bit) 1571{ 1572 struct rockchip_pinctrl *info = bank->drvdata; 1573 int pins_per_reg; 1574 1575 if (bank->bank_num == 0) { 1576 *regmap = info->regmap_pmu; 1577 *reg = RV1108_SCHMITT_PMU_OFFSET; 1578 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1579 } else { 1580 *regmap = info->regmap_base; 1581 *reg = RV1108_SCHMITT_GRF_OFFSET; 1582 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1583 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1584 } 1585 *reg += ((pin_num / pins_per_reg) * 4); 1586 *bit = pin_num % pins_per_reg; 1587 1588 return 0; 1589} 1590 1591#define RV1126_PULL_PMU_OFFSET 0x40 1592#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 1593#define RV1126_PULL_PINS_PER_REG 8 1594#define RV1126_PULL_BITS_PER_PIN 2 1595#define RV1126_PULL_BANK_STRIDE 16 1596#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ 1597 1598static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1599 int pin_num, struct regmap **regmap, 1600 int *reg, u8 *bit) 1601{ 1602 struct rockchip_pinctrl *info = bank->drvdata; 1603 1604 /* The first 24 pins of the first bank are located in PMU */ 1605 if (bank->bank_num == 0) { 1606 if (RV1126_GPIO_C4_D7(pin_num)) { 1607 *regmap = info->regmap_base; 1608 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1609 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); 1610 *bit = pin_num % RV1126_PULL_PINS_PER_REG; 1611 *bit *= RV1126_PULL_BITS_PER_PIN; 1612 return 0; 1613 } 1614 *regmap = info->regmap_pmu; 1615 *reg = RV1126_PULL_PMU_OFFSET; 1616 } else { 1617 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; 1618 *regmap = info->regmap_base; 1619 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; 1620 } 1621 1622 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); 1623 *bit = (pin_num % RV1126_PULL_PINS_PER_REG); 1624 *bit *= RV1126_PULL_BITS_PER_PIN; 1625 1626 return 0; 1627} 1628 1629#define RV1126_DRV_PMU_OFFSET 0x20 1630#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 1631#define RV1126_DRV_BITS_PER_PIN 4 1632#define RV1126_DRV_PINS_PER_REG 4 1633#define RV1126_DRV_BANK_STRIDE 32 1634 1635static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1636 int pin_num, struct regmap **regmap, 1637 int *reg, u8 *bit) 1638{ 1639 struct rockchip_pinctrl *info = bank->drvdata; 1640 1641 /* The first 24 pins of the first bank are located in PMU */ 1642 if (bank->bank_num == 0) { 1643 if (RV1126_GPIO_C4_D7(pin_num)) { 1644 *regmap = info->regmap_base; 1645 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1646 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); 1647 *reg -= 0x4; 1648 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1649 *bit *= RV1126_DRV_BITS_PER_PIN; 1650 return 0; 1651 } 1652 *regmap = info->regmap_pmu; 1653 *reg = RV1126_DRV_PMU_OFFSET; 1654 } else { 1655 *regmap = info->regmap_base; 1656 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; 1657 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; 1658 } 1659 1660 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); 1661 *bit = pin_num % RV1126_DRV_PINS_PER_REG; 1662 *bit *= RV1126_DRV_BITS_PER_PIN; 1663 1664 return 0; 1665} 1666 1667#define RV1126_SCHMITT_PMU_OFFSET 0x60 1668#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 1669#define RV1126_SCHMITT_BANK_STRIDE 16 1670#define RV1126_SCHMITT_PINS_PER_GRF_REG 8 1671#define RV1126_SCHMITT_PINS_PER_PMU_REG 8 1672 1673static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1674 int pin_num, 1675 struct regmap **regmap, 1676 int *reg, u8 *bit) 1677{ 1678 struct rockchip_pinctrl *info = bank->drvdata; 1679 int pins_per_reg; 1680 1681 if (bank->bank_num == 0) { 1682 if (RV1126_GPIO_C4_D7(pin_num)) { 1683 *regmap = info->regmap_base; 1684 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1685 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); 1686 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; 1687 return 0; 1688 } 1689 *regmap = info->regmap_pmu; 1690 *reg = RV1126_SCHMITT_PMU_OFFSET; 1691 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; 1692 } else { 1693 *regmap = info->regmap_base; 1694 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; 1695 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; 1696 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; 1697 } 1698 *reg += ((pin_num / pins_per_reg) * 4); 1699 *bit = pin_num % pins_per_reg; 1700 1701 return 0; 1702} 1703 1704#define RK3308_SCHMITT_PINS_PER_REG 8 1705#define RK3308_SCHMITT_BANK_STRIDE 16 1706#define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1707 1708static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1709 int pin_num, struct regmap **regmap, 1710 int *reg, u8 *bit) 1711{ 1712 struct rockchip_pinctrl *info = bank->drvdata; 1713 1714 *regmap = info->regmap_base; 1715 *reg = RK3308_SCHMITT_GRF_OFFSET; 1716 1717 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1718 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1719 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1720 1721 return 0; 1722} 1723 1724#define RK2928_PULL_OFFSET 0x118 1725#define RK2928_PULL_PINS_PER_REG 16 1726#define RK2928_PULL_BANK_STRIDE 8 1727 1728static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1729 int pin_num, struct regmap **regmap, 1730 int *reg, u8 *bit) 1731{ 1732 struct rockchip_pinctrl *info = bank->drvdata; 1733 1734 *regmap = info->regmap_base; 1735 *reg = RK2928_PULL_OFFSET; 1736 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1737 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1738 1739 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1740 1741 return 0; 1742}; 1743 1744#define RK3128_PULL_OFFSET 0x118 1745 1746static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1747 int pin_num, struct regmap **regmap, 1748 int *reg, u8 *bit) 1749{ 1750 struct rockchip_pinctrl *info = bank->drvdata; 1751 1752 *regmap = info->regmap_base; 1753 *reg = RK3128_PULL_OFFSET; 1754 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1755 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1756 1757 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1758 1759 return 0; 1760} 1761 1762#define RK3188_PULL_OFFSET 0x164 1763#define RK3188_PULL_BITS_PER_PIN 2 1764#define RK3188_PULL_PINS_PER_REG 8 1765#define RK3188_PULL_BANK_STRIDE 16 1766#define RK3188_PULL_PMU_OFFSET 0x64 1767 1768static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1769 int pin_num, struct regmap **regmap, 1770 int *reg, u8 *bit) 1771{ 1772 struct rockchip_pinctrl *info = bank->drvdata; 1773 1774 /* The first 12 pins of the first bank are located elsewhere */ 1775 if (bank->bank_num == 0 && pin_num < 12) { 1776 *regmap = info->regmap_pmu ? info->regmap_pmu 1777 : bank->regmap_pull; 1778 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1779 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1780 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1781 *bit *= RK3188_PULL_BITS_PER_PIN; 1782 } else { 1783 *regmap = info->regmap_pull ? info->regmap_pull 1784 : info->regmap_base; 1785 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1786 1787 /* correct the offset, as it is the 2nd pull register */ 1788 *reg -= 4; 1789 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1790 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1791 1792 /* 1793 * The bits in these registers have an inverse ordering 1794 * with the lowest pin being in bits 15:14 and the highest 1795 * pin in bits 1:0 1796 */ 1797 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1798 *bit *= RK3188_PULL_BITS_PER_PIN; 1799 } 1800 1801 return 0; 1802} 1803 1804#define RK3288_PULL_OFFSET 0x140 1805static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1806 int pin_num, struct regmap **regmap, 1807 int *reg, u8 *bit) 1808{ 1809 struct rockchip_pinctrl *info = bank->drvdata; 1810 1811 /* The first 24 pins of the first bank are located in PMU */ 1812 if (bank->bank_num == 0) { 1813 *regmap = info->regmap_pmu; 1814 *reg = RK3188_PULL_PMU_OFFSET; 1815 1816 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1817 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1818 *bit *= RK3188_PULL_BITS_PER_PIN; 1819 } else { 1820 *regmap = info->regmap_base; 1821 *reg = RK3288_PULL_OFFSET; 1822 1823 /* correct the offset, as we're starting with the 2nd bank */ 1824 *reg -= 0x10; 1825 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1826 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1827 1828 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1829 *bit *= RK3188_PULL_BITS_PER_PIN; 1830 } 1831 1832 return 0; 1833} 1834 1835#define RK3288_DRV_PMU_OFFSET 0x70 1836#define RK3288_DRV_GRF_OFFSET 0x1c0 1837#define RK3288_DRV_BITS_PER_PIN 2 1838#define RK3288_DRV_PINS_PER_REG 8 1839#define RK3288_DRV_BANK_STRIDE 16 1840 1841static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1842 int pin_num, struct regmap **regmap, 1843 int *reg, u8 *bit) 1844{ 1845 struct rockchip_pinctrl *info = bank->drvdata; 1846 1847 /* The first 24 pins of the first bank are located in PMU */ 1848 if (bank->bank_num == 0) { 1849 *regmap = info->regmap_pmu; 1850 *reg = RK3288_DRV_PMU_OFFSET; 1851 1852 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1853 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1854 *bit *= RK3288_DRV_BITS_PER_PIN; 1855 } else { 1856 *regmap = info->regmap_base; 1857 *reg = RK3288_DRV_GRF_OFFSET; 1858 1859 /* correct the offset, as we're starting with the 2nd bank */ 1860 *reg -= 0x10; 1861 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1862 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1863 1864 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1865 *bit *= RK3288_DRV_BITS_PER_PIN; 1866 } 1867 1868 return 0; 1869} 1870 1871#define RK3228_PULL_OFFSET 0x100 1872 1873static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1874 int pin_num, struct regmap **regmap, 1875 int *reg, u8 *bit) 1876{ 1877 struct rockchip_pinctrl *info = bank->drvdata; 1878 1879 *regmap = info->regmap_base; 1880 *reg = RK3228_PULL_OFFSET; 1881 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1882 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1883 1884 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1885 *bit *= RK3188_PULL_BITS_PER_PIN; 1886 1887 return 0; 1888} 1889 1890#define RK3228_DRV_GRF_OFFSET 0x200 1891 1892static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1893 int pin_num, struct regmap **regmap, 1894 int *reg, u8 *bit) 1895{ 1896 struct rockchip_pinctrl *info = bank->drvdata; 1897 1898 *regmap = info->regmap_base; 1899 *reg = RK3228_DRV_GRF_OFFSET; 1900 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1901 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1902 1903 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1904 *bit *= RK3288_DRV_BITS_PER_PIN; 1905 1906 return 0; 1907} 1908 1909#define RK3308_PULL_OFFSET 0xa0 1910 1911static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1912 int pin_num, struct regmap **regmap, 1913 int *reg, u8 *bit) 1914{ 1915 struct rockchip_pinctrl *info = bank->drvdata; 1916 1917 *regmap = info->regmap_base; 1918 *reg = RK3308_PULL_OFFSET; 1919 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1920 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1921 1922 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1923 *bit *= RK3188_PULL_BITS_PER_PIN; 1924 1925 return 0; 1926} 1927 1928#define RK3308_DRV_GRF_OFFSET 0x100 1929 1930static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1931 int pin_num, struct regmap **regmap, 1932 int *reg, u8 *bit) 1933{ 1934 struct rockchip_pinctrl *info = bank->drvdata; 1935 1936 *regmap = info->regmap_base; 1937 *reg = RK3308_DRV_GRF_OFFSET; 1938 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1939 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1940 1941 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1942 *bit *= RK3288_DRV_BITS_PER_PIN; 1943 1944 return 0; 1945} 1946 1947#define RK3368_PULL_GRF_OFFSET 0x100 1948#define RK3368_PULL_PMU_OFFSET 0x10 1949 1950static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1951 int pin_num, struct regmap **regmap, 1952 int *reg, u8 *bit) 1953{ 1954 struct rockchip_pinctrl *info = bank->drvdata; 1955 1956 /* The first 32 pins of the first bank are located in PMU */ 1957 if (bank->bank_num == 0) { 1958 *regmap = info->regmap_pmu; 1959 *reg = RK3368_PULL_PMU_OFFSET; 1960 1961 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1962 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1963 *bit *= RK3188_PULL_BITS_PER_PIN; 1964 } else { 1965 *regmap = info->regmap_base; 1966 *reg = RK3368_PULL_GRF_OFFSET; 1967 1968 /* correct the offset, as we're starting with the 2nd bank */ 1969 *reg -= 0x10; 1970 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1971 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1972 1973 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1974 *bit *= RK3188_PULL_BITS_PER_PIN; 1975 } 1976 1977 return 0; 1978} 1979 1980#define RK3368_DRV_PMU_OFFSET 0x20 1981#define RK3368_DRV_GRF_OFFSET 0x200 1982 1983static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1984 int pin_num, struct regmap **regmap, 1985 int *reg, u8 *bit) 1986{ 1987 struct rockchip_pinctrl *info = bank->drvdata; 1988 1989 /* The first 32 pins of the first bank are located in PMU */ 1990 if (bank->bank_num == 0) { 1991 *regmap = info->regmap_pmu; 1992 *reg = RK3368_DRV_PMU_OFFSET; 1993 1994 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1995 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1996 *bit *= RK3288_DRV_BITS_PER_PIN; 1997 } else { 1998 *regmap = info->regmap_base; 1999 *reg = RK3368_DRV_GRF_OFFSET; 2000 2001 /* correct the offset, as we're starting with the 2nd bank */ 2002 *reg -= 0x10; 2003 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2004 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2005 2006 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2007 *bit *= RK3288_DRV_BITS_PER_PIN; 2008 } 2009 2010 return 0; 2011} 2012 2013#define RK3399_PULL_GRF_OFFSET 0xe040 2014#define RK3399_PULL_PMU_OFFSET 0x40 2015#define RK3399_DRV_3BITS_PER_PIN 3 2016 2017static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2018 int pin_num, struct regmap **regmap, 2019 int *reg, u8 *bit) 2020{ 2021 struct rockchip_pinctrl *info = bank->drvdata; 2022 2023 /* The bank0:16 and bank1:32 pins are located in PMU */ 2024 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2025 *regmap = info->regmap_pmu; 2026 *reg = RK3399_PULL_PMU_OFFSET; 2027 2028 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2029 2030 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2031 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2032 *bit *= RK3188_PULL_BITS_PER_PIN; 2033 } else { 2034 *regmap = info->regmap_base; 2035 *reg = RK3399_PULL_GRF_OFFSET; 2036 2037 /* correct the offset, as we're starting with the 3rd bank */ 2038 *reg -= 0x20; 2039 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2040 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2041 2042 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2043 *bit *= RK3188_PULL_BITS_PER_PIN; 2044 } 2045 2046 return 0; 2047} 2048 2049static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2050 int pin_num, struct regmap **regmap, 2051 int *reg, u8 *bit) 2052{ 2053 struct rockchip_pinctrl *info = bank->drvdata; 2054 int drv_num = (pin_num / 8); 2055 2056 /* The bank0:16 and bank1:32 pins are located in PMU */ 2057 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2058 *regmap = info->regmap_pmu; 2059 else 2060 *regmap = info->regmap_base; 2061 2062 *reg = bank->drv[drv_num].offset; 2063 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2064 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2065 *bit = (pin_num % 8) * 3; 2066 else 2067 *bit = (pin_num % 8) * 2; 2068 2069 return 0; 2070} 2071 2072#define RK3506_DRV_BITS_PER_PIN 8 2073#define RK3506_DRV_PINS_PER_REG 2 2074#define RK3506_DRV_GPIO0_A_OFFSET 0x100 2075#define RK3506_DRV_GPIO0_D_OFFSET 0x830 2076#define RK3506_DRV_GPIO1_OFFSET 0x140 2077#define RK3506_DRV_GPIO2_OFFSET 0x180 2078#define RK3506_DRV_GPIO3_OFFSET 0x1c0 2079#define RK3506_DRV_GPIO4_OFFSET 0x840 2080 2081static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2082 int pin_num, struct regmap **regmap, 2083 int *reg, u8 *bit) 2084{ 2085 struct rockchip_pinctrl *info = bank->drvdata; 2086 int ret = 0; 2087 2088 switch (bank->bank_num) { 2089 case 0: 2090 *regmap = info->regmap_pmu; 2091 if (pin_num > 24) { 2092 ret = -EINVAL; 2093 } else if (pin_num < 24) { 2094 *reg = RK3506_DRV_GPIO0_A_OFFSET; 2095 } else { 2096 *reg = RK3506_DRV_GPIO0_D_OFFSET; 2097 *bit = 3; 2098 2099 return 0; 2100 } 2101 break; 2102 2103 case 1: 2104 *regmap = info->regmap_ioc1; 2105 if (pin_num < 28) 2106 *reg = RK3506_DRV_GPIO1_OFFSET; 2107 else 2108 ret = -EINVAL; 2109 break; 2110 2111 case 2: 2112 *regmap = info->regmap_base; 2113 if (pin_num < 17) 2114 *reg = RK3506_DRV_GPIO2_OFFSET; 2115 else 2116 ret = -EINVAL; 2117 break; 2118 2119 case 3: 2120 *regmap = info->regmap_base; 2121 if (pin_num < 15) 2122 *reg = RK3506_DRV_GPIO3_OFFSET; 2123 else 2124 ret = -EINVAL; 2125 break; 2126 2127 case 4: 2128 *regmap = info->regmap_base; 2129 if (pin_num < 8 || pin_num > 11) { 2130 ret = -EINVAL; 2131 } else { 2132 *reg = RK3506_DRV_GPIO4_OFFSET; 2133 *bit = 10; 2134 2135 return 0; 2136 } 2137 break; 2138 2139 default: 2140 ret = -EINVAL; 2141 break; 2142 } 2143 2144 if (ret) { 2145 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); 2146 2147 return ret; 2148 } 2149 2150 *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4); 2151 *bit = pin_num % RK3506_DRV_PINS_PER_REG; 2152 *bit *= RK3506_DRV_BITS_PER_PIN; 2153 2154 return 0; 2155} 2156 2157#define RK3506_PULL_BITS_PER_PIN 2 2158#define RK3506_PULL_PINS_PER_REG 8 2159#define RK3506_PULL_GPIO0_A_OFFSET 0x200 2160#define RK3506_PULL_GPIO0_D_OFFSET 0x830 2161#define RK3506_PULL_GPIO1_OFFSET 0x210 2162#define RK3506_PULL_GPIO2_OFFSET 0x220 2163#define RK3506_PULL_GPIO3_OFFSET 0x230 2164#define RK3506_PULL_GPIO4_OFFSET 0x840 2165 2166static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2167 int pin_num, struct regmap **regmap, 2168 int *reg, u8 *bit) 2169{ 2170 struct rockchip_pinctrl *info = bank->drvdata; 2171 int ret = 0; 2172 2173 switch (bank->bank_num) { 2174 case 0: 2175 *regmap = info->regmap_pmu; 2176 if (pin_num > 24) { 2177 ret = -EINVAL; 2178 } else if (pin_num < 24) { 2179 *reg = RK3506_PULL_GPIO0_A_OFFSET; 2180 } else { 2181 *reg = RK3506_PULL_GPIO0_D_OFFSET; 2182 *bit = 5; 2183 2184 return 0; 2185 } 2186 break; 2187 2188 case 1: 2189 *regmap = info->regmap_ioc1; 2190 if (pin_num < 28) 2191 *reg = RK3506_PULL_GPIO1_OFFSET; 2192 else 2193 ret = -EINVAL; 2194 break; 2195 2196 case 2: 2197 *regmap = info->regmap_base; 2198 if (pin_num < 17) 2199 *reg = RK3506_PULL_GPIO2_OFFSET; 2200 else 2201 ret = -EINVAL; 2202 break; 2203 2204 case 3: 2205 *regmap = info->regmap_base; 2206 if (pin_num < 15) 2207 *reg = RK3506_PULL_GPIO3_OFFSET; 2208 else 2209 ret = -EINVAL; 2210 break; 2211 2212 case 4: 2213 *regmap = info->regmap_base; 2214 if (pin_num < 8 || pin_num > 11) { 2215 ret = -EINVAL; 2216 } else { 2217 *reg = RK3506_PULL_GPIO4_OFFSET; 2218 *bit = 13; 2219 2220 return 0; 2221 } 2222 break; 2223 2224 default: 2225 ret = -EINVAL; 2226 break; 2227 } 2228 2229 if (ret) { 2230 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); 2231 2232 return ret; 2233 } 2234 2235 *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4); 2236 *bit = pin_num % RK3506_PULL_PINS_PER_REG; 2237 *bit *= RK3506_PULL_BITS_PER_PIN; 2238 2239 return 0; 2240} 2241 2242#define RK3506_SMT_BITS_PER_PIN 1 2243#define RK3506_SMT_PINS_PER_REG 8 2244#define RK3506_SMT_GPIO0_A_OFFSET 0x400 2245#define RK3506_SMT_GPIO0_D_OFFSET 0x830 2246#define RK3506_SMT_GPIO1_OFFSET 0x410 2247#define RK3506_SMT_GPIO2_OFFSET 0x420 2248#define RK3506_SMT_GPIO3_OFFSET 0x430 2249#define RK3506_SMT_GPIO4_OFFSET 0x840 2250 2251static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2252 int pin_num, 2253 struct regmap **regmap, 2254 int *reg, u8 *bit) 2255{ 2256 struct rockchip_pinctrl *info = bank->drvdata; 2257 int ret = 0; 2258 2259 switch (bank->bank_num) { 2260 case 0: 2261 *regmap = info->regmap_pmu; 2262 if (pin_num > 24) { 2263 ret = -EINVAL; 2264 } else if (pin_num < 24) { 2265 *reg = RK3506_SMT_GPIO0_A_OFFSET; 2266 } else { 2267 *reg = RK3506_SMT_GPIO0_D_OFFSET; 2268 *bit = 9; 2269 2270 return 0; 2271 } 2272 break; 2273 2274 case 1: 2275 *regmap = info->regmap_ioc1; 2276 if (pin_num < 28) 2277 *reg = RK3506_SMT_GPIO1_OFFSET; 2278 else 2279 ret = -EINVAL; 2280 break; 2281 2282 case 2: 2283 *regmap = info->regmap_base; 2284 if (pin_num < 17) 2285 *reg = RK3506_SMT_GPIO2_OFFSET; 2286 else 2287 ret = -EINVAL; 2288 break; 2289 2290 case 3: 2291 *regmap = info->regmap_base; 2292 if (pin_num < 15) 2293 *reg = RK3506_SMT_GPIO3_OFFSET; 2294 else 2295 ret = -EINVAL; 2296 break; 2297 2298 case 4: 2299 *regmap = info->regmap_base; 2300 if (pin_num < 8 || pin_num > 11) { 2301 ret = -EINVAL; 2302 } else { 2303 *reg = RK3506_SMT_GPIO4_OFFSET; 2304 *bit = 8; 2305 2306 return 0; 2307 } 2308 break; 2309 2310 default: 2311 ret = -EINVAL; 2312 break; 2313 } 2314 2315 if (ret) { 2316 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num); 2317 2318 return ret; 2319 } 2320 2321 *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4); 2322 *bit = pin_num % RK3506_SMT_PINS_PER_REG; 2323 *bit *= RK3506_SMT_BITS_PER_PIN; 2324 2325 return 0; 2326} 2327 2328#define RK3528_DRV_BITS_PER_PIN 8 2329#define RK3528_DRV_PINS_PER_REG 2 2330#define RK3528_DRV_GPIO0_OFFSET 0x100 2331#define RK3528_DRV_GPIO1_OFFSET 0x20120 2332#define RK3528_DRV_GPIO2_OFFSET 0x30160 2333#define RK3528_DRV_GPIO3_OFFSET 0x20190 2334#define RK3528_DRV_GPIO4_OFFSET 0x101C0 2335 2336static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2337 int pin_num, struct regmap **regmap, 2338 int *reg, u8 *bit) 2339{ 2340 struct rockchip_pinctrl *info = bank->drvdata; 2341 2342 *regmap = info->regmap_base; 2343 2344 if (bank->bank_num == 0) 2345 *reg = RK3528_DRV_GPIO0_OFFSET; 2346 else if (bank->bank_num == 1) 2347 *reg = RK3528_DRV_GPIO1_OFFSET; 2348 else if (bank->bank_num == 2) 2349 *reg = RK3528_DRV_GPIO2_OFFSET; 2350 else if (bank->bank_num == 3) 2351 *reg = RK3528_DRV_GPIO3_OFFSET; 2352 else if (bank->bank_num == 4) 2353 *reg = RK3528_DRV_GPIO4_OFFSET; 2354 else 2355 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2356 2357 *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4); 2358 *bit = pin_num % RK3528_DRV_PINS_PER_REG; 2359 *bit *= RK3528_DRV_BITS_PER_PIN; 2360 2361 return 0; 2362} 2363 2364#define RK3528_PULL_BITS_PER_PIN 2 2365#define RK3528_PULL_PINS_PER_REG 8 2366#define RK3528_PULL_GPIO0_OFFSET 0x200 2367#define RK3528_PULL_GPIO1_OFFSET 0x20210 2368#define RK3528_PULL_GPIO2_OFFSET 0x30220 2369#define RK3528_PULL_GPIO3_OFFSET 0x20230 2370#define RK3528_PULL_GPIO4_OFFSET 0x10240 2371 2372static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2373 int pin_num, struct regmap **regmap, 2374 int *reg, u8 *bit) 2375{ 2376 struct rockchip_pinctrl *info = bank->drvdata; 2377 2378 *regmap = info->regmap_base; 2379 2380 if (bank->bank_num == 0) 2381 *reg = RK3528_PULL_GPIO0_OFFSET; 2382 else if (bank->bank_num == 1) 2383 *reg = RK3528_PULL_GPIO1_OFFSET; 2384 else if (bank->bank_num == 2) 2385 *reg = RK3528_PULL_GPIO2_OFFSET; 2386 else if (bank->bank_num == 3) 2387 *reg = RK3528_PULL_GPIO3_OFFSET; 2388 else if (bank->bank_num == 4) 2389 *reg = RK3528_PULL_GPIO4_OFFSET; 2390 else 2391 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2392 2393 *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4); 2394 *bit = pin_num % RK3528_PULL_PINS_PER_REG; 2395 *bit *= RK3528_PULL_BITS_PER_PIN; 2396 2397 return 0; 2398} 2399 2400#define RK3528_SMT_BITS_PER_PIN 1 2401#define RK3528_SMT_PINS_PER_REG 8 2402#define RK3528_SMT_GPIO0_OFFSET 0x400 2403#define RK3528_SMT_GPIO1_OFFSET 0x20410 2404#define RK3528_SMT_GPIO2_OFFSET 0x30420 2405#define RK3528_SMT_GPIO3_OFFSET 0x20430 2406#define RK3528_SMT_GPIO4_OFFSET 0x10440 2407 2408static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2409 int pin_num, 2410 struct regmap **regmap, 2411 int *reg, u8 *bit) 2412{ 2413 struct rockchip_pinctrl *info = bank->drvdata; 2414 2415 *regmap = info->regmap_base; 2416 2417 if (bank->bank_num == 0) 2418 *reg = RK3528_SMT_GPIO0_OFFSET; 2419 else if (bank->bank_num == 1) 2420 *reg = RK3528_SMT_GPIO1_OFFSET; 2421 else if (bank->bank_num == 2) 2422 *reg = RK3528_SMT_GPIO2_OFFSET; 2423 else if (bank->bank_num == 3) 2424 *reg = RK3528_SMT_GPIO3_OFFSET; 2425 else if (bank->bank_num == 4) 2426 *reg = RK3528_SMT_GPIO4_OFFSET; 2427 else 2428 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2429 2430 *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4); 2431 *bit = pin_num % RK3528_SMT_PINS_PER_REG; 2432 *bit *= RK3528_SMT_BITS_PER_PIN; 2433 2434 return 0; 2435} 2436 2437#define RK3562_DRV_BITS_PER_PIN 8 2438#define RK3562_DRV_PINS_PER_REG 2 2439#define RK3562_DRV_GPIO0_OFFSET 0x20070 2440#define RK3562_DRV_GPIO1_OFFSET 0x200 2441#define RK3562_DRV_GPIO2_OFFSET 0x240 2442#define RK3562_DRV_GPIO3_OFFSET 0x10280 2443#define RK3562_DRV_GPIO4_OFFSET 0x102C0 2444 2445static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2446 int pin_num, struct regmap **regmap, 2447 int *reg, u8 *bit) 2448{ 2449 struct rockchip_pinctrl *info = bank->drvdata; 2450 2451 *regmap = info->regmap_base; 2452 switch (bank->bank_num) { 2453 case 0: 2454 *reg = RK3562_DRV_GPIO0_OFFSET; 2455 break; 2456 2457 case 1: 2458 *reg = RK3562_DRV_GPIO1_OFFSET; 2459 break; 2460 2461 case 2: 2462 *reg = RK3562_DRV_GPIO2_OFFSET; 2463 break; 2464 2465 case 3: 2466 *reg = RK3562_DRV_GPIO3_OFFSET; 2467 break; 2468 2469 case 4: 2470 *reg = RK3562_DRV_GPIO4_OFFSET; 2471 break; 2472 2473 default: 2474 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2475 break; 2476 } 2477 2478 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4); 2479 *bit = pin_num % RK3562_DRV_PINS_PER_REG; 2480 *bit *= RK3562_DRV_BITS_PER_PIN; 2481 2482 return 0; 2483} 2484 2485#define RK3562_PULL_BITS_PER_PIN 2 2486#define RK3562_PULL_PINS_PER_REG 8 2487#define RK3562_PULL_GPIO0_OFFSET 0x20020 2488#define RK3562_PULL_GPIO1_OFFSET 0x80 2489#define RK3562_PULL_GPIO2_OFFSET 0x90 2490#define RK3562_PULL_GPIO3_OFFSET 0x100A0 2491#define RK3562_PULL_GPIO4_OFFSET 0x100B0 2492 2493static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2494 int pin_num, struct regmap **regmap, 2495 int *reg, u8 *bit) 2496{ 2497 struct rockchip_pinctrl *info = bank->drvdata; 2498 2499 *regmap = info->regmap_base; 2500 switch (bank->bank_num) { 2501 case 0: 2502 *reg = RK3562_PULL_GPIO0_OFFSET; 2503 break; 2504 2505 case 1: 2506 *reg = RK3562_PULL_GPIO1_OFFSET; 2507 break; 2508 2509 case 2: 2510 *reg = RK3562_PULL_GPIO2_OFFSET; 2511 break; 2512 2513 case 3: 2514 *reg = RK3562_PULL_GPIO3_OFFSET; 2515 break; 2516 2517 case 4: 2518 *reg = RK3562_PULL_GPIO4_OFFSET; 2519 break; 2520 2521 default: 2522 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2523 break; 2524 } 2525 2526 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4); 2527 *bit = pin_num % RK3562_PULL_PINS_PER_REG; 2528 *bit *= RK3562_PULL_BITS_PER_PIN; 2529 2530 return 0; 2531} 2532 2533#define RK3562_SMT_BITS_PER_PIN 2 2534#define RK3562_SMT_PINS_PER_REG 8 2535#define RK3562_SMT_GPIO0_OFFSET 0x20030 2536#define RK3562_SMT_GPIO1_OFFSET 0xC0 2537#define RK3562_SMT_GPIO2_OFFSET 0xD0 2538#define RK3562_SMT_GPIO3_OFFSET 0x100E0 2539#define RK3562_SMT_GPIO4_OFFSET 0x100F0 2540 2541static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2542 int pin_num, 2543 struct regmap **regmap, 2544 int *reg, u8 *bit) 2545{ 2546 struct rockchip_pinctrl *info = bank->drvdata; 2547 2548 *regmap = info->regmap_base; 2549 switch (bank->bank_num) { 2550 case 0: 2551 *reg = RK3562_SMT_GPIO0_OFFSET; 2552 break; 2553 2554 case 1: 2555 *reg = RK3562_SMT_GPIO1_OFFSET; 2556 break; 2557 2558 case 2: 2559 *reg = RK3562_SMT_GPIO2_OFFSET; 2560 break; 2561 2562 case 3: 2563 *reg = RK3562_SMT_GPIO3_OFFSET; 2564 break; 2565 2566 case 4: 2567 *reg = RK3562_SMT_GPIO4_OFFSET; 2568 break; 2569 2570 default: 2571 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2572 break; 2573 } 2574 2575 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4); 2576 *bit = pin_num % RK3562_SMT_PINS_PER_REG; 2577 *bit *= RK3562_SMT_BITS_PER_PIN; 2578 2579 return 0; 2580} 2581 2582#define RK3568_PULL_PMU_OFFSET 0x20 2583#define RK3568_PULL_GRF_OFFSET 0x80 2584#define RK3568_PULL_BITS_PER_PIN 2 2585#define RK3568_PULL_PINS_PER_REG 8 2586#define RK3568_PULL_BANK_STRIDE 0x10 2587 2588static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2589 int pin_num, struct regmap **regmap, 2590 int *reg, u8 *bit) 2591{ 2592 struct rockchip_pinctrl *info = bank->drvdata; 2593 2594 if (bank->bank_num == 0) { 2595 *regmap = info->regmap_pmu; 2596 *reg = RK3568_PULL_PMU_OFFSET; 2597 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 2598 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 2599 2600 *bit = pin_num % RK3568_PULL_PINS_PER_REG; 2601 *bit *= RK3568_PULL_BITS_PER_PIN; 2602 } else { 2603 *regmap = info->regmap_base; 2604 *reg = RK3568_PULL_GRF_OFFSET; 2605 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 2606 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 2607 2608 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 2609 *bit *= RK3568_PULL_BITS_PER_PIN; 2610 } 2611 2612 return 0; 2613} 2614 2615#define RK3568_DRV_PMU_OFFSET 0x70 2616#define RK3568_DRV_GRF_OFFSET 0x200 2617#define RK3568_DRV_BITS_PER_PIN 8 2618#define RK3568_DRV_PINS_PER_REG 2 2619#define RK3568_DRV_BANK_STRIDE 0x40 2620 2621static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2622 int pin_num, struct regmap **regmap, 2623 int *reg, u8 *bit) 2624{ 2625 struct rockchip_pinctrl *info = bank->drvdata; 2626 2627 /* The first 32 pins of the first bank are located in PMU */ 2628 if (bank->bank_num == 0) { 2629 *regmap = info->regmap_pmu; 2630 *reg = RK3568_DRV_PMU_OFFSET; 2631 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2632 2633 *bit = pin_num % RK3568_DRV_PINS_PER_REG; 2634 *bit *= RK3568_DRV_BITS_PER_PIN; 2635 } else { 2636 *regmap = info->regmap_base; 2637 *reg = RK3568_DRV_GRF_OFFSET; 2638 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 2639 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 2640 2641 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 2642 *bit *= RK3568_DRV_BITS_PER_PIN; 2643 } 2644 2645 return 0; 2646} 2647 2648#define RK3576_DRV_BITS_PER_PIN 4 2649#define RK3576_DRV_PINS_PER_REG 4 2650#define RK3576_DRV_GPIO0_AL_OFFSET 0x10 2651#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014 2652#define RK3576_DRV_GPIO1_OFFSET 0x6020 2653#define RK3576_DRV_GPIO2_OFFSET 0x6040 2654#define RK3576_DRV_GPIO3_OFFSET 0x6060 2655#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080 2656#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090 2657#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098 2658 2659static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2660 int pin_num, struct regmap **regmap, 2661 int *reg, u8 *bit) 2662{ 2663 struct rockchip_pinctrl *info = bank->drvdata; 2664 2665 *regmap = info->regmap_base; 2666 2667 if (bank->bank_num == 0 && pin_num < 12) 2668 *reg = RK3576_DRV_GPIO0_AL_OFFSET; 2669 else if (bank->bank_num == 0) 2670 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc; 2671 else if (bank->bank_num == 1) 2672 *reg = RK3576_DRV_GPIO1_OFFSET; 2673 else if (bank->bank_num == 2) 2674 *reg = RK3576_DRV_GPIO2_OFFSET; 2675 else if (bank->bank_num == 3) 2676 *reg = RK3576_DRV_GPIO3_OFFSET; 2677 else if (bank->bank_num == 4 && pin_num < 16) 2678 *reg = RK3576_DRV_GPIO4_AL_OFFSET; 2679 else if (bank->bank_num == 4 && pin_num < 24) 2680 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10; 2681 else if (bank->bank_num == 4) 2682 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18; 2683 else 2684 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2685 2686 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4); 2687 *bit = pin_num % RK3576_DRV_PINS_PER_REG; 2688 *bit *= RK3576_DRV_BITS_PER_PIN; 2689 2690 return 0; 2691} 2692 2693#define RK3576_PULL_BITS_PER_PIN 2 2694#define RK3576_PULL_PINS_PER_REG 8 2695#define RK3576_PULL_GPIO0_AL_OFFSET 0x20 2696#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028 2697#define RK3576_PULL_GPIO1_OFFSET 0x6110 2698#define RK3576_PULL_GPIO2_OFFSET 0x6120 2699#define RK3576_PULL_GPIO3_OFFSET 0x6130 2700#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140 2701#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148 2702#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C 2703 2704static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2705 int pin_num, struct regmap **regmap, 2706 int *reg, u8 *bit) 2707{ 2708 struct rockchip_pinctrl *info = bank->drvdata; 2709 2710 *regmap = info->regmap_base; 2711 2712 if (bank->bank_num == 0 && pin_num < 12) 2713 *reg = RK3576_PULL_GPIO0_AL_OFFSET; 2714 else if (bank->bank_num == 0) 2715 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4; 2716 else if (bank->bank_num == 1) 2717 *reg = RK3576_PULL_GPIO1_OFFSET; 2718 else if (bank->bank_num == 2) 2719 *reg = RK3576_PULL_GPIO2_OFFSET; 2720 else if (bank->bank_num == 3) 2721 *reg = RK3576_PULL_GPIO3_OFFSET; 2722 else if (bank->bank_num == 4 && pin_num < 16) 2723 *reg = RK3576_PULL_GPIO4_AL_OFFSET; 2724 else if (bank->bank_num == 4 && pin_num < 24) 2725 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8; 2726 else if (bank->bank_num == 4) 2727 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc; 2728 else 2729 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2730 2731 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4); 2732 *bit = pin_num % RK3576_PULL_PINS_PER_REG; 2733 *bit *= RK3576_PULL_BITS_PER_PIN; 2734 2735 return 0; 2736} 2737 2738#define RK3576_SMT_BITS_PER_PIN 1 2739#define RK3576_SMT_PINS_PER_REG 8 2740#define RK3576_SMT_GPIO0_AL_OFFSET 0x30 2741#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040 2742#define RK3576_SMT_GPIO1_OFFSET 0x6210 2743#define RK3576_SMT_GPIO2_OFFSET 0x6220 2744#define RK3576_SMT_GPIO3_OFFSET 0x6230 2745#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240 2746#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248 2747#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C 2748 2749static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2750 int pin_num, 2751 struct regmap **regmap, 2752 int *reg, u8 *bit) 2753{ 2754 struct rockchip_pinctrl *info = bank->drvdata; 2755 2756 *regmap = info->regmap_base; 2757 2758 if (bank->bank_num == 0 && pin_num < 12) 2759 *reg = RK3576_SMT_GPIO0_AL_OFFSET; 2760 else if (bank->bank_num == 0) 2761 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4; 2762 else if (bank->bank_num == 1) 2763 *reg = RK3576_SMT_GPIO1_OFFSET; 2764 else if (bank->bank_num == 2) 2765 *reg = RK3576_SMT_GPIO2_OFFSET; 2766 else if (bank->bank_num == 3) 2767 *reg = RK3576_SMT_GPIO3_OFFSET; 2768 else if (bank->bank_num == 4 && pin_num < 16) 2769 *reg = RK3576_SMT_GPIO4_AL_OFFSET; 2770 else if (bank->bank_num == 4 && pin_num < 24) 2771 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8; 2772 else if (bank->bank_num == 4) 2773 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc; 2774 else 2775 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num); 2776 2777 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4); 2778 *bit = pin_num % RK3576_SMT_PINS_PER_REG; 2779 *bit *= RK3576_SMT_BITS_PER_PIN; 2780 2781 return 0; 2782} 2783 2784#define RK3588_PMU1_IOC_REG (0x0000) 2785#define RK3588_PMU2_IOC_REG (0x4000) 2786#define RK3588_BUS_IOC_REG (0x8000) 2787#define RK3588_VCCIO1_4_IOC_REG (0x9000) 2788#define RK3588_VCCIO3_5_IOC_REG (0xA000) 2789#define RK3588_VCCIO2_IOC_REG (0xB000) 2790#define RK3588_VCCIO6_IOC_REG (0xC000) 2791#define RK3588_EMMC_IOC_REG (0xD000) 2792 2793static const u32 rk3588_ds_regs[][2] = { 2794 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010}, 2795 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014}, 2796 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018}, 2797 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014}, 2798 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018}, 2799 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C}, 2800 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020}, 2801 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024}, 2802 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020}, 2803 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024}, 2804 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028}, 2805 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C}, 2806 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030}, 2807 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034}, 2808 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038}, 2809 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C}, 2810 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040}, 2811 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044}, 2812 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048}, 2813 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C}, 2814 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050}, 2815 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054}, 2816 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058}, 2817 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C}, 2818 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060}, 2819 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064}, 2820 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068}, 2821 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C}, 2822 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070}, 2823 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074}, 2824 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078}, 2825 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C}, 2826 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080}, 2827 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084}, 2828 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088}, 2829 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C}, 2830 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090}, 2831 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090}, 2832 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094}, 2833 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098}, 2834 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C}, 2835}; 2836 2837static const u32 rk3588_p_regs[][2] = { 2838 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020}, 2839 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024}, 2840 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028}, 2841 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C}, 2842 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030}, 2843 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110}, 2844 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114}, 2845 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118}, 2846 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C}, 2847 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120}, 2848 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120}, 2849 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124}, 2850 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128}, 2851 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C}, 2852 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130}, 2853 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134}, 2854 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138}, 2855 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C}, 2856 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140}, 2857 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144}, 2858 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148}, 2859 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148}, 2860 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C}, 2861}; 2862 2863static const u32 rk3588_smt_regs[][2] = { 2864 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030}, 2865 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034}, 2866 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040}, 2867 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044}, 2868 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048}, 2869 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210}, 2870 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214}, 2871 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218}, 2872 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C}, 2873 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220}, 2874 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220}, 2875 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224}, 2876 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228}, 2877 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C}, 2878 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230}, 2879 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234}, 2880 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238}, 2881 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C}, 2882 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240}, 2883 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244}, 2884 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248}, 2885 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248}, 2886 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C}, 2887}; 2888 2889#define RK3588_PULL_BITS_PER_PIN 2 2890#define RK3588_PULL_PINS_PER_REG 8 2891 2892static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2893 int pin_num, struct regmap **regmap, 2894 int *reg, u8 *bit) 2895{ 2896 struct rockchip_pinctrl *info = bank->drvdata; 2897 u8 bank_num = bank->bank_num; 2898 u32 pin = bank_num * 32 + pin_num; 2899 int i; 2900 2901 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) { 2902 if (pin >= rk3588_p_regs[i][0]) { 2903 *reg = rk3588_p_regs[i][1]; 2904 *regmap = info->regmap_base; 2905 *bit = pin_num % RK3588_PULL_PINS_PER_REG; 2906 *bit *= RK3588_PULL_BITS_PER_PIN; 2907 return 0; 2908 } 2909 } 2910 2911 return -EINVAL; 2912} 2913 2914#define RK3588_DRV_BITS_PER_PIN 4 2915#define RK3588_DRV_PINS_PER_REG 4 2916 2917static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2918 int pin_num, struct regmap **regmap, 2919 int *reg, u8 *bit) 2920{ 2921 struct rockchip_pinctrl *info = bank->drvdata; 2922 u8 bank_num = bank->bank_num; 2923 u32 pin = bank_num * 32 + pin_num; 2924 int i; 2925 2926 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) { 2927 if (pin >= rk3588_ds_regs[i][0]) { 2928 *reg = rk3588_ds_regs[i][1]; 2929 *regmap = info->regmap_base; 2930 *bit = pin_num % RK3588_DRV_PINS_PER_REG; 2931 *bit *= RK3588_DRV_BITS_PER_PIN; 2932 return 0; 2933 } 2934 } 2935 2936 return -EINVAL; 2937} 2938 2939#define RK3588_SMT_BITS_PER_PIN 1 2940#define RK3588_SMT_PINS_PER_REG 8 2941 2942static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2943 int pin_num, 2944 struct regmap **regmap, 2945 int *reg, u8 *bit) 2946{ 2947 struct rockchip_pinctrl *info = bank->drvdata; 2948 u8 bank_num = bank->bank_num; 2949 u32 pin = bank_num * 32 + pin_num; 2950 int i; 2951 2952 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) { 2953 if (pin >= rk3588_smt_regs[i][0]) { 2954 *reg = rk3588_smt_regs[i][1]; 2955 *regmap = info->regmap_base; 2956 *bit = pin_num % RK3588_SMT_PINS_PER_REG; 2957 *bit *= RK3588_SMT_BITS_PER_PIN; 2958 return 0; 2959 } 2960 } 2961 2962 return -EINVAL; 2963} 2964 2965static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2966 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2967 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2968 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2969 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2970 { 4, 7, 10, 13, 16, 19, 22, 26 } 2971}; 2972 2973static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2974 int pin_num) 2975{ 2976 struct rockchip_pinctrl *info = bank->drvdata; 2977 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2978 struct device *dev = info->dev; 2979 struct regmap *regmap; 2980 int reg, ret; 2981 u32 data, temp, rmask_bits; 2982 u8 bit; 2983 int drv_type = bank->drv[pin_num / 8].drv_type; 2984 2985 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2986 if (ret) 2987 return ret; 2988 2989 switch (drv_type) { 2990 case DRV_TYPE_IO_1V8_3V0_AUTO: 2991 case DRV_TYPE_IO_3V3_ONLY: 2992 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2993 switch (bit) { 2994 case 0 ... 12: 2995 /* regular case, nothing to do */ 2996 break; 2997 case 15: 2998 /* 2999 * drive-strength offset is special, as it is 3000 * spread over 2 registers 3001 */ 3002 ret = regmap_read(regmap, reg, &data); 3003 if (ret) 3004 return ret; 3005 3006 ret = regmap_read(regmap, reg + 0x4, &temp); 3007 if (ret) 3008 return ret; 3009 3010 /* 3011 * the bit data[15] contains bit 0 of the value 3012 * while temp[1:0] contains bits 2 and 1 3013 */ 3014 data >>= 15; 3015 temp &= 0x3; 3016 temp <<= 1; 3017 data |= temp; 3018 3019 return rockchip_perpin_drv_list[drv_type][data]; 3020 case 18 ... 21: 3021 /* setting fully enclosed in the second register */ 3022 reg += 4; 3023 bit -= 16; 3024 break; 3025 default: 3026 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 3027 bit, drv_type); 3028 return -EINVAL; 3029 } 3030 3031 break; 3032 case DRV_TYPE_IO_DEFAULT: 3033 case DRV_TYPE_IO_1V8_OR_3V0: 3034 case DRV_TYPE_IO_1V8_ONLY: 3035 rmask_bits = RK3288_DRV_BITS_PER_PIN; 3036 break; 3037 default: 3038 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 3039 return -EINVAL; 3040 } 3041 3042 ret = regmap_read(regmap, reg, &data); 3043 if (ret) 3044 return ret; 3045 3046 data >>= bit; 3047 data &= (1 << rmask_bits) - 1; 3048 3049 return rockchip_perpin_drv_list[drv_type][data]; 3050} 3051 3052static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 3053 int pin_num, int strength) 3054{ 3055 struct rockchip_pinctrl *info = bank->drvdata; 3056 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3057 struct device *dev = info->dev; 3058 struct regmap *regmap; 3059 int reg, ret, i; 3060 u32 data, rmask, rmask_bits, temp; 3061 u8 bit; 3062 int drv_type = bank->drv[pin_num / 8].drv_type; 3063 3064 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n", 3065 bank->bank_num, pin_num, strength); 3066 3067 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 3068 if (ret) 3069 return ret; 3070 if (ctrl->type == RK3588) { 3071 rmask_bits = RK3588_DRV_BITS_PER_PIN; 3072 ret = strength; 3073 goto config; 3074 } else if (ctrl->type == RK3506 || 3075 ctrl->type == RK3528 || 3076 ctrl->type == RK3562 || 3077 ctrl->type == RK3568) { 3078 rmask_bits = RK3568_DRV_BITS_PER_PIN; 3079 ret = (1 << (strength + 1)) - 1; 3080 goto config; 3081 } else if (ctrl->type == RK3576) { 3082 rmask_bits = RK3576_DRV_BITS_PER_PIN; 3083 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1)); 3084 goto config; 3085 } 3086 3087 if (ctrl->type == RV1126) { 3088 rmask_bits = RV1126_DRV_BITS_PER_PIN; 3089 ret = strength; 3090 goto config; 3091 } 3092 3093 ret = -EINVAL; 3094 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 3095 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 3096 ret = i; 3097 break; 3098 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 3099 ret = rockchip_perpin_drv_list[drv_type][i]; 3100 break; 3101 } 3102 } 3103 3104 if (ret < 0) { 3105 dev_err(dev, "unsupported driver strength %d\n", strength); 3106 return ret; 3107 } 3108 3109 switch (drv_type) { 3110 case DRV_TYPE_IO_1V8_3V0_AUTO: 3111 case DRV_TYPE_IO_3V3_ONLY: 3112 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 3113 switch (bit) { 3114 case 0 ... 12: 3115 /* regular case, nothing to do */ 3116 break; 3117 case 15: 3118 /* 3119 * drive-strength offset is special, as it is spread 3120 * over 2 registers, the bit data[15] contains bit 0 3121 * of the value while temp[1:0] contains bits 2 and 1 3122 */ 3123 data = (ret & 0x1) << 15; 3124 temp = (ret >> 0x1) & 0x3; 3125 3126 rmask = BIT(15) | BIT(31); 3127 data |= BIT(31); 3128 ret = regmap_update_bits(regmap, reg, rmask, data); 3129 if (ret) 3130 return ret; 3131 3132 rmask = 0x3 | (0x3 << 16); 3133 temp |= (0x3 << 16); 3134 reg += 0x4; 3135 ret = regmap_update_bits(regmap, reg, rmask, temp); 3136 3137 return ret; 3138 case 18 ... 21: 3139 /* setting fully enclosed in the second register */ 3140 reg += 4; 3141 bit -= 16; 3142 break; 3143 default: 3144 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n", 3145 bit, drv_type); 3146 return -EINVAL; 3147 } 3148 break; 3149 case DRV_TYPE_IO_DEFAULT: 3150 case DRV_TYPE_IO_1V8_OR_3V0: 3151 case DRV_TYPE_IO_1V8_ONLY: 3152 rmask_bits = RK3288_DRV_BITS_PER_PIN; 3153 break; 3154 case DRV_TYPE_IO_LEVEL_2_BIT: 3155 ret = regmap_read(regmap, reg, &data); 3156 if (ret) 3157 return ret; 3158 data >>= bit; 3159 3160 return data & 0x3; 3161 case DRV_TYPE_IO_LEVEL_8_BIT: 3162 ret = regmap_read(regmap, reg, &data); 3163 if (ret) 3164 return ret; 3165 data >>= bit; 3166 data &= (1 << 8) - 1; 3167 3168 ret = hweight8(data); 3169 if (ret > 0) 3170 return ret - 1; 3171 else 3172 return -EINVAL; 3173 default: 3174 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type); 3175 return -EINVAL; 3176 } 3177 3178config: 3179 if (ctrl->type == RK3506) { 3180 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { 3181 rmask_bits = 2; 3182 ret = strength; 3183 } 3184 } 3185 /* enable the write to the equivalent lower bits */ 3186 data = ((1 << rmask_bits) - 1) << (bit + 16); 3187 rmask = data | (data >> 16); 3188 data |= (ret << bit); 3189 3190 ret = regmap_update_bits(regmap, reg, rmask, data); 3191 3192 return ret; 3193} 3194 3195static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 3196 { 3197 PIN_CONFIG_BIAS_DISABLE, 3198 PIN_CONFIG_BIAS_PULL_UP, 3199 PIN_CONFIG_BIAS_PULL_DOWN, 3200 PIN_CONFIG_BIAS_BUS_HOLD 3201 }, 3202 { 3203 PIN_CONFIG_BIAS_DISABLE, 3204 PIN_CONFIG_BIAS_PULL_DOWN, 3205 PIN_CONFIG_BIAS_DISABLE, 3206 PIN_CONFIG_BIAS_PULL_UP 3207 }, 3208}; 3209 3210static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 3211{ 3212 struct rockchip_pinctrl *info = bank->drvdata; 3213 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3214 struct device *dev = info->dev; 3215 struct regmap *regmap; 3216 int reg, ret, pull_type; 3217 u8 bit; 3218 u32 data; 3219 3220 /* rk3066b does support any pulls */ 3221 if (ctrl->type == RK3066B) 3222 return PIN_CONFIG_BIAS_DISABLE; 3223 3224 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 3225 if (ret) 3226 return ret; 3227 3228 ret = regmap_read(regmap, reg, &data); 3229 if (ret) 3230 return ret; 3231 3232 switch (ctrl->type) { 3233 case RK2928: 3234 case RK3128: 3235 return !(data & BIT(bit)) 3236 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 3237 : PIN_CONFIG_BIAS_DISABLE; 3238 case PX30: 3239 case RV1108: 3240 case RK3188: 3241 case RK3288: 3242 case RK3308: 3243 case RK3328: 3244 case RK3368: 3245 case RK3399: 3246 case RK3528: 3247 case RK3562: 3248 case RK3568: 3249 case RK3576: 3250 case RK3588: 3251 pull_type = bank->pull_type[pin_num / 8]; 3252 data >>= bit; 3253 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 3254 /* 3255 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 3256 * where that pull up value becomes 3. 3257 */ 3258 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 3259 if (data == 3) 3260 data = 1; 3261 } 3262 3263 return rockchip_pull_list[pull_type][data]; 3264 default: 3265 dev_err(dev, "unsupported pinctrl type\n"); 3266 return -EINVAL; 3267 }; 3268} 3269 3270static int rockchip_set_pull(struct rockchip_pin_bank *bank, 3271 int pin_num, int pull) 3272{ 3273 struct rockchip_pinctrl *info = bank->drvdata; 3274 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3275 struct device *dev = info->dev; 3276 struct regmap *regmap; 3277 int reg, ret, i, pull_type; 3278 u8 bit; 3279 u32 data, rmask; 3280 3281 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull); 3282 3283 /* rk3066b does support any pulls */ 3284 if (ctrl->type == RK3066B) 3285 return pull ? -EINVAL : 0; 3286 3287 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 3288 if (ret) 3289 return ret; 3290 3291 switch (ctrl->type) { 3292 case RK2928: 3293 case RK3128: 3294 data = BIT(bit + 16); 3295 if (pull == PIN_CONFIG_BIAS_DISABLE) 3296 data |= BIT(bit); 3297 ret = regmap_write(regmap, reg, data); 3298 break; 3299 case PX30: 3300 case RV1108: 3301 case RV1126: 3302 case RK3188: 3303 case RK3288: 3304 case RK3308: 3305 case RK3328: 3306 case RK3368: 3307 case RK3399: 3308 case RK3506: 3309 case RK3528: 3310 case RK3562: 3311 case RK3568: 3312 case RK3576: 3313 case RK3588: 3314 pull_type = bank->pull_type[pin_num / 8]; 3315 ret = -EINVAL; 3316 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 3317 i++) { 3318 if (rockchip_pull_list[pull_type][i] == pull) { 3319 ret = i; 3320 break; 3321 } 3322 } 3323 /* 3324 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 3325 * where that pull up value becomes 3. 3326 */ 3327 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 3328 if (ret == 1) 3329 ret = 3; 3330 } 3331 3332 if (ret < 0) { 3333 dev_err(dev, "unsupported pull setting %d\n", pull); 3334 return ret; 3335 } 3336 3337 /* enable the write to the equivalent lower bits */ 3338 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 3339 rmask = data | (data >> 16); 3340 data |= (ret << bit); 3341 3342 ret = regmap_update_bits(regmap, reg, rmask, data); 3343 break; 3344 default: 3345 dev_err(dev, "unsupported pinctrl type\n"); 3346 return -EINVAL; 3347 } 3348 3349 return ret; 3350} 3351 3352#define RK3328_SCHMITT_BITS_PER_PIN 1 3353#define RK3328_SCHMITT_PINS_PER_REG 16 3354#define RK3328_SCHMITT_BANK_STRIDE 8 3355#define RK3328_SCHMITT_GRF_OFFSET 0x380 3356 3357static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 3358 int pin_num, 3359 struct regmap **regmap, 3360 int *reg, u8 *bit) 3361{ 3362 struct rockchip_pinctrl *info = bank->drvdata; 3363 3364 *regmap = info->regmap_base; 3365 *reg = RK3328_SCHMITT_GRF_OFFSET; 3366 3367 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 3368 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 3369 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 3370 3371 return 0; 3372} 3373 3374#define RK3568_SCHMITT_BITS_PER_PIN 2 3375#define RK3568_SCHMITT_PINS_PER_REG 8 3376#define RK3568_SCHMITT_BANK_STRIDE 0x10 3377#define RK3568_SCHMITT_GRF_OFFSET 0xc0 3378#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 3379 3380static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 3381 int pin_num, 3382 struct regmap **regmap, 3383 int *reg, u8 *bit) 3384{ 3385 struct rockchip_pinctrl *info = bank->drvdata; 3386 3387 if (bank->bank_num == 0) { 3388 *regmap = info->regmap_pmu; 3389 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 3390 } else { 3391 *regmap = info->regmap_base; 3392 *reg = RK3568_SCHMITT_GRF_OFFSET; 3393 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 3394 } 3395 3396 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 3397 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 3398 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 3399 3400 return 0; 3401} 3402 3403static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 3404{ 3405 struct rockchip_pinctrl *info = bank->drvdata; 3406 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3407 struct regmap *regmap; 3408 int reg, ret; 3409 u8 bit; 3410 u32 data; 3411 3412 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 3413 if (ret) 3414 return ret; 3415 3416 ret = regmap_read(regmap, reg, &data); 3417 if (ret) 3418 return ret; 3419 3420 data >>= bit; 3421 switch (ctrl->type) { 3422 case RK3562: 3423 case RK3568: 3424 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1); 3425 default: 3426 break; 3427 } 3428 3429 if (ctrl->type == RK3506) 3430 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) 3431 return data & 0x3; 3432 3433 return data & 0x1; 3434} 3435 3436static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 3437 int pin_num, int enable) 3438{ 3439 struct rockchip_pinctrl *info = bank->drvdata; 3440 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3441 struct device *dev = info->dev; 3442 struct regmap *regmap; 3443 int reg, ret; 3444 u8 bit; 3445 u32 data, rmask; 3446 3447 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n", 3448 bank->bank_num, pin_num, enable); 3449 3450 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 3451 if (ret) 3452 return ret; 3453 3454 /* enable the write to the equivalent lower bits */ 3455 switch (ctrl->type) { 3456 case RK3562: 3457 case RK3568: 3458 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 3459 rmask = data | (data >> 16); 3460 data |= ((enable ? 0x2 : 0x1) << bit); 3461 break; 3462 default: 3463 data = BIT(bit + 16) | (enable << bit); 3464 rmask = BIT(bit + 16) | BIT(bit); 3465 break; 3466 } 3467 3468 if (ctrl->type == RK3506) { 3469 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) { 3470 data = 0x3 << (bit + 16); 3471 rmask = data | (data >> 16); 3472 data |= ((enable ? 0x3 : 0) << bit); 3473 } 3474 } 3475 3476 return regmap_update_bits(regmap, reg, rmask, data); 3477} 3478 3479/* 3480 * Pinmux_ops handling 3481 */ 3482 3483static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 3484{ 3485 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3486 3487 return info->nfunctions; 3488} 3489 3490static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 3491 unsigned selector) 3492{ 3493 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3494 3495 return info->functions[selector].name; 3496} 3497 3498static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 3499 unsigned selector, const char * const **groups, 3500 unsigned * const num_groups) 3501{ 3502 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3503 3504 *groups = info->functions[selector].groups; 3505 *num_groups = info->functions[selector].ngroups; 3506 3507 return 0; 3508} 3509 3510static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 3511 unsigned group) 3512{ 3513 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3514 const unsigned int *pins = info->groups[group].pins; 3515 const struct rockchip_pin_config *data = info->groups[group].data; 3516 struct device *dev = info->dev; 3517 struct rockchip_pin_bank *bank; 3518 int cnt, ret = 0; 3519 3520 dev_dbg(dev, "enable function %s group %s\n", 3521 info->functions[selector].name, info->groups[group].name); 3522 3523 /* 3524 * for each pin in the pin group selected, program the corresponding 3525 * pin function number in the config register. 3526 */ 3527 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 3528 bank = pin_to_bank(info, pins[cnt]); 3529 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 3530 data[cnt].func); 3531 if (ret) 3532 break; 3533 } 3534 3535 if (ret) { 3536 /* revert the already done pin settings */ 3537 for (cnt--; cnt >= 0; cnt--) { 3538 bank = pin_to_bank(info, pins[cnt]); 3539 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 3540 } 3541 3542 return ret; 3543 } 3544 3545 return 0; 3546} 3547 3548static int rockchip_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, 3549 struct pinctrl_gpio_range *range, 3550 unsigned int offset) 3551{ 3552 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3553 struct rockchip_pin_bank *bank; 3554 3555 bank = pin_to_bank(info, offset); 3556 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO); 3557} 3558 3559static const struct pinmux_ops rockchip_pmx_ops = { 3560 .get_functions_count = rockchip_pmx_get_funcs_count, 3561 .get_function_name = rockchip_pmx_get_func_name, 3562 .get_function_groups = rockchip_pmx_get_groups, 3563 .set_mux = rockchip_pmx_set, 3564 .gpio_request_enable = rockchip_pmx_gpio_request_enable, 3565}; 3566 3567/* 3568 * Pinconf_ops handling 3569 */ 3570 3571static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 3572 enum pin_config_param pull) 3573{ 3574 switch (ctrl->type) { 3575 case RK2928: 3576 case RK3128: 3577 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 3578 pull == PIN_CONFIG_BIAS_DISABLE); 3579 case RK3066B: 3580 return pull ? false : true; 3581 case PX30: 3582 case RV1108: 3583 case RV1126: 3584 case RK3188: 3585 case RK3288: 3586 case RK3308: 3587 case RK3328: 3588 case RK3368: 3589 case RK3399: 3590 case RK3506: 3591 case RK3528: 3592 case RK3562: 3593 case RK3568: 3594 case RK3576: 3595 case RK3588: 3596 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 3597 } 3598 3599 return false; 3600} 3601 3602static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank, 3603 unsigned int pin, u32 param, u32 arg) 3604{ 3605 struct rockchip_pin_deferred *cfg; 3606 3607 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); 3608 if (!cfg) 3609 return -ENOMEM; 3610 3611 cfg->pin = pin; 3612 cfg->param = param; 3613 cfg->arg = arg; 3614 3615 list_add_tail(&cfg->head, &bank->deferred_pins); 3616 3617 return 0; 3618} 3619 3620/* set the pin config settings for a specified pin */ 3621static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 3622 unsigned long *configs, unsigned num_configs) 3623{ 3624 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3625 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 3626 struct gpio_chip *gpio = &bank->gpio_chip; 3627 enum pin_config_param param; 3628 u32 arg; 3629 int i; 3630 int rc; 3631 3632 for (i = 0; i < num_configs; i++) { 3633 param = pinconf_to_config_param(configs[i]); 3634 arg = pinconf_to_config_argument(configs[i]); 3635 3636 if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) { 3637 /* 3638 * Check for gpio driver not being probed yet. 3639 * The lock makes sure that either gpio-probe has completed 3640 * or the gpio driver hasn't probed yet. 3641 */ 3642 mutex_lock(&bank->deferred_lock); 3643 if (!gpio || !gpio->direction_output) { 3644 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param, 3645 arg); 3646 mutex_unlock(&bank->deferred_lock); 3647 if (rc) 3648 return rc; 3649 3650 break; 3651 } 3652 mutex_unlock(&bank->deferred_lock); 3653 } 3654 3655 switch (param) { 3656 case PIN_CONFIG_BIAS_DISABLE: 3657 rc = rockchip_set_pull(bank, pin - bank->pin_base, 3658 param); 3659 if (rc) 3660 return rc; 3661 break; 3662 case PIN_CONFIG_BIAS_PULL_UP: 3663 case PIN_CONFIG_BIAS_PULL_DOWN: 3664 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 3665 case PIN_CONFIG_BIAS_BUS_HOLD: 3666 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 3667 return -ENOTSUPP; 3668 3669 if (!arg) 3670 return -EINVAL; 3671 3672 rc = rockchip_set_pull(bank, pin - bank->pin_base, 3673 param); 3674 if (rc) 3675 return rc; 3676 break; 3677 case PIN_CONFIG_LEVEL: 3678 rc = rockchip_set_mux(bank, pin - bank->pin_base, 3679 RK_FUNC_GPIO); 3680 if (rc != RK_FUNC_GPIO) 3681 return -EINVAL; 3682 3683 rc = gpio->direction_output(gpio, pin - bank->pin_base, 3684 arg); 3685 if (rc) 3686 return rc; 3687 break; 3688 case PIN_CONFIG_INPUT_ENABLE: 3689 rc = rockchip_set_mux(bank, pin - bank->pin_base, 3690 RK_FUNC_GPIO); 3691 if (rc != RK_FUNC_GPIO) 3692 return -EINVAL; 3693 3694 rc = gpio->direction_input(gpio, pin - bank->pin_base); 3695 if (rc) 3696 return rc; 3697 break; 3698 case PIN_CONFIG_DRIVE_STRENGTH: 3699 /* rk3288 is the first with per-pin drive-strength */ 3700 if (!info->ctrl->drv_calc_reg) 3701 return -ENOTSUPP; 3702 3703 rc = rockchip_set_drive_perpin(bank, 3704 pin - bank->pin_base, arg); 3705 if (rc < 0) 3706 return rc; 3707 break; 3708 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3709 if (!info->ctrl->schmitt_calc_reg) 3710 return -ENOTSUPP; 3711 3712 rc = rockchip_set_schmitt(bank, 3713 pin - bank->pin_base, arg); 3714 if (rc < 0) 3715 return rc; 3716 break; 3717 default: 3718 return -ENOTSUPP; 3719 break; 3720 } 3721 } /* for each config */ 3722 3723 return 0; 3724} 3725 3726/* get the pin config settings for a specified pin */ 3727static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 3728 unsigned long *config) 3729{ 3730 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 3731 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 3732 struct gpio_chip *gpio = &bank->gpio_chip; 3733 enum pin_config_param param = pinconf_to_config_param(*config); 3734 u16 arg; 3735 int rc; 3736 3737 switch (param) { 3738 case PIN_CONFIG_BIAS_DISABLE: 3739 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 3740 return -EINVAL; 3741 3742 arg = 0; 3743 break; 3744 case PIN_CONFIG_BIAS_PULL_UP: 3745 case PIN_CONFIG_BIAS_PULL_DOWN: 3746 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 3747 case PIN_CONFIG_BIAS_BUS_HOLD: 3748 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 3749 return -ENOTSUPP; 3750 3751 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 3752 return -EINVAL; 3753 3754 arg = 1; 3755 break; 3756 case PIN_CONFIG_LEVEL: 3757 rc = rockchip_get_mux(bank, pin - bank->pin_base); 3758 if (rc != RK_FUNC_GPIO) 3759 return -EINVAL; 3760 3761 if (!gpio || !gpio->get) { 3762 arg = 0; 3763 break; 3764 } 3765 3766 rc = gpio->get(gpio, pin - bank->pin_base); 3767 if (rc < 0) 3768 return rc; 3769 3770 arg = rc ? 1 : 0; 3771 break; 3772 case PIN_CONFIG_DRIVE_STRENGTH: 3773 /* rk3288 is the first with per-pin drive-strength */ 3774 if (!info->ctrl->drv_calc_reg) 3775 return -ENOTSUPP; 3776 3777 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 3778 if (rc < 0) 3779 return rc; 3780 3781 arg = rc; 3782 break; 3783 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 3784 if (!info->ctrl->schmitt_calc_reg) 3785 return -ENOTSUPP; 3786 3787 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 3788 if (rc < 0) 3789 return rc; 3790 3791 arg = rc; 3792 break; 3793 default: 3794 return -ENOTSUPP; 3795 break; 3796 } 3797 3798 *config = pinconf_to_config_packed(param, arg); 3799 3800 return 0; 3801} 3802 3803static const struct pinconf_ops rockchip_pinconf_ops = { 3804 .pin_config_get = rockchip_pinconf_get, 3805 .pin_config_set = rockchip_pinconf_set, 3806 .is_generic = true, 3807}; 3808 3809static const struct of_device_id rockchip_bank_match[] = { 3810 { .compatible = "rockchip,gpio-bank" }, 3811 { .compatible = "rockchip,rk3188-gpio-bank0" }, 3812 {}, 3813}; 3814 3815static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 3816 struct device_node *np) 3817{ 3818 struct device_node *child; 3819 3820 for_each_child_of_node(np, child) { 3821 if (of_match_node(rockchip_bank_match, child)) 3822 continue; 3823 3824 info->nfunctions++; 3825 info->ngroups += of_get_child_count(child); 3826 } 3827} 3828 3829static int rockchip_pinctrl_parse_groups(struct device_node *np, 3830 struct rockchip_pin_group *grp, 3831 struct rockchip_pinctrl *info, 3832 u32 index) 3833{ 3834 struct device *dev = info->dev; 3835 struct rockchip_pin_bank *bank; 3836 int size; 3837 const __be32 *list; 3838 int num; 3839 int i, j; 3840 int ret; 3841 3842 dev_dbg(dev, "group(%d): %pOFn\n", index, np); 3843 3844 /* Initialise group */ 3845 grp->name = np->name; 3846 3847 /* 3848 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 3849 * do sanity check and calculate pins number 3850 */ 3851 list = of_get_property(np, "rockchip,pins", &size); 3852 /* we do not check return since it's safe node passed down */ 3853 size /= sizeof(*list); 3854 if (!size || size % 4) 3855 return dev_err_probe(dev, -EINVAL, 3856 "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n", 3857 np, size); 3858 3859 grp->npins = size / 4; 3860 3861 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL); 3862 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL); 3863 if (!grp->pins || !grp->data) 3864 return -ENOMEM; 3865 3866 for (i = 0, j = 0; i < size; i += 4, j++) { 3867 const __be32 *phandle; 3868 struct device_node *np_config; 3869 3870 num = be32_to_cpu(*list++); 3871 bank = bank_num_to_bank(info, num); 3872 if (IS_ERR(bank)) 3873 return PTR_ERR(bank); 3874 3875 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 3876 grp->data[j].func = be32_to_cpu(*list++); 3877 3878 phandle = list++; 3879 if (!phandle) 3880 return -EINVAL; 3881 3882 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 3883 ret = pinconf_generic_parse_dt_config(np_config, NULL, 3884 &grp->data[j].configs, &grp->data[j].nconfigs); 3885 of_node_put(np_config); 3886 if (ret) 3887 return ret; 3888 } 3889 3890 return 0; 3891} 3892 3893static int rockchip_pinctrl_parse_functions(struct device_node *np, 3894 struct rockchip_pinctrl *info, 3895 u32 index) 3896{ 3897 struct device *dev = info->dev; 3898 struct rockchip_pmx_func *func; 3899 struct rockchip_pin_group *grp; 3900 int ret; 3901 static u32 grp_index; 3902 u32 i = 0; 3903 3904 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np); 3905 3906 func = &info->functions[index]; 3907 3908 /* Initialise function */ 3909 func->name = np->name; 3910 func->ngroups = of_get_child_count(np); 3911 if (func->ngroups <= 0) 3912 return 0; 3913 3914 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL); 3915 if (!func->groups) 3916 return -ENOMEM; 3917 3918 for_each_child_of_node_scoped(np, child) { 3919 func->groups[i] = child->name; 3920 grp = &info->groups[grp_index++]; 3921 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 3922 if (ret) 3923 return ret; 3924 } 3925 3926 return 0; 3927} 3928 3929static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 3930 struct rockchip_pinctrl *info) 3931{ 3932 struct device *dev = &pdev->dev; 3933 struct device_node *np = dev->of_node; 3934 int ret; 3935 int i; 3936 3937 rockchip_pinctrl_child_count(info, np); 3938 3939 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); 3940 dev_dbg(dev, "ngroups = %d\n", info->ngroups); 3941 3942 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL); 3943 if (!info->functions) 3944 return -ENOMEM; 3945 3946 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL); 3947 if (!info->groups) 3948 return -ENOMEM; 3949 3950 i = 0; 3951 3952 for_each_child_of_node_scoped(np, child) { 3953 if (of_match_node(rockchip_bank_match, child)) 3954 continue; 3955 3956 ret = rockchip_pinctrl_parse_functions(child, info, i++); 3957 if (ret) { 3958 dev_err(dev, "failed to parse function\n"); 3959 return ret; 3960 } 3961 } 3962 3963 return 0; 3964} 3965 3966static int rockchip_pinctrl_register(struct platform_device *pdev, 3967 struct rockchip_pinctrl *info) 3968{ 3969 struct pinctrl_desc *ctrldesc = &info->pctl; 3970 struct pinctrl_pin_desc *pindesc, *pdesc; 3971 struct rockchip_pin_bank *pin_bank; 3972 struct device *dev = &pdev->dev; 3973 char **pin_names; 3974 int pin, bank, ret; 3975 int k; 3976 3977 ctrldesc->name = "rockchip-pinctrl"; 3978 ctrldesc->owner = THIS_MODULE; 3979 ctrldesc->pctlops = &rockchip_pctrl_ops; 3980 ctrldesc->pmxops = &rockchip_pmx_ops; 3981 ctrldesc->confops = &rockchip_pinconf_ops; 3982 3983 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL); 3984 if (!pindesc) 3985 return -ENOMEM; 3986 3987 ctrldesc->pins = pindesc; 3988 ctrldesc->npins = info->ctrl->nr_pins; 3989 3990 pdesc = pindesc; 3991 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) { 3992 pin_bank = &info->ctrl->pin_banks[bank]; 3993 3994 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins); 3995 if (IS_ERR(pin_names)) 3996 return PTR_ERR(pin_names); 3997 3998 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3999 pdesc->number = k; 4000 pdesc->name = pin_names[pin]; 4001 pdesc++; 4002 } 4003 4004 INIT_LIST_HEAD(&pin_bank->deferred_pins); 4005 mutex_init(&pin_bank->deferred_lock); 4006 } 4007 4008 ret = rockchip_pinctrl_parse_dt(pdev, info); 4009 if (ret) 4010 return ret; 4011 4012 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 4013 if (IS_ERR(info->pctl_dev)) 4014 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 4015 4016 return 0; 4017} 4018 4019static const struct of_device_id rockchip_pinctrl_dt_match[]; 4020 4021/* retrieve the soc specific data */ 4022static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 4023 struct rockchip_pinctrl *d, 4024 struct platform_device *pdev) 4025{ 4026 struct device *dev = &pdev->dev; 4027 struct device_node *node = dev->of_node; 4028 const struct of_device_id *match; 4029 struct rockchip_pin_ctrl *ctrl; 4030 struct rockchip_pin_bank *bank; 4031 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 4032 4033 match = of_match_node(rockchip_pinctrl_dt_match, node); 4034 ctrl = (struct rockchip_pin_ctrl *)match->data; 4035 4036 grf_offs = ctrl->grf_mux_offset; 4037 pmu_offs = ctrl->pmu_mux_offset; 4038 drv_pmu_offs = ctrl->pmu_drv_offset; 4039 drv_grf_offs = ctrl->grf_drv_offset; 4040 bank = ctrl->pin_banks; 4041 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 4042 int bank_pins = 0; 4043 4044 raw_spin_lock_init(&bank->slock); 4045 bank->drvdata = d; 4046 bank->pin_base = ctrl->nr_pins; 4047 ctrl->nr_pins += bank->nr_pins; 4048 4049 /* calculate iomux and drv offsets */ 4050 for (j = 0; j < 4; j++) { 4051 struct rockchip_iomux *iom = &bank->iomux[j]; 4052 struct rockchip_drv *drv = &bank->drv[j]; 4053 int inc; 4054 4055 if (bank_pins >= bank->nr_pins) 4056 break; 4057 4058 /* preset iomux offset value, set new start value */ 4059 if (iom->offset >= 0) { 4060 if ((iom->type & IOMUX_SOURCE_PMU) || 4061 (iom->type & IOMUX_L_SOURCE_PMU)) 4062 pmu_offs = iom->offset; 4063 else 4064 grf_offs = iom->offset; 4065 } else { /* set current iomux offset */ 4066 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || 4067 (iom->type & IOMUX_L_SOURCE_PMU)) ? 4068 pmu_offs : grf_offs; 4069 } 4070 4071 /* preset drv offset value, set new start value */ 4072 if (drv->offset >= 0) { 4073 if (iom->type & IOMUX_SOURCE_PMU) 4074 drv_pmu_offs = drv->offset; 4075 else 4076 drv_grf_offs = drv->offset; 4077 } else { /* set current drv offset */ 4078 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 4079 drv_pmu_offs : drv_grf_offs; 4080 } 4081 4082 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 4083 i, j, iom->offset, drv->offset); 4084 4085 /* 4086 * Increase offset according to iomux width. 4087 * 4bit iomux'es are spread over two registers. 4088 */ 4089 inc = (iom->type & (IOMUX_WIDTH_4BIT | 4090 IOMUX_WIDTH_3BIT | 4091 IOMUX_WIDTH_2BIT)) ? 8 : 4; 4092 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) 4093 pmu_offs += inc; 4094 else 4095 grf_offs += inc; 4096 4097 /* 4098 * Increase offset according to drv width. 4099 * 3bit drive-strenth'es are spread over two registers. 4100 */ 4101 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 4102 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 4103 inc = 8; 4104 else 4105 inc = 4; 4106 4107 if (iom->type & IOMUX_SOURCE_PMU) 4108 drv_pmu_offs += inc; 4109 else 4110 drv_grf_offs += inc; 4111 4112 bank_pins += 8; 4113 } 4114 4115 /* calculate the per-bank recalced_mask */ 4116 for (j = 0; j < ctrl->niomux_recalced; j++) { 4117 int pin = 0; 4118 4119 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 4120 pin = ctrl->iomux_recalced[j].pin; 4121 bank->recalced_mask |= BIT(pin); 4122 } 4123 } 4124 4125 /* calculate the per-bank route_mask */ 4126 for (j = 0; j < ctrl->niomux_routes; j++) { 4127 int pin = 0; 4128 4129 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 4130 pin = ctrl->iomux_routes[j].pin; 4131 bank->route_mask |= BIT(pin); 4132 } 4133 } 4134 } 4135 4136 return ctrl; 4137} 4138 4139#define RK3288_GRF_GPIO6C_IOMUX 0x64 4140#define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 4141 4142static u32 rk3288_grf_gpio6c_iomux; 4143 4144static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 4145{ 4146 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 4147 int ret = pinctrl_force_sleep(info->pctl_dev); 4148 4149 if (ret) 4150 return ret; 4151 4152 /* 4153 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 4154 * the setting here, and restore it at resume. 4155 */ 4156 if (info->ctrl->type == RK3288) { 4157 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 4158 &rk3288_grf_gpio6c_iomux); 4159 if (ret) { 4160 pinctrl_force_default(info->pctl_dev); 4161 return ret; 4162 } 4163 } 4164 4165 return 0; 4166} 4167 4168static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 4169{ 4170 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 4171 int ret; 4172 4173 if (info->ctrl->type == RK3288) { 4174 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 4175 rk3288_grf_gpio6c_iomux | 4176 GPIO6C6_SEL_WRITE_ENABLE); 4177 if (ret) 4178 return ret; 4179 } 4180 4181 return pinctrl_force_default(info->pctl_dev); 4182} 4183 4184static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 4185 rockchip_pinctrl_resume); 4186 4187static int rockchip_pinctrl_probe(struct platform_device *pdev) 4188{ 4189 struct rockchip_pinctrl *info; 4190 struct device *dev = &pdev->dev; 4191 struct device_node *np = dev->of_node, *node; 4192 struct rockchip_pin_ctrl *ctrl; 4193 struct resource *res; 4194 void __iomem *base; 4195 int ret; 4196 4197 if (!dev->of_node) 4198 return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); 4199 4200 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 4201 if (!info) 4202 return -ENOMEM; 4203 4204 info->dev = dev; 4205 4206 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 4207 if (!ctrl) 4208 return dev_err_probe(dev, -EINVAL, "driver data not available\n"); 4209 info->ctrl = ctrl; 4210 4211 node = of_parse_phandle(np, "rockchip,grf", 0); 4212 if (node) { 4213 info->regmap_base = syscon_node_to_regmap(node); 4214 of_node_put(node); 4215 if (IS_ERR(info->regmap_base)) 4216 return PTR_ERR(info->regmap_base); 4217 } else { 4218 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 4219 if (IS_ERR(base)) 4220 return PTR_ERR(base); 4221 4222 rockchip_regmap_config.max_register = resource_size(res) - 4; 4223 rockchip_regmap_config.name = "rockchip,pinctrl"; 4224 info->regmap_base = 4225 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 4226 4227 /* to check for the old dt-bindings */ 4228 info->reg_size = resource_size(res); 4229 4230 /* Honor the old binding, with pull registers as 2nd resource */ 4231 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 4232 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 4233 if (IS_ERR(base)) 4234 return PTR_ERR(base); 4235 4236 rockchip_regmap_config.max_register = resource_size(res) - 4; 4237 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 4238 info->regmap_pull = 4239 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config); 4240 } 4241 } 4242 4243 /* try to find the optional reference to the pmu syscon */ 4244 info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu"); 4245 4246 /* try to find the optional reference to the ioc1 syscon */ 4247 info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1"); 4248 4249 ret = rockchip_pinctrl_register(pdev, info); 4250 if (ret) 4251 return ret; 4252 4253 platform_set_drvdata(pdev, info); 4254 4255 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 4256 if (ret) 4257 return dev_err_probe(dev, ret, "failed to register gpio device\n"); 4258 4259 return 0; 4260} 4261 4262static void rockchip_pinctrl_remove(struct platform_device *pdev) 4263{ 4264 struct rockchip_pinctrl *info = platform_get_drvdata(pdev); 4265 struct rockchip_pin_bank *bank; 4266 struct rockchip_pin_deferred *cfg; 4267 int i; 4268 4269 of_platform_depopulate(&pdev->dev); 4270 4271 for (i = 0; i < info->ctrl->nr_banks; i++) { 4272 bank = &info->ctrl->pin_banks[i]; 4273 4274 mutex_lock(&bank->deferred_lock); 4275 while (!list_empty(&bank->deferred_pins)) { 4276 cfg = list_first_entry(&bank->deferred_pins, 4277 struct rockchip_pin_deferred, head); 4278 list_del(&cfg->head); 4279 kfree(cfg); 4280 } 4281 mutex_unlock(&bank->deferred_lock); 4282 } 4283} 4284 4285static struct rockchip_pin_bank px30_pin_banks[] = { 4286 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4287 IOMUX_SOURCE_PMU, 4288 IOMUX_SOURCE_PMU, 4289 IOMUX_SOURCE_PMU 4290 ), 4291 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 4292 IOMUX_WIDTH_4BIT, 4293 IOMUX_WIDTH_4BIT, 4294 IOMUX_WIDTH_4BIT 4295 ), 4296 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 4297 IOMUX_WIDTH_4BIT, 4298 IOMUX_WIDTH_4BIT, 4299 IOMUX_WIDTH_4BIT 4300 ), 4301 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 4302 IOMUX_WIDTH_4BIT, 4303 IOMUX_WIDTH_4BIT, 4304 IOMUX_WIDTH_4BIT 4305 ), 4306}; 4307 4308static struct rockchip_pin_ctrl px30_pin_ctrl = { 4309 .pin_banks = px30_pin_banks, 4310 .nr_banks = ARRAY_SIZE(px30_pin_banks), 4311 .label = "PX30-GPIO", 4312 .type = PX30, 4313 .grf_mux_offset = 0x0, 4314 .pmu_mux_offset = 0x0, 4315 .iomux_routes = px30_mux_route_data, 4316 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 4317 .pull_calc_reg = px30_calc_pull_reg_and_bit, 4318 .drv_calc_reg = px30_calc_drv_reg_and_bit, 4319 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 4320}; 4321 4322static struct rockchip_pin_bank rv1108_pin_banks[] = { 4323 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4324 IOMUX_SOURCE_PMU, 4325 IOMUX_SOURCE_PMU, 4326 IOMUX_SOURCE_PMU), 4327 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 4328 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 4329 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 4330}; 4331 4332static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 4333 .pin_banks = rv1108_pin_banks, 4334 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 4335 .label = "RV1108-GPIO", 4336 .type = RV1108, 4337 .grf_mux_offset = 0x10, 4338 .pmu_mux_offset = 0x0, 4339 .iomux_recalced = rv1108_mux_recalced_data, 4340 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 4341 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 4342 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 4343 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 4344}; 4345 4346static struct rockchip_pin_bank rv1126_pin_banks[] = { 4347 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 4348 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 4349 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 4350 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, 4351 IOMUX_WIDTH_4BIT), 4352 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 4353 IOMUX_WIDTH_4BIT, 4354 IOMUX_WIDTH_4BIT, 4355 IOMUX_WIDTH_4BIT, 4356 IOMUX_WIDTH_4BIT, 4357 0x10010, 0x10018, 0x10020, 0x10028), 4358 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 4359 IOMUX_WIDTH_4BIT, 4360 IOMUX_WIDTH_4BIT, 4361 IOMUX_WIDTH_4BIT, 4362 IOMUX_WIDTH_4BIT), 4363 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 4364 IOMUX_WIDTH_4BIT, 4365 IOMUX_WIDTH_4BIT, 4366 IOMUX_WIDTH_4BIT, 4367 IOMUX_WIDTH_4BIT), 4368 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", 4369 IOMUX_WIDTH_4BIT, 0, 0, 0), 4370}; 4371 4372static struct rockchip_pin_ctrl rv1126_pin_ctrl = { 4373 .pin_banks = rv1126_pin_banks, 4374 .nr_banks = ARRAY_SIZE(rv1126_pin_banks), 4375 .label = "RV1126-GPIO", 4376 .type = RV1126, 4377 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ 4378 .pmu_mux_offset = 0x0, 4379 .iomux_routes = rv1126_mux_route_data, 4380 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), 4381 .iomux_recalced = rv1126_mux_recalced_data, 4382 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), 4383 .pull_calc_reg = rv1126_calc_pull_reg_and_bit, 4384 .drv_calc_reg = rv1126_calc_drv_reg_and_bit, 4385 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit, 4386}; 4387 4388static struct rockchip_pin_bank rk2928_pin_banks[] = { 4389 PIN_BANK(0, 32, "gpio0"), 4390 PIN_BANK(1, 32, "gpio1"), 4391 PIN_BANK(2, 32, "gpio2"), 4392 PIN_BANK(3, 32, "gpio3"), 4393}; 4394 4395static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 4396 .pin_banks = rk2928_pin_banks, 4397 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 4398 .label = "RK2928-GPIO", 4399 .type = RK2928, 4400 .grf_mux_offset = 0xa8, 4401 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 4402}; 4403 4404static struct rockchip_pin_bank rk3036_pin_banks[] = { 4405 PIN_BANK(0, 32, "gpio0"), 4406 PIN_BANK(1, 32, "gpio1"), 4407 PIN_BANK(2, 32, "gpio2"), 4408}; 4409 4410static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 4411 .pin_banks = rk3036_pin_banks, 4412 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 4413 .label = "RK3036-GPIO", 4414 .type = RK2928, 4415 .grf_mux_offset = 0xa8, 4416 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 4417}; 4418 4419static struct rockchip_pin_bank rk3066a_pin_banks[] = { 4420 PIN_BANK(0, 32, "gpio0"), 4421 PIN_BANK(1, 32, "gpio1"), 4422 PIN_BANK(2, 32, "gpio2"), 4423 PIN_BANK(3, 32, "gpio3"), 4424 PIN_BANK(4, 32, "gpio4"), 4425 PIN_BANK(6, 16, "gpio6"), 4426}; 4427 4428static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 4429 .pin_banks = rk3066a_pin_banks, 4430 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 4431 .label = "RK3066a-GPIO", 4432 .type = RK2928, 4433 .grf_mux_offset = 0xa8, 4434 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 4435}; 4436 4437static struct rockchip_pin_bank rk3066b_pin_banks[] = { 4438 PIN_BANK(0, 32, "gpio0"), 4439 PIN_BANK(1, 32, "gpio1"), 4440 PIN_BANK(2, 32, "gpio2"), 4441 PIN_BANK(3, 32, "gpio3"), 4442}; 4443 4444static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 4445 .pin_banks = rk3066b_pin_banks, 4446 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 4447 .label = "RK3066b-GPIO", 4448 .type = RK3066B, 4449 .grf_mux_offset = 0x60, 4450}; 4451 4452static struct rockchip_pin_bank rk3128_pin_banks[] = { 4453 PIN_BANK(0, 32, "gpio0"), 4454 PIN_BANK(1, 32, "gpio1"), 4455 PIN_BANK(2, 32, "gpio2"), 4456 PIN_BANK(3, 32, "gpio3"), 4457}; 4458 4459static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 4460 .pin_banks = rk3128_pin_banks, 4461 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 4462 .label = "RK3128-GPIO", 4463 .type = RK3128, 4464 .grf_mux_offset = 0xa8, 4465 .iomux_recalced = rk3128_mux_recalced_data, 4466 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 4467 .iomux_routes = rk3128_mux_route_data, 4468 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 4469 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 4470}; 4471 4472static struct rockchip_pin_bank rk3188_pin_banks[] = { 4473 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 4474 PIN_BANK(1, 32, "gpio1"), 4475 PIN_BANK(2, 32, "gpio2"), 4476 PIN_BANK(3, 32, "gpio3"), 4477}; 4478 4479static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 4480 .pin_banks = rk3188_pin_banks, 4481 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 4482 .label = "RK3188-GPIO", 4483 .type = RK3188, 4484 .grf_mux_offset = 0x60, 4485 .iomux_routes = rk3188_mux_route_data, 4486 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 4487 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 4488}; 4489 4490static struct rockchip_pin_bank rk3228_pin_banks[] = { 4491 PIN_BANK(0, 32, "gpio0"), 4492 PIN_BANK(1, 32, "gpio1"), 4493 PIN_BANK(2, 32, "gpio2"), 4494 PIN_BANK(3, 32, "gpio3"), 4495}; 4496 4497static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 4498 .pin_banks = rk3228_pin_banks, 4499 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 4500 .label = "RK3228-GPIO", 4501 .type = RK3288, 4502 .grf_mux_offset = 0x0, 4503 .iomux_routes = rk3228_mux_route_data, 4504 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 4505 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4506 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4507}; 4508 4509static struct rockchip_pin_bank rk3288_pin_banks[] = { 4510 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 4511 IOMUX_SOURCE_PMU, 4512 IOMUX_SOURCE_PMU, 4513 IOMUX_UNROUTED 4514 ), 4515 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 4516 IOMUX_UNROUTED, 4517 IOMUX_UNROUTED, 4518 0 4519 ), 4520 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 4521 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 4522 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4523 IOMUX_WIDTH_4BIT, 4524 0, 4525 0 4526 ), 4527 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 4528 0, 4529 0, 4530 IOMUX_UNROUTED 4531 ), 4532 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 4533 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 4534 0, 4535 IOMUX_WIDTH_4BIT, 4536 IOMUX_UNROUTED 4537 ), 4538 PIN_BANK(8, 16, "gpio8"), 4539}; 4540 4541static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 4542 .pin_banks = rk3288_pin_banks, 4543 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 4544 .label = "RK3288-GPIO", 4545 .type = RK3288, 4546 .grf_mux_offset = 0x0, 4547 .pmu_mux_offset = 0x84, 4548 .iomux_routes = rk3288_mux_route_data, 4549 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 4550 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 4551 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 4552}; 4553 4554static struct rockchip_pin_bank rk3308_pin_banks[] = { 4555 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 4556 IOMUX_WIDTH_2BIT, 4557 IOMUX_WIDTH_2BIT, 4558 IOMUX_WIDTH_2BIT), 4559 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 4560 IOMUX_WIDTH_2BIT, 4561 IOMUX_WIDTH_2BIT, 4562 IOMUX_WIDTH_2BIT), 4563 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 4564 IOMUX_WIDTH_2BIT, 4565 IOMUX_WIDTH_2BIT, 4566 IOMUX_WIDTH_2BIT), 4567 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 4568 IOMUX_WIDTH_2BIT, 4569 IOMUX_WIDTH_2BIT, 4570 IOMUX_WIDTH_2BIT), 4571 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 4572 IOMUX_WIDTH_2BIT, 4573 IOMUX_WIDTH_2BIT, 4574 IOMUX_WIDTH_2BIT), 4575}; 4576 4577static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 4578 .pin_banks = rk3308_pin_banks, 4579 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 4580 .label = "RK3308-GPIO", 4581 .type = RK3308, 4582 .grf_mux_offset = 0x0, 4583 .iomux_recalced = rk3308_mux_recalced_data, 4584 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 4585 .iomux_routes = rk3308_mux_route_data, 4586 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 4587 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 4588 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 4589 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 4590}; 4591 4592static struct rockchip_pin_bank rk3328_pin_banks[] = { 4593 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 4594 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 4595 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 4596 IOMUX_WIDTH_2BIT, 4597 IOMUX_WIDTH_3BIT, 4598 0), 4599 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 4600 IOMUX_WIDTH_3BIT, 4601 IOMUX_WIDTH_3BIT, 4602 0, 4603 0), 4604}; 4605 4606static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 4607 .pin_banks = rk3328_pin_banks, 4608 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 4609 .label = "RK3328-GPIO", 4610 .type = RK3328, 4611 .grf_mux_offset = 0x0, 4612 .iomux_recalced = rk3328_mux_recalced_data, 4613 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 4614 .iomux_routes = rk3328_mux_route_data, 4615 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 4616 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4617 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4618 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 4619}; 4620 4621static struct rockchip_pin_bank rk3368_pin_banks[] = { 4622 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4623 IOMUX_SOURCE_PMU, 4624 IOMUX_SOURCE_PMU, 4625 IOMUX_SOURCE_PMU 4626 ), 4627 PIN_BANK(1, 32, "gpio1"), 4628 PIN_BANK(2, 32, "gpio2"), 4629 PIN_BANK(3, 32, "gpio3"), 4630}; 4631 4632static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 4633 .pin_banks = rk3368_pin_banks, 4634 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 4635 .label = "RK3368-GPIO", 4636 .type = RK3368, 4637 .grf_mux_offset = 0x0, 4638 .pmu_mux_offset = 0x0, 4639 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 4640 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 4641}; 4642 4643static struct rockchip_pin_bank rk3399_pin_banks[] = { 4644 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 4645 IOMUX_SOURCE_PMU, 4646 IOMUX_SOURCE_PMU, 4647 IOMUX_SOURCE_PMU, 4648 IOMUX_SOURCE_PMU, 4649 DRV_TYPE_IO_1V8_ONLY, 4650 DRV_TYPE_IO_1V8_ONLY, 4651 DRV_TYPE_IO_DEFAULT, 4652 DRV_TYPE_IO_DEFAULT, 4653 0x80, 4654 0x88, 4655 -1, 4656 -1, 4657 PULL_TYPE_IO_1V8_ONLY, 4658 PULL_TYPE_IO_1V8_ONLY, 4659 PULL_TYPE_IO_DEFAULT, 4660 PULL_TYPE_IO_DEFAULT 4661 ), 4662 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 4663 IOMUX_SOURCE_PMU, 4664 IOMUX_SOURCE_PMU, 4665 IOMUX_SOURCE_PMU, 4666 DRV_TYPE_IO_1V8_OR_3V0, 4667 DRV_TYPE_IO_1V8_OR_3V0, 4668 DRV_TYPE_IO_1V8_OR_3V0, 4669 DRV_TYPE_IO_1V8_OR_3V0, 4670 0xa0, 4671 0xa8, 4672 0xb0, 4673 0xb8 4674 ), 4675 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 4676 DRV_TYPE_IO_1V8_OR_3V0, 4677 DRV_TYPE_IO_1V8_ONLY, 4678 DRV_TYPE_IO_1V8_ONLY, 4679 PULL_TYPE_IO_DEFAULT, 4680 PULL_TYPE_IO_DEFAULT, 4681 PULL_TYPE_IO_1V8_ONLY, 4682 PULL_TYPE_IO_1V8_ONLY 4683 ), 4684 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 4685 DRV_TYPE_IO_3V3_ONLY, 4686 DRV_TYPE_IO_3V3_ONLY, 4687 DRV_TYPE_IO_1V8_OR_3V0 4688 ), 4689 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 4690 DRV_TYPE_IO_1V8_3V0_AUTO, 4691 DRV_TYPE_IO_1V8_OR_3V0, 4692 DRV_TYPE_IO_1V8_OR_3V0 4693 ), 4694}; 4695 4696static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 4697 .pin_banks = rk3399_pin_banks, 4698 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 4699 .label = "RK3399-GPIO", 4700 .type = RK3399, 4701 .grf_mux_offset = 0xe000, 4702 .pmu_mux_offset = 0x0, 4703 .grf_drv_offset = 0xe100, 4704 .pmu_drv_offset = 0x80, 4705 .iomux_routes = rk3399_mux_route_data, 4706 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 4707 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 4708 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 4709}; 4710 4711static struct rockchip_pin_bank rk3506_pin_banks[] = { 4712 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0", 4713 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 4714 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 4715 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, 4716 IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU, 4717 0x0, 0x8, 0x10, 0x830, 4718 DRV_TYPE_IO_LEVEL_8_BIT, 4719 DRV_TYPE_IO_LEVEL_8_BIT, 4720 DRV_TYPE_IO_LEVEL_8_BIT, 4721 DRV_TYPE_IO_LEVEL_2_BIT, 4722 0, 0, 0, 1), 4723 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1", 4724 IOMUX_WIDTH_4BIT, 4725 IOMUX_WIDTH_4BIT, 4726 IOMUX_WIDTH_4BIT, 4727 IOMUX_WIDTH_4BIT, 4728 0x20, 0x28, 0x30, 0x38, 4729 DRV_TYPE_IO_LEVEL_8_BIT, 4730 DRV_TYPE_IO_LEVEL_8_BIT, 4731 DRV_TYPE_IO_LEVEL_8_BIT, 4732 DRV_TYPE_IO_LEVEL_8_BIT), 4733 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2", 4734 IOMUX_WIDTH_4BIT, 4735 IOMUX_WIDTH_4BIT, 4736 IOMUX_WIDTH_4BIT, 4737 IOMUX_WIDTH_4BIT, 4738 0x40, 0x48, 0x50, 0x58, 4739 DRV_TYPE_IO_LEVEL_8_BIT, 4740 DRV_TYPE_IO_LEVEL_8_BIT, 4741 DRV_TYPE_IO_LEVEL_8_BIT, 4742 DRV_TYPE_IO_LEVEL_8_BIT), 4743 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3", 4744 IOMUX_WIDTH_4BIT, 4745 IOMUX_WIDTH_4BIT, 4746 IOMUX_WIDTH_4BIT, 4747 IOMUX_WIDTH_4BIT, 4748 0x60, 0x68, 0x70, 0x78, 4749 DRV_TYPE_IO_LEVEL_8_BIT, 4750 DRV_TYPE_IO_LEVEL_8_BIT, 4751 DRV_TYPE_IO_LEVEL_8_BIT, 4752 DRV_TYPE_IO_LEVEL_8_BIT), 4753 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4", 4754 IOMUX_WIDTH_4BIT, 4755 IOMUX_WIDTH_4BIT, 4756 IOMUX_WIDTH_4BIT, 4757 IOMUX_WIDTH_4BIT, 4758 0x80, 0x88, 0x90, 0x98, 4759 DRV_TYPE_IO_LEVEL_2_BIT, 4760 DRV_TYPE_IO_LEVEL_2_BIT, 4761 DRV_TYPE_IO_LEVEL_2_BIT, 4762 DRV_TYPE_IO_LEVEL_2_BIT, 4763 1, 1, 1, 1), 4764}; 4765 4766static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = { 4767 .pin_banks = rk3506_pin_banks, 4768 .nr_banks = ARRAY_SIZE(rk3506_pin_banks), 4769 .label = "RK3506-GPIO", 4770 .type = RK3506, 4771 .pull_calc_reg = rk3506_calc_pull_reg_and_bit, 4772 .drv_calc_reg = rk3506_calc_drv_reg_and_bit, 4773 .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit, 4774}; 4775 4776static struct rockchip_pin_bank rk3528_pin_banks[] = { 4777 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", 4778 IOMUX_WIDTH_4BIT, 4779 IOMUX_WIDTH_4BIT, 4780 IOMUX_WIDTH_4BIT, 4781 IOMUX_WIDTH_4BIT, 4782 0, 0, 0, 0), 4783 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 4784 IOMUX_WIDTH_4BIT, 4785 IOMUX_WIDTH_4BIT, 4786 IOMUX_WIDTH_4BIT, 4787 IOMUX_WIDTH_4BIT, 4788 0x20020, 0x20028, 0x20030, 0x20038), 4789 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", 4790 IOMUX_WIDTH_4BIT, 4791 IOMUX_WIDTH_4BIT, 4792 IOMUX_WIDTH_4BIT, 4793 IOMUX_WIDTH_4BIT, 4794 0x30040, 0, 0, 0), 4795 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", 4796 IOMUX_WIDTH_4BIT, 4797 IOMUX_WIDTH_4BIT, 4798 IOMUX_WIDTH_4BIT, 4799 IOMUX_WIDTH_4BIT, 4800 0x20060, 0x20068, 0x20070, 0), 4801 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4", 4802 IOMUX_WIDTH_4BIT, 4803 IOMUX_WIDTH_4BIT, 4804 IOMUX_WIDTH_4BIT, 4805 IOMUX_WIDTH_4BIT, 4806 0x10080, 0x10088, 0x10090, 0x10098), 4807}; 4808 4809static struct rockchip_pin_ctrl rk3528_pin_ctrl = { 4810 .pin_banks = rk3528_pin_banks, 4811 .nr_banks = ARRAY_SIZE(rk3528_pin_banks), 4812 .label = "RK3528-GPIO", 4813 .type = RK3528, 4814 .pull_calc_reg = rk3528_calc_pull_reg_and_bit, 4815 .drv_calc_reg = rk3528_calc_drv_reg_and_bit, 4816 .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit, 4817}; 4818 4819static struct rockchip_pin_bank rk3562_pin_banks[] = { 4820 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", 4821 IOMUX_WIDTH_4BIT, 4822 IOMUX_WIDTH_4BIT, 4823 IOMUX_WIDTH_4BIT, 4824 IOMUX_WIDTH_4BIT, 4825 0x20000, 0x20008, 0x20010, 0x20018), 4826 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", 4827 IOMUX_WIDTH_4BIT, 4828 IOMUX_WIDTH_4BIT, 4829 IOMUX_WIDTH_4BIT, 4830 IOMUX_WIDTH_4BIT, 4831 0, 0x08, 0x10, 0x18), 4832 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", 4833 IOMUX_WIDTH_4BIT, 4834 IOMUX_WIDTH_4BIT, 4835 IOMUX_WIDTH_4BIT, 4836 IOMUX_WIDTH_4BIT, 4837 0x20, 0, 0, 0), 4838 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", 4839 IOMUX_WIDTH_4BIT, 4840 IOMUX_WIDTH_4BIT, 4841 IOMUX_WIDTH_4BIT, 4842 IOMUX_WIDTH_4BIT, 4843 0x10040, 0x10048, 0x10050, 0x10058), 4844 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4", 4845 IOMUX_WIDTH_4BIT, 4846 IOMUX_WIDTH_4BIT, 4847 0, 4848 0, 4849 0x10060, 0x10068, 0, 0), 4850}; 4851 4852static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = { 4853 .pin_banks = rk3562_pin_banks, 4854 .nr_banks = ARRAY_SIZE(rk3562_pin_banks), 4855 .label = "RK3562-GPIO", 4856 .type = RK3562, 4857 .pull_calc_reg = rk3562_calc_pull_reg_and_bit, 4858 .drv_calc_reg = rk3562_calc_drv_reg_and_bit, 4859 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit, 4860}; 4861 4862static struct rockchip_pin_bank rk3568_pin_banks[] = { 4863 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4864 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4865 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 4866 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 4867 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 4868 IOMUX_WIDTH_4BIT, 4869 IOMUX_WIDTH_4BIT, 4870 IOMUX_WIDTH_4BIT), 4871 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 4872 IOMUX_WIDTH_4BIT, 4873 IOMUX_WIDTH_4BIT, 4874 IOMUX_WIDTH_4BIT), 4875 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 4876 IOMUX_WIDTH_4BIT, 4877 IOMUX_WIDTH_4BIT, 4878 IOMUX_WIDTH_4BIT), 4879 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4880 IOMUX_WIDTH_4BIT, 4881 IOMUX_WIDTH_4BIT, 4882 IOMUX_WIDTH_4BIT), 4883}; 4884 4885static struct rockchip_pin_ctrl rk3568_pin_ctrl = { 4886 .pin_banks = rk3568_pin_banks, 4887 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 4888 .label = "RK3568-GPIO", 4889 .type = RK3568, 4890 .grf_mux_offset = 0x0, 4891 .pmu_mux_offset = 0x0, 4892 .grf_drv_offset = 0x0200, 4893 .pmu_drv_offset = 0x0070, 4894 .iomux_routes = rk3568_mux_route_data, 4895 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 4896 .pull_calc_reg = rk3568_calc_pull_reg_and_bit, 4897 .drv_calc_reg = rk3568_calc_drv_reg_and_bit, 4898 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit, 4899}; 4900 4901#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \ 4902 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \ 4903 IOMUX_WIDTH_4BIT, \ 4904 IOMUX_WIDTH_4BIT, \ 4905 IOMUX_WIDTH_4BIT, \ 4906 IOMUX_WIDTH_4BIT, \ 4907 OFFSET0, OFFSET1, \ 4908 OFFSET2, OFFSET3, \ 4909 PULL_TYPE_IO_1V8_ONLY, \ 4910 PULL_TYPE_IO_1V8_ONLY, \ 4911 PULL_TYPE_IO_1V8_ONLY, \ 4912 PULL_TYPE_IO_1V8_ONLY) 4913 4914static struct rockchip_pin_bank rk3576_pin_banks[] = { 4915 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C), 4916 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038), 4917 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058), 4918 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078), 4919 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398), 4920}; 4921 4922static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = { 4923 .pin_banks = rk3576_pin_banks, 4924 .nr_banks = ARRAY_SIZE(rk3576_pin_banks), 4925 .label = "RK3576-GPIO", 4926 .type = RK3576, 4927 .pull_calc_reg = rk3576_calc_pull_reg_and_bit, 4928 .drv_calc_reg = rk3576_calc_drv_reg_and_bit, 4929 .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit, 4930}; 4931 4932static struct rockchip_pin_bank rk3588_pin_banks[] = { 4933 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0", 4934 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4935 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1", 4936 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4937 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2", 4938 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4939 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3", 4940 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4941 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4", 4942 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY), 4943}; 4944 4945static struct rockchip_pin_ctrl rk3588_pin_ctrl = { 4946 .pin_banks = rk3588_pin_banks, 4947 .nr_banks = ARRAY_SIZE(rk3588_pin_banks), 4948 .label = "RK3588-GPIO", 4949 .type = RK3588, 4950 .pull_calc_reg = rk3588_calc_pull_reg_and_bit, 4951 .drv_calc_reg = rk3588_calc_drv_reg_and_bit, 4952 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit, 4953}; 4954 4955static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4956 { .compatible = "rockchip,px30-pinctrl", 4957 .data = &px30_pin_ctrl }, 4958 { .compatible = "rockchip,rv1108-pinctrl", 4959 .data = &rv1108_pin_ctrl }, 4960 { .compatible = "rockchip,rv1126-pinctrl", 4961 .data = &rv1126_pin_ctrl }, 4962 { .compatible = "rockchip,rk2928-pinctrl", 4963 .data = &rk2928_pin_ctrl }, 4964 { .compatible = "rockchip,rk3036-pinctrl", 4965 .data = &rk3036_pin_ctrl }, 4966 { .compatible = "rockchip,rk3066a-pinctrl", 4967 .data = &rk3066a_pin_ctrl }, 4968 { .compatible = "rockchip,rk3066b-pinctrl", 4969 .data = &rk3066b_pin_ctrl }, 4970 { .compatible = "rockchip,rk3128-pinctrl", 4971 .data = (void *)&rk3128_pin_ctrl }, 4972 { .compatible = "rockchip,rk3188-pinctrl", 4973 .data = &rk3188_pin_ctrl }, 4974 { .compatible = "rockchip,rk3228-pinctrl", 4975 .data = &rk3228_pin_ctrl }, 4976 { .compatible = "rockchip,rk3288-pinctrl", 4977 .data = &rk3288_pin_ctrl }, 4978 { .compatible = "rockchip,rk3308-pinctrl", 4979 .data = &rk3308_pin_ctrl }, 4980 { .compatible = "rockchip,rk3328-pinctrl", 4981 .data = &rk3328_pin_ctrl }, 4982 { .compatible = "rockchip,rk3368-pinctrl", 4983 .data = &rk3368_pin_ctrl }, 4984 { .compatible = "rockchip,rk3399-pinctrl", 4985 .data = &rk3399_pin_ctrl }, 4986 { .compatible = "rockchip,rk3506-pinctrl", 4987 .data = &rk3506_pin_ctrl }, 4988 { .compatible = "rockchip,rk3528-pinctrl", 4989 .data = &rk3528_pin_ctrl }, 4990 { .compatible = "rockchip,rk3562-pinctrl", 4991 .data = &rk3562_pin_ctrl }, 4992 { .compatible = "rockchip,rk3568-pinctrl", 4993 .data = &rk3568_pin_ctrl }, 4994 { .compatible = "rockchip,rk3576-pinctrl", 4995 .data = &rk3576_pin_ctrl }, 4996 { .compatible = "rockchip,rk3588-pinctrl", 4997 .data = &rk3588_pin_ctrl }, 4998 {}, 4999}; 5000 5001static struct platform_driver rockchip_pinctrl_driver = { 5002 .probe = rockchip_pinctrl_probe, 5003 .remove = rockchip_pinctrl_remove, 5004 .driver = { 5005 .name = "rockchip-pinctrl", 5006 .pm = &rockchip_pinctrl_dev_pm_ops, 5007 .of_match_table = rockchip_pinctrl_dt_match, 5008 }, 5009}; 5010 5011static int __init rockchip_pinctrl_drv_register(void) 5012{ 5013 return platform_driver_register(&rockchip_pinctrl_driver); 5014} 5015postcore_initcall(rockchip_pinctrl_drv_register); 5016 5017static void __exit rockchip_pinctrl_drv_unregister(void) 5018{ 5019 platform_driver_unregister(&rockchip_pinctrl_driver); 5020} 5021module_exit(rockchip_pinctrl_drv_unregister); 5022 5023MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 5024MODULE_LICENSE("GPL"); 5025MODULE_ALIAS("platform:pinctrl-rockchip"); 5026MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
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