pinctrl-mpfs-iomux0.c

  1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <linux/bitfield.h>
  4#include <linux/cleanup.h>
  5#include <linux/module.h>
  6#include <linux/mfd/syscon.h>
  7#include <linux/mod_devicetable.h>
  8#include <linux/of.h>
  9#include <linux/platform_device.h>
 10#include <linux/regmap.h>
 11#include <linux/seq_file.h>
 12
 13#include <linux/pinctrl/pinconf-generic.h>
 14#include <linux/pinctrl/pinconf.h>
 15#include <linux/pinctrl/pinctrl.h>
 16#include <linux/pinctrl/pinmux.h>
 17
 18#include "core.h"
 19#include "pinctrl-utils.h"
 20#include "pinconf.h"
 21#include "pinmux.h"
 22
 23#define MPFS_IOMUX0_REG 0x200
 24
 25struct mpfs_iomux0_pinctrl {
 26	struct pinctrl_dev *pctrl;
 27	struct device *dev;
 28	struct regmap *regmap;
 29	struct pinctrl_desc desc;
 30};
 31
 32struct mpfs_iomux0_pin_group {
 33	const char *name;
 34	const unsigned int *pins;
 35	u32 mask;
 36	u32 setting;
 37};
 38
 39struct mpfs_iomux0_function {
 40	const char *name;
 41	const char * const *groups;
 42};
 43
 44static const struct pinctrl_pin_desc mpfs_iomux0_pins[] = {
 45	PINCTRL_PIN(0, "spi0"),
 46	PINCTRL_PIN(1, "spi1"),
 47	PINCTRL_PIN(2, "i2c0"),
 48	PINCTRL_PIN(3, "i2c1"),
 49	PINCTRL_PIN(4, "can0"),
 50	PINCTRL_PIN(5, "can1"),
 51	PINCTRL_PIN(6, "qspi"),
 52	PINCTRL_PIN(7, "uart0"),
 53	PINCTRL_PIN(8, "uart1"),
 54	PINCTRL_PIN(9, "uart2"),
 55	PINCTRL_PIN(10, "uart3"),
 56	PINCTRL_PIN(11, "uart4"),
 57	PINCTRL_PIN(12, "mdio0"),
 58	PINCTRL_PIN(13, "mdio1"),
 59};
 60
 61static const unsigned int mpfs_iomux0_spi0_pins[] = { 0 };
 62static const unsigned int mpfs_iomux0_spi1_pins[] = { 1 };
 63static const unsigned int mpfs_iomux0_i2c0_pins[] = { 2 };
 64static const unsigned int mpfs_iomux0_i2c1_pins[] = { 3 };
 65static const unsigned int mpfs_iomux0_can0_pins[] = { 4 };
 66static const unsigned int mpfs_iomux0_can1_pins[] = { 5 };
 67static const unsigned int mpfs_iomux0_qspi_pins[] = { 6 };
 68static const unsigned int mpfs_iomux0_uart0_pins[] = { 7 };
 69static const unsigned int mpfs_iomux0_uart1_pins[] = { 8 };
 70static const unsigned int mpfs_iomux0_uart2_pins[] = { 9 };
 71static const unsigned int mpfs_iomux0_uart3_pins[] = { 10 };
 72static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 };
 73static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 };
 74static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 };
 75
 76#define MPFS_IOMUX0_GROUP(_name, _mask) { \
 77	.name = #_name "_mssio",	\
 78	.pins = mpfs_iomux0_##_name##_pins,	\
 79	.mask = _mask,	\
 80	.setting = 0x0,	\
 81}, { \
 82	.name = #_name "_fabric",	\
 83	.pins = mpfs_iomux0_##_name##_pins,	\
 84	.mask = _mask,	\
 85	.setting = _mask,	\
 86}
 87
 88static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = {
 89	MPFS_IOMUX0_GROUP(spi0, BIT(0)),
 90	MPFS_IOMUX0_GROUP(spi1, BIT(1)),
 91	MPFS_IOMUX0_GROUP(i2c0, BIT(2)),
 92	MPFS_IOMUX0_GROUP(i2c1, BIT(3)),
 93	MPFS_IOMUX0_GROUP(can0, BIT(4)),
 94	MPFS_IOMUX0_GROUP(can1, BIT(5)),
 95	MPFS_IOMUX0_GROUP(qspi, BIT(6)),
 96	MPFS_IOMUX0_GROUP(uart0, BIT(7)),
 97	MPFS_IOMUX0_GROUP(uart1, BIT(8)),
 98	MPFS_IOMUX0_GROUP(uart2, BIT(9)),
 99	MPFS_IOMUX0_GROUP(uart3, BIT(10)),
100	MPFS_IOMUX0_GROUP(uart4, BIT(11)),
101	MPFS_IOMUX0_GROUP(mdio0, BIT(12)),
102	MPFS_IOMUX0_GROUP(mdio1, BIT(13)),
103};
104
105static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" };
106static const char * const mpfs_iomux0_spi1_groups[] = { "spi1_mssio", "spi1_fabric" };
107static const char * const mpfs_iomux0_i2c0_groups[] = { "i2c0_mssio", "i2c0_fabric" };
108static const char * const mpfs_iomux0_i2c1_groups[] = { "i2c1_mssio", "i2c1_fabric" };
109static const char * const mpfs_iomux0_can0_groups[] = { "can0_mssio", "can0_fabric" };
110static const char * const mpfs_iomux0_can1_groups[] = { "can1_mssio", "can1_fabric" };
111static const char * const mpfs_iomux0_qspi_groups[] = { "qspi_mssio", "qspi_fabric" };
112static const char * const mpfs_iomux0_uart0_groups[] = { "uart0_mssio", "uart0_fabric" };
113static const char * const mpfs_iomux0_uart1_groups[] = { "uart1_mssio", "uart1_fabric" };
114static const char * const mpfs_iomux0_uart2_groups[] = { "uart2_mssio", "uart2_fabric" };
115static const char * const mpfs_iomux0_uart3_groups[] = { "uart3_mssio", "uart3_fabric" };
116static const char * const mpfs_iomux0_uart4_groups[] = { "uart4_mssio", "uart4_fabric" };
117static const char * const mpfs_iomux0_mdio0_groups[] = { "mdio0_mssio", "mdio0_fabric" };
118static const char * const mpfs_iomux0_mdio1_groups[] = { "mdio1_mssio", "mdio1_fabric" };
119
120#define MPFS_IOMUX0_FUNCTION(_name) { \
121	.name = #_name,	\
122	.groups = mpfs_iomux0_##_name##_groups,	\
123}
124
125static const struct mpfs_iomux0_function mpfs_iomux0_functions[] = {
126	MPFS_IOMUX0_FUNCTION(spi0),
127	MPFS_IOMUX0_FUNCTION(spi1),
128	MPFS_IOMUX0_FUNCTION(i2c0),
129	MPFS_IOMUX0_FUNCTION(i2c1),
130	MPFS_IOMUX0_FUNCTION(can0),
131	MPFS_IOMUX0_FUNCTION(can1),
132	MPFS_IOMUX0_FUNCTION(qspi),
133	MPFS_IOMUX0_FUNCTION(uart0),
134	MPFS_IOMUX0_FUNCTION(uart1),
135	MPFS_IOMUX0_FUNCTION(uart2),
136	MPFS_IOMUX0_FUNCTION(uart3),
137	MPFS_IOMUX0_FUNCTION(uart4),
138	MPFS_IOMUX0_FUNCTION(mdio0),
139	MPFS_IOMUX0_FUNCTION(mdio1),
140};
141
142static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
143				     unsigned int pin)
144{
145	struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
146	u32 val;
147
148	seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin);
149
150	regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val);
151	val = (val & BIT(pin)) >> pin;
152
153	seq_printf(seq, "val: %x\n", val);
154}
155
156static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev)
157{
158	return ARRAY_SIZE(mpfs_iomux0_pin_groups);
159}
160
161static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
162{
163	return mpfs_iomux0_pin_groups[selector].name;
164}
165
166static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
167				  const unsigned int **pins, unsigned int *num_pins)
168{
169	*pins = mpfs_iomux0_pin_groups[selector].pins;
170	*num_pins = 1;
171
172	return 0;
173}
174
175static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops = {
176	.get_groups_count = mpfs_iomux0_groups_count,
177	.get_group_name = mpfs_iomux0_group_name,
178	.get_group_pins = mpfs_iomux0_group_pins,
179	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
180	.dt_free_map = pinctrl_utils_free_map,
181	.pin_dbg_show = mpfs_iomux0_pin_dbg_show,
182};
183
184static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
185				      unsigned int gsel)
186{
187	struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
188	struct device *dev = pctrl->dev;
189	const struct mpfs_iomux0_pin_group *group;
190	const struct mpfs_iomux0_function *function;
191
192	group = &mpfs_iomux0_pin_groups[gsel];
193	function = &mpfs_iomux0_functions[fsel];
194
195	dev_dbg(dev, "Setting func %s mask %x setting %x\n",
196		function->name, group->mask, group->setting);
197	regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->setting);
198
199	return 0;
200}
201
202static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
203{
204	return ARRAY_SIZE(mpfs_iomux0_functions);
205}
206
207static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pctldev,
208						    unsigned int selector)
209{
210	return mpfs_iomux0_functions[selector].name;
211}
212
213static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
214					 const char * const **groups,
215					 unsigned int * const num_groups)
216{
217	*groups = mpfs_iomux0_functions[selector].groups;
218	*num_groups = 2;
219
220	return 0;
221}
222
223static const struct pinmux_ops mpfs_iomux0_pinmux_ops = {
224	.get_functions_count = mpfs_iomux0_pinmux_get_funcs_count,
225	.get_function_name = mpfs_iomux0_pinmux_get_func_name,
226	.get_function_groups = mpfs_iomux0_pinmux_get_groups,
227	.set_mux = mpfs_iomux0_pinmux_set_mux,
228};
229
230static int mpfs_iomux0_probe(struct platform_device *pdev)
231{
232	struct device *dev = &pdev->dev;
233	struct mpfs_iomux0_pinctrl *pctrl;
234
235	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
236	if (!pctrl)
237		return -ENOMEM;
238
239	pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
240	if (IS_ERR(pctrl->regmap))
241		dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
242
243	pctrl->desc.name = dev_name(dev);
244	pctrl->desc.pins = mpfs_iomux0_pins;
245	pctrl->desc.npins = ARRAY_SIZE(mpfs_iomux0_pins);
246	pctrl->desc.pctlops = &mpfs_iomux0_pinctrl_ops;
247	pctrl->desc.pmxops = &mpfs_iomux0_pinmux_ops;
248	pctrl->desc.owner = THIS_MODULE;
249
250	pctrl->dev = dev;
251
252	platform_set_drvdata(pdev, pctrl);
253
254	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
255	if (IS_ERR(pctrl->pctrl))
256		return PTR_ERR(pctrl->pctrl);
257
258	return 0;
259}
260
261static const struct of_device_id mpfs_iomux0_of_match[] = {
262	{ .compatible = "microchip,mpfs-pinctrl-iomux0" },
263	{ }
264};
265MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match);
266
267static struct platform_driver mpfs_iomux0_driver = {
268	.driver = {
269		.name = "mpfs-pinctrl-iomux0",
270		.of_match_table = mpfs_iomux0_of_match,
271	},
272	.probe = mpfs_iomux0_probe,
273};
274module_platform_driver(mpfs_iomux0_driver);
275
276MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
277MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver");
278MODULE_LICENSE("GPL");