pinctrl-mcp23s08.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* MCP23S08 SPI/I2C GPIO driver */
  3
  4#include <linux/bitops.h>
  5#include <linux/kernel.h>
  6#include <linux/device.h>
  7#include <linux/mutex.h>
  8#include <linux/mod_devicetable.h>
  9#include <linux/module.h>
 10#include <linux/export.h>
 11#include <linux/gpio/driver.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/seq_file.h>
 14#include <linux/slab.h>
 15#include <asm/byteorder.h>
 16#include <linux/interrupt.h>
 17#include <linux/regmap.h>
 18#include <linux/pinctrl/pinctrl.h>
 19#include <linux/pinctrl/pinconf.h>
 20#include <linux/pinctrl/pinconf-generic.h>
 21
 22#include "pinctrl-mcp23s08.h"
 23
 24/* Registers are all 8 bits wide.
 25 *
 26 * The mcp23s17 has twice as many bits, and can be configured to work
 27 * with either 16 bit registers or with two adjacent 8 bit banks.
 28 */
 29#define MCP_IODIR	0x00		/* init/reset:  all ones */
 30#define MCP_IPOL	0x01
 31#define MCP_GPINTEN	0x02
 32#define MCP_DEFVAL	0x03
 33#define MCP_INTCON	0x04
 34#define MCP_IOCON	0x05
 35#	define IOCON_MIRROR	(1 << 6)
 36#	define IOCON_SEQOP	(1 << 5)
 37#	define IOCON_HAEN	(1 << 3)
 38#	define IOCON_ODR	(1 << 2)
 39#	define IOCON_INTPOL	(1 << 1)
 40#	define IOCON_INTCC	(1)
 41#define MCP_GPPU	0x06
 42#define MCP_INTF	0x07
 43#define MCP_INTCAP	0x08
 44#define MCP_GPIO	0x09
 45#define MCP_OLAT	0x0a
 46
 47static const struct regmap_range mcp23x08_volatile_range = {
 48	.range_min = MCP_INTF,
 49	.range_max = MCP_GPIO,
 50};
 51
 52static const struct regmap_access_table mcp23x08_volatile_table = {
 53	.yes_ranges = &mcp23x08_volatile_range,
 54	.n_yes_ranges = 1,
 55};
 56
 57static const struct regmap_range mcp23x08_precious_range = {
 58	.range_min = MCP_GPIO,
 59	.range_max = MCP_GPIO,
 60};
 61
 62static const struct regmap_access_table mcp23x08_precious_table = {
 63	.yes_ranges = &mcp23x08_precious_range,
 64	.n_yes_ranges = 1,
 65};
 66
 67const struct regmap_config mcp23x08_regmap = {
 68	.reg_bits = 8,
 69	.val_bits = 8,
 70
 71	.reg_stride = 1,
 72	.volatile_table = &mcp23x08_volatile_table,
 73	.precious_table = &mcp23x08_precious_table,
 74	.num_reg_defaults_raw = MCP_OLAT + 1,
 75	.cache_type = REGCACHE_MAPLE,
 76	.max_register = MCP_OLAT,
 77	.disable_locking = true, /* mcp->lock protects the regmap */
 78};
 79EXPORT_SYMBOL_GPL(mcp23x08_regmap);
 80
 81static const struct regmap_range mcp23x17_volatile_range = {
 82	.range_min = MCP_INTF << 1,
 83	.range_max = MCP_GPIO << 1,
 84};
 85
 86static const struct regmap_access_table mcp23x17_volatile_table = {
 87	.yes_ranges = &mcp23x17_volatile_range,
 88	.n_yes_ranges = 1,
 89};
 90
 91static const struct regmap_range mcp23x17_precious_range = {
 92	.range_min = MCP_INTCAP << 1,
 93	.range_max = MCP_GPIO << 1,
 94};
 95
 96static const struct regmap_access_table mcp23x17_precious_table = {
 97	.yes_ranges = &mcp23x17_precious_range,
 98	.n_yes_ranges = 1,
 99};
100
101const struct regmap_config mcp23x17_regmap = {
102	.reg_bits = 8,
103	.val_bits = 16,
104
105	.reg_stride = 2,
106	.max_register = MCP_OLAT << 1,
107	.volatile_table = &mcp23x17_volatile_table,
108	.precious_table = &mcp23x17_precious_table,
109	.num_reg_defaults_raw = MCP_OLAT + 1,
110	.cache_type = REGCACHE_MAPLE,
111	.val_format_endian = REGMAP_ENDIAN_LITTLE,
112	.disable_locking = true, /* mcp->lock protects the regmap */
113};
114EXPORT_SYMBOL_GPL(mcp23x17_regmap);
115
116static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
117{
118	return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
119}
120
121static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
122{
123	return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
124}
125
126static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
127			   unsigned int mask, unsigned int val)
128{
129	return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
130				  mask, val);
131}
132
133static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
134		       unsigned int pin, bool enabled)
135{
136	u16 mask = BIT(pin);
137	return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
138}
139
140static const struct pinctrl_pin_desc mcp23x08_pins[] = {
141	PINCTRL_PIN(0, "gpio0"),
142	PINCTRL_PIN(1, "gpio1"),
143	PINCTRL_PIN(2, "gpio2"),
144	PINCTRL_PIN(3, "gpio3"),
145	PINCTRL_PIN(4, "gpio4"),
146	PINCTRL_PIN(5, "gpio5"),
147	PINCTRL_PIN(6, "gpio6"),
148	PINCTRL_PIN(7, "gpio7"),
149};
150
151static const struct pinctrl_pin_desc mcp23x17_pins[] = {
152	PINCTRL_PIN(0, "gpio0"),
153	PINCTRL_PIN(1, "gpio1"),
154	PINCTRL_PIN(2, "gpio2"),
155	PINCTRL_PIN(3, "gpio3"),
156	PINCTRL_PIN(4, "gpio4"),
157	PINCTRL_PIN(5, "gpio5"),
158	PINCTRL_PIN(6, "gpio6"),
159	PINCTRL_PIN(7, "gpio7"),
160	PINCTRL_PIN(8, "gpio8"),
161	PINCTRL_PIN(9, "gpio9"),
162	PINCTRL_PIN(10, "gpio10"),
163	PINCTRL_PIN(11, "gpio11"),
164	PINCTRL_PIN(12, "gpio12"),
165	PINCTRL_PIN(13, "gpio13"),
166	PINCTRL_PIN(14, "gpio14"),
167	PINCTRL_PIN(15, "gpio15"),
168};
169
170static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
171{
172	return 0;
173}
174
175static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
176						unsigned int group)
177{
178	return NULL;
179}
180
181static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
182					unsigned int group,
183					const unsigned int **pins,
184					unsigned int *num_pins)
185{
186	return -ENOTSUPP;
187}
188
189static const struct pinctrl_ops mcp_pinctrl_ops = {
190	.get_groups_count = mcp_pinctrl_get_groups_count,
191	.get_group_name = mcp_pinctrl_get_group_name,
192	.get_group_pins = mcp_pinctrl_get_group_pins,
193#ifdef CONFIG_OF
194	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
195	.dt_free_map = pinconf_generic_dt_free_map,
196#endif
197};
198
199static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
200			      unsigned long *config)
201{
202	struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
203	enum pin_config_param param = pinconf_to_config_param(*config);
204	unsigned int data, status;
205	int ret;
206
207	switch (param) {
208	case PIN_CONFIG_BIAS_PULL_UP:
209		mutex_lock(&mcp->lock);
210		ret = mcp_read(mcp, MCP_GPPU, &data);
211		mutex_unlock(&mcp->lock);
212		if (ret < 0)
213			return ret;
214		status = (data & BIT(pin)) ? 1 : 0;
215		break;
216	default:
217		return -ENOTSUPP;
218	}
219
220	*config = 0;
221
222	return status ? 0 : -EINVAL;
223}
224
225static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
226			      unsigned long *configs, unsigned int num_configs)
227{
228	struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
229	enum pin_config_param param;
230	u32 arg;
231	int ret = 0;
232	int i;
233
234	for (i = 0; i < num_configs; i++) {
235		param = pinconf_to_config_param(configs[i]);
236		arg = pinconf_to_config_argument(configs[i]);
237
238		switch (param) {
239		case PIN_CONFIG_BIAS_PULL_UP:
240			mutex_lock(&mcp->lock);
241			ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
242			mutex_unlock(&mcp->lock);
243			break;
244		default:
245			dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
246			return -ENOTSUPP;
247		}
248	}
249
250	return ret;
251}
252
253static const struct pinconf_ops mcp_pinconf_ops = {
254	.pin_config_get = mcp_pinconf_get,
255	.pin_config_set = mcp_pinconf_set,
256	.is_generic = true,
257};
258
259/*----------------------------------------------------------------------*/
260
261static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
262{
263	struct mcp23s08	*mcp = gpiochip_get_data(chip);
264	int status;
265
266	mutex_lock(&mcp->lock);
267	status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
268	mutex_unlock(&mcp->lock);
269
270	return status;
271}
272
273static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
274{
275	struct mcp23s08	*mcp = gpiochip_get_data(chip);
276	int status, ret;
277
278	mutex_lock(&mcp->lock);
279
280	/* REVISIT reading this clears any IRQ ... */
281	ret = mcp_read(mcp, MCP_GPIO, &status);
282	if (ret < 0)
283		status = 0;
284	else {
285		mcp->cached_gpio = status;
286		status = !!(status & (1 << offset));
287	}
288
289	mutex_unlock(&mcp->lock);
290	return status;
291}
292
293static int mcp23s08_get_multiple(struct gpio_chip *chip,
294				 unsigned long *mask, unsigned long *bits)
295{
296	struct mcp23s08 *mcp = gpiochip_get_data(chip);
297	unsigned int status;
298	int ret;
299
300	mutex_lock(&mcp->lock);
301
302	/* REVISIT reading this clears any IRQ ... */
303	ret = mcp_read(mcp, MCP_GPIO, &status);
304	if (ret < 0)
305		status = 0;
306	else {
307		mcp->cached_gpio = status;
308		*bits = status;
309	}
310
311	mutex_unlock(&mcp->lock);
312	return ret;
313}
314
315static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
316{
317	return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
318}
319
320static int mcp23s08_set(struct gpio_chip *chip, unsigned int offset, int value)
321{
322	struct mcp23s08	*mcp = gpiochip_get_data(chip);
323	unsigned mask = BIT(offset);
324	int ret;
325
326	mutex_lock(&mcp->lock);
327	ret = __mcp23s08_set(mcp, mask, !!value);
328	mutex_unlock(&mcp->lock);
329
330	return ret;
331}
332
333static int mcp23s08_set_multiple(struct gpio_chip *chip,
334				 unsigned long *mask, unsigned long *bits)
335{
336	struct mcp23s08	*mcp = gpiochip_get_data(chip);
337	int ret;
338
339	mutex_lock(&mcp->lock);
340	ret = mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
341	mutex_unlock(&mcp->lock);
342
343	return ret;
344}
345
346static int
347mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
348{
349	struct mcp23s08	*mcp = gpiochip_get_data(chip);
350	unsigned mask = BIT(offset);
351	int status;
352
353	mutex_lock(&mcp->lock);
354	status = __mcp23s08_set(mcp, mask, value);
355	if (status == 0) {
356		status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
357	}
358	mutex_unlock(&mcp->lock);
359	return status;
360}
361
362/*----------------------------------------------------------------------*/
363static irqreturn_t mcp23s08_irq(int irq, void *data)
364{
365	struct mcp23s08 *mcp = data;
366	int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten;
367	bool need_unmask = false;
368	unsigned long int enabled_interrupts;
369	unsigned int child_irq;
370	bool intf_set, intcap_changed, gpio_bit_changed,
371		defval_changed, gpio_set;
372
373	mutex_lock(&mcp->lock);
374	if (mcp_read(mcp, MCP_INTF, &intf))
375		goto unlock;
376
377	if (intf == 0) {
378		/* There is no interrupt pending */
379		goto unlock;
380	}
381
382	if (mcp_read(mcp, MCP_INTCON, &intcon))
383		goto unlock;
384
385	if (mcp_read(mcp, MCP_GPINTEN, &gpinten))
386		goto unlock;
387
388	if (mcp_read(mcp, MCP_DEFVAL, &defval))
389		goto unlock;
390
391	/* Mask level interrupts to avoid their immediate reactivation after clearing */
392	if (intcon) {
393		need_unmask = true;
394		if (mcp_write(mcp, MCP_GPINTEN, gpinten & ~intcon))
395			goto unlock;
396	}
397
398	if (mcp_read(mcp, MCP_INTCAP, &intcap))
399		goto unlock;
400
401	/* This clears the interrupt(configurable on S18) */
402	if (mcp_read(mcp, MCP_GPIO, &gpio))
403		goto unlock;
404
405	gpio_orig = mcp->cached_gpio;
406	mcp->cached_gpio = gpio;
407	mutex_unlock(&mcp->lock);
408
409	dev_dbg(mcp->chip.parent,
410		"intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
411		intcap, intf, gpio_orig, gpio);
412
413	enabled_interrupts = gpinten;
414	for_each_set_bit(i, &enabled_interrupts, mcp->chip.ngpio) {
415		/*
416		 * We must check all of the inputs with enabled interrupts
417		 * on the chip, otherwise we may not notice a change
418		 * on more than one pin.
419		 *
420		 * On at least the mcp23s17, INTCAP is only updated
421		 * one byte at a time(INTCAPA and INTCAPB are
422		 * not written to at the same time - only on a per-bank
423		 * basis).
424		 *
425		 * INTF only contains the single bit that caused the
426		 * interrupt per-bank.  On the mcp23s17, there is
427		 * INTFA and INTFB.  If two pins are changed on the A
428		 * side at the same time, INTF will only have one bit
429		 * set.  If one pin on the A side and one pin on the B
430		 * side are changed at the same time, INTF will have
431		 * two bits set.  Thus, INTF can't be the only check
432		 * to see if the input has changed.
433		 */
434
435		intf_set = intf & BIT(i);
436		if (i < 8 && intf_set)
437			intcap_mask = 0x00FF;
438		else if (i >= 8 && intf_set)
439			intcap_mask = 0xFF00;
440		else
441			intcap_mask = 0x00;
442
443		intcap_changed = (intcap_mask &
444			(intcap & BIT(i))) !=
445			(intcap_mask & (BIT(i) & gpio_orig));
446		gpio_set = BIT(i) & gpio;
447		gpio_bit_changed = (BIT(i) & gpio_orig) !=
448			(BIT(i) & gpio);
449		defval_changed = (BIT(i) & intcon) &&
450			((BIT(i) & gpio) !=
451			(BIT(i) & defval));
452
453		if (((gpio_bit_changed || intcap_changed) &&
454			(BIT(i) & mcp->irq_rise) && gpio_set) ||
455		    ((gpio_bit_changed || intcap_changed) &&
456			(BIT(i) & mcp->irq_fall) && !gpio_set) ||
457		    defval_changed) {
458			child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
459			handle_nested_irq(child_irq);
460		}
461	}
462
463	if (need_unmask) {
464		mutex_lock(&mcp->lock);
465		goto unlock;
466	}
467
468	return IRQ_HANDLED;
469
470unlock:
471	if (need_unmask)
472		if (mcp_write(mcp, MCP_GPINTEN, gpinten))
473			dev_err(mcp->chip.parent, "can't unmask GPINTEN\n");
474
475	mutex_unlock(&mcp->lock);
476	return IRQ_HANDLED;
477}
478
479static void mcp23s08_irq_mask(struct irq_data *data)
480{
481	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
482	struct mcp23s08 *mcp = gpiochip_get_data(gc);
483	unsigned int pos = irqd_to_hwirq(data);
484
485	mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
486	gpiochip_disable_irq(gc, pos);
487}
488
489static void mcp23s08_irq_unmask(struct irq_data *data)
490{
491	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
492	struct mcp23s08 *mcp = gpiochip_get_data(gc);
493	unsigned int pos = irqd_to_hwirq(data);
494
495	gpiochip_enable_irq(gc, pos);
496	mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
497}
498
499static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
500{
501	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
502	struct mcp23s08 *mcp = gpiochip_get_data(gc);
503	unsigned int pos = irqd_to_hwirq(data);
504
505	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
506		mcp_set_bit(mcp, MCP_INTCON, pos, false);
507		mcp->irq_rise |= BIT(pos);
508		mcp->irq_fall |= BIT(pos);
509	} else if (type & IRQ_TYPE_EDGE_RISING) {
510		mcp_set_bit(mcp, MCP_INTCON, pos, false);
511		mcp->irq_rise |= BIT(pos);
512		mcp->irq_fall &= ~BIT(pos);
513	} else if (type & IRQ_TYPE_EDGE_FALLING) {
514		mcp_set_bit(mcp, MCP_INTCON, pos, false);
515		mcp->irq_rise &= ~BIT(pos);
516		mcp->irq_fall |= BIT(pos);
517	} else if (type & IRQ_TYPE_LEVEL_HIGH) {
518		mcp_set_bit(mcp, MCP_INTCON, pos, true);
519		mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
520	} else if (type & IRQ_TYPE_LEVEL_LOW) {
521		mcp_set_bit(mcp, MCP_INTCON, pos, true);
522		mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
523	} else
524		return -EINVAL;
525
526	return 0;
527}
528
529static void mcp23s08_irq_bus_lock(struct irq_data *data)
530{
531	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
532	struct mcp23s08 *mcp = gpiochip_get_data(gc);
533
534	mutex_lock(&mcp->lock);
535	regcache_cache_only(mcp->regmap, true);
536}
537
538static void mcp23s08_irq_bus_unlock(struct irq_data *data)
539{
540	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
541	struct mcp23s08 *mcp = gpiochip_get_data(gc);
542
543	regcache_cache_only(mcp->regmap, false);
544	regcache_sync(mcp->regmap);
545
546	mutex_unlock(&mcp->lock);
547}
548
549static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
550{
551	struct gpio_chip *chip = &mcp->chip;
552	int err;
553	unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
554
555	if (mcp->irq_active_high)
556		irqflags |= IRQF_TRIGGER_HIGH;
557	else
558		irqflags |= IRQF_TRIGGER_LOW;
559
560	err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
561					mcp23s08_irq,
562					irqflags, dev_name(chip->parent), mcp);
563	if (err != 0) {
564		dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
565			mcp->irq, err);
566		return err;
567	}
568
569	return 0;
570}
571
572static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
573{
574	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
575	struct mcp23s08 *mcp = gpiochip_get_data(gc);
576
577	seq_puts(p, dev_name(mcp->dev));
578}
579
580static const struct irq_chip mcp23s08_irq_chip = {
581	.irq_mask = mcp23s08_irq_mask,
582	.irq_unmask = mcp23s08_irq_unmask,
583	.irq_set_type = mcp23s08_irq_set_type,
584	.irq_bus_lock = mcp23s08_irq_bus_lock,
585	.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
586	.irq_print_chip = mcp23s08_irq_print_chip,
587	.flags = IRQCHIP_IMMUTABLE,
588	GPIOCHIP_IRQ_RESOURCE_HELPERS,
589};
590
591/*----------------------------------------------------------------------*/
592
593int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
594		       unsigned int addr, unsigned int type, unsigned int base)
595{
596	int status, ret;
597	bool mirror = false;
598	bool open_drain = false;
599
600	mutex_init(&mcp->lock);
601
602	mcp->dev = dev;
603	mcp->addr = addr;
604
605	mcp->irq_active_high = false;
606
607	mcp->chip.direction_input = mcp23s08_direction_input;
608	mcp->chip.get = mcp23s08_get;
609	mcp->chip.get_multiple = mcp23s08_get_multiple;
610	mcp->chip.direction_output = mcp23s08_direction_output;
611	mcp->chip.set = mcp23s08_set;
612	mcp->chip.set_multiple = mcp23s08_set_multiple;
613
614	mcp->chip.base = base;
615	mcp->chip.can_sleep = true;
616	mcp->chip.parent = dev;
617	mcp->chip.owner = THIS_MODULE;
618
619	mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
620
621	/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
622	 * and MCP_IOCON.HAEN = 1, so we work with all chips.
623	 */
624
625	ret = mcp_read(mcp, MCP_IOCON, &status);
626	if (ret < 0)
627		return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
628
629	mcp->irq_controller =
630		device_property_read_bool(dev, "interrupt-controller");
631	if (mcp->irq && mcp->irq_controller) {
632		mcp->irq_active_high =
633			device_property_read_bool(dev,
634					      "microchip,irq-active-high");
635
636		mirror = device_property_read_bool(dev, "microchip,irq-mirror");
637		open_drain = device_property_read_bool(dev, "drive-open-drain");
638	}
639
640	if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
641	     mcp->irq_active_high || open_drain) {
642		/* mcp23s17 has IOCON twice, make sure they are in sync */
643		status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
644		status |= IOCON_HAEN | (IOCON_HAEN << 8);
645		if (mcp->irq_active_high)
646			status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
647		else
648			status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
649
650		if (mirror)
651			status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
652
653		if (open_drain)
654			status |= IOCON_ODR | (IOCON_ODR << 8);
655
656		if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
657			status |= IOCON_INTCC | (IOCON_INTCC << 8);
658
659		ret = mcp_write(mcp, MCP_IOCON, status);
660		if (ret < 0)
661			return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
662	}
663
664	if (mcp->irq && mcp->irq_controller) {
665		struct gpio_irq_chip *girq = &mcp->chip.irq;
666
667		/*
668		 * Disable all pin interrupts, to prevent the interrupt handler from
669		 * calling nested handlers for any currently-enabled interrupts that
670		 * do not (yet) have an actual handler.
671		 */
672		ret = mcp_write(mcp, MCP_GPINTEN, 0);
673		if (ret < 0)
674			return dev_err_probe(dev, ret, "can't disable interrupts\n");
675
676		gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
677		/* This will let us handle the parent IRQ in the driver */
678		girq->parent_handler = NULL;
679		girq->num_parents = 0;
680		girq->parents = NULL;
681		girq->default_type = IRQ_TYPE_NONE;
682		girq->handler = handle_simple_irq;
683		girq->threaded = true;
684	}
685
686	ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
687	if (ret < 0)
688		return dev_err_probe(dev, ret, "can't add GPIO chip\n");
689
690	mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
691	mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
692	mcp->pinctrl_desc.npins = mcp->chip.ngpio;
693	if (mcp->pinctrl_desc.npins == 8)
694		mcp->pinctrl_desc.pins = mcp23x08_pins;
695	else if (mcp->pinctrl_desc.npins == 16)
696		mcp->pinctrl_desc.pins = mcp23x17_pins;
697	mcp->pinctrl_desc.owner = THIS_MODULE;
698
699	mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
700	if (IS_ERR(mcp->pctldev))
701		return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
702
703	if (mcp->irq) {
704		ret = mcp23s08_irq_setup(mcp);
705		if (ret)
706			return dev_err_probe(dev, ret, "can't setup IRQ\n");
707	}
708
709	return 0;
710}
711EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
712
713MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");
714MODULE_LICENSE("GPL");