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pinctrl-keembay.c
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linux-6.19.14/drivers/pinctrl/pinctrl-keembay.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (C) 2020 Intel Corporation */ 3 4#include <linux/bitfield.h> 5#include <linux/bitops.h> 6#include <linux/gpio/driver.h> 7#include <linux/interrupt.h> 8#include <linux/io.h> 9#include <linux/module.h> 10 11#include <linux/pinctrl/pinconf.h> 12#include <linux/pinctrl/pinconf-generic.h> 13#include <linux/pinctrl/pinctrl.h> 14#include <linux/pinctrl/pinmux.h> 15 16#include <linux/platform_device.h> 17 18#include "core.h" 19#include "pinmux.h" 20 21/* GPIO data registers' offsets */ 22#define KEEMBAY_GPIO_DATA_OUT 0x000 23#define KEEMBAY_GPIO_DATA_IN 0x020 24#define KEEMBAY_GPIO_DATA_IN_RAW 0x040 25#define KEEMBAY_GPIO_DATA_HIGH 0x060 26#define KEEMBAY_GPIO_DATA_LOW 0x080 27 28/* GPIO Interrupt and mode registers' offsets */ 29#define KEEMBAY_GPIO_INT_CFG 0x000 30#define KEEMBAY_GPIO_MODE 0x070 31 32/* GPIO mode register bit fields */ 33#define KEEMBAY_GPIO_MODE_PULLUP_MASK GENMASK(13, 12) 34#define KEEMBAY_GPIO_MODE_DRIVE_MASK GENMASK(8, 7) 35#define KEEMBAY_GPIO_MODE_INV_MASK GENMASK(5, 4) 36#define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0) 37#define KEEMBAY_GPIO_MODE_DIR_OVR BIT(15) 38#define KEEMBAY_GPIO_MODE_REN BIT(11) 39#define KEEMBAY_GPIO_MODE_SCHMITT_EN BIT(10) 40#define KEEMBAY_GPIO_MODE_SLEW_RATE BIT(9) 41#define KEEMBAY_GPIO_IRQ_ENABLE BIT(7) 42#define KEEMBAY_GPIO_MODE_DIR BIT(3) 43#define KEEMBAY_GPIO_MODE_DEFAULT 0x7 44#define KEEMBAY_GPIO_MODE_INV_VAL 0x3 45 46#define KEEMBAY_GPIO_DISABLE 0 47#define KEEMBAY_GPIO_PULL_UP 1 48#define KEEMBAY_GPIO_PULL_DOWN 2 49#define KEEMBAY_GPIO_BUS_HOLD 3 50#define KEEMBAY_GPIO_NUM_IRQ 8 51#define KEEMBAY_GPIO_MAX_PER_IRQ 4 52#define KEEMBAY_GPIO_MAX_PER_REG 32 53#define KEEMBAY_GPIO_MIN_STRENGTH 2 54#define KEEMBAY_GPIO_MAX_STRENGTH 12 55#define KEEMBAY_GPIO_SENSE_LOW (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING) 56 57/* GPIO reg address calculation */ 58#define KEEMBAY_GPIO_REG_OFFSET(pin) ((pin) * 4) 59 60/** 61 * struct keembay_mux_desc - Mux properties of each GPIO pin 62 * @mode: Pin mode when operating in this function 63 * @name: Pin function name 64 */ 65struct keembay_mux_desc { 66 u8 mode; 67 const char *name; 68}; 69 70#define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) { \ 71 .number = pin_number, \ 72 .name = pin_name, \ 73 .drv_data = &(struct keembay_mux_desc[]) { \ 74 __VA_ARGS__, { } }, \ 75} \ 76 77#define KEEMBAY_MUX(pin_mode, pin_function) { \ 78 .mode = pin_mode, \ 79 .name = pin_function, \ 80} \ 81 82/** 83 * struct keembay_gpio_irq - Config of each GPIO Interrupt sources 84 * @source: Interrupt source number (0 - 7) 85 * @line: Actual Interrupt line number 86 * @pins: Array of GPIO pins using this Interrupt line 87 * @trigger: Interrupt trigger type for this line 88 * @num_share: Number of pins currently using this Interrupt line 89 */ 90struct keembay_gpio_irq { 91 unsigned int source; 92 unsigned int line; 93 unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ]; 94 unsigned int trigger; 95 unsigned int num_share; 96}; 97 98/** 99 * struct keembay_pinctrl - Intel Keembay pinctrl structure 100 * @pctrl: Pointer to the pin controller device 101 * @base0: First register base address 102 * @base1: Second register base address 103 * @dev: Pointer to the device structure 104 * @chip: GPIO chip used by this pin controller 105 * @soc: Pin control configuration data based on SoC 106 * @lock: Spinlock to protect various gpio config register access 107 * @ngroups: Number of pin groups available 108 * @nfuncs: Number of pin functions available 109 * @npins: Number of GPIO pins available 110 * @irq: Store Interrupt source 111 * @max_gpios_level_type: Store max level trigger type 112 * @max_gpios_edge_type: Store max edge trigger type 113 */ 114struct keembay_pinctrl { 115 struct pinctrl_dev *pctrl; 116 void __iomem *base0; 117 void __iomem *base1; 118 struct device *dev; 119 struct gpio_chip chip; 120 const struct keembay_pin_soc *soc; 121 raw_spinlock_t lock; 122 unsigned int ngroups; 123 unsigned int nfuncs; 124 unsigned int npins; 125 struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ]; 126 int max_gpios_level_type; 127 int max_gpios_edge_type; 128}; 129 130/** 131 * struct keembay_pin_soc - Pin control config data based on SoC 132 * @pins: Pin description structure 133 */ 134struct keembay_pin_soc { 135 const struct pinctrl_pin_desc *pins; 136}; 137 138struct keembay_pinfunction { 139 struct pinfunction func; 140 u8 mux_mode; 141}; 142 143static const struct pinctrl_pin_desc keembay_pins[] = { 144 KEEMBAY_PIN_DESC(0, "GPIO0", 145 KEEMBAY_MUX(0x0, "I2S0_M0"), 146 KEEMBAY_MUX(0x1, "SD0_M1"), 147 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 148 KEEMBAY_MUX(0x3, "I2C0_M3"), 149 KEEMBAY_MUX(0x4, "CAM_M4"), 150 KEEMBAY_MUX(0x5, "ETH_M5"), 151 KEEMBAY_MUX(0x6, "LCD_M6"), 152 KEEMBAY_MUX(0x7, "GPIO_M7")), 153 KEEMBAY_PIN_DESC(1, "GPIO1", 154 KEEMBAY_MUX(0x0, "I2S0_M0"), 155 KEEMBAY_MUX(0x1, "SD0_M1"), 156 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 157 KEEMBAY_MUX(0x3, "I2C0_M3"), 158 KEEMBAY_MUX(0x4, "CAM_M4"), 159 KEEMBAY_MUX(0x5, "ETH_M5"), 160 KEEMBAY_MUX(0x6, "LCD_M6"), 161 KEEMBAY_MUX(0x7, "GPIO_M7")), 162 KEEMBAY_PIN_DESC(2, "GPIO2", 163 KEEMBAY_MUX(0x0, "I2S0_M0"), 164 KEEMBAY_MUX(0x1, "I2S0_M1"), 165 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 166 KEEMBAY_MUX(0x3, "I2C1_M3"), 167 KEEMBAY_MUX(0x4, "CAM_M4"), 168 KEEMBAY_MUX(0x5, "ETH_M5"), 169 KEEMBAY_MUX(0x6, "LCD_M6"), 170 KEEMBAY_MUX(0x7, "GPIO_M7")), 171 KEEMBAY_PIN_DESC(3, "GPIO3", 172 KEEMBAY_MUX(0x0, "I2S0_M0"), 173 KEEMBAY_MUX(0x1, "I2S0_M1"), 174 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 175 KEEMBAY_MUX(0x3, "I2C1_M3"), 176 KEEMBAY_MUX(0x4, "CAM_M4"), 177 KEEMBAY_MUX(0x5, "ETH_M5"), 178 KEEMBAY_MUX(0x6, "LCD_M6"), 179 KEEMBAY_MUX(0x7, "GPIO_M7")), 180 KEEMBAY_PIN_DESC(4, "GPIO4", 181 KEEMBAY_MUX(0x0, "I2S0_M0"), 182 KEEMBAY_MUX(0x1, "I2S0_M1"), 183 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 184 KEEMBAY_MUX(0x3, "I2C2_M3"), 185 KEEMBAY_MUX(0x4, "CAM_M4"), 186 KEEMBAY_MUX(0x5, "ETH_M5"), 187 KEEMBAY_MUX(0x6, "LCD_M6"), 188 KEEMBAY_MUX(0x7, "GPIO_M7")), 189 KEEMBAY_PIN_DESC(5, "GPIO5", 190 KEEMBAY_MUX(0x0, "I2S0_M0"), 191 KEEMBAY_MUX(0x1, "I2S0_M1"), 192 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 193 KEEMBAY_MUX(0x3, "I2C2_M3"), 194 KEEMBAY_MUX(0x4, "CAM_M4"), 195 KEEMBAY_MUX(0x5, "ETH_M5"), 196 KEEMBAY_MUX(0x6, "LCD_M6"), 197 KEEMBAY_MUX(0x7, "GPIO_M7")), 198 KEEMBAY_PIN_DESC(6, "GPIO6", 199 KEEMBAY_MUX(0x0, "I2S1_M0"), 200 KEEMBAY_MUX(0x1, "SD0_M1"), 201 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 202 KEEMBAY_MUX(0x3, "I2C3_M3"), 203 KEEMBAY_MUX(0x4, "CAM_M4"), 204 KEEMBAY_MUX(0x5, "ETH_M5"), 205 KEEMBAY_MUX(0x6, "LCD_M6"), 206 KEEMBAY_MUX(0x7, "GPIO_M7")), 207 KEEMBAY_PIN_DESC(7, "GPIO7", 208 KEEMBAY_MUX(0x0, "I2S1_M0"), 209 KEEMBAY_MUX(0x1, "SD0_M1"), 210 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 211 KEEMBAY_MUX(0x3, "I2C3_M3"), 212 KEEMBAY_MUX(0x4, "CAM_M4"), 213 KEEMBAY_MUX(0x5, "ETH_M5"), 214 KEEMBAY_MUX(0x6, "LCD_M6"), 215 KEEMBAY_MUX(0x7, "GPIO_M7")), 216 KEEMBAY_PIN_DESC(8, "GPIO8", 217 KEEMBAY_MUX(0x0, "I2S1_M0"), 218 KEEMBAY_MUX(0x1, "I2S1_M1"), 219 KEEMBAY_MUX(0x2, "SLVDS0_M2"), 220 KEEMBAY_MUX(0x3, "UART0_M3"), 221 KEEMBAY_MUX(0x4, "CAM_M4"), 222 KEEMBAY_MUX(0x5, "ETH_M5"), 223 KEEMBAY_MUX(0x6, "LCD_M6"), 224 KEEMBAY_MUX(0x7, "GPIO_M7")), 225 KEEMBAY_PIN_DESC(9, "GPIO9", 226 KEEMBAY_MUX(0x0, "I2S1_M0"), 227 KEEMBAY_MUX(0x1, "I2S1_M1"), 228 KEEMBAY_MUX(0x2, "PWM_M2"), 229 KEEMBAY_MUX(0x3, "UART0_M3"), 230 KEEMBAY_MUX(0x4, "CAM_M4"), 231 KEEMBAY_MUX(0x5, "ETH_M5"), 232 KEEMBAY_MUX(0x6, "LCD_M6"), 233 KEEMBAY_MUX(0x7, "GPIO_M7")), 234 KEEMBAY_PIN_DESC(10, "GPIO10", 235 KEEMBAY_MUX(0x0, "I2S2_M0"), 236 KEEMBAY_MUX(0x1, "SD0_M1"), 237 KEEMBAY_MUX(0x2, "PWM_M2"), 238 KEEMBAY_MUX(0x3, "UART0_M3"), 239 KEEMBAY_MUX(0x4, "CAM_M4"), 240 KEEMBAY_MUX(0x5, "ETH_M5"), 241 KEEMBAY_MUX(0x6, "LCD_M6"), 242 KEEMBAY_MUX(0x7, "GPIO_M7")), 243 KEEMBAY_PIN_DESC(11, "GPIO11", 244 KEEMBAY_MUX(0x0, "I2S2_M0"), 245 KEEMBAY_MUX(0x1, "SD0_M1"), 246 KEEMBAY_MUX(0x2, "PWM_M2"), 247 KEEMBAY_MUX(0x3, "UART0_M3"), 248 KEEMBAY_MUX(0x4, "CAM_M4"), 249 KEEMBAY_MUX(0x5, "ETH_M5"), 250 KEEMBAY_MUX(0x6, "LCD_M6"), 251 KEEMBAY_MUX(0x7, "GPIO_M7")), 252 KEEMBAY_PIN_DESC(12, "GPIO12", 253 KEEMBAY_MUX(0x0, "I2S2_M0"), 254 KEEMBAY_MUX(0x1, "I2S2_M1"), 255 KEEMBAY_MUX(0x2, "PWM_M2"), 256 KEEMBAY_MUX(0x3, "SPI0_M3"), 257 KEEMBAY_MUX(0x4, "CAM_M4"), 258 KEEMBAY_MUX(0x5, "ETH_M5"), 259 KEEMBAY_MUX(0x6, "LCD_M6"), 260 KEEMBAY_MUX(0x7, "GPIO_M7")), 261 KEEMBAY_PIN_DESC(13, "GPIO13", 262 KEEMBAY_MUX(0x0, "I2S2_M0"), 263 KEEMBAY_MUX(0x1, "I2S2_M1"), 264 KEEMBAY_MUX(0x2, "PWM_M2"), 265 KEEMBAY_MUX(0x3, "SPI0_M3"), 266 KEEMBAY_MUX(0x4, "CAM_M4"), 267 KEEMBAY_MUX(0x5, "ETH_M5"), 268 KEEMBAY_MUX(0x6, "LCD_M6"), 269 KEEMBAY_MUX(0x7, "GPIO_M7")), 270 KEEMBAY_PIN_DESC(14, "GPIO14", 271 KEEMBAY_MUX(0x0, "UART0_M0"), 272 KEEMBAY_MUX(0x1, "I2S3_M1"), 273 KEEMBAY_MUX(0x2, "PWM_M2"), 274 KEEMBAY_MUX(0x3, "SD1_M3"), 275 KEEMBAY_MUX(0x4, "CAM_M4"), 276 KEEMBAY_MUX(0x5, "ETH_M5"), 277 KEEMBAY_MUX(0x6, "LCD_M6"), 278 KEEMBAY_MUX(0x7, "GPIO_M7")), 279 KEEMBAY_PIN_DESC(15, "GPIO15", 280 KEEMBAY_MUX(0x0, "UART0_M0"), 281 KEEMBAY_MUX(0x1, "I2S3_M1"), 282 KEEMBAY_MUX(0x2, "UART0_M2"), 283 KEEMBAY_MUX(0x3, "SD1_M3"), 284 KEEMBAY_MUX(0x4, "CAM_M4"), 285 KEEMBAY_MUX(0x5, "SPI1_M5"), 286 KEEMBAY_MUX(0x6, "LCD_M6"), 287 KEEMBAY_MUX(0x7, "GPIO_M7")), 288 KEEMBAY_PIN_DESC(16, "GPIO16", 289 KEEMBAY_MUX(0x0, "UART0_M0"), 290 KEEMBAY_MUX(0x1, "I2S3_M1"), 291 KEEMBAY_MUX(0x2, "UART0_M2"), 292 KEEMBAY_MUX(0x3, "SD1_M3"), 293 KEEMBAY_MUX(0x4, "CAM_M4"), 294 KEEMBAY_MUX(0x5, "SPI1_M5"), 295 KEEMBAY_MUX(0x6, "LCD_M6"), 296 KEEMBAY_MUX(0x7, "GPIO_M7")), 297 KEEMBAY_PIN_DESC(17, "GPIO17", 298 KEEMBAY_MUX(0x0, "UART0_M0"), 299 KEEMBAY_MUX(0x1, "I2S3_M1"), 300 KEEMBAY_MUX(0x2, "I2S3_M2"), 301 KEEMBAY_MUX(0x3, "SD1_M3"), 302 KEEMBAY_MUX(0x4, "CAM_M4"), 303 KEEMBAY_MUX(0x5, "SPI1_M5"), 304 KEEMBAY_MUX(0x6, "LCD_M6"), 305 KEEMBAY_MUX(0x7, "GPIO_M7")), 306 KEEMBAY_PIN_DESC(18, "GPIO18", 307 KEEMBAY_MUX(0x0, "UART1_M0"), 308 KEEMBAY_MUX(0x1, "SPI0_M1"), 309 KEEMBAY_MUX(0x2, "I2S3_M2"), 310 KEEMBAY_MUX(0x3, "SD1_M3"), 311 KEEMBAY_MUX(0x4, "CAM_M4"), 312 KEEMBAY_MUX(0x5, "SPI1_M5"), 313 KEEMBAY_MUX(0x6, "LCD_M6"), 314 KEEMBAY_MUX(0x7, "GPIO_M7")), 315 KEEMBAY_PIN_DESC(19, "GPIO19", 316 KEEMBAY_MUX(0x0, "UART1_M0"), 317 KEEMBAY_MUX(0x1, "LCD_M1"), 318 KEEMBAY_MUX(0x2, "DEBUG_M2"), 319 KEEMBAY_MUX(0x3, "SD1_M3"), 320 KEEMBAY_MUX(0x4, "CAM_M4"), 321 KEEMBAY_MUX(0x5, "SPI1_M5"), 322 KEEMBAY_MUX(0x6, "LCD_M6"), 323 KEEMBAY_MUX(0x7, "GPIO_M7")), 324 KEEMBAY_PIN_DESC(20, "GPIO20", 325 KEEMBAY_MUX(0x0, "UART1_M0"), 326 KEEMBAY_MUX(0x1, "LCD_M1"), 327 KEEMBAY_MUX(0x2, "DEBUG_M2"), 328 KEEMBAY_MUX(0x3, "CPR_M3"), 329 KEEMBAY_MUX(0x4, "CAM_M4"), 330 KEEMBAY_MUX(0x5, "SPI1_M5"), 331 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 332 KEEMBAY_MUX(0x7, "GPIO_M7")), 333 KEEMBAY_PIN_DESC(21, "GPIO21", 334 KEEMBAY_MUX(0x0, "UART1_M0"), 335 KEEMBAY_MUX(0x1, "LCD_M1"), 336 KEEMBAY_MUX(0x2, "DEBUG_M2"), 337 KEEMBAY_MUX(0x3, "CPR_M3"), 338 KEEMBAY_MUX(0x4, "CAM_M4"), 339 KEEMBAY_MUX(0x5, "I3C0_M5"), 340 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 341 KEEMBAY_MUX(0x7, "GPIO_M7")), 342 KEEMBAY_PIN_DESC(22, "GPIO22", 343 KEEMBAY_MUX(0x0, "I2C0_M0"), 344 KEEMBAY_MUX(0x1, "UART2_M1"), 345 KEEMBAY_MUX(0x2, "DEBUG_M2"), 346 KEEMBAY_MUX(0x3, "CPR_M3"), 347 KEEMBAY_MUX(0x4, "CAM_M4"), 348 KEEMBAY_MUX(0x5, "I3C0_M5"), 349 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 350 KEEMBAY_MUX(0x7, "GPIO_M7")), 351 KEEMBAY_PIN_DESC(23, "GPIO23", 352 KEEMBAY_MUX(0x0, "I2C0_M0"), 353 KEEMBAY_MUX(0x1, "UART2_M1"), 354 KEEMBAY_MUX(0x2, "DEBUG_M2"), 355 KEEMBAY_MUX(0x3, "CPR_M3"), 356 KEEMBAY_MUX(0x4, "CAM_M4"), 357 KEEMBAY_MUX(0x5, "I3C1_M5"), 358 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 359 KEEMBAY_MUX(0x7, "GPIO_M7")), 360 KEEMBAY_PIN_DESC(24, "GPIO24", 361 KEEMBAY_MUX(0x0, "I2C1_M0"), 362 KEEMBAY_MUX(0x1, "UART2_M1"), 363 KEEMBAY_MUX(0x2, "DEBUG_M2"), 364 KEEMBAY_MUX(0x3, "CPR_M3"), 365 KEEMBAY_MUX(0x4, "CAM_M4"), 366 KEEMBAY_MUX(0x5, "I3C1_M5"), 367 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 368 KEEMBAY_MUX(0x7, "GPIO_M7")), 369 KEEMBAY_PIN_DESC(25, "GPIO25", 370 KEEMBAY_MUX(0x0, "I2C1_M0"), 371 KEEMBAY_MUX(0x1, "UART2_M1"), 372 KEEMBAY_MUX(0x2, "SPI0_M2"), 373 KEEMBAY_MUX(0x3, "CPR_M3"), 374 KEEMBAY_MUX(0x4, "CAM_M4"), 375 KEEMBAY_MUX(0x5, "I3C2_M5"), 376 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 377 KEEMBAY_MUX(0x7, "GPIO_M7")), 378 KEEMBAY_PIN_DESC(26, "GPIO26", 379 KEEMBAY_MUX(0x0, "SPI0_M0"), 380 KEEMBAY_MUX(0x1, "I2C2_M1"), 381 KEEMBAY_MUX(0x2, "UART0_M2"), 382 KEEMBAY_MUX(0x3, "DSU_M3"), 383 KEEMBAY_MUX(0x4, "CAM_M4"), 384 KEEMBAY_MUX(0x5, "I3C2_M5"), 385 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 386 KEEMBAY_MUX(0x7, "GPIO_M7")), 387 KEEMBAY_PIN_DESC(27, "GPIO27", 388 KEEMBAY_MUX(0x0, "SPI0_M0"), 389 KEEMBAY_MUX(0x1, "I2C2_M1"), 390 KEEMBAY_MUX(0x2, "UART0_M2"), 391 KEEMBAY_MUX(0x3, "DSU_M3"), 392 KEEMBAY_MUX(0x4, "CAM_M4"), 393 KEEMBAY_MUX(0x5, "I3C0_M5"), 394 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 395 KEEMBAY_MUX(0x7, "GPIO_M7")), 396 KEEMBAY_PIN_DESC(28, "GPIO28", 397 KEEMBAY_MUX(0x0, "SPI0_M0"), 398 KEEMBAY_MUX(0x1, "I2C3_M1"), 399 KEEMBAY_MUX(0x2, "UART0_M2"), 400 KEEMBAY_MUX(0x3, "PWM_M3"), 401 KEEMBAY_MUX(0x4, "CAM_M4"), 402 KEEMBAY_MUX(0x5, "I3C1_M5"), 403 KEEMBAY_MUX(0x6, "SLVDS0_M6"), 404 KEEMBAY_MUX(0x7, "GPIO_M7")), 405 KEEMBAY_PIN_DESC(29, "GPIO29", 406 KEEMBAY_MUX(0x0, "SPI0_M0"), 407 KEEMBAY_MUX(0x1, "I2C3_M1"), 408 KEEMBAY_MUX(0x2, "UART0_M2"), 409 KEEMBAY_MUX(0x3, "PWM_M3"), 410 KEEMBAY_MUX(0x4, "CAM_M4"), 411 KEEMBAY_MUX(0x5, "I3C2_M5"), 412 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 413 KEEMBAY_MUX(0x7, "GPIO_M7")), 414 KEEMBAY_PIN_DESC(30, "GPIO30", 415 KEEMBAY_MUX(0x0, "SPI0_M0"), 416 KEEMBAY_MUX(0x1, "I2S0_M1"), 417 KEEMBAY_MUX(0x2, "I2C4_M2"), 418 KEEMBAY_MUX(0x3, "PWM_M3"), 419 KEEMBAY_MUX(0x4, "CAM_M4"), 420 KEEMBAY_MUX(0x5, "LCD_M5"), 421 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 422 KEEMBAY_MUX(0x7, "GPIO_M7")), 423 KEEMBAY_PIN_DESC(31, "GPIO31", 424 KEEMBAY_MUX(0x0, "SPI0_M0"), 425 KEEMBAY_MUX(0x1, "I2S0_M1"), 426 KEEMBAY_MUX(0x2, "I2C4_M2"), 427 KEEMBAY_MUX(0x3, "PWM_M3"), 428 KEEMBAY_MUX(0x4, "CAM_M4"), 429 KEEMBAY_MUX(0x5, "UART1_M5"), 430 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 431 KEEMBAY_MUX(0x7, "GPIO_M7")), 432 KEEMBAY_PIN_DESC(32, "GPIO32", 433 KEEMBAY_MUX(0x0, "SD0_M0"), 434 KEEMBAY_MUX(0x1, "SPI0_M1"), 435 KEEMBAY_MUX(0x2, "UART1_M2"), 436 KEEMBAY_MUX(0x3, "PWM_M3"), 437 KEEMBAY_MUX(0x4, "CAM_M4"), 438 KEEMBAY_MUX(0x5, "PCIE_M5"), 439 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 440 KEEMBAY_MUX(0x7, "GPIO_M7")), 441 KEEMBAY_PIN_DESC(33, "GPIO33", 442 KEEMBAY_MUX(0x0, "SD0_M0"), 443 KEEMBAY_MUX(0x1, "SPI0_M1"), 444 KEEMBAY_MUX(0x2, "UART1_M2"), 445 KEEMBAY_MUX(0x3, "PWM_M3"), 446 KEEMBAY_MUX(0x4, "CAM_M4"), 447 KEEMBAY_MUX(0x5, "PCIE_M5"), 448 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 449 KEEMBAY_MUX(0x7, "GPIO_M7")), 450 KEEMBAY_PIN_DESC(34, "GPIO34", 451 KEEMBAY_MUX(0x0, "SD0_M0"), 452 KEEMBAY_MUX(0x1, "SPI0_M1"), 453 KEEMBAY_MUX(0x2, "I2C0_M2"), 454 KEEMBAY_MUX(0x3, "UART1_M3"), 455 KEEMBAY_MUX(0x4, "CAM_M4"), 456 KEEMBAY_MUX(0x5, "I2S0_M5"), 457 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 458 KEEMBAY_MUX(0x7, "GPIO_M7")), 459 KEEMBAY_PIN_DESC(35, "GPIO35", 460 KEEMBAY_MUX(0x0, "SD0_M0"), 461 KEEMBAY_MUX(0x1, "PCIE_M1"), 462 KEEMBAY_MUX(0x2, "I2C0_M2"), 463 KEEMBAY_MUX(0x3, "UART1_M3"), 464 KEEMBAY_MUX(0x4, "CAM_M4"), 465 KEEMBAY_MUX(0x5, "I2S0_M5"), 466 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 467 KEEMBAY_MUX(0x7, "GPIO_M7")), 468 KEEMBAY_PIN_DESC(36, "GPIO36", 469 KEEMBAY_MUX(0x0, "SD0_M0"), 470 KEEMBAY_MUX(0x1, "SPI3_M1"), 471 KEEMBAY_MUX(0x2, "I2C1_M2"), 472 KEEMBAY_MUX(0x3, "DEBUG_M3"), 473 KEEMBAY_MUX(0x4, "CAM_M4"), 474 KEEMBAY_MUX(0x5, "I2S0_M5"), 475 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 476 KEEMBAY_MUX(0x7, "GPIO_M7")), 477 KEEMBAY_PIN_DESC(37, "GPIO37", 478 KEEMBAY_MUX(0x0, "SD0_M0"), 479 KEEMBAY_MUX(0x1, "SPI3_M1"), 480 KEEMBAY_MUX(0x2, "I2C1_M2"), 481 KEEMBAY_MUX(0x3, "DEBUG_M3"), 482 KEEMBAY_MUX(0x4, "CAM_M4"), 483 KEEMBAY_MUX(0x5, "I2S0_M5"), 484 KEEMBAY_MUX(0x6, "SLVDS1_M6"), 485 KEEMBAY_MUX(0x7, "GPIO_M7")), 486 KEEMBAY_PIN_DESC(38, "GPIO38", 487 KEEMBAY_MUX(0x0, "I3C1_M0"), 488 KEEMBAY_MUX(0x1, "SPI3_M1"), 489 KEEMBAY_MUX(0x2, "UART3_M2"), 490 KEEMBAY_MUX(0x3, "DEBUG_M3"), 491 KEEMBAY_MUX(0x4, "CAM_M4"), 492 KEEMBAY_MUX(0x5, "LCD_M5"), 493 KEEMBAY_MUX(0x6, "I2C2_M6"), 494 KEEMBAY_MUX(0x7, "GPIO_M7")), 495 KEEMBAY_PIN_DESC(39, "GPIO39", 496 KEEMBAY_MUX(0x0, "I3C1_M0"), 497 KEEMBAY_MUX(0x1, "SPI3_M1"), 498 KEEMBAY_MUX(0x2, "UART3_M2"), 499 KEEMBAY_MUX(0x3, "DEBUG_M3"), 500 KEEMBAY_MUX(0x4, "CAM_M4"), 501 KEEMBAY_MUX(0x5, "LCD_M5"), 502 KEEMBAY_MUX(0x6, "I2C2_M6"), 503 KEEMBAY_MUX(0x7, "GPIO_M7")), 504 KEEMBAY_PIN_DESC(40, "GPIO40", 505 KEEMBAY_MUX(0x0, "I2S2_M0"), 506 KEEMBAY_MUX(0x1, "SPI3_M1"), 507 KEEMBAY_MUX(0x2, "UART3_M2"), 508 KEEMBAY_MUX(0x3, "DEBUG_M3"), 509 KEEMBAY_MUX(0x4, "CAM_M4"), 510 KEEMBAY_MUX(0x5, "LCD_M5"), 511 KEEMBAY_MUX(0x6, "I2C3_M6"), 512 KEEMBAY_MUX(0x7, "GPIO_M7")), 513 KEEMBAY_PIN_DESC(41, "GPIO41", 514 KEEMBAY_MUX(0x0, "ETH_M0"), 515 KEEMBAY_MUX(0x1, "SPI3_M1"), 516 KEEMBAY_MUX(0x2, "SPI3_M2"), 517 KEEMBAY_MUX(0x3, "DEBUG_M3"), 518 KEEMBAY_MUX(0x4, "CAM_M4"), 519 KEEMBAY_MUX(0x5, "LCD_M5"), 520 KEEMBAY_MUX(0x6, "I2C3_M6"), 521 KEEMBAY_MUX(0x7, "GPIO_M7")), 522 KEEMBAY_PIN_DESC(42, "GPIO42", 523 KEEMBAY_MUX(0x0, "ETH_M0"), 524 KEEMBAY_MUX(0x1, "SD1_M1"), 525 KEEMBAY_MUX(0x2, "SPI3_M2"), 526 KEEMBAY_MUX(0x3, "CPR_M3"), 527 KEEMBAY_MUX(0x4, "CAM_M4"), 528 KEEMBAY_MUX(0x5, "LCD_M5"), 529 KEEMBAY_MUX(0x6, "I2C4_M6"), 530 KEEMBAY_MUX(0x7, "GPIO_M7")), 531 KEEMBAY_PIN_DESC(43, "GPIO43", 532 KEEMBAY_MUX(0x0, "ETH_M0"), 533 KEEMBAY_MUX(0x1, "SD1_M1"), 534 KEEMBAY_MUX(0x2, "SPI3_M2"), 535 KEEMBAY_MUX(0x3, "CPR_M3"), 536 KEEMBAY_MUX(0x4, "I2S0_M4"), 537 KEEMBAY_MUX(0x5, "LCD_M5"), 538 KEEMBAY_MUX(0x6, "I2C4_M6"), 539 KEEMBAY_MUX(0x7, "GPIO_M7")), 540 KEEMBAY_PIN_DESC(44, "GPIO44", 541 KEEMBAY_MUX(0x0, "ETH_M0"), 542 KEEMBAY_MUX(0x1, "SD1_M1"), 543 KEEMBAY_MUX(0x2, "SPI0_M2"), 544 KEEMBAY_MUX(0x3, "CPR_M3"), 545 KEEMBAY_MUX(0x4, "I2S0_M4"), 546 KEEMBAY_MUX(0x5, "LCD_M5"), 547 KEEMBAY_MUX(0x6, "CAM_M6"), 548 KEEMBAY_MUX(0x7, "GPIO_M7")), 549 KEEMBAY_PIN_DESC(45, "GPIO45", 550 KEEMBAY_MUX(0x0, "ETH_M0"), 551 KEEMBAY_MUX(0x1, "SD1_M1"), 552 KEEMBAY_MUX(0x2, "SPI0_M2"), 553 KEEMBAY_MUX(0x3, "CPR_M3"), 554 KEEMBAY_MUX(0x4, "I2S0_M4"), 555 KEEMBAY_MUX(0x5, "LCD_M5"), 556 KEEMBAY_MUX(0x6, "CAM_M6"), 557 KEEMBAY_MUX(0x7, "GPIO_M7")), 558 KEEMBAY_PIN_DESC(46, "GPIO46", 559 KEEMBAY_MUX(0x0, "ETH_M0"), 560 KEEMBAY_MUX(0x1, "SD1_M1"), 561 KEEMBAY_MUX(0x2, "SPI0_M2"), 562 KEEMBAY_MUX(0x3, "TPIU_M3"), 563 KEEMBAY_MUX(0x4, "I2S0_M4"), 564 KEEMBAY_MUX(0x5, "LCD_M5"), 565 KEEMBAY_MUX(0x6, "CAM_M6"), 566 KEEMBAY_MUX(0x7, "GPIO_M7")), 567 KEEMBAY_PIN_DESC(47, "GPIO47", 568 KEEMBAY_MUX(0x0, "ETH_M0"), 569 KEEMBAY_MUX(0x1, "SD1_M1"), 570 KEEMBAY_MUX(0x2, "SPI0_M2"), 571 KEEMBAY_MUX(0x3, "TPIU_M3"), 572 KEEMBAY_MUX(0x4, "I2S0_M4"), 573 KEEMBAY_MUX(0x5, "LCD_M5"), 574 KEEMBAY_MUX(0x6, "CAM_M6"), 575 KEEMBAY_MUX(0x7, "GPIO_M7")), 576 KEEMBAY_PIN_DESC(48, "GPIO48", 577 KEEMBAY_MUX(0x0, "ETH_M0"), 578 KEEMBAY_MUX(0x1, "SPI2_M1"), 579 KEEMBAY_MUX(0x2, "UART2_M2"), 580 KEEMBAY_MUX(0x3, "TPIU_M3"), 581 KEEMBAY_MUX(0x4, "I2S0_M4"), 582 KEEMBAY_MUX(0x5, "LCD_M5"), 583 KEEMBAY_MUX(0x6, "CAM_M6"), 584 KEEMBAY_MUX(0x7, "GPIO_M7")), 585 KEEMBAY_PIN_DESC(49, "GPIO49", 586 KEEMBAY_MUX(0x0, "ETH_M0"), 587 KEEMBAY_MUX(0x1, "SPI2_M1"), 588 KEEMBAY_MUX(0x2, "UART2_M2"), 589 KEEMBAY_MUX(0x3, "TPIU_M3"), 590 KEEMBAY_MUX(0x4, "I2S1_M4"), 591 KEEMBAY_MUX(0x5, "LCD_M5"), 592 KEEMBAY_MUX(0x6, "CAM_M6"), 593 KEEMBAY_MUX(0x7, "GPIO_M7")), 594 KEEMBAY_PIN_DESC(50, "GPIO50", 595 KEEMBAY_MUX(0x0, "ETH_M0"), 596 KEEMBAY_MUX(0x1, "SPI2_M1"), 597 KEEMBAY_MUX(0x2, "UART2_M2"), 598 KEEMBAY_MUX(0x3, "TPIU_M3"), 599 KEEMBAY_MUX(0x4, "I2S1_M4"), 600 KEEMBAY_MUX(0x5, "LCD_M5"), 601 KEEMBAY_MUX(0x6, "CAM_M6"), 602 KEEMBAY_MUX(0x7, "GPIO_M7")), 603 KEEMBAY_PIN_DESC(51, "GPIO51", 604 KEEMBAY_MUX(0x0, "ETH_M0"), 605 KEEMBAY_MUX(0x1, "SPI2_M1"), 606 KEEMBAY_MUX(0x2, "UART2_M2"), 607 KEEMBAY_MUX(0x3, "TPIU_M3"), 608 KEEMBAY_MUX(0x4, "I2S1_M4"), 609 KEEMBAY_MUX(0x5, "LCD_M5"), 610 KEEMBAY_MUX(0x6, "CAM_M6"), 611 KEEMBAY_MUX(0x7, "GPIO_M7")), 612 KEEMBAY_PIN_DESC(52, "GPIO52", 613 KEEMBAY_MUX(0x0, "ETH_M0"), 614 KEEMBAY_MUX(0x1, "SPI2_M1"), 615 KEEMBAY_MUX(0x2, "SD0_M2"), 616 KEEMBAY_MUX(0x3, "TPIU_M3"), 617 KEEMBAY_MUX(0x4, "I2S1_M4"), 618 KEEMBAY_MUX(0x5, "LCD_M5"), 619 KEEMBAY_MUX(0x6, "CAM_M6"), 620 KEEMBAY_MUX(0x7, "GPIO_M7")), 621 KEEMBAY_PIN_DESC(53, "GPIO53", 622 KEEMBAY_MUX(0x0, "ETH_M0"), 623 KEEMBAY_MUX(0x1, "SPI2_M1"), 624 KEEMBAY_MUX(0x2, "SD0_M2"), 625 KEEMBAY_MUX(0x3, "TPIU_M3"), 626 KEEMBAY_MUX(0x4, "I2S2_M4"), 627 KEEMBAY_MUX(0x5, "LCD_M5"), 628 KEEMBAY_MUX(0x6, "CAM_M6"), 629 KEEMBAY_MUX(0x7, "GPIO_M7")), 630 KEEMBAY_PIN_DESC(54, "GPIO54", 631 KEEMBAY_MUX(0x0, "ETH_M0"), 632 KEEMBAY_MUX(0x1, "SPI2_M1"), 633 KEEMBAY_MUX(0x2, "SD0_M2"), 634 KEEMBAY_MUX(0x3, "TPIU_M3"), 635 KEEMBAY_MUX(0x4, "I2S2_M4"), 636 KEEMBAY_MUX(0x5, "LCD_M5"), 637 KEEMBAY_MUX(0x6, "CAM_M6"), 638 KEEMBAY_MUX(0x7, "GPIO_M7")), 639 KEEMBAY_PIN_DESC(55, "GPIO55", 640 KEEMBAY_MUX(0x0, "ETH_M0"), 641 KEEMBAY_MUX(0x1, "SPI2_M1"), 642 KEEMBAY_MUX(0x2, "SD1_M2"), 643 KEEMBAY_MUX(0x3, "TPIU_M3"), 644 KEEMBAY_MUX(0x4, "I2S2_M4"), 645 KEEMBAY_MUX(0x5, "LCD_M5"), 646 KEEMBAY_MUX(0x6, "CAM_M6"), 647 KEEMBAY_MUX(0x7, "GPIO_M7")), 648 KEEMBAY_PIN_DESC(56, "GPIO56", 649 KEEMBAY_MUX(0x0, "ETH_M0"), 650 KEEMBAY_MUX(0x1, "SPI2_M1"), 651 KEEMBAY_MUX(0x2, "SD1_M2"), 652 KEEMBAY_MUX(0x3, "TPIU_M3"), 653 KEEMBAY_MUX(0x4, "I2S2_M4"), 654 KEEMBAY_MUX(0x5, "LCD_M5"), 655 KEEMBAY_MUX(0x6, "CAM_M6"), 656 KEEMBAY_MUX(0x7, "GPIO_M7")), 657 KEEMBAY_PIN_DESC(57, "GPIO57", 658 KEEMBAY_MUX(0x0, "SPI1_M0"), 659 KEEMBAY_MUX(0x1, "I2S1_M1"), 660 KEEMBAY_MUX(0x2, "SD1_M2"), 661 KEEMBAY_MUX(0x3, "TPIU_M3"), 662 KEEMBAY_MUX(0x4, "UART0_M4"), 663 KEEMBAY_MUX(0x5, "LCD_M5"), 664 KEEMBAY_MUX(0x6, "CAM_M6"), 665 KEEMBAY_MUX(0x7, "GPIO_M7")), 666 KEEMBAY_PIN_DESC(58, "GPIO58", 667 KEEMBAY_MUX(0x0, "SPI1_M0"), 668 KEEMBAY_MUX(0x1, "ETH_M1"), 669 KEEMBAY_MUX(0x2, "SD0_M2"), 670 KEEMBAY_MUX(0x3, "TPIU_M3"), 671 KEEMBAY_MUX(0x4, "UART0_M4"), 672 KEEMBAY_MUX(0x5, "LCD_M5"), 673 KEEMBAY_MUX(0x6, "CAM_M6"), 674 KEEMBAY_MUX(0x7, "GPIO_M7")), 675 KEEMBAY_PIN_DESC(59, "GPIO59", 676 KEEMBAY_MUX(0x0, "SPI1_M0"), 677 KEEMBAY_MUX(0x1, "ETH_M1"), 678 KEEMBAY_MUX(0x2, "SD0_M2"), 679 KEEMBAY_MUX(0x3, "TPIU_M3"), 680 KEEMBAY_MUX(0x4, "UART0_M4"), 681 KEEMBAY_MUX(0x5, "LCD_M5"), 682 KEEMBAY_MUX(0x6, "CAM_M6"), 683 KEEMBAY_MUX(0x7, "GPIO_M7")), 684 KEEMBAY_PIN_DESC(60, "GPIO60", 685 KEEMBAY_MUX(0x0, "SPI1_M0"), 686 KEEMBAY_MUX(0x1, "ETH_M1"), 687 KEEMBAY_MUX(0x2, "I3C1_M2"), 688 KEEMBAY_MUX(0x3, "TPIU_M3"), 689 KEEMBAY_MUX(0x4, "UART0_M4"), 690 KEEMBAY_MUX(0x5, "LCD_M5"), 691 KEEMBAY_MUX(0x6, "CAM_M6"), 692 KEEMBAY_MUX(0x7, "GPIO_M7")), 693 KEEMBAY_PIN_DESC(61, "GPIO61", 694 KEEMBAY_MUX(0x0, "SPI1_M0"), 695 KEEMBAY_MUX(0x1, "ETH_M1"), 696 KEEMBAY_MUX(0x2, "SD0_M2"), 697 KEEMBAY_MUX(0x3, "TPIU_M3"), 698 KEEMBAY_MUX(0x4, "UART1_M4"), 699 KEEMBAY_MUX(0x5, "LCD_M5"), 700 KEEMBAY_MUX(0x6, "CAM_M6"), 701 KEEMBAY_MUX(0x7, "GPIO_M7")), 702 KEEMBAY_PIN_DESC(62, "GPIO62", 703 KEEMBAY_MUX(0x0, "SPI1_M0"), 704 KEEMBAY_MUX(0x1, "ETH_M1"), 705 KEEMBAY_MUX(0x2, "SD1_M2"), 706 KEEMBAY_MUX(0x3, "TPIU_M3"), 707 KEEMBAY_MUX(0x4, "UART1_M4"), 708 KEEMBAY_MUX(0x5, "LCD_M5"), 709 KEEMBAY_MUX(0x6, "CAM_M6"), 710 KEEMBAY_MUX(0x7, "GPIO_M7")), 711 KEEMBAY_PIN_DESC(63, "GPIO63", 712 KEEMBAY_MUX(0x0, "I2S1_M0"), 713 KEEMBAY_MUX(0x1, "SPI1_M1"), 714 KEEMBAY_MUX(0x2, "SD1_M2"), 715 KEEMBAY_MUX(0x3, "TPIU_M3"), 716 KEEMBAY_MUX(0x4, "UART1_M4"), 717 KEEMBAY_MUX(0x5, "LCD_M5"), 718 KEEMBAY_MUX(0x6, "CAM_M6"), 719 KEEMBAY_MUX(0x7, "GPIO_M7")), 720 KEEMBAY_PIN_DESC(64, "GPIO64", 721 KEEMBAY_MUX(0x0, "I2S2_M0"), 722 KEEMBAY_MUX(0x1, "SPI1_M1"), 723 KEEMBAY_MUX(0x2, "ETH_M2"), 724 KEEMBAY_MUX(0x3, "TPIU_M3"), 725 KEEMBAY_MUX(0x4, "UART1_M4"), 726 KEEMBAY_MUX(0x5, "LCD_M5"), 727 KEEMBAY_MUX(0x6, "CAM_M6"), 728 KEEMBAY_MUX(0x7, "GPIO_M7")), 729 KEEMBAY_PIN_DESC(65, "GPIO65", 730 KEEMBAY_MUX(0x0, "I3C0_M0"), 731 KEEMBAY_MUX(0x1, "SPI1_M1"), 732 KEEMBAY_MUX(0x2, "SD1_M2"), 733 KEEMBAY_MUX(0x3, "TPIU_M3"), 734 KEEMBAY_MUX(0x4, "SPI0_M4"), 735 KEEMBAY_MUX(0x5, "LCD_M5"), 736 KEEMBAY_MUX(0x6, "CAM_M6"), 737 KEEMBAY_MUX(0x7, "GPIO_M7")), 738 KEEMBAY_PIN_DESC(66, "GPIO66", 739 KEEMBAY_MUX(0x0, "I3C0_M0"), 740 KEEMBAY_MUX(0x1, "ETH_M1"), 741 KEEMBAY_MUX(0x2, "I2C0_M2"), 742 KEEMBAY_MUX(0x3, "TPIU_M3"), 743 KEEMBAY_MUX(0x4, "SPI0_M4"), 744 KEEMBAY_MUX(0x5, "LCD_M5"), 745 KEEMBAY_MUX(0x6, "CAM_M6"), 746 KEEMBAY_MUX(0x7, "GPIO_M7")), 747 KEEMBAY_PIN_DESC(67, "GPIO67", 748 KEEMBAY_MUX(0x0, "I3C1_M0"), 749 KEEMBAY_MUX(0x1, "ETH_M1"), 750 KEEMBAY_MUX(0x2, "I2C0_M2"), 751 KEEMBAY_MUX(0x3, "TPIU_M3"), 752 KEEMBAY_MUX(0x4, "SPI0_M4"), 753 KEEMBAY_MUX(0x5, "LCD_M5"), 754 KEEMBAY_MUX(0x6, "I2S3_M6"), 755 KEEMBAY_MUX(0x7, "GPIO_M7")), 756 KEEMBAY_PIN_DESC(68, "GPIO68", 757 KEEMBAY_MUX(0x0, "I3C1_M0"), 758 KEEMBAY_MUX(0x1, "ETH_M1"), 759 KEEMBAY_MUX(0x2, "I2C1_M2"), 760 KEEMBAY_MUX(0x3, "TPIU_M3"), 761 KEEMBAY_MUX(0x4, "SPI0_M4"), 762 KEEMBAY_MUX(0x5, "LCD_M5"), 763 KEEMBAY_MUX(0x6, "I2S3_M6"), 764 KEEMBAY_MUX(0x7, "GPIO_M7")), 765 KEEMBAY_PIN_DESC(69, "GPIO69", 766 KEEMBAY_MUX(0x0, "I3C2_M0"), 767 KEEMBAY_MUX(0x1, "ETH_M1"), 768 KEEMBAY_MUX(0x2, "I2C1_M2"), 769 KEEMBAY_MUX(0x3, "TPIU_M3"), 770 KEEMBAY_MUX(0x4, "SPI0_M4"), 771 KEEMBAY_MUX(0x5, "LCD_M5"), 772 KEEMBAY_MUX(0x6, "I2S3_M6"), 773 KEEMBAY_MUX(0x7, "GPIO_M7")), 774 KEEMBAY_PIN_DESC(70, "GPIO70", 775 KEEMBAY_MUX(0x0, "I3C2_M0"), 776 KEEMBAY_MUX(0x1, "ETH_M1"), 777 KEEMBAY_MUX(0x2, "SPI0_M2"), 778 KEEMBAY_MUX(0x3, "TPIU_M3"), 779 KEEMBAY_MUX(0x4, "SD0_M4"), 780 KEEMBAY_MUX(0x5, "LCD_M5"), 781 KEEMBAY_MUX(0x6, "I2S3_M6"), 782 KEEMBAY_MUX(0x7, "GPIO_M7")), 783 KEEMBAY_PIN_DESC(71, "GPIO71", 784 KEEMBAY_MUX(0x0, "I3C0_M0"), 785 KEEMBAY_MUX(0x1, "ETH_M1"), 786 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 787 KEEMBAY_MUX(0x3, "TPIU_M3"), 788 KEEMBAY_MUX(0x4, "SD0_M4"), 789 KEEMBAY_MUX(0x5, "LCD_M5"), 790 KEEMBAY_MUX(0x6, "I2S3_M6"), 791 KEEMBAY_MUX(0x7, "GPIO_M7")), 792 KEEMBAY_PIN_DESC(72, "GPIO72", 793 KEEMBAY_MUX(0x0, "I3C1_M0"), 794 KEEMBAY_MUX(0x1, "ETH_M1"), 795 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 796 KEEMBAY_MUX(0x3, "TPIU_M3"), 797 KEEMBAY_MUX(0x4, "SD0_M4"), 798 KEEMBAY_MUX(0x5, "LCD_M5"), 799 KEEMBAY_MUX(0x6, "UART2_M6"), 800 KEEMBAY_MUX(0x7, "GPIO_M7")), 801 KEEMBAY_PIN_DESC(73, "GPIO73", 802 KEEMBAY_MUX(0x0, "I3C2_M0"), 803 KEEMBAY_MUX(0x1, "ETH_M1"), 804 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 805 KEEMBAY_MUX(0x3, "TPIU_M3"), 806 KEEMBAY_MUX(0x4, "SD0_M4"), 807 KEEMBAY_MUX(0x5, "LCD_M5"), 808 KEEMBAY_MUX(0x6, "UART2_M6"), 809 KEEMBAY_MUX(0x7, "GPIO_M7")), 810 KEEMBAY_PIN_DESC(74, "GPIO74", 811 KEEMBAY_MUX(0x0, "I3C0_M0"), 812 KEEMBAY_MUX(0x1, "ETH_M1"), 813 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 814 KEEMBAY_MUX(0x3, "TPIU_M3"), 815 KEEMBAY_MUX(0x4, "SD0_M4"), 816 KEEMBAY_MUX(0x5, "LCD_M5"), 817 KEEMBAY_MUX(0x6, "UART2_M6"), 818 KEEMBAY_MUX(0x7, "GPIO_M7")), 819 KEEMBAY_PIN_DESC(75, "GPIO75", 820 KEEMBAY_MUX(0x0, "I3C0_M0"), 821 KEEMBAY_MUX(0x1, "ETH_M1"), 822 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 823 KEEMBAY_MUX(0x3, "TPIU_M3"), 824 KEEMBAY_MUX(0x4, "SD0_M4"), 825 KEEMBAY_MUX(0x5, "LCD_M5"), 826 KEEMBAY_MUX(0x6, "UART2_M6"), 827 KEEMBAY_MUX(0x7, "GPIO_M7")), 828 KEEMBAY_PIN_DESC(76, "GPIO76", 829 KEEMBAY_MUX(0x0, "I2C2_M0"), 830 KEEMBAY_MUX(0x1, "I3C0_M1"), 831 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 832 KEEMBAY_MUX(0x3, "TPIU_M3"), 833 KEEMBAY_MUX(0x4, "ETH_M4"), 834 KEEMBAY_MUX(0x5, "LCD_M5"), 835 KEEMBAY_MUX(0x6, "UART3_M6"), 836 KEEMBAY_MUX(0x7, "GPIO_M7")), 837 KEEMBAY_PIN_DESC(77, "GPIO77", 838 KEEMBAY_MUX(0x0, "PCIE_M0"), 839 KEEMBAY_MUX(0x1, "I3C1_M1"), 840 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 841 KEEMBAY_MUX(0x3, "TPIU_M3"), 842 KEEMBAY_MUX(0x4, "I3C2_M4"), 843 KEEMBAY_MUX(0x5, "LCD_M5"), 844 KEEMBAY_MUX(0x6, "UART3_M6"), 845 KEEMBAY_MUX(0x7, "GPIO_M7")), 846 KEEMBAY_PIN_DESC(78, "GPIO78", 847 KEEMBAY_MUX(0x0, "PCIE_M0"), 848 KEEMBAY_MUX(0x1, "I3C2_M1"), 849 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 850 KEEMBAY_MUX(0x3, "TPIU_M3"), 851 KEEMBAY_MUX(0x4, "I3C2_M4"), 852 KEEMBAY_MUX(0x5, "LCD_M5"), 853 KEEMBAY_MUX(0x6, "UART3_M6"), 854 KEEMBAY_MUX(0x7, "GPIO_M7")), 855 KEEMBAY_PIN_DESC(79, "GPIO79", 856 KEEMBAY_MUX(0x0, "PCIE_M0"), 857 KEEMBAY_MUX(0x1, "I2C2_M1"), 858 KEEMBAY_MUX(0x2, "SLVDS1_M2"), 859 KEEMBAY_MUX(0x3, "TPIU_M3"), 860 KEEMBAY_MUX(0x4, "I3C2_M4"), 861 KEEMBAY_MUX(0x5, "LCD_M5"), 862 KEEMBAY_MUX(0x6, "UART3_M6"), 863 KEEMBAY_MUX(0x7, "GPIO_M7")), 864}; 865 866static inline u32 keembay_read_reg(void __iomem *base, unsigned int pin) 867{ 868 return readl(base + KEEMBAY_GPIO_REG_OFFSET(pin)); 869} 870 871static inline u32 keembay_read_gpio_reg(void __iomem *base, unsigned int pin) 872{ 873 return keembay_read_reg(base, pin / KEEMBAY_GPIO_MAX_PER_REG); 874} 875 876static inline u32 keembay_read_pin(void __iomem *base, unsigned int pin) 877{ 878 u32 val = keembay_read_gpio_reg(base, pin); 879 880 return !!(val & BIT(pin % KEEMBAY_GPIO_MAX_PER_REG)); 881} 882 883static inline void keembay_write_reg(u32 val, void __iomem *base, unsigned int pin) 884{ 885 writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin)); 886} 887 888static inline void keembay_write_gpio_reg(u32 val, void __iomem *base, unsigned int pin) 889{ 890 keembay_write_reg(val, base, pin / KEEMBAY_GPIO_MAX_PER_REG); 891} 892 893static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin) 894{ 895 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 896 897 /* 898 * This IP doesn't support the falling edge and low level interrupt 899 * trigger. Invert API is used to mimic the falling edge and low 900 * level support 901 */ 902 903 val |= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, KEEMBAY_GPIO_MODE_INV_VAL); 904 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 905} 906 907static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin) 908{ 909 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 910 911 val &= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, 0); 912 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 913} 914 915static int keembay_request_gpio(struct pinctrl_dev *pctldev, 916 struct pinctrl_gpio_range *range, unsigned int pin) 917{ 918 struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); 919 unsigned int val; 920 921 if (pin >= kpc->npins) 922 return -EINVAL; 923 924 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 925 val = FIELD_GET(KEEMBAY_GPIO_MODE_SELECT_MASK, val); 926 927 /* As per Pin Mux Map, Modes 0 to 6 are for peripherals */ 928 if (val != KEEMBAY_GPIO_MODE_DEFAULT) 929 return -EBUSY; 930 931 return 0; 932} 933 934static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel, 935 unsigned int grp_sel) 936{ 937 struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); 938 const struct function_desc *func; 939 struct group_desc *grp; 940 unsigned int val; 941 u8 pin_mode; 942 int pin; 943 944 grp = pinctrl_generic_get_group(pctldev, grp_sel); 945 if (!grp) 946 return -EINVAL; 947 948 func = pinmux_generic_get_function(pctldev, fun_sel); 949 if (!func) 950 return -EINVAL; 951 952 /* Change modes for pins in the selected group */ 953 pin = *grp->grp.pins; 954 pin_mode = *(u8 *)(func->data); 955 956 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 957 val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK); 958 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 959 960 return 0; 961} 962 963static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin) 964{ 965 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 966 967 return FIELD_GET(KEEMBAY_GPIO_MODE_PULLUP_MASK, val); 968} 969 970static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin, 971 unsigned int pull) 972{ 973 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 974 975 val = u32_replace_bits(val, pull, KEEMBAY_GPIO_MODE_PULLUP_MASK); 976 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 977 978 return 0; 979} 980 981static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin) 982{ 983 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 984 985 val = FIELD_GET(KEEMBAY_GPIO_MODE_DRIVE_MASK, val) * 4; 986 if (val) 987 return val; 988 989 return KEEMBAY_GPIO_MIN_STRENGTH; 990} 991 992static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin, 993 unsigned int drive) 994{ 995 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 996 unsigned int strength = clamp_val(drive, KEEMBAY_GPIO_MIN_STRENGTH, 997 KEEMBAY_GPIO_MAX_STRENGTH) / 4; 998 999 val = u32_replace_bits(val, strength, KEEMBAY_GPIO_MODE_DRIVE_MASK); 1000 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1001 1002 return 0; 1003} 1004 1005static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin) 1006{ 1007 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1008 1009 return !!(val & KEEMBAY_GPIO_MODE_SLEW_RATE); 1010} 1011 1012static int keembay_pinconf_set_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin, 1013 unsigned int slew_rate) 1014{ 1015 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1016 1017 if (slew_rate) 1018 val |= KEEMBAY_GPIO_MODE_SLEW_RATE; 1019 else 1020 val &= ~KEEMBAY_GPIO_MODE_SLEW_RATE; 1021 1022 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1023 1024 return 0; 1025} 1026 1027static int keembay_pinconf_get_schmitt(struct keembay_pinctrl *kpc, unsigned int pin) 1028{ 1029 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1030 1031 return !!(val & KEEMBAY_GPIO_MODE_SCHMITT_EN); 1032} 1033 1034static int keembay_pinconf_set_schmitt(struct keembay_pinctrl *kpc, unsigned int pin, 1035 unsigned int schmitt_en) 1036{ 1037 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1038 1039 if (schmitt_en) 1040 val |= KEEMBAY_GPIO_MODE_SCHMITT_EN; 1041 else 1042 val &= ~KEEMBAY_GPIO_MODE_SCHMITT_EN; 1043 1044 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1045 1046 return 0; 1047} 1048 1049static int keembay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1050 unsigned long *cfg) 1051{ 1052 struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); 1053 unsigned int param = pinconf_to_config_param(*cfg); 1054 unsigned int val; 1055 1056 if (pin >= kpc->npins) 1057 return -EINVAL; 1058 1059 switch (param) { 1060 case PIN_CONFIG_BIAS_DISABLE: 1061 if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_DISABLE) 1062 return -EINVAL; 1063 break; 1064 1065 case PIN_CONFIG_BIAS_PULL_UP: 1066 if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_UP) 1067 return -EINVAL; 1068 break; 1069 1070 case PIN_CONFIG_BIAS_PULL_DOWN: 1071 if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_DOWN) 1072 return -EINVAL; 1073 break; 1074 1075 case PIN_CONFIG_BIAS_BUS_HOLD: 1076 if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_BUS_HOLD) 1077 return -EINVAL; 1078 break; 1079 1080 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1081 if (!keembay_pinconf_get_schmitt(kpc, pin)) 1082 return -EINVAL; 1083 break; 1084 1085 case PIN_CONFIG_SLEW_RATE: 1086 val = keembay_pinconf_get_slew_rate(kpc, pin); 1087 *cfg = pinconf_to_config_packed(param, val); 1088 break; 1089 1090 case PIN_CONFIG_DRIVE_STRENGTH: 1091 val = keembay_pinconf_get_drive(kpc, pin); 1092 *cfg = pinconf_to_config_packed(param, val); 1093 break; 1094 1095 default: 1096 return -ENOTSUPP; 1097 } 1098 1099 return 0; 1100} 1101 1102static int keembay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1103 unsigned long *cfg, unsigned int num_configs) 1104{ 1105 struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev); 1106 enum pin_config_param param; 1107 unsigned int arg, i; 1108 int ret = 0; 1109 1110 if (pin >= kpc->npins) 1111 return -EINVAL; 1112 1113 for (i = 0; i < num_configs; i++) { 1114 param = pinconf_to_config_param(cfg[i]); 1115 arg = pinconf_to_config_argument(cfg[i]); 1116 1117 switch (param) { 1118 case PIN_CONFIG_BIAS_DISABLE: 1119 ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_DISABLE); 1120 break; 1121 1122 case PIN_CONFIG_BIAS_PULL_UP: 1123 ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_UP); 1124 break; 1125 1126 case PIN_CONFIG_BIAS_PULL_DOWN: 1127 ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_DOWN); 1128 break; 1129 1130 case PIN_CONFIG_BIAS_BUS_HOLD: 1131 ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_BUS_HOLD); 1132 break; 1133 1134 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1135 ret = keembay_pinconf_set_schmitt(kpc, pin, arg); 1136 break; 1137 1138 case PIN_CONFIG_SLEW_RATE: 1139 ret = keembay_pinconf_set_slew_rate(kpc, pin, arg); 1140 break; 1141 1142 case PIN_CONFIG_DRIVE_STRENGTH: 1143 ret = keembay_pinconf_set_drive(kpc, pin, arg); 1144 break; 1145 1146 default: 1147 return -ENOTSUPP; 1148 } 1149 if (ret) 1150 return ret; 1151 } 1152 return ret; 1153} 1154 1155static const struct pinctrl_ops keembay_pctlops = { 1156 .get_groups_count = pinctrl_generic_get_group_count, 1157 .get_group_name = pinctrl_generic_get_group_name, 1158 .get_group_pins = pinctrl_generic_get_group_pins, 1159 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1160 .dt_free_map = pinconf_generic_dt_free_map, 1161}; 1162 1163static const struct pinmux_ops keembay_pmxops = { 1164 .get_functions_count = pinmux_generic_get_function_count, 1165 .get_function_name = pinmux_generic_get_function_name, 1166 .get_function_groups = pinmux_generic_get_function_groups, 1167 .gpio_request_enable = keembay_request_gpio, 1168 .set_mux = keembay_set_mux, 1169}; 1170 1171static const struct pinconf_ops keembay_confops = { 1172 .is_generic = true, 1173 .pin_config_get = keembay_pinconf_get, 1174 .pin_config_set = keembay_pinconf_set, 1175}; 1176 1177static struct pinctrl_desc keembay_pinctrl_desc = { 1178 .name = "keembay-pinmux", 1179 .pctlops = &keembay_pctlops, 1180 .pmxops = &keembay_pmxops, 1181 .confops = &keembay_confops, 1182 .owner = THIS_MODULE, 1183}; 1184 1185static int keembay_gpio_get(struct gpio_chip *gc, unsigned int pin) 1186{ 1187 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1188 unsigned int val, offset; 1189 1190 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1191 offset = (val & KEEMBAY_GPIO_MODE_DIR) ? KEEMBAY_GPIO_DATA_IN : KEEMBAY_GPIO_DATA_OUT; 1192 1193 return keembay_read_pin(kpc->base0 + offset, pin); 1194} 1195 1196static int keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val) 1197{ 1198 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1199 unsigned int reg_val; 1200 1201 reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin); 1202 if (val) 1203 keembay_write_gpio_reg(reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG), 1204 kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin); 1205 else 1206 keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG), 1207 kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin); 1208 1209 return 0; 1210} 1211 1212static int keembay_gpio_get_direction(struct gpio_chip *gc, unsigned int pin) 1213{ 1214 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1215 unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1216 1217 return !!(val & KEEMBAY_GPIO_MODE_DIR); 1218} 1219 1220static int keembay_gpio_set_direction_in(struct gpio_chip *gc, unsigned int pin) 1221{ 1222 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1223 unsigned int val; 1224 1225 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1226 val |= KEEMBAY_GPIO_MODE_DIR; 1227 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1228 1229 return 0; 1230} 1231 1232static int keembay_gpio_set_direction_out(struct gpio_chip *gc, 1233 unsigned int pin, int value) 1234{ 1235 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1236 unsigned int val; 1237 1238 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1239 val &= ~KEEMBAY_GPIO_MODE_DIR; 1240 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin); 1241 1242 return keembay_gpio_set(gc, pin, value); 1243} 1244 1245static void keembay_gpio_irq_handler(struct irq_desc *desc) 1246{ 1247 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1248 unsigned int kmb_irq = irq_desc_get_irq(desc); 1249 unsigned long reg, clump = 0, bit = 0; 1250 struct irq_chip *parent_chip; 1251 struct keembay_pinctrl *kpc; 1252 unsigned int src, pin, val; 1253 1254 /* Identify GPIO interrupt number from GIC interrupt number */ 1255 for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { 1256 if (kmb_irq == gc->irq.parents[src]) 1257 break; 1258 } 1259 1260 if (src == KEEMBAY_GPIO_NUM_IRQ) 1261 return; 1262 1263 parent_chip = irq_desc_get_chip(desc); 1264 kpc = gpiochip_get_data(gc); 1265 1266 chained_irq_enter(parent_chip, desc); 1267 reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1268 1269 /* 1270 * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit 1271 * and input values were checked to identify the source of the 1272 * Interrupt. The checked enable bit positions are 7, 15, 23 and 31. 1273 */ 1274 for_each_set_clump8(bit, clump, ®, BITS_PER_TYPE(typeof(reg))) { 1275 pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE; 1276 val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin); 1277 kmb_irq = irq_find_mapping(gc->irq.domain, pin); 1278 1279 /* Checks if the interrupt is enabled */ 1280 if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE)) 1281 generic_handle_irq(kmb_irq); 1282 } 1283 chained_irq_exit(parent_chip, desc); 1284} 1285 1286static void keembay_gpio_clear_irq(struct irq_data *data, unsigned long pos, 1287 u32 src, irq_hw_number_t pin) 1288{ 1289 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1290 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1291 unsigned long trig = irqd_get_trigger_type(data); 1292 struct keembay_gpio_irq *irq = &kpc->irq[src]; 1293 unsigned long val; 1294 1295 /* Check if the value of pos/KEEMBAY_GPIO_NUM_IRQ is in valid range. */ 1296 if ((pos / KEEMBAY_GPIO_NUM_IRQ) >= KEEMBAY_GPIO_MAX_PER_IRQ) 1297 return; 1298 1299 /* Retains val register as it handles other interrupts as well. */ 1300 val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1301 1302 bitmap_set_value8(&val, 0, pos); 1303 keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1304 1305 irq->num_share--; 1306 irq->pins[pos / KEEMBAY_GPIO_NUM_IRQ] = 0; 1307 1308 if (trig & IRQ_TYPE_LEVEL_MASK) 1309 keembay_gpio_restore_default(kpc, pin); 1310 1311 if (irq->trigger == IRQ_TYPE_LEVEL_HIGH) 1312 kpc->max_gpios_level_type++; 1313 else if (irq->trigger == IRQ_TYPE_EDGE_RISING) 1314 kpc->max_gpios_edge_type++; 1315} 1316 1317static int keembay_find_free_slot(struct keembay_pinctrl *kpc, unsigned int src) 1318{ 1319 unsigned long val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1320 1321 return bitmap_find_free_region(&val, KEEMBAY_GPIO_MAX_PER_REG, 3) / KEEMBAY_GPIO_NUM_IRQ; 1322} 1323 1324static int keembay_find_free_src(struct keembay_pinctrl *kpc, unsigned int trig) 1325{ 1326 int src, type = 0; 1327 1328 if (trig & IRQ_TYPE_LEVEL_MASK) 1329 type = IRQ_TYPE_LEVEL_HIGH; 1330 else if (trig & IRQ_TYPE_EDGE_BOTH) 1331 type = IRQ_TYPE_EDGE_RISING; 1332 1333 for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { 1334 if (kpc->irq[src].trigger != type) 1335 continue; 1336 1337 if (!keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src) || 1338 kpc->irq[src].num_share < KEEMBAY_GPIO_MAX_PER_IRQ) 1339 return src; 1340 } 1341 1342 return -EBUSY; 1343} 1344 1345static void keembay_gpio_set_irq(struct keembay_pinctrl *kpc, int src, 1346 int slot, irq_hw_number_t pin) 1347{ 1348 unsigned long val = pin | KEEMBAY_GPIO_IRQ_ENABLE; 1349 struct keembay_gpio_irq *irq = &kpc->irq[src]; 1350 unsigned long flags, reg; 1351 1352 raw_spin_lock_irqsave(&kpc->lock, flags); 1353 reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1354 bitmap_set_value8(®, val, slot * 8); 1355 keembay_write_reg(reg, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1356 raw_spin_unlock_irqrestore(&kpc->lock, flags); 1357 1358 if (irq->trigger == IRQ_TYPE_LEVEL_HIGH) 1359 kpc->max_gpios_level_type--; 1360 else if (irq->trigger == IRQ_TYPE_EDGE_RISING) 1361 kpc->max_gpios_edge_type--; 1362 1363 irq->source = src; 1364 irq->pins[slot] = pin; 1365 irq->num_share++; 1366} 1367 1368static void keembay_gpio_irq_enable(struct irq_data *data) 1369{ 1370 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1371 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1372 unsigned int trig = irqd_get_trigger_type(data); 1373 irq_hw_number_t pin = irqd_to_hwirq(data); 1374 int src, slot; 1375 1376 /* Check which Interrupt source and slot is available */ 1377 src = keembay_find_free_src(kpc, trig); 1378 slot = keembay_find_free_slot(kpc, src); 1379 1380 if (src < 0 || slot < 0) 1381 return; 1382 1383 if (trig & KEEMBAY_GPIO_SENSE_LOW) 1384 keembay_gpio_invert(kpc, pin); 1385 1386 keembay_gpio_set_irq(kpc, src, slot, pin); 1387} 1388 1389static void keembay_gpio_irq_ack(struct irq_data *data) 1390{ 1391 /* 1392 * The keembay_gpio_irq_ack function is needed to handle_edge_irq. 1393 * IRQ ack is not possible from the SOC perspective. The IP by itself 1394 * is used for handling interrupts which do not come in short-time and 1395 * not used as protocol or communication interrupts. All the interrupts 1396 * are threaded IRQ interrupts. But this function is expected to be 1397 * present as the gpio IP is registered with irq framework. Otherwise 1398 * handle_edge_irq() fails. 1399 */ 1400} 1401 1402static void keembay_gpio_irq_disable(struct irq_data *data) 1403{ 1404 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1405 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1406 irq_hw_number_t pin = irqd_to_hwirq(data); 1407 unsigned long reg, clump = 0, pos = 0; 1408 unsigned int src; 1409 1410 for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) { 1411 reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src); 1412 for_each_set_clump8(pos, clump, ®, BITS_PER_TYPE(typeof(reg))) { 1413 if ((clump & ~KEEMBAY_GPIO_IRQ_ENABLE) == pin) { 1414 keembay_gpio_clear_irq(data, pos, src, pin); 1415 return; 1416 } 1417 } 1418 } 1419} 1420 1421static int keembay_gpio_irq_set_type(struct irq_data *data, unsigned int type) 1422{ 1423 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1424 struct keembay_pinctrl *kpc = gpiochip_get_data(gc); 1425 1426 /* Change EDGE_BOTH as EDGE_RISING in order to claim the IRQ for power button */ 1427 if (!kpc->max_gpios_edge_type && (type & IRQ_TYPE_EDGE_BOTH)) 1428 type = IRQ_TYPE_EDGE_RISING; 1429 1430 if (!kpc->max_gpios_level_type && (type & IRQ_TYPE_LEVEL_MASK)) 1431 type = IRQ_TYPE_NONE; 1432 1433 if (type & IRQ_TYPE_EDGE_BOTH) 1434 irq_set_handler_locked(data, handle_edge_irq); 1435 else if (type & IRQ_TYPE_LEVEL_MASK) 1436 irq_set_handler_locked(data, handle_level_irq); 1437 else 1438 return -EINVAL; 1439 1440 return 0; 1441} 1442 1443static int keembay_gpio_add_pin_ranges(struct gpio_chip *chip) 1444{ 1445 struct keembay_pinctrl *kpc = gpiochip_get_data(chip); 1446 int ret; 1447 1448 ret = gpiochip_add_pin_range(chip, dev_name(kpc->dev), 0, 0, chip->ngpio); 1449 if (ret) 1450 dev_err_probe(kpc->dev, ret, "failed to add GPIO pin range\n"); 1451 return ret; 1452} 1453 1454static struct irq_chip keembay_gpio_irqchip = { 1455 .name = "keembay-gpio", 1456 .irq_enable = keembay_gpio_irq_enable, 1457 .irq_disable = keembay_gpio_irq_disable, 1458 .irq_set_type = keembay_gpio_irq_set_type, 1459 .irq_ack = keembay_gpio_irq_ack, 1460}; 1461 1462static int keembay_gpiochip_probe(struct keembay_pinctrl *kpc, 1463 struct platform_device *pdev) 1464{ 1465 unsigned int i, level_line = 0, edge_line = 0; 1466 struct gpio_chip *gc = &kpc->chip; 1467 struct gpio_irq_chip *girq; 1468 1469 /* Setup GPIO IRQ chip */ 1470 girq = &kpc->chip.irq; 1471 girq->chip = &keembay_gpio_irqchip; 1472 girq->parent_handler = keembay_gpio_irq_handler; 1473 girq->num_parents = KEEMBAY_GPIO_NUM_IRQ; 1474 girq->parents = devm_kcalloc(kpc->dev, girq->num_parents, 1475 sizeof(*girq->parents), GFP_KERNEL); 1476 1477 if (!girq->parents) 1478 return -ENOMEM; 1479 1480 /* Setup GPIO chip */ 1481 gc->label = dev_name(kpc->dev); 1482 gc->parent = kpc->dev; 1483 gc->request = gpiochip_generic_request; 1484 gc->free = gpiochip_generic_free; 1485 gc->get_direction = keembay_gpio_get_direction; 1486 gc->direction_input = keembay_gpio_set_direction_in; 1487 gc->direction_output = keembay_gpio_set_direction_out; 1488 gc->get = keembay_gpio_get; 1489 gc->set = keembay_gpio_set; 1490 gc->set_config = gpiochip_generic_config; 1491 gc->base = -1; 1492 gc->ngpio = kpc->npins; 1493 gc->add_pin_ranges = keembay_gpio_add_pin_ranges; 1494 1495 for (i = 0; i < KEEMBAY_GPIO_NUM_IRQ; i++) { 1496 struct keembay_gpio_irq *kmb_irq = &kpc->irq[i]; 1497 int irq; 1498 1499 irq = platform_get_irq_optional(pdev, i); 1500 if (irq <= 0) 1501 continue; 1502 1503 girq->parents[i] = irq; 1504 kmb_irq->line = girq->parents[i]; 1505 kmb_irq->source = i; 1506 kmb_irq->trigger = irq_get_trigger_type(girq->parents[i]); 1507 kmb_irq->num_share = 0; 1508 1509 if (kmb_irq->trigger == IRQ_TYPE_LEVEL_HIGH) 1510 level_line++; 1511 else 1512 edge_line++; 1513 } 1514 1515 kpc->max_gpios_level_type = level_line * KEEMBAY_GPIO_MAX_PER_IRQ; 1516 kpc->max_gpios_edge_type = edge_line * KEEMBAY_GPIO_MAX_PER_IRQ; 1517 1518 girq->default_type = IRQ_TYPE_NONE; 1519 girq->handler = handle_bad_irq; 1520 1521 return devm_gpiochip_add_data(kpc->dev, gc, kpc); 1522} 1523 1524static int keembay_build_groups(struct keembay_pinctrl *kpc) 1525{ 1526 struct pingroup *grp; 1527 unsigned int i; 1528 1529 kpc->ngroups = kpc->npins; 1530 grp = devm_kcalloc(kpc->dev, kpc->ngroups, sizeof(*grp), GFP_KERNEL); 1531 if (!grp) 1532 return -ENOMEM; 1533 1534 /* Each pin is categorised as one group */ 1535 for (i = 0; i < kpc->ngroups; i++) { 1536 const struct pinctrl_pin_desc *pdesc = keembay_pins + i; 1537 struct pingroup *kmb_grp = grp + i; 1538 1539 kmb_grp->name = pdesc->name; 1540 kmb_grp->pins = (int *)&pdesc->number; 1541 pinctrl_generic_add_group(kpc->pctrl, kmb_grp->name, 1542 kmb_grp->pins, 1, NULL); 1543 } 1544 1545 return 0; 1546} 1547 1548static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc, struct device *dev) 1549{ 1550 int ret; 1551 1552 keembay_pinctrl_desc.pins = keembay_pins; 1553 ret = of_property_read_u32(dev->of_node, "ngpios", &kpc->npins); 1554 if (ret < 0) 1555 return ret; 1556 keembay_pinctrl_desc.npins = kpc->npins; 1557 1558 kpc->pctrl = devm_pinctrl_register(kpc->dev, &keembay_pinctrl_desc, kpc); 1559 1560 return PTR_ERR_OR_ZERO(kpc->pctrl); 1561} 1562 1563static int keembay_add_functions(struct keembay_pinctrl *kpc, 1564 struct keembay_pinfunction *functions) 1565{ 1566 unsigned int i; 1567 1568 /* Assign the groups for each function */ 1569 for (i = 0; i < kpc->nfuncs; i++) { 1570 struct keembay_pinfunction *func = &functions[i]; 1571 const char **group_names; 1572 unsigned int grp_idx = 0; 1573 int j; 1574 1575 group_names = devm_kcalloc(kpc->dev, func->func.ngroups, 1576 sizeof(*group_names), GFP_KERNEL); 1577 if (!group_names) 1578 return -ENOMEM; 1579 1580 for (j = 0; j < kpc->npins; j++) { 1581 const struct pinctrl_pin_desc *pdesc = &keembay_pins[j]; 1582 struct keembay_mux_desc *mux; 1583 1584 for (mux = pdesc->drv_data; mux->name; mux++) { 1585 if (!strcmp(mux->name, func->func.name)) 1586 group_names[grp_idx++] = pdesc->name; 1587 } 1588 } 1589 1590 func->func.groups = group_names; 1591 } 1592 1593 /* Add all functions */ 1594 for (i = 0; i < kpc->nfuncs; i++) 1595 pinmux_generic_add_pinfunction(kpc->pctrl, &functions[i].func, 1596 &functions[i].mux_mode); 1597 1598 return 0; 1599} 1600 1601static int keembay_build_functions(struct keembay_pinctrl *kpc) 1602{ 1603 struct keembay_pinfunction *keembay_funcs, *new_funcs; 1604 int i; 1605 1606 /* 1607 * Allocate maximum possible number of functions. Assume every pin 1608 * being part of 8 (hw maximum) globally unique muxes. 1609 */ 1610 kpc->nfuncs = 0; 1611 keembay_funcs = devm_kcalloc(kpc->dev, kpc->npins * 8, 1612 sizeof(*keembay_funcs), GFP_KERNEL); 1613 if (!keembay_funcs) 1614 return -ENOMEM; 1615 1616 /* Setup 1 function for each unique mux */ 1617 for (i = 0; i < kpc->npins; i++) { 1618 const struct pinctrl_pin_desc *pdesc = keembay_pins + i; 1619 struct keembay_mux_desc *mux; 1620 1621 for (mux = pdesc->drv_data; mux->name; mux++) { 1622 struct keembay_pinfunction *fdesc; 1623 1624 /* Check if we already have function for this mux */ 1625 for (fdesc = keembay_funcs; fdesc->func.name; fdesc++) { 1626 if (!strcmp(mux->name, fdesc->func.name)) { 1627 fdesc->func.ngroups++; 1628 break; 1629 } 1630 } 1631 1632 /* Setup new function for this mux we didn't see before */ 1633 if (!fdesc->func.name) { 1634 fdesc->func.name = mux->name; 1635 fdesc->func.ngroups = 1; 1636 fdesc->mux_mode = mux->mode; 1637 kpc->nfuncs++; 1638 } 1639 } 1640 } 1641 1642 /* Reallocate memory based on actual number of functions */ 1643 new_funcs = devm_krealloc_array(kpc->dev, keembay_funcs, 1644 kpc->nfuncs, sizeof(*new_funcs), 1645 GFP_KERNEL); 1646 if (!new_funcs) 1647 return -ENOMEM; 1648 1649 return keembay_add_functions(kpc, new_funcs); 1650} 1651 1652static const struct keembay_pin_soc keembay_data = { 1653 .pins = keembay_pins, 1654}; 1655 1656static const struct of_device_id keembay_pinctrl_match[] = { 1657 { .compatible = "intel,keembay-pinctrl", .data = &keembay_data }, 1658 { } 1659}; 1660MODULE_DEVICE_TABLE(of, keembay_pinctrl_match); 1661 1662static int keembay_pinctrl_probe(struct platform_device *pdev) 1663{ 1664 struct device *dev = &pdev->dev; 1665 struct keembay_pinctrl *kpc; 1666 int ret; 1667 1668 kpc = devm_kzalloc(dev, sizeof(*kpc), GFP_KERNEL); 1669 if (!kpc) 1670 return -ENOMEM; 1671 1672 kpc->dev = dev; 1673 kpc->soc = device_get_match_data(dev); 1674 1675 kpc->base0 = devm_platform_ioremap_resource(pdev, 0); 1676 if (IS_ERR(kpc->base0)) 1677 return PTR_ERR(kpc->base0); 1678 1679 kpc->base1 = devm_platform_ioremap_resource(pdev, 1); 1680 if (IS_ERR(kpc->base1)) 1681 return PTR_ERR(kpc->base1); 1682 1683 raw_spin_lock_init(&kpc->lock); 1684 1685 ret = keembay_pinctrl_reg(kpc, dev); 1686 if (ret) 1687 return ret; 1688 1689 ret = keembay_build_groups(kpc); 1690 if (ret) 1691 return ret; 1692 1693 ret = keembay_build_functions(kpc); 1694 if (ret) 1695 return ret; 1696 1697 ret = keembay_gpiochip_probe(kpc, pdev); 1698 if (ret) 1699 return ret; 1700 1701 platform_set_drvdata(pdev, kpc); 1702 1703 return 0; 1704} 1705 1706static struct platform_driver keembay_pinctrl_driver = { 1707 .probe = keembay_pinctrl_probe, 1708 .driver = { 1709 .name = "keembay-pinctrl", 1710 .of_match_table = keembay_pinctrl_match, 1711 }, 1712}; 1713module_platform_driver(keembay_pinctrl_driver); 1714 1715MODULE_AUTHOR("Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>"); 1716MODULE_AUTHOR("Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>"); 1717MODULE_AUTHOR("Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>"); 1718MODULE_DESCRIPTION("Intel Keem Bay SoC pinctrl/GPIO driver"); 1719MODULE_LICENSE("GPL");
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