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pinctrl-gemini.c
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linux-6.19.14/drivers/pinctrl/pinctrl-gemini.c
1/* 2 * Driver for the Gemini pin controller 3 * 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * This is a group-only pin controller. 7 */ 8#include <linux/err.h> 9#include <linux/init.h> 10#include <linux/io.h> 11#include <linux/mfd/syscon.h> 12#include <linux/of.h> 13#include <linux/platform_device.h> 14#include <linux/regmap.h> 15#include <linux/seq_file.h> 16#include <linux/slab.h> 17#include <linux/string_choices.h> 18 19#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/pinconf-generic.h> 21#include <linux/pinctrl/pinconf.h> 22#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinmux.h> 24 25#include "pinctrl-utils.h" 26 27#define DRIVER_NAME "pinctrl-gemini" 28 29/** 30 * struct gemini_pin_conf - information about configuring a pin 31 * @pin: the pin number 32 * @reg: config register 33 * @mask: the bits affecting the configuration of the pin 34 */ 35struct gemini_pin_conf { 36 unsigned int pin; 37 u32 reg; 38 u32 mask; 39}; 40 41/** 42 * struct gemini_pmx - state holder for the gemini pin controller 43 * @dev: a pointer back to containing device 44 * @virtbase: the offset to the controller in virtual memory 45 * @map: regmap to access registers 46 * @is_3512: whether the SoC/package is the 3512 variant 47 * @is_3516: whether the SoC/package is the 3516 variant 48 * @flash_pin: whether the flash pin (extended pins for parallel 49 * flash) is set 50 * @confs: pin config information 51 * @nconfs: number of pin config information items 52 */ 53struct gemini_pmx { 54 struct device *dev; 55 struct pinctrl_dev *pctl; 56 struct regmap *map; 57 bool is_3512; 58 bool is_3516; 59 bool flash_pin; 60 const struct gemini_pin_conf *confs; 61 unsigned int nconfs; 62}; 63 64/** 65 * struct gemini_pin_group - describes a Gemini pin group 66 * @name: the name of this specific pin group 67 * @pins: an array of discrete physical pins used in this group, taken 68 * from the driver-local pin enumeration space 69 * @num_pins: the number of pins in this group array, i.e. the number of 70 * elements in .pins so we can iterate over that array 71 * @mask: bits to clear to enable this when doing pin muxing 72 * @value: bits to set to enable this when doing pin muxing 73 * @driving_mask: bitmask for the IO Pad driving register for this 74 * group, if it supports altering the driving strength of 75 * its lines. 76 */ 77struct gemini_pin_group { 78 const char *name; 79 const unsigned int *pins; 80 const unsigned int num_pins; 81 u32 mask; 82 u32 value; 83 u32 driving_mask; 84}; 85 86/* Some straight-forward control registers */ 87#define GLOBAL_WORD_ID 0x00 88#define GLOBAL_STATUS 0x04 89#define GLOBAL_STATUS_FLPIN BIT(20) 90#define GLOBAL_IODRIVE 0x10 91#define GLOBAL_GMAC_CTRL_SKEW 0x1c 92#define GLOBAL_GMAC0_DATA_SKEW 0x20 93#define GLOBAL_GMAC1_DATA_SKEW 0x24 94/* 95 * Global Miscellaneous Control Register 96 * This register controls all Gemini pad/pin multiplexing 97 * 98 * It is a tricky register though: 99 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot 100 * be brought back online, so it means permanent disablement of the 101 * corresponding pads. 102 * - For the bits named *_DISABLE, once you enable something, it cannot be 103 * DISABLED again. So you select a flash configuration once, and then 104 * you are stuck with it. 105 */ 106#define GLOBAL_MISC_CTRL 0x30 107#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) 108/* Not really used */ 109#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) 110/* Activated with GMAC1 */ 111#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) 112/* This will be the default */ 113#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 114#define TVC_CLK_PAD_ENABLE BIT(20) 115#define PCI_CLK_PAD_ENABLE BIT(17) 116#define LPC_CLK_PAD_ENABLE BIT(16) 117#define TVC_PADS_ENABLE BIT(9) 118#define SSP_PADS_ENABLE BIT(8) 119#define LCD_PADS_ENABLE BIT(7) 120#define LPC_PADS_ENABLE BIT(6) 121#define PCI_PADS_ENABLE BIT(5) 122#define IDE_PADS_ENABLE BIT(4) 123#define DRAM_PADS_POWERDOWN BIT(3) 124#define NAND_PADS_DISABLE BIT(2) 125#define PFLASH_PADS_DISABLE BIT(1) 126#define SFLASH_PADS_DISABLE BIT(0) 127#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) 128#define PADS_MAXBIT 27 129 130/* Ordered by bit index */ 131static const char * const gemini_padgroups[] = { 132 "serial flash", 133 "parallel flash", 134 "NAND flash", 135 "DRAM", 136 "IDE", 137 "PCI", 138 "LPC", 139 "LCD", 140 "SSP", 141 "TVC", 142 NULL, NULL, NULL, NULL, NULL, NULL, 143 "LPC CLK", 144 "PCI CLK", 145 NULL, NULL, 146 "TVC CLK", 147 NULL, NULL, NULL, NULL, NULL, 148 "GMAC1", 149}; 150 151static const struct pinctrl_pin_desc gemini_3512_pins[] = { 152 /* Row A */ 153 PINCTRL_PIN(0, "A1 VREF CTRL"), 154 PINCTRL_PIN(1, "A2 VCC2IO CTRL"), 155 PINCTRL_PIN(2, "A3 DRAM CK"), 156 PINCTRL_PIN(3, "A4 DRAM CK N"), 157 PINCTRL_PIN(4, "A5 DRAM A5"), 158 PINCTRL_PIN(5, "A6 DRAM CKE"), 159 PINCTRL_PIN(6, "A7 DRAM DQ11"), 160 PINCTRL_PIN(7, "A8 DRAM DQ0"), 161 PINCTRL_PIN(8, "A9 DRAM DQ5"), 162 PINCTRL_PIN(9, "A10 DRAM DQ6"), 163 PINCTRL_PIN(10, "A11 DRAM DRAM VREF"), 164 PINCTRL_PIN(11, "A12 DRAM BA1"), 165 PINCTRL_PIN(12, "A13 DRAM A2"), 166 PINCTRL_PIN(13, "A14 PCI GNT1 N"), 167 PINCTRL_PIN(14, "A15 PCI REQ9 N"), 168 PINCTRL_PIN(15, "A16 PCI REQ2 N"), 169 PINCTRL_PIN(16, "A17 PCI REQ3 N"), 170 PINCTRL_PIN(17, "A18 PCI AD31"), 171 /* Row B */ 172 PINCTRL_PIN(18, "B1 VCCK CTRL"), 173 PINCTRL_PIN(19, "B2 PWR EN"), 174 PINCTRL_PIN(20, "B3 RTC CLKI"), 175 PINCTRL_PIN(21, "B4 DRAM A4"), 176 PINCTRL_PIN(22, "B5 DRAM A6"), 177 PINCTRL_PIN(23, "B6 DRAM A12"), 178 PINCTRL_PIN(24, "B7 DRAM DQS1"), 179 PINCTRL_PIN(25, "B8 DRAM DQ15"), 180 PINCTRL_PIN(26, "B9 DRAM DQ4"), 181 PINCTRL_PIN(27, "B10 DRAM DQS0"), 182 PINCTRL_PIN(28, "B11 DRAM WE N"), 183 PINCTRL_PIN(29, "B12 DRAM A10"), 184 PINCTRL_PIN(30, "B13 DRAM A3"), 185 PINCTRL_PIN(31, "B14 PCI GNT0 N"), 186 PINCTRL_PIN(32, "B15 PCI GNT3 N"), 187 PINCTRL_PIN(33, "B16 PCI REQ1 N"), 188 PINCTRL_PIN(34, "B17 PCI AD30"), 189 PINCTRL_PIN(35, "B18 PCI AD29"), 190 /* Row C */ 191 PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */ 192 PINCTRL_PIN(37, "C2 XTALI"), 193 PINCTRL_PIN(38, "C3 PWR BTN"), 194 PINCTRL_PIN(39, "C4 RTC CLKO"), 195 PINCTRL_PIN(40, "C5 DRAM A7"), 196 PINCTRL_PIN(41, "C6 DRAM A11"), 197 PINCTRL_PIN(42, "C7 DRAM DQ10"), 198 PINCTRL_PIN(43, "C8 DRAM DQ14"), 199 PINCTRL_PIN(44, "C9 DRAM DQ3"), 200 PINCTRL_PIN(45, "C10 DRAM DQ7"), 201 PINCTRL_PIN(46, "C11 DRAM CAS N"), 202 PINCTRL_PIN(47, "C12 DRAM A0"), 203 PINCTRL_PIN(48, "C13 PCI INT0 N"), 204 PINCTRL_PIN(49, "C14 EXT RESET N"), 205 PINCTRL_PIN(50, "C15 PCI GNT2 N"), 206 PINCTRL_PIN(51, "C16 PCI AD28"), 207 PINCTRL_PIN(52, "C17 PCI AD27"), 208 PINCTRL_PIN(53, "C18 PCI AD26"), 209 /* Row D */ 210 PINCTRL_PIN(54, "D1 AVCCKHA"), 211 PINCTRL_PIN(55, "D2 AGNDIOHA"), 212 PINCTRL_PIN(56, "D3 XTALO"), 213 PINCTRL_PIN(57, "D4 AVCC3IOHA"), 214 PINCTRL_PIN(58, "D5 DRAM A8"), 215 PINCTRL_PIN(59, "D6 DRAM A9"), 216 PINCTRL_PIN(60, "D7 DRAM DQ9"), 217 PINCTRL_PIN(61, "D8 DRAM DQ13"), 218 PINCTRL_PIN(62, "D9 DRAM DQ2"), 219 PINCTRL_PIN(63, "D10 DRAM A13"), 220 PINCTRL_PIN(64, "D11 DRAM RAS N"), 221 PINCTRL_PIN(65, "D12 DRAM A1"), 222 PINCTRL_PIN(66, "D13 PCI INTC N"), 223 PINCTRL_PIN(67, "D14 PCI CLK"), 224 PINCTRL_PIN(68, "D15 PCI AD25"), 225 PINCTRL_PIN(69, "D16 PCI AD24"), 226 PINCTRL_PIN(70, "D17 PCI CBE3 N"), 227 PINCTRL_PIN(71, "D18 PCI AD23"), 228 /* Row E */ 229 PINCTRL_PIN(72, "E1 AVCC3IOHA"), 230 PINCTRL_PIN(73, "E2 EBG"), 231 PINCTRL_PIN(74, "E3 AVCC3IOHB"), 232 PINCTRL_PIN(75, "E4 REXT"), 233 PINCTRL_PIN(76, "E5 GND"), 234 PINCTRL_PIN(77, "E6 DRAM DQM1"), 235 PINCTRL_PIN(78, "E7 DRAM DQ8"), 236 PINCTRL_PIN(79, "E8 DRAM DQ12"), 237 PINCTRL_PIN(80, "E9 DRAM DQ1"), 238 PINCTRL_PIN(81, "E10 DRAM DQM0"), 239 PINCTRL_PIN(82, "E11 DRAM BA0"), 240 PINCTRL_PIN(83, "E12 PCI INTA N"), 241 PINCTRL_PIN(84, "E13 PCI INTB N"), 242 PINCTRL_PIN(85, "E14 GND"), 243 PINCTRL_PIN(86, "E15 PCI AD22"), 244 PINCTRL_PIN(87, "E16 PCI AD21"), 245 PINCTRL_PIN(88, "E17 PCI AD20"), 246 PINCTRL_PIN(89, "E18 PCI AD19"), 247 /* Row F */ 248 PINCTRL_PIN(90, "F1 SATA0 RXDP"), 249 PINCTRL_PIN(91, "F2 SATA0 RXDN"), 250 PINCTRL_PIN(92, "F3 AGNDK 0"), 251 PINCTRL_PIN(93, "F4 AVCC3 S"), 252 PINCTRL_PIN(94, "F5 AVCCK P"), 253 PINCTRL_PIN(95, "F6 GND"), 254 PINCTRL_PIN(96, "F7 VCC2IOHA 2"), 255 PINCTRL_PIN(97, "F8 VCC2IOHA 2"), 256 PINCTRL_PIN(98, "F9 V1"), 257 PINCTRL_PIN(99, "F10 V1"), 258 PINCTRL_PIN(100, "F11 VCC2IOHA 2"), 259 PINCTRL_PIN(101, "F12 VCC2IOHA 2"), 260 PINCTRL_PIN(102, "F13 GND"), 261 PINCTRL_PIN(103, "F14 PCI AD18"), 262 PINCTRL_PIN(104, "F15 PCI AD17"), 263 PINCTRL_PIN(105, "F16 PCI AD16"), 264 PINCTRL_PIN(106, "F17 PCI CBE2 N"), 265 PINCTRL_PIN(107, "F18 PCI FRAME N"), 266 /* Row G */ 267 PINCTRL_PIN(108, "G1 SATA0 TXDP"), 268 PINCTRL_PIN(109, "G2 SATA0 TXDN"), 269 PINCTRL_PIN(110, "G3 AGNDK 1"), 270 PINCTRL_PIN(111, "G4 AVCCK 0"), 271 PINCTRL_PIN(112, "G5 TEST CLKOUT"), 272 PINCTRL_PIN(113, "G6 AGND"), 273 PINCTRL_PIN(114, "G7 GND"), 274 PINCTRL_PIN(115, "G8 VCC2IOHA 2"), 275 PINCTRL_PIN(116, "G9 V1"), 276 PINCTRL_PIN(117, "G10 V1"), 277 PINCTRL_PIN(118, "G11 VCC2IOHA 2"), 278 PINCTRL_PIN(119, "G12 GND"), 279 PINCTRL_PIN(120, "G13 VCC3IOHA"), 280 PINCTRL_PIN(121, "G14 PCI IRDY N"), 281 PINCTRL_PIN(122, "G15 PCI TRDY N"), 282 PINCTRL_PIN(123, "G16 PCI DEVSEL N"), 283 PINCTRL_PIN(124, "G17 PCI STOP N"), 284 PINCTRL_PIN(125, "G18 PCI PAR"), 285 /* Row H */ 286 PINCTRL_PIN(126, "H1 SATA1 TXDP"), 287 PINCTRL_PIN(127, "H2 SATA1 TXDN"), 288 PINCTRL_PIN(128, "H3 AGNDK 2"), 289 PINCTRL_PIN(129, "H4 AVCCK 1"), 290 PINCTRL_PIN(130, "H5 AVCCK S"), 291 PINCTRL_PIN(131, "H6 AVCCKHB"), 292 PINCTRL_PIN(132, "H7 AGND"), 293 PINCTRL_PIN(133, "H8 GND"), 294 PINCTRL_PIN(134, "H9 GND"), 295 PINCTRL_PIN(135, "H10 GND"), 296 PINCTRL_PIN(136, "H11 GND"), 297 PINCTRL_PIN(137, "H12 VCC3IOHA"), 298 PINCTRL_PIN(138, "H13 VCC3IOHA"), 299 PINCTRL_PIN(139, "H14 PCI CBE1 N"), 300 PINCTRL_PIN(140, "H15 PCI AD15"), 301 PINCTRL_PIN(141, "H16 PCI AD14"), 302 PINCTRL_PIN(142, "H17 PCI AD13"), 303 PINCTRL_PIN(143, "H18 PCI AD12"), 304 /* Row J (for some reason I is skipped) */ 305 PINCTRL_PIN(144, "J1 SATA1 RXDP"), 306 PINCTRL_PIN(145, "J2 SATA1 RXDN"), 307 PINCTRL_PIN(146, "J3 AGNDK 3"), 308 PINCTRL_PIN(147, "J4 AVCCK 2"), 309 PINCTRL_PIN(148, "J5 IDE DA1"), 310 PINCTRL_PIN(149, "J6 V1"), 311 PINCTRL_PIN(150, "J7 V1"), 312 PINCTRL_PIN(151, "J8 GND"), 313 PINCTRL_PIN(152, "J9 GND"), 314 PINCTRL_PIN(153, "J10 GND"), 315 PINCTRL_PIN(154, "J11 GND"), 316 PINCTRL_PIN(155, "J12 V1"), 317 PINCTRL_PIN(156, "J13 V1"), 318 PINCTRL_PIN(157, "J14 PCI AD11"), 319 PINCTRL_PIN(158, "J15 PCI AD10"), 320 PINCTRL_PIN(159, "J16 PCI AD9"), 321 PINCTRL_PIN(160, "J17 PCI AD8"), 322 PINCTRL_PIN(161, "J18 PCI CBE0 N"), 323 /* Row K */ 324 PINCTRL_PIN(162, "K1 IDE CS1 N"), 325 PINCTRL_PIN(163, "K2 IDE CS0 N"), 326 PINCTRL_PIN(164, "K3 AVCCK 3"), 327 PINCTRL_PIN(165, "K4 IDE DA2"), 328 PINCTRL_PIN(166, "K5 IDE DA0"), 329 PINCTRL_PIN(167, "K6 V1"), 330 PINCTRL_PIN(168, "K7 V1"), 331 PINCTRL_PIN(169, "K8 GND"), 332 PINCTRL_PIN(170, "K9 GND"), 333 PINCTRL_PIN(171, "K10 GND"), 334 PINCTRL_PIN(172, "K11 GND"), 335 PINCTRL_PIN(173, "K12 V1"), 336 PINCTRL_PIN(174, "K13 V1"), 337 PINCTRL_PIN(175, "K14 PCI AD3"), 338 PINCTRL_PIN(176, "K15 PCI AD4"), 339 PINCTRL_PIN(177, "K16 PCI AD5"), 340 PINCTRL_PIN(178, "K17 PCI AD6"), 341 PINCTRL_PIN(179, "K18 PCI AD7"), 342 /* Row L */ 343 PINCTRL_PIN(180, "L1 IDE INTRQ"), 344 PINCTRL_PIN(181, "L2 IDE DMACK N"), 345 PINCTRL_PIN(182, "L3 IDE IORDY"), 346 PINCTRL_PIN(183, "L4 IDE DIOR N"), 347 PINCTRL_PIN(184, "L5 IDE DIOW N"), 348 PINCTRL_PIN(185, "L6 VCC3IOHA"), 349 PINCTRL_PIN(186, "L7 VCC3IOHA"), 350 PINCTRL_PIN(187, "L8 GND"), 351 PINCTRL_PIN(188, "L9 GND"), 352 PINCTRL_PIN(189, "L10 GND"), 353 PINCTRL_PIN(190, "L11 GND"), 354 PINCTRL_PIN(191, "L12 VCC3IOHA"), 355 PINCTRL_PIN(192, "L13 VCC3IOHA"), 356 PINCTRL_PIN(193, "L14 GPIO0 30"), 357 PINCTRL_PIN(194, "L15 GPIO0 31"), 358 PINCTRL_PIN(195, "L16 PCI AD0"), 359 PINCTRL_PIN(196, "L17 PCI AD1"), 360 PINCTRL_PIN(197, "L18 PCI AD2"), 361 /* Row M */ 362 PINCTRL_PIN(198, "M1 IDE DMARQ"), 363 PINCTRL_PIN(199, "M2 IDE DD15"), 364 PINCTRL_PIN(200, "M3 IDE DD0"), 365 PINCTRL_PIN(201, "M4 IDE DD14"), 366 PINCTRL_PIN(202, "M5 IDE DD1"), 367 PINCTRL_PIN(203, "M6 VCC3IOHA"), 368 PINCTRL_PIN(204, "M7 GND"), 369 PINCTRL_PIN(205, "M8 VCC2IOHA 1"), 370 PINCTRL_PIN(206, "M9 V1"), 371 PINCTRL_PIN(207, "M10 V1"), 372 PINCTRL_PIN(208, "M11 VCC3IOHA"), 373 PINCTRL_PIN(209, "M12 GND"), 374 PINCTRL_PIN(210, "M13 VCC3IOHA"), 375 PINCTRL_PIN(211, "M14 GPIO0 25"), 376 PINCTRL_PIN(212, "M15 GPIO0 26"), 377 PINCTRL_PIN(213, "M16 GPIO0 27"), 378 PINCTRL_PIN(214, "M17 GPIO0 28"), 379 PINCTRL_PIN(215, "M18 GPIO0 29"), 380 /* Row N */ 381 PINCTRL_PIN(216, "N1 IDE DD13"), 382 PINCTRL_PIN(217, "N2 IDE DD2"), 383 PINCTRL_PIN(218, "N3 IDE DD12"), 384 PINCTRL_PIN(219, "N4 IDE DD3"), 385 PINCTRL_PIN(220, "N5 IDE DD11"), 386 PINCTRL_PIN(221, "N6 GND"), 387 PINCTRL_PIN(222, "N7 VCC2IOHA 1"), 388 PINCTRL_PIN(223, "N8 VCC2IOHA 1"), 389 PINCTRL_PIN(224, "N9 V1"), 390 PINCTRL_PIN(225, "N10 V1"), 391 PINCTRL_PIN(226, "N11 VCC3IOHA"), 392 PINCTRL_PIN(227, "N12 VCC3IOHA"), 393 PINCTRL_PIN(228, "N13 GND"), 394 PINCTRL_PIN(229, "N14 GPIO0 20"), 395 PINCTRL_PIN(230, "N15 GPIO0 21"), 396 PINCTRL_PIN(231, "N16 GPIO0 22"), 397 PINCTRL_PIN(232, "N17 GPIO0 23"), 398 PINCTRL_PIN(233, "N18 GPIO0 24"), 399 /* Row P (for some reason O is skipped) */ 400 PINCTRL_PIN(234, "P1 IDE DD4"), 401 PINCTRL_PIN(235, "P2 IDE DD10"), 402 PINCTRL_PIN(236, "P3 IDE DD5"), 403 PINCTRL_PIN(237, "P4 IDE DD9"), 404 PINCTRL_PIN(238, "P5 GND"), 405 PINCTRL_PIN(239, "P6 USB XSCO"), 406 PINCTRL_PIN(240, "P7 GMAC0 TXD3"), 407 PINCTRL_PIN(241, "P8 GMAC0 TXEN"), 408 PINCTRL_PIN(242, "P9 GMAC0 RXD2"), 409 PINCTRL_PIN(243, "P10 GMAC1 TXC"), 410 PINCTRL_PIN(244, "P11 GMAC1 RXD1"), 411 PINCTRL_PIN(245, "P12 MODE SEL 1"), 412 PINCTRL_PIN(246, "P13 GPIO1 28"), 413 PINCTRL_PIN(247, "P14 GND"), 414 PINCTRL_PIN(248, "P15 GPIO0 5"), 415 PINCTRL_PIN(249, "P16 GPIO0 17"), 416 PINCTRL_PIN(250, "P17 GPIO0 18"), 417 PINCTRL_PIN(251, "P18 GPIO0 19"), 418 /* Row R (for some reason Q is skipped) */ 419 PINCTRL_PIN(252, "R1 IDE DD6"), 420 PINCTRL_PIN(253, "R2 IDE DD8"), 421 PINCTRL_PIN(254, "R3 IDE DD7"), 422 PINCTRL_PIN(255, "R4 IDE RESET N"), 423 PINCTRL_PIN(256, "R5 ICE0 DBGACK"), 424 PINCTRL_PIN(257, "R6 USB XSCI"), 425 PINCTRL_PIN(258, "R7 GMAC0 TXD2"), 426 PINCTRL_PIN(259, "R8 GMAC0 RXDV"), 427 PINCTRL_PIN(260, "R9 GMAC0 RXD3"), 428 PINCTRL_PIN(261, "R10 GMAC1 TXD0"), 429 PINCTRL_PIN(262, "R11 GMAC1 RXD0"), 430 PINCTRL_PIN(263, "R12 MODE SEL 0"), 431 PINCTRL_PIN(264, "R13 MODE SEL 3"), 432 PINCTRL_PIN(265, "R14 GPIO0 0"), 433 PINCTRL_PIN(266, "R15 GPIO0 4"), 434 PINCTRL_PIN(267, "R16 GPIO0 9"), 435 PINCTRL_PIN(268, "R17 GPIO0 15"), 436 PINCTRL_PIN(269, "R18 GPIO0 16"), 437 /* Row T (for some reason S is skipped) */ 438 PINCTRL_PIN(270, "T1 ICE0 DBGRQ"), 439 PINCTRL_PIN(271, "T2 ICE0 IDO"), 440 PINCTRL_PIN(272, "T3 ICE0 ICK"), 441 PINCTRL_PIN(273, "T4 ICE0 IMS"), 442 PINCTRL_PIN(274, "T5 ICE0 IDI"), 443 PINCTRL_PIN(275, "T6 USB RREF"), 444 PINCTRL_PIN(276, "T7 GMAC0 TXD1"), 445 PINCTRL_PIN(277, "T8 GMAC0 RXC"), 446 PINCTRL_PIN(278, "T9 GMAC0 CRS"), 447 PINCTRL_PIN(279, "T10 GMAC1 TXD1"), 448 PINCTRL_PIN(280, "T11 GMAC1 RXC"), 449 PINCTRL_PIN(281, "T12 GMAC1 CRS"), 450 PINCTRL_PIN(282, "T13 EXT CLK"), 451 PINCTRL_PIN(283, "T14 GPIO1 31"), 452 PINCTRL_PIN(284, "T15 GPIO0 3"), 453 PINCTRL_PIN(285, "T16 GPIO0 8"), 454 PINCTRL_PIN(286, "T17 GPIO0 12"), 455 PINCTRL_PIN(287, "T18 GPIO0 14"), 456 /* Row U */ 457 PINCTRL_PIN(288, "U1 ICE0 IRST N"), 458 PINCTRL_PIN(289, "U2 USB0 VCCHSRT"), 459 PINCTRL_PIN(290, "U3 USB0 DP"), 460 PINCTRL_PIN(291, "U4 USB VCCA U20"), 461 PINCTRL_PIN(292, "U5 USB1 DP"), 462 PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"), 463 PINCTRL_PIN(294, "U7 GMAC0 TXD0"), 464 PINCTRL_PIN(295, "U8 GMAC0 RXD0"), 465 PINCTRL_PIN(296, "U9 GMAC1 COL"), 466 PINCTRL_PIN(297, "U10 GMAC1 TXD2"), 467 PINCTRL_PIN(298, "U11 GMAC1 RXDV"), 468 PINCTRL_PIN(299, "U12 GMAC1 RXD3"), 469 PINCTRL_PIN(300, "U13 MODE SEL 2"), 470 PINCTRL_PIN(301, "U14 GPIO1 30"), 471 PINCTRL_PIN(302, "U15 GPIO0 2"), 472 PINCTRL_PIN(303, "U16 GPIO0 7"), 473 PINCTRL_PIN(304, "U17 GPIO0 11"), 474 PINCTRL_PIN(305, "U18 GPIO0 13"), 475 /* Row V */ 476 PINCTRL_PIN(306, "V1 USB0 GNDHSRT"), 477 PINCTRL_PIN(307, "V2 USB0 DM"), 478 PINCTRL_PIN(308, "V3 USB GNDA U20"), 479 PINCTRL_PIN(309, "V4 USB1 DM"), 480 PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"), 481 PINCTRL_PIN(311, "V6 GMAC0 COL"), 482 PINCTRL_PIN(312, "V7 GMAC0 TXC"), 483 PINCTRL_PIN(313, "V8 GMAC0 RXD1"), 484 PINCTRL_PIN(314, "V9 REF CLK"), 485 PINCTRL_PIN(315, "V10 GMAC1 TXD3"), 486 PINCTRL_PIN(316, "V11 GMAC1 TXEN"), 487 PINCTRL_PIN(317, "V12 GMAC1 RXD2"), 488 PINCTRL_PIN(318, "V13 M30 CLK"), 489 PINCTRL_PIN(319, "V14 GPIO1 29"), 490 PINCTRL_PIN(320, "V15 GPIO0 1"), 491 PINCTRL_PIN(321, "V16 GPIO0 6"), 492 PINCTRL_PIN(322, "V17 GPIO0 10"), 493 PINCTRL_PIN(323, "V18 SYS RESET N"), 494}; 495 496 497/* Digital ground */ 498static const unsigned int gnd_3512_pins[] = { 499 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169, 500 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247 501}; 502 503static const unsigned int dram_3512_pins[] = { 504 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29, 505 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77, 506 78, 79, 80, 81, 82 507}; 508 509static const unsigned int rtc_3512_pins[] = { 57, 20, 39 }; 510 511static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 }; 512 513static const unsigned int system_3512_pins[] = { 514 318, 264, 300, 245, 263, 282, 314, 323, 49, 515}; 516 517static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 }; 518 519static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 }; 520 521static const unsigned int ide_3512_pins[] = { 522 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202, 523 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255 524}; 525 526static const unsigned int sata_3512_pins[] = { 527 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129, 528 128, 127, 126, 147, 146, 145, 144, 164 529}; 530 531static const unsigned int usb_3512_pins[] = { 532 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293 533}; 534 535/* GMII, ethernet pins */ 536static const unsigned int gmii_gmac0_3512_pins[] = { 537 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 538}; 539 540static const unsigned int gmii_gmac1_3512_pins[] = { 541 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 542}; 543 544static const unsigned int pci_3512_pins[] = { 545 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69, 546 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123, 547 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177, 548 178, 179, 195, 196, 197 549}; 550 551/* 552 * Apparently the LPC interface is using the PCICLK for the clocking so 553 * PCI needs to be active at the same time. 554 */ 555static const unsigned int lpc_3512_pins[] = { 556 285, /* LPC_LAD[0] */ 557 304, /* LPC_SERIRQ */ 558 286, /* LPC_LAD[2] */ 559 305, /* LPC_LFRAME# */ 560 287, /* LPC_LAD[3] */ 561 268, /* LPC_LAD[1] */ 562}; 563 564/* Character LCD */ 565static const unsigned int lcd_3512_pins[] = { 566 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211 567}; 568 569static const unsigned int ssp_3512_pins[] = { 570 285, /* SSP_97RST# SSP AC97 Reset, active low */ 571 304, /* SSP_FSC */ 572 286, /* SSP_ECLK */ 573 305, /* SSP_TXD */ 574 287, /* SSP_RXD */ 575 268, /* SSP_SCLK */ 576}; 577 578static const unsigned int uart_rxtx_3512_pins[] = { 579 267, /* UART_SIN serial input, RX */ 580 322, /* UART_SOUT serial output, TX */ 581}; 582 583static const unsigned int uart_modem_3512_pins[] = { 584 285, /* UART_NDCD DCD carrier detect */ 585 304, /* UART_NDTR DTR data terminal ready */ 586 286, /* UART_NDSR DSR data set ready */ 587 305, /* UART_NRTS RTS request to send */ 588 287, /* UART_NCTS CTS clear to send */ 589 268, /* UART_NRI RI ring indicator */ 590}; 591 592static const unsigned int tvc_3512_pins[] = { 593 246, /* TVC_DATA[0] */ 594 319, /* TVC_DATA[1] */ 595 301, /* TVC_DATA[2] */ 596 283, /* TVC_DATA[3] */ 597 320, /* TVC_DATA[4] */ 598 302, /* TVC_DATA[5] */ 599 284, /* TVC_DATA[6] */ 600 266, /* TVC_DATA[7] */ 601}; 602 603static const unsigned int tvc_clk_3512_pins[] = { 604 265, /* TVC_CLK */ 605}; 606 607/* NAND flash pins */ 608static const unsigned int nflash_3512_pins[] = { 609 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 610 253, 254, 249, 250, 232, 233, 211, 193, 194 611}; 612 613/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 614static const unsigned int pflash_3512_pins[] = { 615 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 616 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 617 214, 215, 193, 194 618}; 619 620/* 621 * The parallel flash can be set up in a 26-bit address bus mode exposing 622 * A[0-15] (A[15] takes the place of ALE), but it has the 623 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 624 * used at the same time. 625 */ 626static const unsigned int pflash_3512_pins_extended[] = { 627 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 628 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 629 214, 215, 193, 194, 630 /* The extra pins */ 631 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281, 632 265, 633}; 634 635/* Serial flash pins CE0, CE1, DI, DO, CK */ 636static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; 637 638/* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */ 639static const unsigned int gpio0a_3512_pins[] = { 265 }; 640 641/* The GPIO0B (1-4) pins overlap with TVC and ICE */ 642static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 }; 643 644/* The GPIO0C (5-7) pins overlap with ICE */ 645static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 }; 646 647/* The GPIO0D (9,10) pins overlap with UART RX/TX */ 648static const unsigned int gpio0d_3512_pins[] = { 267, 322 }; 649 650/* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ 651static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 }; 652 653/* The GPIO0F (16) pins overlap with LCD */ 654static const unsigned int gpio0f_3512_pins[] = { 269 }; 655 656/* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ 657static const unsigned int gpio0g_3512_pins[] = { 249, 250 }; 658 659/* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ 660static const unsigned int gpio0h_3512_pins[] = { 251, 229 }; 661 662/* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ 663static const unsigned int gpio0i_3512_pins[] = { 230, 231 }; 664 665/* The GPIO0J (23) pins overlap with all flash */ 666static const unsigned int gpio0j_3512_pins[] = { 232 }; 667 668/* The GPIO0K (24,25) pins overlap with all flash and LCD */ 669static const unsigned int gpio0k_3512_pins[] = { 233, 211 }; 670 671/* The GPIO0L (26-29) pins overlap with parallel flash */ 672static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 }; 673 674/* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ 675static const unsigned int gpio0m_3512_pins[] = { 193, 194 }; 676 677/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 678static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 }; 679 680/* The GPIO1B (5-10, 27) pins overlap with just IDE */ 681static const unsigned int gpio1b_3512_pins[] = { 682 180, 181, 182, 183, 184, 198, 255 683}; 684 685/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 686static const unsigned int gpio1c_3512_pins[] = { 687 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 688 252, 253, 254 689}; 690 691/* The GPIO1D (28-31) pins overlap with LCD and TVC */ 692static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; 693 694/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ 695static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; 696 697/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ 698static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; 699 700/* The GPIO2C (8-31) pins overlap with PCI */ 701static const unsigned int gpio2c_3512_pins[] = { 702 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105, 703 140, 141, 142, 143, 157, 158, 159, 160 704}; 705 706/* Groups for the 3512 SoC/package */ 707static const struct gemini_pin_group gemini_3512_pin_groups[] = { 708 { 709 .name = "gndgrp", 710 .pins = gnd_3512_pins, 711 .num_pins = ARRAY_SIZE(gnd_3512_pins), 712 }, 713 { 714 .name = "dramgrp", 715 .pins = dram_3512_pins, 716 .num_pins = ARRAY_SIZE(dram_3512_pins), 717 .mask = DRAM_PADS_POWERDOWN, 718 }, 719 { 720 .name = "rtcgrp", 721 .pins = rtc_3512_pins, 722 .num_pins = ARRAY_SIZE(rtc_3512_pins), 723 }, 724 { 725 .name = "powergrp", 726 .pins = power_3512_pins, 727 .num_pins = ARRAY_SIZE(power_3512_pins), 728 }, 729 { 730 .name = "systemgrp", 731 .pins = system_3512_pins, 732 .num_pins = ARRAY_SIZE(system_3512_pins), 733 }, 734 { 735 .name = "vcontrolgrp", 736 .pins = vcontrol_3512_pins, 737 .num_pins = ARRAY_SIZE(vcontrol_3512_pins), 738 }, 739 { 740 .name = "icegrp", 741 .pins = ice_3512_pins, 742 .num_pins = ARRAY_SIZE(ice_3512_pins), 743 /* Conflict with some GPIO groups */ 744 }, 745 { 746 .name = "idegrp", 747 .pins = ide_3512_pins, 748 .num_pins = ARRAY_SIZE(ide_3512_pins), 749 /* Conflict with all flash usage */ 750 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 751 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 752 .driving_mask = GENMASK(21, 20), 753 }, 754 { 755 .name = "satagrp", 756 .pins = sata_3512_pins, 757 .num_pins = ARRAY_SIZE(sata_3512_pins), 758 }, 759 { 760 .name = "usbgrp", 761 .pins = usb_3512_pins, 762 .num_pins = ARRAY_SIZE(usb_3512_pins), 763 }, 764 { 765 .name = "gmii_gmac0_grp", 766 .pins = gmii_gmac0_3512_pins, 767 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), 768 .driving_mask = GENMASK(17, 16), 769 }, 770 { 771 .name = "gmii_gmac1_grp", 772 .pins = gmii_gmac1_3512_pins, 773 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), 774 /* Bring out RGMII on the GMAC1 pins */ 775 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 776 .driving_mask = GENMASK(19, 18), 777 }, 778 { 779 .name = "pcigrp", 780 .pins = pci_3512_pins, 781 .num_pins = ARRAY_SIZE(pci_3512_pins), 782 /* Conflict only with GPIO2 */ 783 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 784 .driving_mask = GENMASK(23, 22), 785 }, 786 { 787 .name = "lpcgrp", 788 .pins = lpc_3512_pins, 789 .num_pins = ARRAY_SIZE(lpc_3512_pins), 790 /* Conflict with SSP and UART modem pins */ 791 .mask = SSP_PADS_ENABLE, 792 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 793 }, 794 { 795 .name = "lcdgrp", 796 .pins = lcd_3512_pins, 797 .num_pins = ARRAY_SIZE(lcd_3512_pins), 798 /* Conflict with TVC and ICE */ 799 .mask = TVC_PADS_ENABLE, 800 .value = LCD_PADS_ENABLE, 801 }, 802 { 803 .name = "sspgrp", 804 .pins = ssp_3512_pins, 805 .num_pins = ARRAY_SIZE(ssp_3512_pins), 806 /* Conflict with LPC and UART modem pins */ 807 .mask = LPC_PADS_ENABLE, 808 .value = SSP_PADS_ENABLE, 809 }, 810 { 811 .name = "uartrxtxgrp", 812 .pins = uart_rxtx_3512_pins, 813 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins), 814 /* No conflicts except GPIO */ 815 }, 816 { 817 .name = "uartmodemgrp", 818 .pins = uart_modem_3512_pins, 819 .num_pins = ARRAY_SIZE(uart_modem_3512_pins), 820 /* 821 * Conflict with LPC and SSP, 822 * so when those are both disabled, modem UART can thrive. 823 */ 824 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 825 }, 826 { 827 .name = "tvcgrp", 828 .pins = tvc_3512_pins, 829 .num_pins = ARRAY_SIZE(tvc_3512_pins), 830 /* Conflict with character LCD and ICE */ 831 .mask = LCD_PADS_ENABLE, 832 .value = TVC_PADS_ENABLE, 833 }, 834 { 835 .name = "tvcclkgrp", 836 .pins = tvc_clk_3512_pins, 837 .num_pins = ARRAY_SIZE(tvc_clk_3512_pins), 838 .value = TVC_CLK_PAD_ENABLE, 839 }, 840 /* 841 * The construction is done such that it is possible to use a serial 842 * flash together with a NAND or parallel (NOR) flash, but it is not 843 * possible to use NAND and parallel flash together. To use serial 844 * flash with one of the two others, the muxbits need to be flipped 845 * around before any access. 846 */ 847 { 848 .name = "nflashgrp", 849 .pins = nflash_3512_pins, 850 .num_pins = ARRAY_SIZE(nflash_3512_pins), 851 /* Conflict with IDE, parallel and serial flash */ 852 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 853 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 854 }, 855 { 856 .name = "pflashgrp", 857 .pins = pflash_3512_pins, 858 .num_pins = ARRAY_SIZE(pflash_3512_pins), 859 /* Conflict with IDE, NAND and serial flash */ 860 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 861 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 862 }, 863 { 864 .name = "sflashgrp", 865 .pins = sflash_3512_pins, 866 .num_pins = ARRAY_SIZE(sflash_3512_pins), 867 /* Conflict with IDE, NAND and parallel flash */ 868 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 869 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 870 }, 871 { 872 .name = "gpio0agrp", 873 .pins = gpio0a_3512_pins, 874 .num_pins = ARRAY_SIZE(gpio0a_3512_pins), 875 /* Conflict with TVC CLK */ 876 .mask = TVC_CLK_PAD_ENABLE, 877 }, 878 { 879 .name = "gpio0bgrp", 880 .pins = gpio0b_3512_pins, 881 .num_pins = ARRAY_SIZE(gpio0b_3512_pins), 882 /* Conflict with TVC and ICE */ 883 .mask = TVC_PADS_ENABLE, 884 }, 885 { 886 .name = "gpio0cgrp", 887 .pins = gpio0c_3512_pins, 888 .num_pins = ARRAY_SIZE(gpio0c_3512_pins), 889 /* Conflict with ICE */ 890 }, 891 { 892 .name = "gpio0dgrp", 893 .pins = gpio0d_3512_pins, 894 .num_pins = ARRAY_SIZE(gpio0d_3512_pins), 895 /* Conflict with UART RX/TX */ 896 }, 897 { 898 .name = "gpio0egrp", 899 .pins = gpio0e_3512_pins, 900 .num_pins = ARRAY_SIZE(gpio0e_3512_pins), 901 /* Conflict with LPC, UART modem pins, SSP */ 902 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 903 }, 904 { 905 .name = "gpio0fgrp", 906 .pins = gpio0f_3512_pins, 907 .num_pins = ARRAY_SIZE(gpio0f_3512_pins), 908 /* Conflict with LCD */ 909 .mask = LCD_PADS_ENABLE, 910 }, 911 { 912 .name = "gpio0ggrp", 913 .pins = gpio0g_3512_pins, 914 .num_pins = ARRAY_SIZE(gpio0g_3512_pins), 915 /* Conflict with NAND flash */ 916 .value = NAND_PADS_DISABLE, 917 }, 918 { 919 .name = "gpio0hgrp", 920 .pins = gpio0h_3512_pins, 921 .num_pins = ARRAY_SIZE(gpio0h_3512_pins), 922 /* Conflict with parallel flash */ 923 .value = PFLASH_PADS_DISABLE, 924 }, 925 { 926 .name = "gpio0igrp", 927 .pins = gpio0i_3512_pins, 928 .num_pins = ARRAY_SIZE(gpio0i_3512_pins), 929 /* Conflict with serial flash */ 930 .value = SFLASH_PADS_DISABLE, 931 }, 932 { 933 .name = "gpio0jgrp", 934 .pins = gpio0j_3512_pins, 935 .num_pins = ARRAY_SIZE(gpio0j_3512_pins), 936 /* Conflict with all flash */ 937 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 938 SFLASH_PADS_DISABLE, 939 }, 940 { 941 .name = "gpio0kgrp", 942 .pins = gpio0k_3512_pins, 943 .num_pins = ARRAY_SIZE(gpio0k_3512_pins), 944 /* Conflict with all flash and LCD */ 945 .mask = LCD_PADS_ENABLE, 946 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 947 SFLASH_PADS_DISABLE, 948 }, 949 { 950 .name = "gpio0lgrp", 951 .pins = gpio0l_3512_pins, 952 .num_pins = ARRAY_SIZE(gpio0l_3512_pins), 953 /* Conflict with parallel flash */ 954 .value = PFLASH_PADS_DISABLE, 955 }, 956 { 957 .name = "gpio0mgrp", 958 .pins = gpio0m_3512_pins, 959 .num_pins = ARRAY_SIZE(gpio0m_3512_pins), 960 /* Conflict with parallel and NAND flash */ 961 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 962 }, 963 { 964 .name = "gpio1agrp", 965 .pins = gpio1a_3512_pins, 966 .num_pins = ARRAY_SIZE(gpio1a_3512_pins), 967 /* Conflict with IDE and parallel flash */ 968 .mask = IDE_PADS_ENABLE, 969 .value = PFLASH_PADS_DISABLE, 970 }, 971 { 972 .name = "gpio1bgrp", 973 .pins = gpio1b_3512_pins, 974 .num_pins = ARRAY_SIZE(gpio1b_3512_pins), 975 /* Conflict with IDE only */ 976 .mask = IDE_PADS_ENABLE, 977 }, 978 { 979 .name = "gpio1cgrp", 980 .pins = gpio1c_3512_pins, 981 .num_pins = ARRAY_SIZE(gpio1c_3512_pins), 982 /* Conflict with IDE, parallel and NAND flash */ 983 .mask = IDE_PADS_ENABLE, 984 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 985 }, 986 { 987 .name = "gpio1dgrp", 988 .pins = gpio1d_3512_pins, 989 .num_pins = ARRAY_SIZE(gpio1d_3512_pins), 990 /* Conflict with LCD and TVC */ 991 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, 992 }, 993 { 994 .name = "gpio2agrp", 995 .pins = gpio2a_3512_pins, 996 .num_pins = ARRAY_SIZE(gpio2a_3512_pins), 997 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 998 /* Conflict with GMII GMAC1 and extended parallel flash */ 999 }, 1000 { 1001 .name = "gpio2bgrp", 1002 .pins = gpio2b_3512_pins, 1003 .num_pins = ARRAY_SIZE(gpio2b_3512_pins), 1004 /* Conflict with GMII GMAC1, extended parallel flash and LCD */ 1005 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1006 }, 1007 { 1008 .name = "gpio2cgrp", 1009 .pins = gpio2c_3512_pins, 1010 .num_pins = ARRAY_SIZE(gpio2c_3512_pins), 1011 /* Conflict with PCI */ 1012 .mask = PCI_PADS_ENABLE, 1013 }, 1014}; 1015 1016/* Pin names for the pinmux subsystem, 3516 variant */ 1017static const struct pinctrl_pin_desc gemini_3516_pins[] = { 1018 /* Row A */ 1019 PINCTRL_PIN(0, "A1 AVCC3IOHA"), 1020 PINCTRL_PIN(1, "A2 DRAM CK N"), 1021 PINCTRL_PIN(2, "A3 DRAM CK"), 1022 PINCTRL_PIN(3, "A4 DRAM DQM1"), 1023 PINCTRL_PIN(4, "A5 DRAM DQ9"), 1024 PINCTRL_PIN(5, "A6 DRAM DQ13"), 1025 PINCTRL_PIN(6, "A7 DRAM DQ1"), 1026 PINCTRL_PIN(7, "A8 DRAM DQ2"), 1027 PINCTRL_PIN(8, "A9 DRAM DQ4"), 1028 PINCTRL_PIN(9, "A10 DRAM VREF"), 1029 PINCTRL_PIN(10, "A11 DRAM DQ24"), 1030 PINCTRL_PIN(11, "A12 DRAM DQ28"), 1031 PINCTRL_PIN(12, "A13 DRAM DQ30"), 1032 PINCTRL_PIN(13, "A14 DRAM DQ18"), 1033 PINCTRL_PIN(14, "A15 DRAM DQ21"), 1034 PINCTRL_PIN(15, "A16 DRAM CAS_N"), 1035 PINCTRL_PIN(16, "A17 DRAM BA1"), 1036 PINCTRL_PIN(17, "A18 PCI INTA N"), 1037 PINCTRL_PIN(18, "A19 PCI INTB N"), 1038 PINCTRL_PIN(19, "A20 PCI INTC N"), 1039 /* Row B */ 1040 PINCTRL_PIN(20, "B1 PWR EN"), 1041 PINCTRL_PIN(21, "B2 GND"), 1042 PINCTRL_PIN(22, "B3 RTC CLKO"), 1043 PINCTRL_PIN(23, "B4 DRAM A5"), 1044 PINCTRL_PIN(24, "B5 DRAM A6"), 1045 PINCTRL_PIN(25, "B6 DRAM DQS1"), 1046 PINCTRL_PIN(26, "B7 DRAM DQ11"), 1047 PINCTRL_PIN(27, "B8 DRAM DQ0"), 1048 PINCTRL_PIN(28, "B9 DRAM DQS0"), 1049 PINCTRL_PIN(29, "B10 DRAM DQ7"), 1050 PINCTRL_PIN(30, "B11 DRAM DQS3"), 1051 PINCTRL_PIN(31, "B12 DRAM DQ27"), 1052 PINCTRL_PIN(32, "B13 DRAM DQ31"), 1053 PINCTRL_PIN(33, "B14 DRAM DQ20"), 1054 PINCTRL_PIN(34, "B15 DRAM DQS2"), 1055 PINCTRL_PIN(35, "B16 DRAM WE N"), 1056 PINCTRL_PIN(36, "B17 DRAM A10"), 1057 PINCTRL_PIN(37, "B18 DRAM A2"), 1058 PINCTRL_PIN(38, "B19 GND"), 1059 PINCTRL_PIN(39, "B20 PCI GNT0 N"), 1060 /* Row C */ 1061 PINCTRL_PIN(40, "C1 AGNDIOHA"), 1062 PINCTRL_PIN(41, "C2 XTALI"), 1063 PINCTRL_PIN(42, "C3 GND"), 1064 PINCTRL_PIN(43, "C4 RTC CLKI"), 1065 PINCTRL_PIN(44, "C5 DRAM A12"), 1066 PINCTRL_PIN(45, "C6 DRAM A11"), 1067 PINCTRL_PIN(46, "C7 DRAM DQ8"), 1068 PINCTRL_PIN(47, "C8 DRAM DQ10"), 1069 PINCTRL_PIN(48, "C9 DRAM DQ3"), 1070 PINCTRL_PIN(49, "C10 DRAM DQ6"), 1071 PINCTRL_PIN(50, "C11 DRAM DQM0"), 1072 PINCTRL_PIN(51, "C12 DRAM DQ26"), 1073 PINCTRL_PIN(52, "C13 DRAM DQ16"), 1074 PINCTRL_PIN(53, "C14 DRAM DQ22"), 1075 PINCTRL_PIN(54, "C15 DRAM DQM2"), 1076 PINCTRL_PIN(55, "C16 DRAM BA0"), 1077 PINCTRL_PIN(56, "C17 DRAM A3"), 1078 PINCTRL_PIN(57, "C18 GND"), 1079 PINCTRL_PIN(58, "C19 PCI GNT1 N"), 1080 PINCTRL_PIN(59, "C20 PCI REQ2 N"), 1081 /* Row D */ 1082 PINCTRL_PIN(60, "D1 AVCC3IOAHA"), 1083 PINCTRL_PIN(61, "D2 AVCCKHA"), 1084 PINCTRL_PIN(62, "D3 XTALO"), 1085 PINCTRL_PIN(63, "D4 GND"), 1086 PINCTRL_PIN(64, "D5 CIR RXD"), 1087 PINCTRL_PIN(65, "D6 DRAM A7"), 1088 PINCTRL_PIN(66, "D7 DRAM A4"), 1089 PINCTRL_PIN(67, "D8 DRAM A8"), 1090 PINCTRL_PIN(68, "D9 DRAM CKE"), 1091 PINCTRL_PIN(69, "D10 DRAM DQ14"), 1092 PINCTRL_PIN(70, "D11 DRAM DQ5"), 1093 PINCTRL_PIN(71, "D12 DRAM DQ25"), 1094 PINCTRL_PIN(72, "D13 DRAM DQ17"), 1095 PINCTRL_PIN(73, "D14 DRAM DQ23"), 1096 PINCTRL_PIN(74, "D15 DRAM RAS N"), 1097 PINCTRL_PIN(75, "D16 DRAM A1"), 1098 PINCTRL_PIN(76, "D17 GND"), 1099 PINCTRL_PIN(77, "D18 EXT RESET N"), 1100 PINCTRL_PIN(78, "D19 PCI REQ1 N"), 1101 PINCTRL_PIN(79, "D20 PCI REQ3 N"), 1102 /* Row E */ 1103 PINCTRL_PIN(80, "E1 VCC2IO CTRL"), 1104 PINCTRL_PIN(81, "E2 VREF CTRL"), 1105 PINCTRL_PIN(82, "E3 CIR RST N"), 1106 PINCTRL_PIN(83, "E4 PWR BTN"), 1107 PINCTRL_PIN(84, "E5 GND"), 1108 PINCTRL_PIN(85, "E6 CIR TXD"), 1109 PINCTRL_PIN(86, "E7 VCCK CTRL"), 1110 PINCTRL_PIN(87, "E8 DRAM A9"), 1111 PINCTRL_PIN(88, "E9 DRAM DQ12"), 1112 PINCTRL_PIN(89, "E10 DRAM DQ15"), 1113 PINCTRL_PIN(90, "E11 DRAM DQM3"), 1114 PINCTRL_PIN(91, "E12 DRAM DQ29"), 1115 PINCTRL_PIN(92, "E13 DRAM DQ19"), 1116 PINCTRL_PIN(93, "E14 DRAM A13"), 1117 PINCTRL_PIN(94, "E15 DRAM A0"), 1118 PINCTRL_PIN(95, "E16 GND"), 1119 PINCTRL_PIN(96, "E17 PCI INTD N"), 1120 PINCTRL_PIN(97, "E18 PCI GNT3 N"), 1121 PINCTRL_PIN(98, "E19 PCI AD29"), 1122 PINCTRL_PIN(99, "E20 PCI AD28"), 1123 /* Row F */ 1124 PINCTRL_PIN(100, "F1 AVCCKHB"), 1125 PINCTRL_PIN(101, "F2 AVCCK P"), 1126 PINCTRL_PIN(102, "F3 EBG"), 1127 PINCTRL_PIN(103, "F4 REXT"), 1128 PINCTRL_PIN(104, "F5 AVCC3IOHB"), 1129 PINCTRL_PIN(105, "F6 GND"), 1130 PINCTRL_PIN(106, "F7 VCC2IOHA 2"), 1131 PINCTRL_PIN(107, "F8 VCC2IOHA 2"), 1132 PINCTRL_PIN(108, "F9 VCC2IOHA 2"), 1133 PINCTRL_PIN(109, "F10 V1"), 1134 PINCTRL_PIN(110, "F11 V1"), 1135 PINCTRL_PIN(111, "F12 VCC2IOHA 2"), 1136 PINCTRL_PIN(112, "F13 VCC2IOHA 2"), 1137 PINCTRL_PIN(113, "F14 VCC2IOHA 2"), 1138 PINCTRL_PIN(114, "F15 GND"), 1139 PINCTRL_PIN(115, "F16 PCI CLK"), 1140 PINCTRL_PIN(116, "F17 PCI GNT2 N"), 1141 PINCTRL_PIN(117, "F18 PCI AD31"), 1142 PINCTRL_PIN(118, "F19 PCI AD26"), 1143 PINCTRL_PIN(119, "F20 PCI CBE3 N"), 1144 /* Row G */ 1145 PINCTRL_PIN(120, "G1 SATA0 RXDP"), 1146 PINCTRL_PIN(121, "G2 SATA0 RXDN"), 1147 PINCTRL_PIN(122, "G3 AGNDK 0"), 1148 PINCTRL_PIN(123, "G4 AVCCK S"), 1149 PINCTRL_PIN(124, "G5 AVCC3 S"), 1150 PINCTRL_PIN(125, "G6 VCC2IOHA 2"), 1151 PINCTRL_PIN(126, "G7 GND"), 1152 PINCTRL_PIN(127, "G8 VCC2IOHA 2"), 1153 PINCTRL_PIN(128, "G9 V1"), 1154 PINCTRL_PIN(129, "G10 V1"), 1155 PINCTRL_PIN(130, "G11 V1"), 1156 PINCTRL_PIN(131, "G12 V1"), 1157 PINCTRL_PIN(132, "G13 VCC2IOHA 2"), 1158 PINCTRL_PIN(133, "G14 GND"), 1159 PINCTRL_PIN(134, "G15 VCC3IOHA"), 1160 PINCTRL_PIN(135, "G16 PCI REQ0 N"), 1161 PINCTRL_PIN(136, "G17 PCI AD30"), 1162 PINCTRL_PIN(137, "G18 PCI AD24"), 1163 PINCTRL_PIN(138, "G19 PCI AD23"), 1164 PINCTRL_PIN(139, "G20 PCI AD21"), 1165 /* Row H */ 1166 PINCTRL_PIN(140, "H1 SATA0 TXDP"), 1167 PINCTRL_PIN(141, "H2 SATA0 TXDN"), 1168 PINCTRL_PIN(142, "H3 AGNDK 1"), 1169 PINCTRL_PIN(143, "H4 AVCCK 0"), 1170 PINCTRL_PIN(144, "H5 TEST CLKOUT"), 1171 PINCTRL_PIN(145, "H6 AGND"), 1172 PINCTRL_PIN(146, "H7 VCC2IOHA 2"), 1173 PINCTRL_PIN(147, "H8 GND"), 1174 PINCTRL_PIN(148, "H9 GND"), 1175 PINCTRL_PIN(149, "H10 GDN"), 1176 PINCTRL_PIN(150, "H11 GND"), 1177 PINCTRL_PIN(151, "H12 GND"), 1178 PINCTRL_PIN(152, "H13 GND"), 1179 PINCTRL_PIN(153, "H14 VCC3IOHA"), 1180 PINCTRL_PIN(154, "H15 VCC3IOHA"), 1181 PINCTRL_PIN(155, "H16 PCI AD27"), 1182 PINCTRL_PIN(156, "H17 PCI AD25"), 1183 PINCTRL_PIN(157, "H18 PCI AD22"), 1184 PINCTRL_PIN(158, "H19 PCI AD18"), 1185 PINCTRL_PIN(159, "H20 PCI AD17"), 1186 /* Row J (for some reason I is skipped) */ 1187 PINCTRL_PIN(160, "J1 SATA1 TXDP"), 1188 PINCTRL_PIN(161, "J2 SATA1 TXDN"), 1189 PINCTRL_PIN(162, "J3 AGNDK 2"), 1190 PINCTRL_PIN(163, "J4 AVCCK 1"), 1191 PINCTRL_PIN(164, "J5 AGND"), 1192 PINCTRL_PIN(165, "J6 AGND"), 1193 PINCTRL_PIN(166, "J7 V1"), 1194 PINCTRL_PIN(167, "J8 GND"), 1195 PINCTRL_PIN(168, "J9 GND"), 1196 PINCTRL_PIN(169, "J10 GND"), 1197 PINCTRL_PIN(170, "J11 GND"), 1198 PINCTRL_PIN(171, "J12 GND"), 1199 PINCTRL_PIN(172, "J13 GND"), 1200 PINCTRL_PIN(173, "J14 V1"), 1201 PINCTRL_PIN(174, "J15 VCC3IOHA"), 1202 PINCTRL_PIN(175, "J16 PCI AD19"), 1203 PINCTRL_PIN(176, "J17 PCI AD20"), 1204 PINCTRL_PIN(177, "J18 PCI AD16"), 1205 PINCTRL_PIN(178, "J19 PCI CBE2 N"), 1206 PINCTRL_PIN(179, "J20 PCI FRAME N"), 1207 /* Row K */ 1208 PINCTRL_PIN(180, "K1 SATA1 RXDP"), 1209 PINCTRL_PIN(181, "K2 SATA1 RXDN"), 1210 PINCTRL_PIN(182, "K3 AGNDK 3"), 1211 PINCTRL_PIN(183, "K4 AVCCK 2"), 1212 PINCTRL_PIN(184, "K5 AGND"), 1213 PINCTRL_PIN(185, "K6 V1"), 1214 PINCTRL_PIN(186, "K7 V1"), 1215 PINCTRL_PIN(187, "K8 GND"), 1216 PINCTRL_PIN(188, "K9 GND"), 1217 PINCTRL_PIN(189, "K10 GND"), 1218 PINCTRL_PIN(190, "K11 GND"), 1219 PINCTRL_PIN(191, "K12 GND"), 1220 PINCTRL_PIN(192, "K13 GND"), 1221 PINCTRL_PIN(193, "K14 V1"), 1222 PINCTRL_PIN(194, "K15 V1"), 1223 PINCTRL_PIN(195, "K16 PCI TRDY N"), 1224 PINCTRL_PIN(196, "K17 PCI IRDY N"), 1225 PINCTRL_PIN(197, "K18 PCI DEVSEL N"), 1226 PINCTRL_PIN(198, "K19 PCI STOP N"), 1227 PINCTRL_PIN(199, "K20 PCI PAR"), 1228 /* Row L */ 1229 PINCTRL_PIN(200, "L1 IDE CS0 N"), 1230 PINCTRL_PIN(201, "L2 IDE DA0"), 1231 PINCTRL_PIN(202, "L3 AVCCK 3"), 1232 PINCTRL_PIN(203, "L4 AGND"), 1233 PINCTRL_PIN(204, "L5 IDE DIOR N"), 1234 PINCTRL_PIN(205, "L6 V1"), 1235 PINCTRL_PIN(206, "L7 V1"), 1236 PINCTRL_PIN(207, "L8 GND"), 1237 PINCTRL_PIN(208, "L9 GND"), 1238 PINCTRL_PIN(209, "L10 GND"), 1239 PINCTRL_PIN(210, "L11 GND"), 1240 PINCTRL_PIN(211, "L12 GND"), 1241 PINCTRL_PIN(212, "L13 GND"), 1242 PINCTRL_PIN(213, "L14 V1"), 1243 PINCTRL_PIN(214, "L15 V1"), 1244 PINCTRL_PIN(215, "L16 PCI AD12"), 1245 PINCTRL_PIN(216, "L17 PCI AD13"), 1246 PINCTRL_PIN(217, "L18 PCI AD14"), 1247 PINCTRL_PIN(218, "L19 PCI AD15"), 1248 PINCTRL_PIN(219, "L20 PCI CBE1 N"), 1249 /* Row M */ 1250 PINCTRL_PIN(220, "M1 IDE DA1"), 1251 PINCTRL_PIN(221, "M2 IDE CS1 N"), 1252 PINCTRL_PIN(222, "M3 IDE DA2"), 1253 PINCTRL_PIN(223, "M4 IDE DMACK N"), 1254 PINCTRL_PIN(224, "M5 IDE DD1"), 1255 PINCTRL_PIN(225, "M6 VCC3IOHA"), 1256 PINCTRL_PIN(226, "M7 V1"), 1257 PINCTRL_PIN(227, "M8 GND"), 1258 PINCTRL_PIN(228, "M9 GND"), 1259 PINCTRL_PIN(229, "M10 GND"), 1260 PINCTRL_PIN(230, "M11 GND"), 1261 PINCTRL_PIN(231, "M12 GND"), 1262 PINCTRL_PIN(232, "M13 GND"), 1263 PINCTRL_PIN(233, "M14 V1"), 1264 PINCTRL_PIN(234, "M15 VCC3IOHA"), 1265 PINCTRL_PIN(235, "M16 PCI AD7"), 1266 PINCTRL_PIN(236, "M17 PCI AD6"), 1267 PINCTRL_PIN(237, "M18 PCI AD9"), 1268 PINCTRL_PIN(238, "M19 PCI AD10"), 1269 PINCTRL_PIN(239, "M20 PCI AD11"), 1270 /* Row N */ 1271 PINCTRL_PIN(240, "N1 IDE IORDY"), 1272 PINCTRL_PIN(241, "N2 IDE INTRQ"), 1273 PINCTRL_PIN(242, "N3 IDE DIOW N"), 1274 PINCTRL_PIN(243, "N4 IDE DD15"), 1275 PINCTRL_PIN(244, "N5 IDE DMARQ"), 1276 PINCTRL_PIN(245, "N6 VCC3IOHA"), 1277 PINCTRL_PIN(246, "N7 VCC3IOHA"), 1278 PINCTRL_PIN(247, "N8 GND"), 1279 PINCTRL_PIN(248, "N9 GND"), 1280 PINCTRL_PIN(249, "N10 GND"), 1281 PINCTRL_PIN(250, "N11 GND"), 1282 PINCTRL_PIN(251, "N12 GND"), 1283 PINCTRL_PIN(252, "N13 GND"), 1284 PINCTRL_PIN(253, "N14 VCC3IOHA"), 1285 PINCTRL_PIN(254, "N15 VCC3IOHA"), 1286 PINCTRL_PIN(255, "N16 PCI CLKRUN N"), 1287 PINCTRL_PIN(256, "N17 PCI AD0"), 1288 PINCTRL_PIN(257, "N18 PCI AD4"), 1289 PINCTRL_PIN(258, "N19 PCI CBE0 N"), 1290 PINCTRL_PIN(259, "N20 PCI AD8"), 1291 /* Row P (for some reason O is skipped) */ 1292 PINCTRL_PIN(260, "P1 IDE DD0"), 1293 PINCTRL_PIN(261, "P2 IDE DD14"), 1294 PINCTRL_PIN(262, "P3 IDE DD2"), 1295 PINCTRL_PIN(263, "P4 IDE DD4"), 1296 PINCTRL_PIN(264, "P5 IDE DD3"), 1297 PINCTRL_PIN(265, "P6 VCC3IOHA"), 1298 PINCTRL_PIN(266, "P7 GND"), 1299 PINCTRL_PIN(267, "P8 VCC2IOHA 1"), 1300 PINCTRL_PIN(268, "P9 V1"), 1301 PINCTRL_PIN(269, "P10 V1"), 1302 PINCTRL_PIN(270, "P11 V1"), 1303 PINCTRL_PIN(271, "P12 V1"), 1304 PINCTRL_PIN(272, "P13 VCC3IOHA"), 1305 PINCTRL_PIN(273, "P14 GND"), 1306 PINCTRL_PIN(274, "P15 VCC3IOHA"), 1307 PINCTRL_PIN(275, "P16 GPIO0 30"), 1308 PINCTRL_PIN(276, "P17 GPIO0 28"), 1309 PINCTRL_PIN(277, "P18 PCI AD1"), 1310 PINCTRL_PIN(278, "P19 PCI AD3"), 1311 PINCTRL_PIN(279, "P20 PCI AD5"), 1312 /* Row R (for some reason Q is skipped) */ 1313 PINCTRL_PIN(280, "R1 IDE DD13"), 1314 PINCTRL_PIN(281, "R2 IDE DD12"), 1315 PINCTRL_PIN(282, "R3 IDE DD10"), 1316 PINCTRL_PIN(283, "R4 IDE DD6"), 1317 PINCTRL_PIN(284, "R5 ICE0 IDI"), 1318 PINCTRL_PIN(285, "R6 GND"), 1319 PINCTRL_PIN(286, "R7 VCC2IOHA 1"), 1320 PINCTRL_PIN(287, "R8 VCC2IOHA 1"), 1321 PINCTRL_PIN(288, "R9 VCC2IOHA 1"), 1322 PINCTRL_PIN(289, "R10 V1"), 1323 PINCTRL_PIN(290, "R11 V1"), 1324 PINCTRL_PIN(291, "R12 VCC3IOHA"), 1325 PINCTRL_PIN(292, "R13 VCC3IOHA"), 1326 PINCTRL_PIN(293, "R14 VCC3IOHA"), 1327 PINCTRL_PIN(294, "R15 GND"), 1328 PINCTRL_PIN(295, "R16 GPIO0 23"), 1329 PINCTRL_PIN(296, "R17 GPIO0 21"), 1330 PINCTRL_PIN(297, "R18 GPIO0 26"), 1331 PINCTRL_PIN(298, "R19 GPIO0 31"), 1332 PINCTRL_PIN(299, "R20 PCI AD2"), 1333 /* Row T (for some reason S is skipped) */ 1334 PINCTRL_PIN(300, "T1 IDE DD11"), 1335 PINCTRL_PIN(301, "T2 IDE DD5"), 1336 PINCTRL_PIN(302, "T3 IDE DD8"), 1337 PINCTRL_PIN(303, "T4 ICE0 IDO"), 1338 PINCTRL_PIN(304, "T5 GND"), 1339 PINCTRL_PIN(305, "T6 USB GNDA U20"), 1340 PINCTRL_PIN(306, "T7 GMAC0 TXD0"), 1341 PINCTRL_PIN(307, "T8 GMAC0 TXEN"), 1342 PINCTRL_PIN(308, "T9 GMAC1 TXD3"), 1343 PINCTRL_PIN(309, "T10 GMAC1 RXDV"), 1344 PINCTRL_PIN(310, "T11 GMAC1 RXD2"), 1345 PINCTRL_PIN(311, "T12 GPIO1 29"), 1346 PINCTRL_PIN(312, "T13 GPIO0 3"), 1347 PINCTRL_PIN(313, "T14 GPIO0 9"), 1348 PINCTRL_PIN(314, "T15 GPIO0 16"), 1349 PINCTRL_PIN(315, "T16 GND"), 1350 PINCTRL_PIN(316, "T17 GPIO0 14"), 1351 PINCTRL_PIN(317, "T18 GPIO0 19"), 1352 PINCTRL_PIN(318, "T19 GPIO0 27"), 1353 PINCTRL_PIN(319, "T20 GPIO0 29"), 1354 /* Row U */ 1355 PINCTRL_PIN(320, "U1 IDE DD9"), 1356 PINCTRL_PIN(321, "U2 IDE DD7"), 1357 PINCTRL_PIN(322, "U3 ICE0 ICK"), 1358 PINCTRL_PIN(323, "U4 GND"), 1359 PINCTRL_PIN(324, "U5 USB XSCO"), 1360 PINCTRL_PIN(325, "U6 GMAC0 TXD1"), 1361 PINCTRL_PIN(326, "U7 GMAC0 TXD3"), 1362 PINCTRL_PIN(327, "U8 GMAC0 TXC"), 1363 PINCTRL_PIN(328, "U9 GMAC0 RXD3"), 1364 PINCTRL_PIN(329, "U10 GMAC1 TXD0"), 1365 PINCTRL_PIN(330, "U11 GMAC1 CRS"), 1366 PINCTRL_PIN(331, "U12 EXT CLK"), 1367 PINCTRL_PIN(332, "U13 DEV DEF"), 1368 PINCTRL_PIN(333, "U14 GPIO0 0"), 1369 PINCTRL_PIN(334, "U15 GPIO0 4"), 1370 PINCTRL_PIN(335, "U16 GPIO0 10"), 1371 PINCTRL_PIN(336, "U17 GND"), 1372 PINCTRL_PIN(337, "U18 GPIO0 17"), 1373 PINCTRL_PIN(338, "U19 GPIO0 22"), 1374 PINCTRL_PIN(339, "U20 GPIO0 25"), 1375 /* Row V */ 1376 PINCTRL_PIN(340, "V1 ICE0 DBGACK"), 1377 PINCTRL_PIN(341, "V2 ICE0 DBGRQ"), 1378 PINCTRL_PIN(342, "V3 GND"), 1379 PINCTRL_PIN(343, "V4 ICE0 IRST N"), 1380 PINCTRL_PIN(344, "V5 USB XSCI"), 1381 PINCTRL_PIN(345, "V6 GMAC0 COL"), 1382 PINCTRL_PIN(346, "V7 GMAC0 TXD2"), 1383 PINCTRL_PIN(347, "V8 GMAC0 RXDV"), 1384 PINCTRL_PIN(348, "V9 GMAC0 RXD1"), 1385 PINCTRL_PIN(349, "V10 GMAC1 COL"), 1386 PINCTRL_PIN(350, "V11 GMAC1 TXC"), 1387 PINCTRL_PIN(351, "V12 GMAC1 RXD1"), 1388 PINCTRL_PIN(352, "V13 MODE SEL1"), 1389 PINCTRL_PIN(353, "V14 GPIO1 28"), 1390 PINCTRL_PIN(354, "V15 GPIO0 1"), 1391 PINCTRL_PIN(355, "V16 GPIO0 8"), 1392 PINCTRL_PIN(356, "V17 GPIO0 11"), 1393 PINCTRL_PIN(357, "V18 GND"), 1394 PINCTRL_PIN(358, "V19 GPIO0 18"), 1395 PINCTRL_PIN(359, "V20 GPIO0 24"), 1396 /* Row W */ 1397 PINCTRL_PIN(360, "W1 IDE RESET N"), 1398 PINCTRL_PIN(361, "W2 GND"), 1399 PINCTRL_PIN(362, "W3 USB0 VCCHSRT"), 1400 PINCTRL_PIN(363, "W4 USB0 DP"), 1401 PINCTRL_PIN(364, "W5 USB VCCA U20"), 1402 PINCTRL_PIN(365, "W6 USB1 DP"), 1403 PINCTRL_PIN(366, "W7 USB1 GNDHSRT"), 1404 PINCTRL_PIN(367, "W8 GMAC0 RXD0"), 1405 PINCTRL_PIN(368, "W9 GMAC0 CRS"), 1406 PINCTRL_PIN(369, "W10 GMAC1 TXD2"), 1407 PINCTRL_PIN(370, "W11 GMAC1 TXEN"), 1408 PINCTRL_PIN(371, "W12 GMAC1 RXD3"), 1409 PINCTRL_PIN(372, "W13 MODE SEL0"), 1410 PINCTRL_PIN(373, "W14 MODE SEL3"), 1411 PINCTRL_PIN(374, "W15 GPIO1 31"), 1412 PINCTRL_PIN(375, "W16 GPIO0 5"), 1413 PINCTRL_PIN(376, "W17 GPIO0 7"), 1414 PINCTRL_PIN(377, "W18 GPIO0 12"), 1415 PINCTRL_PIN(378, "W19 GND"), 1416 PINCTRL_PIN(379, "W20 GPIO0 20"), 1417 /* Row Y */ 1418 PINCTRL_PIN(380, "Y1 ICE0 IMS"), 1419 PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"), 1420 PINCTRL_PIN(382, "Y3 USB0 DM"), 1421 PINCTRL_PIN(383, "Y4 USB RREF"), 1422 PINCTRL_PIN(384, "Y5 USB1 DM"), 1423 PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"), 1424 PINCTRL_PIN(386, "Y7 GMAC0 RXC"), 1425 PINCTRL_PIN(387, "Y8 GMAC0 RXD2"), 1426 PINCTRL_PIN(388, "Y9 REF CLK"), 1427 PINCTRL_PIN(389, "Y10 GMAC1 TXD1"), 1428 PINCTRL_PIN(390, "Y11 GMAC1 RXC"), 1429 PINCTRL_PIN(391, "Y12 GMAC1 RXD0"), 1430 PINCTRL_PIN(392, "Y13 M30 CLK"), 1431 PINCTRL_PIN(393, "Y14 MODE SEL2"), 1432 PINCTRL_PIN(394, "Y15 GPIO1 30"), 1433 PINCTRL_PIN(395, "Y16 GPIO0 2"), 1434 PINCTRL_PIN(396, "Y17 GPIO0 6"), 1435 PINCTRL_PIN(397, "Y18 SYS RESET N"), 1436 PINCTRL_PIN(398, "Y19 GPIO0 13"), 1437 PINCTRL_PIN(399, "Y20 GPIO0 15"), 1438}; 1439 1440/* Digital ground */ 1441static const unsigned int gnd_3516_pins[] = { 1442 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150, 1443 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192, 1444 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248, 1445 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357, 1446 361, 378 1447}; 1448 1449static const unsigned int dram_3516_pins[] = { 1450 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26, 1451 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50, 1452 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 1453 87, 88, 89, 90, 91, 92, 93, 94 1454}; 1455 1456static const unsigned int rtc_3516_pins[] = { 0, 43, 22 }; 1457 1458static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 }; 1459 1460static const unsigned int cir_3516_pins[] = { 85, 64, 82 }; 1461 1462static const unsigned int system_3516_pins[] = { 1463 332, 392, 372, 373, 393, 352, 331, 388, 397, 77 1464}; 1465 1466static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 }; 1467 1468static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 }; 1469 1470static const unsigned int ide_3516_pins[] = { 1471 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260, 1472 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360 1473}; 1474 1475static const unsigned int sata_3516_pins[] = { 1476 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143, 1477 144, 160, 161, 162, 163, 180, 181, 182, 183, 202 1478}; 1479 1480static const unsigned int usb_3516_pins[] = { 1481 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385 1482}; 1483 1484/* GMII, ethernet pins */ 1485static const unsigned int gmii_gmac0_3516_pins[] = { 1486 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 1487}; 1488 1489static const unsigned int gmii_gmac1_3516_pins[] = { 1490 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 1491}; 1492 1493static const unsigned int pci_3516_pins[] = { 1494 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118, 1495 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177, 1496 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236, 1497 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299 1498}; 1499 1500/* 1501 * Apparently the LPC interface is using the PCICLK for the clocking so 1502 * PCI needs to be active at the same time. 1503 */ 1504static const unsigned int lpc_3516_pins[] = { 1505 355, /* LPC_LAD[0] */ 1506 356, /* LPC_SERIRQ */ 1507 377, /* LPC_LAD[2] */ 1508 398, /* LPC_LFRAME# */ 1509 316, /* LPC_LAD[3] */ 1510 399, /* LPC_LAD[1] */ 1511}; 1512 1513/* Character LCD */ 1514static const unsigned int lcd_3516_pins[] = { 1515 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339 1516}; 1517 1518static const unsigned int ssp_3516_pins[] = { 1519 355, /* SSP_97RST# SSP AC97 Reset, active low */ 1520 356, /* SSP_FSC */ 1521 377, /* SSP_ECLK */ 1522 398, /* SSP_TXD */ 1523 316, /* SSP_RXD */ 1524 399, /* SSP_SCLK */ 1525}; 1526 1527static const unsigned int uart_rxtx_3516_pins[] = { 1528 313, /* UART_SIN serial input, RX */ 1529 335, /* UART_SOUT serial output, TX */ 1530}; 1531 1532static const unsigned int uart_modem_3516_pins[] = { 1533 355, /* UART_NDCD DCD carrier detect */ 1534 356, /* UART_NDTR DTR data terminal ready */ 1535 377, /* UART_NDSR DSR data set ready */ 1536 398, /* UART_NRTS RTS request to send */ 1537 316, /* UART_NCTS CTS clear to send */ 1538 399, /* UART_NRI RI ring indicator */ 1539}; 1540 1541static const unsigned int tvc_3516_pins[] = { 1542 353, /* TVC_DATA[0] */ 1543 311, /* TVC_DATA[1] */ 1544 394, /* TVC_DATA[2] */ 1545 374, /* TVC_DATA[3] */ 1546 354, /* TVC_DATA[4] */ 1547 395, /* TVC_DATA[5] */ 1548 312, /* TVC_DATA[6] */ 1549 334, /* TVC_DATA[7] */ 1550}; 1551 1552static const unsigned int tvc_clk_3516_pins[] = { 1553 333, /* TVC_CLK */ 1554}; 1555 1556/* NAND flash pins */ 1557static const unsigned int nflash_3516_pins[] = { 1558 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1559 302, 321, 337, 358, 295, 359, 339, 275, 298 1560}; 1561 1562/* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 1563static const unsigned int pflash_3516_pins[] = { 1564 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1565 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1566 276, 319, 275, 298 1567}; 1568 1569/* 1570 * The parallel flash can be set up in a 26-bit address bus mode exposing 1571 * A[0-15] (A[15] takes the place of ALE), but it has the 1572 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 1573 * used at the same time. 1574 */ 1575static const unsigned int pflash_3516_pins_extended[] = { 1576 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1577 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1578 276, 319, 275, 298, 1579 /* The extra pins */ 1580 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330, 1581 333 1582}; 1583 1584/* Serial flash pins CE0, CE1, DI, DO, CK */ 1585static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; 1586 1587/* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ 1588static const unsigned int gpio0a_3516_pins[] = { 354, 395, 312, 334 }; 1589 1590/* The GPIO0B (5-7) pins overlap with ICE */ 1591static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; 1592 1593/* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ 1594static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 }; 1595 1596/* The GPIO0D (9,10) pins overlap with UART RX/TX */ 1597static const unsigned int gpio0d_3516_pins[] = { 313, 335 }; 1598 1599/* The GPIO0E (16) pins overlap with LCD */ 1600static const unsigned int gpio0e_3516_pins[] = { 314 }; 1601 1602/* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ 1603static const unsigned int gpio0f_3516_pins[] = { 337, 358 }; 1604 1605/* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ 1606static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 }; 1607 1608/* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ 1609static const unsigned int gpio0h_3516_pins[] = { 296, 338 }; 1610 1611/* The GPIO0I (23) pins overlap with all flash */ 1612static const unsigned int gpio0i_3516_pins[] = { 295 }; 1613 1614/* The GPIO0J (24,25) pins overlap with all flash and LCD */ 1615static const unsigned int gpio0j_3516_pins[] = { 359, 339 }; 1616 1617/* The GPIO0K (30,31) pins overlap with NAND flash */ 1618static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; 1619 1620/* The GPIO0L (0) pins overlap with TVC_CLK */ 1621static const unsigned int gpio0l_3516_pins[] = { 333 }; 1622 1623/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 1624static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; 1625 1626/* The GPIO1B (5-10,27) pins overlap with just IDE */ 1627static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 }; 1628 1629/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 1630static const unsigned int gpio1c_3516_pins[] = { 1631 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1632 302, 321 1633}; 1634 1635/* The GPIO1D (28-31) pins overlap with TVC */ 1636static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; 1637 1638/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ 1639static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; 1640 1641/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ 1642static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; 1643 1644/* The GPIO2C (8-31) pins overlap with PCI */ 1645static const unsigned int gpio2c_3516_pins[] = { 1646 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139, 1647 157, 138, 137, 156, 118, 155, 99, 98, 136, 117 1648}; 1649 1650/* Groups for the 3516 SoC/package */ 1651static const struct gemini_pin_group gemini_3516_pin_groups[] = { 1652 { 1653 .name = "gndgrp", 1654 .pins = gnd_3516_pins, 1655 .num_pins = ARRAY_SIZE(gnd_3516_pins), 1656 }, 1657 { 1658 .name = "dramgrp", 1659 .pins = dram_3516_pins, 1660 .num_pins = ARRAY_SIZE(dram_3516_pins), 1661 .mask = DRAM_PADS_POWERDOWN, 1662 }, 1663 { 1664 .name = "rtcgrp", 1665 .pins = rtc_3516_pins, 1666 .num_pins = ARRAY_SIZE(rtc_3516_pins), 1667 }, 1668 { 1669 .name = "powergrp", 1670 .pins = power_3516_pins, 1671 .num_pins = ARRAY_SIZE(power_3516_pins), 1672 }, 1673 { 1674 .name = "cirgrp", 1675 .pins = cir_3516_pins, 1676 .num_pins = ARRAY_SIZE(cir_3516_pins), 1677 }, 1678 { 1679 .name = "systemgrp", 1680 .pins = system_3516_pins, 1681 .num_pins = ARRAY_SIZE(system_3516_pins), 1682 }, 1683 { 1684 .name = "vcontrolgrp", 1685 .pins = vcontrol_3516_pins, 1686 .num_pins = ARRAY_SIZE(vcontrol_3516_pins), 1687 }, 1688 { 1689 .name = "icegrp", 1690 .pins = ice_3516_pins, 1691 .num_pins = ARRAY_SIZE(ice_3516_pins), 1692 /* Conflict with some GPIO groups */ 1693 }, 1694 { 1695 .name = "idegrp", 1696 .pins = ide_3516_pins, 1697 .num_pins = ARRAY_SIZE(ide_3516_pins), 1698 /* Conflict with all flash usage */ 1699 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 1700 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1701 .driving_mask = GENMASK(21, 20), 1702 }, 1703 { 1704 .name = "satagrp", 1705 .pins = sata_3516_pins, 1706 .num_pins = ARRAY_SIZE(sata_3516_pins), 1707 }, 1708 { 1709 .name = "usbgrp", 1710 .pins = usb_3516_pins, 1711 .num_pins = ARRAY_SIZE(usb_3516_pins), 1712 }, 1713 { 1714 .name = "gmii_gmac0_grp", 1715 .pins = gmii_gmac0_3516_pins, 1716 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), 1717 .mask = GEMINI_GMAC_IOSEL_MASK, 1718 .driving_mask = GENMASK(17, 16), 1719 }, 1720 { 1721 .name = "gmii_gmac1_grp", 1722 .pins = gmii_gmac1_3516_pins, 1723 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), 1724 /* Bring out RGMII on the GMAC1 pins */ 1725 .mask = GEMINI_GMAC_IOSEL_MASK, 1726 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1727 .driving_mask = GENMASK(19, 18), 1728 }, 1729 { 1730 .name = "pcigrp", 1731 .pins = pci_3516_pins, 1732 .num_pins = ARRAY_SIZE(pci_3516_pins), 1733 /* Conflict only with GPIO2 */ 1734 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 1735 .driving_mask = GENMASK(23, 22), 1736 }, 1737 { 1738 .name = "lpcgrp", 1739 .pins = lpc_3516_pins, 1740 .num_pins = ARRAY_SIZE(lpc_3516_pins), 1741 /* Conflict with SSP */ 1742 .mask = SSP_PADS_ENABLE, 1743 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 1744 }, 1745 { 1746 .name = "lcdgrp", 1747 .pins = lcd_3516_pins, 1748 .num_pins = ARRAY_SIZE(lcd_3516_pins), 1749 .mask = TVC_PADS_ENABLE, 1750 .value = LCD_PADS_ENABLE, 1751 }, 1752 { 1753 .name = "sspgrp", 1754 .pins = ssp_3516_pins, 1755 .num_pins = ARRAY_SIZE(ssp_3516_pins), 1756 /* Conflict with LPC */ 1757 .mask = LPC_PADS_ENABLE, 1758 .value = SSP_PADS_ENABLE, 1759 }, 1760 { 1761 .name = "uartrxtxgrp", 1762 .pins = uart_rxtx_3516_pins, 1763 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins), 1764 /* No conflicts except GPIO */ 1765 }, 1766 { 1767 .name = "uartmodemgrp", 1768 .pins = uart_modem_3516_pins, 1769 .num_pins = ARRAY_SIZE(uart_modem_3516_pins), 1770 /* 1771 * Conflict with LPC and SSP, 1772 * so when those are both disabled, modem UART can thrive. 1773 */ 1774 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1775 }, 1776 { 1777 .name = "tvcgrp", 1778 .pins = tvc_3516_pins, 1779 .num_pins = ARRAY_SIZE(tvc_3516_pins), 1780 /* Conflict with character LCD */ 1781 .mask = LCD_PADS_ENABLE, 1782 .value = TVC_PADS_ENABLE, 1783 }, 1784 { 1785 .name = "tvcclkgrp", 1786 .pins = tvc_clk_3516_pins, 1787 .num_pins = ARRAY_SIZE(tvc_clk_3516_pins), 1788 .value = TVC_CLK_PAD_ENABLE, 1789 }, 1790 /* 1791 * The construction is done such that it is possible to use a serial 1792 * flash together with a NAND or parallel (NOR) flash, but it is not 1793 * possible to use NAND and parallel flash together. To use serial 1794 * flash with one of the two others, the muxbits need to be flipped 1795 * around before any access. 1796 */ 1797 { 1798 .name = "nflashgrp", 1799 .pins = nflash_3516_pins, 1800 .num_pins = ARRAY_SIZE(nflash_3516_pins), 1801 /* Conflict with IDE, parallel and serial flash */ 1802 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 1803 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1804 }, 1805 { 1806 .name = "pflashgrp", 1807 .pins = pflash_3516_pins, 1808 .num_pins = ARRAY_SIZE(pflash_3516_pins), 1809 /* Conflict with IDE, NAND and serial flash */ 1810 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1811 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 1812 }, 1813 { 1814 .name = "sflashgrp", 1815 .pins = sflash_3516_pins, 1816 .num_pins = ARRAY_SIZE(sflash_3516_pins), 1817 /* Conflict with IDE, NAND and parallel flash */ 1818 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1819 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1820 }, 1821 { 1822 .name = "gpio0agrp", 1823 .pins = gpio0a_3516_pins, 1824 .num_pins = ARRAY_SIZE(gpio0a_3516_pins), 1825 /* Conflict with TVC and ICE */ 1826 .mask = TVC_PADS_ENABLE, 1827 }, 1828 { 1829 .name = "gpio0bgrp", 1830 .pins = gpio0b_3516_pins, 1831 .num_pins = ARRAY_SIZE(gpio0b_3516_pins), 1832 /* Conflict with ICE */ 1833 }, 1834 { 1835 .name = "gpio0cgrp", 1836 .pins = gpio0c_3516_pins, 1837 .num_pins = ARRAY_SIZE(gpio0c_3516_pins), 1838 /* Conflict with LPC, UART and SSP */ 1839 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1840 }, 1841 { 1842 .name = "gpio0dgrp", 1843 .pins = gpio0d_3516_pins, 1844 .num_pins = ARRAY_SIZE(gpio0d_3516_pins), 1845 /* Conflict with UART */ 1846 }, 1847 { 1848 .name = "gpio0egrp", 1849 .pins = gpio0e_3516_pins, 1850 .num_pins = ARRAY_SIZE(gpio0e_3516_pins), 1851 /* Conflict with LCD */ 1852 .mask = LCD_PADS_ENABLE, 1853 }, 1854 { 1855 .name = "gpio0fgrp", 1856 .pins = gpio0f_3516_pins, 1857 .num_pins = ARRAY_SIZE(gpio0f_3516_pins), 1858 /* Conflict with NAND flash */ 1859 .value = NAND_PADS_DISABLE, 1860 }, 1861 { 1862 .name = "gpio0ggrp", 1863 .pins = gpio0g_3516_pins, 1864 .num_pins = ARRAY_SIZE(gpio0g_3516_pins), 1865 /* Conflict with parallel flash */ 1866 .value = PFLASH_PADS_DISABLE, 1867 }, 1868 { 1869 .name = "gpio0hgrp", 1870 .pins = gpio0h_3516_pins, 1871 .num_pins = ARRAY_SIZE(gpio0h_3516_pins), 1872 /* Conflict with serial flash */ 1873 .value = SFLASH_PADS_DISABLE, 1874 }, 1875 { 1876 .name = "gpio0igrp", 1877 .pins = gpio0i_3516_pins, 1878 .num_pins = ARRAY_SIZE(gpio0i_3516_pins), 1879 /* Conflict with all flash */ 1880 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1881 SFLASH_PADS_DISABLE, 1882 }, 1883 { 1884 .name = "gpio0jgrp", 1885 .pins = gpio0j_3516_pins, 1886 .num_pins = ARRAY_SIZE(gpio0j_3516_pins), 1887 /* Conflict with all flash and LCD */ 1888 .mask = LCD_PADS_ENABLE, 1889 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1890 SFLASH_PADS_DISABLE, 1891 }, 1892 { 1893 .name = "gpio0kgrp", 1894 .pins = gpio0k_3516_pins, 1895 .num_pins = ARRAY_SIZE(gpio0k_3516_pins), 1896 /* Conflict with parallel and NAND flash */ 1897 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 1898 }, 1899 { 1900 .name = "gpio0lgrp", 1901 .pins = gpio0l_3516_pins, 1902 .num_pins = ARRAY_SIZE(gpio0l_3516_pins), 1903 /* Conflict with TVE CLK */ 1904 .mask = TVC_CLK_PAD_ENABLE, 1905 }, 1906 { 1907 .name = "gpio1agrp", 1908 .pins = gpio1a_3516_pins, 1909 .num_pins = ARRAY_SIZE(gpio1a_3516_pins), 1910 /* Conflict with IDE and parallel flash */ 1911 .mask = IDE_PADS_ENABLE, 1912 .value = PFLASH_PADS_DISABLE, 1913 }, 1914 { 1915 .name = "gpio1bgrp", 1916 .pins = gpio1b_3516_pins, 1917 .num_pins = ARRAY_SIZE(gpio1b_3516_pins), 1918 /* Conflict with IDE only */ 1919 .mask = IDE_PADS_ENABLE, 1920 }, 1921 { 1922 .name = "gpio1cgrp", 1923 .pins = gpio1c_3516_pins, 1924 .num_pins = ARRAY_SIZE(gpio1c_3516_pins), 1925 /* Conflict with IDE, parallel and NAND flash */ 1926 .mask = IDE_PADS_ENABLE, 1927 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1928 }, 1929 { 1930 .name = "gpio1dgrp", 1931 .pins = gpio1d_3516_pins, 1932 .num_pins = ARRAY_SIZE(gpio1d_3516_pins), 1933 /* Conflict with TVC */ 1934 .mask = TVC_PADS_ENABLE, 1935 }, 1936 { 1937 .name = "gpio2agrp", 1938 .pins = gpio2a_3516_pins, 1939 .num_pins = ARRAY_SIZE(gpio2a_3516_pins), 1940 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1941 /* Conflict with GMII GMAC1 and extended parallel flash */ 1942 }, 1943 { 1944 .name = "gpio2bgrp", 1945 .pins = gpio2b_3516_pins, 1946 .num_pins = ARRAY_SIZE(gpio2b_3516_pins), 1947 /* Conflict with GMII GMAC1, extended parallel flash and LCD */ 1948 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, 1949 }, 1950 { 1951 .name = "gpio2cgrp", 1952 .pins = gpio2c_3516_pins, 1953 .num_pins = ARRAY_SIZE(gpio2c_3516_pins), 1954 /* Conflict with PCI */ 1955 .mask = PCI_PADS_ENABLE, 1956 }, 1957}; 1958 1959static int gemini_get_groups_count(struct pinctrl_dev *pctldev) 1960{ 1961 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1962 1963 if (pmx->is_3512) 1964 return ARRAY_SIZE(gemini_3512_pin_groups); 1965 if (pmx->is_3516) 1966 return ARRAY_SIZE(gemini_3516_pin_groups); 1967 return 0; 1968} 1969 1970static const char *gemini_get_group_name(struct pinctrl_dev *pctldev, 1971 unsigned int selector) 1972{ 1973 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1974 1975 if (pmx->is_3512) 1976 return gemini_3512_pin_groups[selector].name; 1977 if (pmx->is_3516) 1978 return gemini_3516_pin_groups[selector].name; 1979 return NULL; 1980} 1981 1982static int gemini_get_group_pins(struct pinctrl_dev *pctldev, 1983 unsigned int selector, 1984 const unsigned int **pins, 1985 unsigned int *num_pins) 1986{ 1987 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1988 1989 /* The special case with the 3516 flash pin */ 1990 if (pmx->flash_pin && 1991 pmx->is_3512 && 1992 !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) { 1993 *pins = pflash_3512_pins_extended; 1994 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended); 1995 return 0; 1996 } 1997 if (pmx->flash_pin && 1998 pmx->is_3516 && 1999 !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) { 2000 *pins = pflash_3516_pins_extended; 2001 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended); 2002 return 0; 2003 } 2004 if (pmx->is_3512) { 2005 *pins = gemini_3512_pin_groups[selector].pins; 2006 *num_pins = gemini_3512_pin_groups[selector].num_pins; 2007 } 2008 if (pmx->is_3516) { 2009 *pins = gemini_3516_pin_groups[selector].pins; 2010 *num_pins = gemini_3516_pin_groups[selector].num_pins; 2011 } 2012 return 0; 2013} 2014 2015static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 2016 unsigned int offset) 2017{ 2018 seq_printf(s, " " DRIVER_NAME); 2019} 2020 2021static const struct pinctrl_ops gemini_pctrl_ops = { 2022 .get_groups_count = gemini_get_groups_count, 2023 .get_group_name = gemini_get_group_name, 2024 .get_group_pins = gemini_get_group_pins, 2025 .pin_dbg_show = gemini_pin_dbg_show, 2026 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2027 .dt_free_map = pinconf_generic_dt_free_map, 2028}; 2029 2030/** 2031 * struct gemini_pmx_func - describes Gemini pinmux functions 2032 * @name: the name of this specific function 2033 * @groups: corresponding pin groups 2034 */ 2035struct gemini_pmx_func { 2036 const char *name; 2037 const char * const *groups; 2038 const unsigned int num_groups; 2039}; 2040 2041static const char * const dramgrps[] = { "dramgrp" }; 2042static const char * const rtcgrps[] = { "rtcgrp" }; 2043static const char * const powergrps[] = { "powergrp" }; 2044static const char * const cirgrps[] = { "cirgrp" }; 2045static const char * const systemgrps[] = { "systemgrp" }; 2046static const char * const vcontrolgrps[] = { "vcontrolgrp" }; 2047static const char * const icegrps[] = { "icegrp" }; 2048static const char * const idegrps[] = { "idegrp" }; 2049static const char * const satagrps[] = { "satagrp" }; 2050static const char * const usbgrps[] = { "usbgrp" }; 2051static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; 2052static const char * const pcigrps[] = { "pcigrp" }; 2053static const char * const lpcgrps[] = { "lpcgrp" }; 2054static const char * const lcdgrps[] = { "lcdgrp" }; 2055static const char * const sspgrps[] = { "sspgrp" }; 2056static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" }; 2057static const char * const tvcgrps[] = { "tvcgrp" }; 2058static const char * const nflashgrps[] = { "nflashgrp" }; 2059static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" }; 2060static const char * const sflashgrps[] = { "sflashgrp" }; 2061static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", 2062 "gpio0dgrp", "gpio0egrp", "gpio0fgrp", 2063 "gpio0ggrp", "gpio0hgrp", "gpio0igrp", 2064 "gpio0jgrp", "gpio0kgrp", "gpio0lgrp", 2065 "gpio0mgrp" }; 2066static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", 2067 "gpio1dgrp" }; 2068static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; 2069 2070static const struct gemini_pmx_func gemini_pmx_functions[] = { 2071 { 2072 .name = "dram", 2073 .groups = dramgrps, 2074 .num_groups = ARRAY_SIZE(idegrps), 2075 }, 2076 { 2077 .name = "rtc", 2078 .groups = rtcgrps, 2079 .num_groups = ARRAY_SIZE(rtcgrps), 2080 }, 2081 { 2082 .name = "power", 2083 .groups = powergrps, 2084 .num_groups = ARRAY_SIZE(powergrps), 2085 }, 2086 { 2087 /* This function is strictly unavailable on 3512 */ 2088 .name = "cir", 2089 .groups = cirgrps, 2090 .num_groups = ARRAY_SIZE(cirgrps), 2091 }, 2092 { 2093 .name = "system", 2094 .groups = systemgrps, 2095 .num_groups = ARRAY_SIZE(systemgrps), 2096 }, 2097 { 2098 .name = "vcontrol", 2099 .groups = vcontrolgrps, 2100 .num_groups = ARRAY_SIZE(vcontrolgrps), 2101 }, 2102 { 2103 .name = "ice", 2104 .groups = icegrps, 2105 .num_groups = ARRAY_SIZE(icegrps), 2106 }, 2107 { 2108 .name = "ide", 2109 .groups = idegrps, 2110 .num_groups = ARRAY_SIZE(idegrps), 2111 }, 2112 { 2113 .name = "sata", 2114 .groups = satagrps, 2115 .num_groups = ARRAY_SIZE(satagrps), 2116 }, 2117 { 2118 .name = "usb", 2119 .groups = usbgrps, 2120 .num_groups = ARRAY_SIZE(usbgrps), 2121 }, 2122 { 2123 .name = "gmii", 2124 .groups = gmiigrps, 2125 .num_groups = ARRAY_SIZE(gmiigrps), 2126 }, 2127 { 2128 .name = "pci", 2129 .groups = pcigrps, 2130 .num_groups = ARRAY_SIZE(pcigrps), 2131 }, 2132 { 2133 .name = "lpc", 2134 .groups = lpcgrps, 2135 .num_groups = ARRAY_SIZE(lpcgrps), 2136 }, 2137 { 2138 .name = "lcd", 2139 .groups = lcdgrps, 2140 .num_groups = ARRAY_SIZE(lcdgrps), 2141 }, 2142 { 2143 .name = "ssp", 2144 .groups = sspgrps, 2145 .num_groups = ARRAY_SIZE(sspgrps), 2146 }, 2147 { 2148 .name = "uart", 2149 .groups = uartgrps, 2150 .num_groups = ARRAY_SIZE(uartgrps), 2151 }, 2152 { 2153 .name = "tvc", 2154 .groups = tvcgrps, 2155 .num_groups = ARRAY_SIZE(tvcgrps), 2156 }, 2157 { 2158 .name = "nflash", 2159 .groups = nflashgrps, 2160 .num_groups = ARRAY_SIZE(nflashgrps), 2161 }, 2162 { 2163 .name = "pflash", 2164 .groups = pflashgrps, 2165 .num_groups = ARRAY_SIZE(pflashgrps), 2166 }, 2167 { 2168 .name = "sflash", 2169 .groups = sflashgrps, 2170 .num_groups = ARRAY_SIZE(sflashgrps), 2171 }, 2172 { 2173 .name = "gpio0", 2174 .groups = gpio0grps, 2175 .num_groups = ARRAY_SIZE(gpio0grps), 2176 }, 2177 { 2178 .name = "gpio1", 2179 .groups = gpio1grps, 2180 .num_groups = ARRAY_SIZE(gpio1grps), 2181 }, 2182 { 2183 .name = "gpio2", 2184 .groups = gpio2grps, 2185 .num_groups = ARRAY_SIZE(gpio2grps), 2186 }, 2187}; 2188 2189 2190static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev, 2191 unsigned int selector, 2192 unsigned int group) 2193{ 2194 struct gemini_pmx *pmx; 2195 const struct gemini_pmx_func *func; 2196 const struct gemini_pin_group *grp; 2197 u32 before, after, expected; 2198 unsigned long tmp; 2199 int i; 2200 2201 pmx = pinctrl_dev_get_drvdata(pctldev); 2202 2203 func = &gemini_pmx_functions[selector]; 2204 if (pmx->is_3512) 2205 grp = &gemini_3512_pin_groups[group]; 2206 else if (pmx->is_3516) 2207 grp = &gemini_3516_pin_groups[group]; 2208 else { 2209 dev_err(pmx->dev, "invalid SoC type\n"); 2210 return -ENODEV; 2211 } 2212 2213 dev_dbg(pmx->dev, 2214 "ACTIVATE function \"%s\" with group \"%s\"\n", 2215 func->name, grp->name); 2216 2217 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); 2218 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, 2219 grp->mask | grp->value, 2220 grp->value); 2221 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); 2222 2223 /* Which bits changed */ 2224 before &= PADS_MASK; 2225 after &= PADS_MASK; 2226 expected = before &= ~grp->mask; 2227 expected |= grp->value; 2228 expected &= PADS_MASK; 2229 2230 /* Print changed states */ 2231 tmp = grp->mask; 2232 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2233 bool enabled = !(i > 3); 2234 2235 /* Did not go low though it should */ 2236 if (after & BIT(i)) { 2237 dev_err(pmx->dev, 2238 "pin group %s could not be %s: " 2239 "probably a hardware limitation\n", 2240 gemini_padgroups[i], 2241 str_enabled_disabled(enabled)); 2242 dev_err(pmx->dev, 2243 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2244 before, after, expected); 2245 } else { 2246 dev_dbg(pmx->dev, 2247 "padgroup %s %s\n", 2248 gemini_padgroups[i], 2249 str_enabled_disabled(enabled)); 2250 } 2251 } 2252 2253 tmp = grp->value; 2254 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2255 bool enabled = (i > 3); 2256 2257 /* Did not go high though it should */ 2258 if (!(after & BIT(i))) { 2259 dev_err(pmx->dev, 2260 "pin group %s could not be %s: " 2261 "probably a hardware limitation\n", 2262 gemini_padgroups[i], 2263 str_enabled_disabled(enabled)); 2264 dev_err(pmx->dev, 2265 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2266 before, after, expected); 2267 } else { 2268 dev_dbg(pmx->dev, 2269 "padgroup %s %s\n", 2270 gemini_padgroups[i], 2271 str_enabled_disabled(enabled)); 2272 } 2273 } 2274 2275 return 0; 2276} 2277 2278static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2279{ 2280 return ARRAY_SIZE(gemini_pmx_functions); 2281} 2282 2283static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev, 2284 unsigned int selector) 2285{ 2286 return gemini_pmx_functions[selector].name; 2287} 2288 2289static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev, 2290 unsigned int selector, 2291 const char * const **groups, 2292 unsigned int * const num_groups) 2293{ 2294 *groups = gemini_pmx_functions[selector].groups; 2295 *num_groups = gemini_pmx_functions[selector].num_groups; 2296 return 0; 2297} 2298 2299static const struct pinmux_ops gemini_pmx_ops = { 2300 .get_functions_count = gemini_pmx_get_funcs_count, 2301 .get_function_name = gemini_pmx_get_func_name, 2302 .get_function_groups = gemini_pmx_get_groups, 2303 .set_mux = gemini_pmx_set_mux, 2304}; 2305 2306#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ 2307 .pin = _n, \ 2308 .reg = _r, \ 2309 .mask = GENMASK(_hb, _lb) \ 2310} 2311 2312static const struct gemini_pin_conf gemini_confs_3512[] = { 2313 GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ 2314 GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ 2315 GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ 2316 GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ 2317 GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ 2318 GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ 2319 GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ 2320 GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ 2321 GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ 2322 GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ 2323 GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ 2324 GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ 2325 GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ 2326 GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ 2327 GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ 2328 GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ 2329 GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ 2330 GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ 2331 GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ 2332 GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ 2333 GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ 2334 GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ 2335 GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ 2336 GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ 2337}; 2338 2339static const struct gemini_pin_conf gemini_confs_3516[] = { 2340 GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ 2341 GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ 2342 GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ 2343 GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ 2344 GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ 2345 GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ 2346 GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ 2347 GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ 2348 GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ 2349 GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ 2350 GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ 2351 GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ 2352 GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ 2353 GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ 2354 GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ 2355 GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ 2356 GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ 2357 GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ 2358 GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ 2359 GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ 2360 GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ 2361 GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ 2362 GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ 2363 GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ 2364}; 2365 2366static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, 2367 unsigned int pin) 2368{ 2369 const struct gemini_pin_conf *retconf; 2370 int i; 2371 2372 for (i = 0; i < pmx->nconfs; i++) { 2373 retconf = &pmx->confs[i]; 2374 if (retconf->pin == pin) 2375 return retconf; 2376 } 2377 return NULL; 2378} 2379 2380static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2381 unsigned long *config) 2382{ 2383 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2384 enum pin_config_param param = pinconf_to_config_param(*config); 2385 const struct gemini_pin_conf *conf; 2386 u32 val; 2387 2388 switch (param) { 2389 case PIN_CONFIG_SKEW_DELAY: 2390 conf = gemini_get_pin_conf(pmx, pin); 2391 if (!conf) 2392 return -ENOTSUPP; 2393 regmap_read(pmx->map, conf->reg, &val); 2394 val &= conf->mask; 2395 val >>= (ffs(conf->mask) - 1); 2396 *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); 2397 break; 2398 default: 2399 return -ENOTSUPP; 2400 } 2401 2402 return 0; 2403} 2404 2405static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2406 unsigned long *configs, unsigned int num_configs) 2407{ 2408 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2409 const struct gemini_pin_conf *conf; 2410 enum pin_config_param param; 2411 u32 arg; 2412 int ret = 0; 2413 int i; 2414 2415 for (i = 0; i < num_configs; i++) { 2416 param = pinconf_to_config_param(configs[i]); 2417 arg = pinconf_to_config_argument(configs[i]); 2418 2419 switch (param) { 2420 case PIN_CONFIG_SKEW_DELAY: 2421 if (arg > 0xf) 2422 return -EINVAL; 2423 conf = gemini_get_pin_conf(pmx, pin); 2424 if (!conf) { 2425 dev_err(pmx->dev, 2426 "invalid pin for skew delay %d\n", pin); 2427 return -ENOTSUPP; 2428 } 2429 arg <<= (ffs(conf->mask) - 1); 2430 dev_dbg(pmx->dev, 2431 "set pin %d to skew delay mask %08x, val %08x\n", 2432 pin, conf->mask, arg); 2433 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); 2434 break; 2435 default: 2436 dev_err(pmx->dev, "Invalid config param %04x\n", param); 2437 return -ENOTSUPP; 2438 } 2439 } 2440 2441 return ret; 2442} 2443 2444static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev, 2445 unsigned selector, 2446 unsigned long *configs, 2447 unsigned num_configs) 2448{ 2449 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 2450 const struct gemini_pin_group *grp = NULL; 2451 enum pin_config_param param; 2452 u32 arg; 2453 u32 val; 2454 int i; 2455 2456 if (pmx->is_3512) 2457 grp = &gemini_3512_pin_groups[selector]; 2458 if (pmx->is_3516) 2459 grp = &gemini_3516_pin_groups[selector]; 2460 2461 /* First figure out if this group supports configs */ 2462 if (!grp->driving_mask) { 2463 dev_err(pmx->dev, "pin config group \"%s\" does " 2464 "not support drive strength setting\n", 2465 grp->name); 2466 return -EINVAL; 2467 } 2468 2469 for (i = 0; i < num_configs; i++) { 2470 param = pinconf_to_config_param(configs[i]); 2471 arg = pinconf_to_config_argument(configs[i]); 2472 2473 switch (param) { 2474 case PIN_CONFIG_DRIVE_STRENGTH: 2475 switch (arg) { 2476 case 4: 2477 val = 0; 2478 break; 2479 case 8: 2480 val = 1; 2481 break; 2482 case 12: 2483 val = 2; 2484 break; 2485 case 16: 2486 val = 3; 2487 break; 2488 default: 2489 dev_err(pmx->dev, 2490 "invalid drive strength %d mA\n", 2491 arg); 2492 return -ENOTSUPP; 2493 } 2494 val <<= (ffs(grp->driving_mask) - 1); 2495 regmap_update_bits(pmx->map, GLOBAL_IODRIVE, 2496 grp->driving_mask, 2497 val); 2498 dev_dbg(pmx->dev, 2499 "set group %s to %d mA drive strength mask %08x val %08x\n", 2500 grp->name, arg, grp->driving_mask, val); 2501 break; 2502 default: 2503 dev_err(pmx->dev, "invalid config param %04x\n", param); 2504 return -ENOTSUPP; 2505 } 2506 } 2507 2508 return 0; 2509} 2510 2511static const struct pinconf_ops gemini_pinconf_ops = { 2512 .pin_config_get = gemini_pinconf_get, 2513 .pin_config_set = gemini_pinconf_set, 2514 .pin_config_group_set = gemini_pinconf_group_set, 2515 .is_generic = true, 2516}; 2517 2518static struct pinctrl_desc gemini_pmx_desc = { 2519 .name = DRIVER_NAME, 2520 .pctlops = &gemini_pctrl_ops, 2521 .pmxops = &gemini_pmx_ops, 2522 .confops = &gemini_pinconf_ops, 2523 .owner = THIS_MODULE, 2524}; 2525 2526static int gemini_pmx_probe(struct platform_device *pdev) 2527{ 2528 struct gemini_pmx *pmx; 2529 struct regmap *map; 2530 struct device *dev = &pdev->dev; 2531 struct device *parent; 2532 unsigned long tmp; 2533 u32 val; 2534 int ret; 2535 int i; 2536 2537 /* Create state holders etc for this driver */ 2538 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 2539 if (!pmx) 2540 return -ENOMEM; 2541 2542 pmx->dev = &pdev->dev; 2543 parent = dev->parent; 2544 if (!parent) { 2545 dev_err(dev, "no parent to pin controller\n"); 2546 return -ENODEV; 2547 } 2548 map = syscon_node_to_regmap(parent->of_node); 2549 if (IS_ERR(map)) { 2550 dev_err(dev, "no syscon regmap\n"); 2551 return PTR_ERR(map); 2552 } 2553 pmx->map = map; 2554 2555 /* Check that regmap works at first call, then no more */ 2556 ret = regmap_read(map, GLOBAL_WORD_ID, &val); 2557 if (ret) { 2558 dev_err(dev, "cannot access regmap\n"); 2559 return ret; 2560 } 2561 val >>= 8; 2562 val &= 0xffff; 2563 if (val == 0x3512) { 2564 pmx->is_3512 = true; 2565 pmx->confs = gemini_confs_3512; 2566 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); 2567 gemini_pmx_desc.pins = gemini_3512_pins; 2568 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); 2569 dev_info(dev, "detected 3512 chip variant\n"); 2570 } else if (val == 0x3516) { 2571 pmx->is_3516 = true; 2572 pmx->confs = gemini_confs_3516; 2573 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); 2574 gemini_pmx_desc.pins = gemini_3516_pins; 2575 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); 2576 dev_info(dev, "detected 3516 chip variant\n"); 2577 } else { 2578 dev_err(dev, "unknown chip ID: %04x\n", val); 2579 return -ENODEV; 2580 } 2581 2582 ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); 2583 dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); 2584 /* Mask off relevant pads */ 2585 val &= PADS_MASK; 2586 /* Invert the meaning of the DRAM+flash pads */ 2587 val ^= 0x0f; 2588 /* Print initial state */ 2589 tmp = val; 2590 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2591 dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i], 2592 str_enabled_disabled(val & BIT(i))); 2593 } 2594 2595 /* Check if flash pin is set */ 2596 regmap_read(map, GLOBAL_STATUS, &val); 2597 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); 2598 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); 2599 2600 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); 2601 if (IS_ERR(pmx->pctl)) { 2602 dev_err(dev, "could not register pinmux driver\n"); 2603 return PTR_ERR(pmx->pctl); 2604 } 2605 2606 dev_info(dev, "initialized Gemini pin control driver\n"); 2607 2608 return 0; 2609} 2610 2611static const struct of_device_id gemini_pinctrl_match[] = { 2612 { .compatible = "cortina,gemini-pinctrl" }, 2613 {}, 2614}; 2615 2616static struct platform_driver gemini_pmx_driver = { 2617 .driver = { 2618 .name = DRIVER_NAME, 2619 .of_match_table = gemini_pinctrl_match, 2620 }, 2621 .probe = gemini_pmx_probe, 2622}; 2623 2624static int __init gemini_pmx_init(void) 2625{ 2626 return platform_driver_register(&gemini_pmx_driver); 2627} 2628arch_initcall(gemini_pmx_init);
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