pinctrl-equilibrium.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 *  Copyright(c) 2019 Intel Corporation.
  4 */
  5
  6#ifndef __PINCTRL_EQUILIBRIUM_H
  7#define __PINCTRL_EQUILIBRIUM_H
  8
  9/* PINPAD register offset */
 10#define REG_PMX_BASE	0x0	/* Port Multiplexer Control Register */
 11#define REG_PUEN	0x80	/* PULL UP Enable Register */
 12#define REG_PDEN	0x84	/* PULL DOWN Enable Register */
 13#define REG_SRC		0x88	/* Slew Rate Control Register */
 14#define REG_DCC0	0x8C	/* Drive Current Control Register 0 */
 15#define REG_DCC1	0x90	/* Drive Current Control Register 1 */
 16#define REG_OD		0x94	/* Open Drain Enable Register */
 17#define REG_AVAIL	0x98	/* Pad Control Availability Register */
 18#define DRV_CUR_PINS	16	/* Drive Current pin number per register */
 19#define REG_DRCC(x)	(REG_DCC0 + (x) * 4) /* Driver current macro */
 20
 21/* GPIO register offset */
 22#define GPIO_OUT	0x0	/* Data Output Register */
 23#define GPIO_IN		0x4	/* Data Input Register */
 24#define GPIO_DIR	0x8	/* Direction Register */
 25#define GPIO_EXINTCR0	0x18	/* External Interrupt Control Register 0 */
 26#define GPIO_EXINTCR1	0x1C	/* External Interrupt Control Register 1 */
 27#define GPIO_IRNCR	0x20	/* IRN Capture Register */
 28#define GPIO_IRNICR	0x24	/* IRN Interrupt Control Register */
 29#define GPIO_IRNEN	0x28	/* IRN Interrupt Enable Register */
 30#define GPIO_IRNCFG	0x2C	/* IRN Interrupt Configuration Register */
 31#define GPIO_IRNRNSET	0x30	/* IRN Interrupt Enable Set Register */
 32#define GPIO_IRNENCLR	0x34	/* IRN Interrupt Enable Clear Register */
 33#define GPIO_OUTSET	0x40	/* Output Set Register */
 34#define GPIO_OUTCLR	0x44	/* Output Clear Register */
 35#define GPIO_DIRSET	0x48	/* Direction Set Register */
 36#define GPIO_DIRCLR	0x4C	/* Direction Clear Register */
 37
 38/* parse given pin's driver current value */
 39#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
 40
 41#define GPIO_EDGE_TRIG		0
 42#define GPIO_LEVEL_TRIG		1
 43#define GPIO_SINGLE_EDGE	0
 44#define GPIO_BOTH_EDGE		1
 45#define GPIO_POSITIVE_TRIG	0
 46#define GPIO_NEGATIVE_TRIG	1
 47
 48#define EQBR_GPIO_MODE		0
 49
 50typedef enum {
 51	OP_COUNT_NR_FUNCS,
 52	OP_ADD_FUNCS,
 53	OP_COUNT_NR_FUNC_GRPS,
 54	OP_ADD_FUNC_GRPS,
 55	OP_NONE,
 56} funcs_util_ops;
 57
 58/**
 59 * struct gpio_irq_type: gpio irq configuration
 60 * @trig_type: level trigger or edge trigger
 61 * @edge_type: sigle edge or both edge
 62 * @logic_type: positive trigger or negative trigger
 63 */
 64struct gpio_irq_type {
 65	unsigned int trig_type;
 66	unsigned int edge_type;
 67	unsigned int logic_type;
 68};
 69
 70/**
 71 * struct eqbr_pin_bank: represent a pin bank.
 72 * @membase: base address of the pin bank register.
 73 * @id: bank id, to idenify the unique bank.
 74 * @pin_base: starting pin number of the pin bank.
 75 * @nr_pins: number of the pins of the pin bank.
 76 * @aval_pinmap: available pin bitmap of the pin bank.
 77 */
 78struct eqbr_pin_bank {
 79	void __iomem		*membase;
 80	unsigned int		id;
 81	unsigned int		pin_base;
 82	unsigned int		nr_pins;
 83	u32			aval_pinmap;
 84};
 85
 86struct fwnode_handle;
 87
 88/**
 89 * struct eqbr_gpio_ctrl: represent a gpio controller.
 90 * @chip: gpio chip.
 91 * @fwnode: firmware node of gpio controller.
 92 * @bank: pointer to corresponding pin bank.
 93 * @membase: base address of the gpio controller.
 94 * @name: gpio chip name.
 95 * @virq: irq number of the gpio chip to parent's irq domain.
 96 * @lock: spin lock to protect gpio register write.
 97 */
 98struct eqbr_gpio_ctrl {
 99	struct gpio_generic_chip chip;
100	struct fwnode_handle	*fwnode;
101	struct eqbr_pin_bank	*bank;
102	void __iomem		*membase;
103	const char		*name;
104	unsigned int		virq;
105	raw_spinlock_t		lock; /* protect gpio register */
106};
107
108/**
109 * struct eqbr_pinctrl_drv_data:
110 * @dev: device instance representing the controller.
111 * @pctl_desc: pin controller descriptor.
112 * @pctl_dev: pin control class device
113 * @membase: base address of pin controller
114 * @pin_banks: list of pin banks of the driver.
115 * @nr_banks: number of pin banks.
116 * @gpio_ctrls: list of gpio controllers.
117 * @nr_gpio_ctrls: number of gpio controllers.
118 * @lock: protect pinctrl register write
119 */
120struct eqbr_pinctrl_drv_data {
121	struct device			*dev;
122	struct pinctrl_desc		pctl_desc;
123	struct pinctrl_dev		*pctl_dev;
124	void __iomem			*membase;
125	struct eqbr_pin_bank		*pin_banks;
126	unsigned int			nr_banks;
127	struct eqbr_gpio_ctrl		*gpio_ctrls;
128	unsigned int			nr_gpio_ctrls;
129	raw_spinlock_t			lock; /* protect pinpad register */
130};
131
132#endif /* __PINCTRL_EQUILIBRIUM_H */