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pinctrl-equilibrium.c
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linux-6.19.14/drivers/pinctrl/pinctrl-equilibrium.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (C) 2019 Intel Corporation */ 3 4#include <linux/gpio/driver.h> 5#include <linux/gpio/generic.h> 6#include <linux/module.h> 7#include <linux/of.h> 8#include <linux/of_address.h> 9#include <linux/of_irq.h> 10#include <linux/pinctrl/pinctrl.h> 11#include <linux/pinctrl/pinconf.h> 12#include <linux/pinctrl/pinconf-generic.h> 13#include <linux/pinctrl/pinmux.h> 14#include <linux/platform_device.h> 15#include <linux/property.h> 16 17#include "core.h" 18#include "pinconf.h" 19#include "pinmux.h" 20#include "pinctrl-equilibrium.h" 21 22#define PIN_NAME_FMT "io-%d" 23#define PIN_NAME_LEN 10 24#define PAD_REG_OFF 0x100 25 26static void eqbr_irq_mask(struct irq_data *d) 27{ 28 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 29 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 30 unsigned int offset = irqd_to_hwirq(d); 31 unsigned long flags; 32 33 raw_spin_lock_irqsave(&gctrl->lock, flags); 34 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); 35 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 36 gpiochip_disable_irq(gc, offset); 37} 38 39static void eqbr_irq_unmask(struct irq_data *d) 40{ 41 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 42 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 43 unsigned int offset = irqd_to_hwirq(d); 44 unsigned long flags; 45 46 gc->direction_input(gc, offset); 47 gpiochip_enable_irq(gc, offset); 48 raw_spin_lock_irqsave(&gctrl->lock, flags); 49 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); 50 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 51} 52 53static void eqbr_irq_ack(struct irq_data *d) 54{ 55 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 56 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 57 unsigned int offset = irqd_to_hwirq(d); 58 unsigned long flags; 59 60 raw_spin_lock_irqsave(&gctrl->lock, flags); 61 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); 62 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 63} 64 65static void eqbr_irq_mask_ack(struct irq_data *d) 66{ 67 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 68 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 69 unsigned int offset = irqd_to_hwirq(d); 70 unsigned long flags; 71 72 raw_spin_lock_irqsave(&gctrl->lock, flags); 73 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); 74 writel(BIT(offset), gctrl->membase + GPIO_IRNCR); 75 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 76} 77 78static inline void eqbr_cfg_bit(void __iomem *addr, 79 unsigned int offset, unsigned int set) 80{ 81 if (set) 82 writel(readl(addr) | BIT(offset), addr); 83 else 84 writel(readl(addr) & ~BIT(offset), addr); 85} 86 87static int eqbr_irq_type_cfg(struct gpio_irq_type *type, 88 struct eqbr_gpio_ctrl *gctrl, 89 unsigned int offset) 90{ 91 unsigned long flags; 92 93 raw_spin_lock_irqsave(&gctrl->lock, flags); 94 eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type); 95 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type); 96 eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type); 97 raw_spin_unlock_irqrestore(&gctrl->lock, flags); 98 99 return 0; 100} 101 102static int eqbr_irq_set_type(struct irq_data *d, unsigned int type) 103{ 104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 105 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 106 unsigned int offset = irqd_to_hwirq(d); 107 struct gpio_irq_type it; 108 109 memset(&it, 0, sizeof(it)); 110 111 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) 112 return 0; 113 114 switch (type) { 115 case IRQ_TYPE_EDGE_RISING: 116 it.trig_type = GPIO_EDGE_TRIG; 117 it.edge_type = GPIO_SINGLE_EDGE; 118 it.logic_type = GPIO_POSITIVE_TRIG; 119 break; 120 121 case IRQ_TYPE_EDGE_FALLING: 122 it.trig_type = GPIO_EDGE_TRIG; 123 it.edge_type = GPIO_SINGLE_EDGE; 124 it.logic_type = GPIO_NEGATIVE_TRIG; 125 break; 126 127 case IRQ_TYPE_EDGE_BOTH: 128 it.trig_type = GPIO_EDGE_TRIG; 129 it.edge_type = GPIO_BOTH_EDGE; 130 it.logic_type = GPIO_POSITIVE_TRIG; 131 break; 132 133 case IRQ_TYPE_LEVEL_HIGH: 134 it.trig_type = GPIO_LEVEL_TRIG; 135 it.edge_type = GPIO_SINGLE_EDGE; 136 it.logic_type = GPIO_POSITIVE_TRIG; 137 break; 138 139 case IRQ_TYPE_LEVEL_LOW: 140 it.trig_type = GPIO_LEVEL_TRIG; 141 it.edge_type = GPIO_SINGLE_EDGE; 142 it.logic_type = GPIO_NEGATIVE_TRIG; 143 break; 144 145 default: 146 return -EINVAL; 147 } 148 149 eqbr_irq_type_cfg(&it, gctrl, offset); 150 if (it.trig_type == GPIO_EDGE_TRIG) 151 irq_set_handler_locked(d, handle_edge_irq); 152 else 153 irq_set_handler_locked(d, handle_level_irq); 154 155 return 0; 156} 157 158static void eqbr_irq_handler(struct irq_desc *desc) 159{ 160 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 161 struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc); 162 struct irq_chip *ic = irq_desc_get_chip(desc); 163 unsigned long pins, offset; 164 165 chained_irq_enter(ic, desc); 166 pins = readl(gctrl->membase + GPIO_IRNCR); 167 168 for_each_set_bit(offset, &pins, gc->ngpio) 169 generic_handle_domain_irq(gc->irq.domain, offset); 170 171 chained_irq_exit(ic, desc); 172} 173 174static const struct irq_chip eqbr_irq_chip = { 175 .name = "gpio_irq", 176 .irq_ack = eqbr_irq_ack, 177 .irq_mask = eqbr_irq_mask, 178 .irq_mask_ack = eqbr_irq_mask_ack, 179 .irq_unmask = eqbr_irq_unmask, 180 .irq_set_type = eqbr_irq_set_type, 181 .flags = IRQCHIP_IMMUTABLE, 182 GPIOCHIP_IRQ_RESOURCE_HELPERS, 183}; 184 185static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl) 186{ 187 struct gpio_irq_chip *girq; 188 struct gpio_chip *gc; 189 190 gc = &gctrl->chip.gc; 191 gc->label = gctrl->name; 192 gc->fwnode = gctrl->fwnode; 193 gc->request = gpiochip_generic_request; 194 gc->free = gpiochip_generic_free; 195 196 if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) { 197 dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n", 198 gctrl->name); 199 return 0; 200 } 201 202 girq = &gctrl->chip.gc.irq; 203 gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); 204 girq->parent_handler = eqbr_irq_handler; 205 girq->num_parents = 1; 206 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); 207 if (!girq->parents) 208 return -ENOMEM; 209 210 girq->default_type = IRQ_TYPE_NONE; 211 girq->handler = handle_bad_irq; 212 girq->parents[0] = gctrl->virq; 213 214 return 0; 215} 216 217static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata) 218{ 219 struct gpio_generic_chip_config config; 220 struct device *dev = drvdata->dev; 221 struct eqbr_gpio_ctrl *gctrl; 222 struct device_node *np; 223 struct resource res; 224 int i, ret; 225 226 for (i = 0; i < drvdata->nr_gpio_ctrls; i++) { 227 gctrl = drvdata->gpio_ctrls + i; 228 np = to_of_node(gctrl->fwnode); 229 230 gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i); 231 if (!gctrl->name) 232 return -ENOMEM; 233 234 if (of_address_to_resource(np, 0, &res)) { 235 dev_err(dev, "Failed to get GPIO register address\n"); 236 return -ENXIO; 237 } 238 239 gctrl->membase = devm_ioremap_resource(dev, &res); 240 if (IS_ERR(gctrl->membase)) 241 return PTR_ERR(gctrl->membase); 242 243 gctrl->virq = irq_of_parse_and_map(np, 0); 244 if (!gctrl->virq) { 245 dev_err(dev, "%s: failed to parse and map irq\n", 246 gctrl->name); 247 return -ENXIO; 248 } 249 raw_spin_lock_init(&gctrl->lock); 250 251 config = (struct gpio_generic_chip_config) { 252 .dev = dev, 253 .sz = gctrl->bank->nr_pins / 8, 254 .dat = gctrl->membase + GPIO_IN, 255 .set = gctrl->membase + GPIO_OUTSET, 256 .clr = gctrl->membase + GPIO_OUTCLR, 257 .dirout = gctrl->membase + GPIO_DIR, 258 }; 259 260 ret = gpio_generic_chip_init(&gctrl->chip, &config); 261 if (ret) { 262 dev_err(dev, "unable to init generic GPIO\n"); 263 return ret; 264 } 265 266 ret = gpiochip_setup(dev, gctrl); 267 if (ret) 268 return ret; 269 270 ret = devm_gpiochip_add_data(dev, &gctrl->chip.gc, gctrl); 271 if (ret) 272 return ret; 273 } 274 275 return 0; 276} 277 278static inline struct eqbr_pin_bank 279*find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin) 280{ 281 struct eqbr_pin_bank *bank; 282 int i; 283 284 for (i = 0; i < pctl->nr_banks; i++) { 285 bank = &pctl->pin_banks[i]; 286 if (pin >= bank->pin_base && 287 (pin - bank->pin_base) < bank->nr_pins) 288 return bank; 289 } 290 291 return NULL; 292} 293 294static const struct pinctrl_ops eqbr_pctl_ops = { 295 .get_groups_count = pinctrl_generic_get_group_count, 296 .get_group_name = pinctrl_generic_get_group_name, 297 .get_group_pins = pinctrl_generic_get_group_pins, 298 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 299 .dt_free_map = pinconf_generic_dt_free_map, 300}; 301 302static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl, 303 unsigned int pmx, unsigned int pin) 304{ 305 struct eqbr_pin_bank *bank; 306 unsigned long flags; 307 unsigned int offset; 308 void __iomem *mem; 309 310 bank = find_pinbank_via_pin(pctl, pin); 311 if (!bank) { 312 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); 313 return -ENODEV; 314 } 315 mem = bank->membase; 316 offset = pin - bank->pin_base; 317 318 if (!(bank->aval_pinmap & BIT(offset))) { 319 dev_err(pctl->dev, 320 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", 321 pin, bank->pin_base, bank->aval_pinmap); 322 return -ENODEV; 323 } 324 325 raw_spin_lock_irqsave(&pctl->lock, flags); 326 writel(pmx, mem + (offset * 4)); 327 raw_spin_unlock_irqrestore(&pctl->lock, flags); 328 return 0; 329} 330 331static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev, 332 unsigned int selector, unsigned int group) 333{ 334 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 335 const struct function_desc *func; 336 struct group_desc *grp; 337 unsigned int *pinmux; 338 int i; 339 340 func = pinmux_generic_get_function(pctldev, selector); 341 if (!func) 342 return -EINVAL; 343 344 grp = pinctrl_generic_get_group(pctldev, group); 345 if (!grp) 346 return -EINVAL; 347 348 pinmux = grp->data; 349 for (i = 0; i < grp->grp.npins; i++) 350 eqbr_set_pin_mux(pctl, pinmux[i], grp->grp.pins[i]); 351 352 return 0; 353} 354 355static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev, 356 struct pinctrl_gpio_range *range, 357 unsigned int pin) 358{ 359 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 360 361 return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin); 362} 363 364static const struct pinmux_ops eqbr_pinmux_ops = { 365 .get_functions_count = pinmux_generic_get_function_count, 366 .get_function_name = pinmux_generic_get_function_name, 367 .get_function_groups = pinmux_generic_get_function_groups, 368 .set_mux = eqbr_pinmux_set_mux, 369 .gpio_request_enable = eqbr_pinmux_gpio_request, 370 .strict = true, 371}; 372 373static int get_drv_cur(void __iomem *mem, unsigned int offset) 374{ 375 unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/ 376 unsigned int pin_offset = offset % DRV_CUR_PINS; 377 378 return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset); 379} 380 381static struct eqbr_gpio_ctrl 382*get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl, 383 struct eqbr_pin_bank *bank) 384{ 385 int i; 386 387 for (i = 0; i < pctl->nr_gpio_ctrls; i++) { 388 if (pctl->gpio_ctrls[i].bank == bank) 389 return &pctl->gpio_ctrls[i]; 390 } 391 392 return NULL; 393} 394 395static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 396 unsigned long *config) 397{ 398 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 399 enum pin_config_param param = pinconf_to_config_param(*config); 400 struct eqbr_gpio_ctrl *gctrl; 401 struct eqbr_pin_bank *bank; 402 unsigned long flags; 403 unsigned int offset; 404 void __iomem *mem; 405 u32 val; 406 407 bank = find_pinbank_via_pin(pctl, pin); 408 if (!bank) { 409 dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin); 410 return -ENODEV; 411 } 412 mem = bank->membase; 413 offset = pin - bank->pin_base; 414 415 if (!(bank->aval_pinmap & BIT(offset))) { 416 dev_err(pctl->dev, 417 "PIN: %u is not valid, pinbase: %u, bitmap: %u\n", 418 pin, bank->pin_base, bank->aval_pinmap); 419 return -ENODEV; 420 } 421 422 raw_spin_lock_irqsave(&pctl->lock, flags); 423 switch (param) { 424 case PIN_CONFIG_BIAS_PULL_UP: 425 val = !!(readl(mem + REG_PUEN) & BIT(offset)); 426 break; 427 case PIN_CONFIG_BIAS_PULL_DOWN: 428 val = !!(readl(mem + REG_PDEN) & BIT(offset)); 429 break; 430 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 431 val = !!(readl(mem + REG_OD) & BIT(offset)); 432 break; 433 case PIN_CONFIG_DRIVE_STRENGTH: 434 val = get_drv_cur(mem, offset); 435 break; 436 case PIN_CONFIG_SLEW_RATE: 437 val = !!(readl(mem + REG_SRC) & BIT(offset)); 438 break; 439 case PIN_CONFIG_OUTPUT_ENABLE: 440 gctrl = get_gpio_ctrls_via_bank(pctl, bank); 441 if (!gctrl) { 442 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", 443 bank->pin_base, pin); 444 raw_spin_unlock_irqrestore(&pctl->lock, flags); 445 return -ENODEV; 446 } 447 val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset)); 448 break; 449 default: 450 raw_spin_unlock_irqrestore(&pctl->lock, flags); 451 return -ENOTSUPP; 452 } 453 raw_spin_unlock_irqrestore(&pctl->lock, flags); 454 *config = pinconf_to_config_packed(param, val); 455 456 return 0; 457} 458 459static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 460 unsigned long *configs, unsigned int num_configs) 461{ 462 struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev); 463 struct eqbr_gpio_ctrl *gctrl; 464 enum pin_config_param param; 465 struct eqbr_pin_bank *bank; 466 unsigned int val, offset; 467 struct gpio_chip *gc; 468 unsigned long flags; 469 void __iomem *mem; 470 u32 regval, mask; 471 int i; 472 473 for (i = 0; i < num_configs; i++) { 474 param = pinconf_to_config_param(configs[i]); 475 val = pinconf_to_config_argument(configs[i]); 476 477 bank = find_pinbank_via_pin(pctl, pin); 478 if (!bank) { 479 dev_err(pctl->dev, 480 "Couldn't find pin bank for pin %u\n", pin); 481 return -ENODEV; 482 } 483 mem = bank->membase; 484 offset = pin - bank->pin_base; 485 486 switch (param) { 487 case PIN_CONFIG_BIAS_PULL_UP: 488 mem += REG_PUEN; 489 mask = BIT(offset); 490 break; 491 case PIN_CONFIG_BIAS_PULL_DOWN: 492 mem += REG_PDEN; 493 mask = BIT(offset); 494 break; 495 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 496 mem += REG_OD; 497 mask = BIT(offset); 498 break; 499 case PIN_CONFIG_DRIVE_STRENGTH: 500 mem += REG_DRCC(offset / DRV_CUR_PINS); 501 offset = (offset % DRV_CUR_PINS) * 2; 502 mask = GENMASK(1, 0) << offset; 503 break; 504 case PIN_CONFIG_SLEW_RATE: 505 mem += REG_SRC; 506 mask = BIT(offset); 507 break; 508 case PIN_CONFIG_OUTPUT_ENABLE: 509 gctrl = get_gpio_ctrls_via_bank(pctl, bank); 510 if (!gctrl) { 511 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n", 512 bank->pin_base, pin); 513 return -ENODEV; 514 } 515 gc = &gctrl->chip.gc; 516 gc->direction_output(gc, offset, 0); 517 continue; 518 default: 519 return -ENOTSUPP; 520 } 521 522 raw_spin_lock_irqsave(&pctl->lock, flags); 523 regval = readl(mem); 524 regval = (regval & ~mask) | ((val << offset) & mask); 525 writel(regval, mem); 526 raw_spin_unlock_irqrestore(&pctl->lock, flags); 527 } 528 529 return 0; 530} 531 532static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev, 533 unsigned int group, unsigned long *config) 534{ 535 unsigned int i, npins, old = 0; 536 const unsigned int *pins; 537 int ret; 538 539 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 540 if (ret) 541 return ret; 542 543 for (i = 0; i < npins; i++) { 544 if (eqbr_pinconf_get(pctldev, pins[i], config)) 545 return -ENOTSUPP; 546 547 if (i && old != *config) 548 return -ENOTSUPP; 549 550 old = *config; 551 } 552 return 0; 553} 554 555static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev, 556 unsigned int group, unsigned long *configs, 557 unsigned int num_configs) 558{ 559 const unsigned int *pins; 560 unsigned int i, npins; 561 int ret; 562 563 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 564 if (ret) 565 return ret; 566 567 for (i = 0; i < npins; i++) { 568 ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs); 569 if (ret) 570 return ret; 571 } 572 return 0; 573} 574 575static const struct pinconf_ops eqbr_pinconf_ops = { 576 .is_generic = true, 577 .pin_config_get = eqbr_pinconf_get, 578 .pin_config_set = eqbr_pinconf_set, 579 .pin_config_group_get = eqbr_pinconf_group_get, 580 .pin_config_group_set = eqbr_pinconf_group_set, 581 .pin_config_config_dbg_show = pinconf_generic_dump_config, 582}; 583 584static bool is_func_exist(struct pinfunction *funcs, const char *name, 585 unsigned int nr_funcs, unsigned int *idx) 586{ 587 int i; 588 589 if (!funcs) 590 return false; 591 592 for (i = 0; i < nr_funcs; i++) { 593 if (funcs[i].name && !strcmp(funcs[i].name, name)) { 594 *idx = i; 595 return true; 596 } 597 } 598 599 return false; 600} 601 602static int funcs_utils(struct device *dev, struct pinfunction *funcs, 603 unsigned int *nr_funcs, funcs_util_ops op) 604{ 605 struct device_node *node = dev->of_node; 606 struct property *prop; 607 const char *fn_name; 608 const char **groups; 609 unsigned int fid; 610 int i, j; 611 612 i = 0; 613 for_each_child_of_node_scoped(node, np) { 614 prop = of_find_property(np, "groups", NULL); 615 if (!prop) 616 continue; 617 618 if (of_property_read_string(np, "function", &fn_name)) { 619 /* some groups may not have function, it's OK */ 620 dev_dbg(dev, "Group %s: not function binded!\n", 621 (char *)prop->value); 622 continue; 623 } 624 625 switch (op) { 626 case OP_COUNT_NR_FUNCS: 627 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 628 *nr_funcs = *nr_funcs + 1; 629 break; 630 631 case OP_ADD_FUNCS: 632 if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 633 funcs[i].name = fn_name; 634 break; 635 636 case OP_COUNT_NR_FUNC_GRPS: 637 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) 638 funcs[fid].ngroups++; 639 break; 640 641 case OP_ADD_FUNC_GRPS: 642 if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) { 643 groups = (const char **)funcs[fid].groups; 644 for (j = 0; j < funcs[fid].ngroups; j++) 645 if (!groups[j]) 646 break; 647 groups[j] = prop->value; 648 } 649 break; 650 651 default: 652 return -EINVAL; 653 } 654 i++; 655 } 656 657 return 0; 658} 659 660static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata) 661{ 662 struct device *dev = drvdata->dev; 663 struct pinfunction *funcs = NULL; 664 unsigned int nr_funcs = 0; 665 int i, ret; 666 667 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS); 668 if (ret) 669 return ret; 670 671 funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL); 672 if (!funcs) 673 return -ENOMEM; 674 675 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS); 676 if (ret) 677 return ret; 678 679 ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS); 680 if (ret) 681 return ret; 682 683 for (i = 0; i < nr_funcs; i++) { 684 if (!funcs[i].ngroups) 685 continue; 686 funcs[i].groups = devm_kcalloc(dev, funcs[i].ngroups, 687 sizeof(*(funcs[i].groups)), 688 GFP_KERNEL); 689 if (!funcs[i].groups) 690 return -ENOMEM; 691 } 692 693 ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS); 694 if (ret) 695 return ret; 696 697 for (i = 0; i < nr_funcs; i++) { 698 699 /* Ignore the same function with multiple groups */ 700 if (funcs[i].name == NULL) 701 continue; 702 703 ret = pinmux_generic_add_pinfunction(drvdata->pctl_dev, 704 &funcs[i], drvdata); 705 if (ret < 0) { 706 dev_err(dev, "Failed to register function %s\n", 707 funcs[i].name); 708 return ret; 709 } 710 } 711 712 return 0; 713} 714 715static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata) 716{ 717 struct device *dev = drvdata->dev; 718 struct device_node *node = dev->of_node; 719 unsigned int *pins, *pinmux, pin_id, pinmux_id; 720 struct pingroup group, *grp = &group; 721 struct property *prop; 722 int j, err; 723 724 for_each_child_of_node_scoped(node, np) { 725 prop = of_find_property(np, "groups", NULL); 726 if (!prop) 727 continue; 728 729 err = of_property_count_u32_elems(np, "pins"); 730 if (err < 0) { 731 dev_err(dev, "No pins in the group: %s\n", prop->name); 732 return err; 733 } 734 grp->npins = err; 735 grp->name = prop->value; 736 pins = devm_kcalloc(dev, grp->npins, sizeof(*pins), GFP_KERNEL); 737 if (!pins) 738 return -ENOMEM; 739 740 grp->pins = pins; 741 742 pinmux = devm_kcalloc(dev, grp->npins, sizeof(*pinmux), GFP_KERNEL); 743 if (!pinmux) 744 return -ENOMEM; 745 746 for (j = 0; j < grp->npins; j++) { 747 if (of_property_read_u32_index(np, "pins", j, &pin_id)) { 748 dev_err(dev, "Group %s: Read intel pins id failed\n", 749 grp->name); 750 return -EINVAL; 751 } 752 if (pin_id >= drvdata->pctl_desc.npins) { 753 dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n", 754 grp->name, j, pin_id); 755 return -EINVAL; 756 } 757 pins[j] = pin_id; 758 if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) { 759 dev_err(dev, "Group %s: Read intel pinmux id failed\n", 760 grp->name); 761 return -EINVAL; 762 } 763 pinmux[j] = pinmux_id; 764 } 765 766 err = pinctrl_generic_add_group(drvdata->pctl_dev, 767 grp->name, grp->pins, grp->npins, 768 pinmux); 769 if (err < 0) { 770 dev_err(dev, "Failed to register group %s\n", grp->name); 771 return err; 772 } 773 memset(&group, 0, sizeof(group)); 774 pinmux = NULL; 775 } 776 777 return 0; 778} 779 780static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata) 781{ 782 struct pinctrl_desc *pctl_desc; 783 struct pinctrl_pin_desc *pdesc; 784 struct device *dev; 785 unsigned int nr_pins; 786 char *pin_names; 787 int i, ret; 788 789 dev = drvdata->dev; 790 pctl_desc = &drvdata->pctl_desc; 791 pctl_desc->name = "eqbr-pinctrl"; 792 pctl_desc->owner = THIS_MODULE; 793 pctl_desc->pctlops = &eqbr_pctl_ops; 794 pctl_desc->pmxops = &eqbr_pinmux_ops; 795 pctl_desc->confops = &eqbr_pinconf_ops; 796 raw_spin_lock_init(&drvdata->lock); 797 798 for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++) 799 nr_pins += drvdata->pin_banks[i].nr_pins; 800 801 pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL); 802 if (!pdesc) 803 return -ENOMEM; 804 pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL); 805 if (!pin_names) 806 return -ENOMEM; 807 808 for (i = 0; i < nr_pins; i++) { 809 sprintf(pin_names, PIN_NAME_FMT, i); 810 pdesc[i].number = i; 811 pdesc[i].name = pin_names; 812 pin_names += PIN_NAME_LEN; 813 } 814 pctl_desc->pins = pdesc; 815 pctl_desc->npins = nr_pins; 816 dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins); 817 818 ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata, 819 &drvdata->pctl_dev); 820 if (ret) 821 return ret; 822 823 ret = eqbr_build_groups(drvdata); 824 if (ret) { 825 dev_err(dev, "Failed to build groups\n"); 826 return ret; 827 } 828 829 ret = eqbr_build_functions(drvdata); 830 if (ret) { 831 dev_err(dev, "Failed to build functions\n"); 832 return ret; 833 } 834 835 return pinctrl_enable(drvdata->pctl_dev); 836} 837 838static int pinbank_init(struct device_node *np, 839 struct eqbr_pinctrl_drv_data *drvdata, 840 struct eqbr_pin_bank *bank, unsigned int id) 841{ 842 struct device *dev = drvdata->dev; 843 struct of_phandle_args spec; 844 int ret; 845 846 bank->membase = drvdata->membase + id * PAD_REG_OFF; 847 848 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec); 849 if (ret) { 850 dev_err(dev, "gpio-range not available!\n"); 851 return ret; 852 } 853 854 bank->pin_base = spec.args[1]; 855 bank->nr_pins = spec.args[2]; 856 of_node_put(spec.np); 857 858 bank->aval_pinmap = readl(bank->membase + REG_AVAIL); 859 bank->id = id; 860 861 dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n", 862 id, bank->membase, bank->pin_base, 863 bank->nr_pins, bank->aval_pinmap); 864 865 return ret; 866} 867 868static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata) 869{ 870 struct device *dev = drvdata->dev; 871 struct device_node *np_gpio; 872 struct eqbr_gpio_ctrl *gctrls; 873 struct eqbr_pin_bank *banks; 874 int i, nr_gpio; 875 876 /* Count gpio bank number */ 877 nr_gpio = 0; 878 for_each_node_by_name(np_gpio, "gpio") { 879 if (of_device_is_available(np_gpio)) 880 nr_gpio++; 881 } 882 883 if (!nr_gpio) { 884 dev_err(dev, "NO pin bank available!\n"); 885 return -ENODEV; 886 } 887 888 /* Count pin bank number and gpio controller number */ 889 banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL); 890 if (!banks) 891 return -ENOMEM; 892 893 gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL); 894 if (!gctrls) 895 return -ENOMEM; 896 897 dev_dbg(dev, "found %d gpio controller!\n", nr_gpio); 898 899 /* Initialize Pin bank */ 900 i = 0; 901 for_each_node_by_name(np_gpio, "gpio") { 902 if (!of_device_is_available(np_gpio)) 903 continue; 904 905 pinbank_init(np_gpio, drvdata, banks + i, i); 906 907 gctrls[i].fwnode = of_fwnode_handle(np_gpio); 908 gctrls[i].bank = banks + i; 909 i++; 910 } 911 912 drvdata->pin_banks = banks; 913 drvdata->nr_banks = nr_gpio; 914 drvdata->gpio_ctrls = gctrls; 915 drvdata->nr_gpio_ctrls = nr_gpio; 916 917 return 0; 918} 919 920static int eqbr_pinctrl_probe(struct platform_device *pdev) 921{ 922 struct eqbr_pinctrl_drv_data *drvdata; 923 struct device *dev = &pdev->dev; 924 int ret; 925 926 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 927 if (!drvdata) 928 return -ENOMEM; 929 930 drvdata->dev = dev; 931 932 drvdata->membase = devm_platform_ioremap_resource(pdev, 0); 933 if (IS_ERR(drvdata->membase)) 934 return PTR_ERR(drvdata->membase); 935 936 ret = pinbank_probe(drvdata); 937 if (ret) 938 return ret; 939 940 ret = pinctrl_reg(drvdata); 941 if (ret) 942 return ret; 943 944 ret = gpiolib_reg(drvdata); 945 if (ret) 946 return ret; 947 948 platform_set_drvdata(pdev, drvdata); 949 return 0; 950} 951 952static const struct of_device_id eqbr_pinctrl_dt_match[] = { 953 { .compatible = "intel,lgm-io" }, 954 {} 955}; 956MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match); 957 958static struct platform_driver eqbr_pinctrl_driver = { 959 .probe = eqbr_pinctrl_probe, 960 .driver = { 961 .name = "eqbr-pinctrl", 962 .of_match_table = eqbr_pinctrl_dt_match, 963 }, 964}; 965 966module_platform_driver(eqbr_pinctrl_driver); 967 968MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>"); 969MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)"); 970MODULE_LICENSE("GPL v2");
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