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pinctrl-eic7700.c
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linux-6.19.14/drivers/pinctrl/pinctrl-eic7700.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ESWIN Pinctrl Controller Platform Device Driver 4 * 5 * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All rights reserved. 6 * 7 * Authors: Samuel Holland <samuel.holland@sifive.com> 8 * Yulin Lu <luyulin@eswincomputing.com> 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/device.h> 13#include <linux/io.h> 14#include <linux/mod_devicetable.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/seq_file.h> 19#include <linux/regulator/consumer.h> 20 21#include <linux/pinctrl/pinconf.h> 22#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinmux.h> 25 26#include "core.h" 27#include "pinmux.h" 28#include "pinconf.h" 29 30#define EIC7700_PIN_REG(i) (4 * (i)) 31#define EIC7700_IE BIT(0) 32#define EIC7700_PU BIT(1) 33#define EIC7700_PD BIT(2) 34#define EIC7700_DS GENMASK(6, 3) 35#define EIC7700_ST BIT(7) 36#define EIC7700_FUNC_SEL GENMASK(18, 16) 37 38#define EIC7700_BIAS (EIC7700_PD | EIC7700_PU) 39#define EIC7700_PINCONF GENMASK(7, 0) 40 41#define EIC7700_RGMII0_SEL_MODE (0x310 - 0x80) 42#define EIC7700_RGMII1_SEL_MODE (0x314 - 0x80) 43#define EIC7700_MS GENMASK(1, 0) 44#define EIC7700_MS_3V3 0x0 45#define EIC7700_MS_1V8 0x3 46 47#define EIC7700_FUNCTIONS_PER_PIN 8 48 49struct eic7700_pin { 50 u8 functions[EIC7700_FUNCTIONS_PER_PIN]; 51}; 52 53struct eic7700_pinctrl { 54 void __iomem *base; 55 struct pinctrl_desc desc; 56 unsigned int functions_count; 57 struct pinfunction functions[] __counted_by(functions_count); 58}; 59 60enum { 61 F_DISABLED, 62 F_BOOT_SEL, 63 F_CHIP_MODE, 64 F_EMMC, 65 F_FAN_TACH, 66 F_GPIO, 67 F_HDMI, 68 F_I2C, 69 F_I2S, 70 F_JTAG, 71 F_DDR_REF_CLK_SEL, 72 F_LPDDR_REF_CLK, 73 F_MIPI_CSI, 74 F_OSC, 75 F_PCIE, 76 F_PWM, 77 F_RGMII, 78 F_RESET, 79 F_SATA, 80 F_SDIO, 81 F_SPI, 82 F_S_MODE, 83 F_UART, 84 F_USB, 85 EIC7700_FUNCTIONS_COUNT 86}; 87 88static const char *const eic7700_functions[EIC7700_FUNCTIONS_COUNT] = { 89 [F_DISABLED] = "disabled", 90 [F_BOOT_SEL] = "boot_sel", 91 [F_CHIP_MODE] = "chip_mode", 92 [F_EMMC] = "emmc", 93 [F_FAN_TACH] = "fan_tach", 94 [F_GPIO] = "gpio", 95 [F_HDMI] = "hdmi", 96 [F_I2C] = "i2c", 97 [F_I2S] = "i2s", 98 [F_JTAG] = "jtag", 99 [F_DDR_REF_CLK_SEL] = "ddr_ref_clk_sel", 100 [F_LPDDR_REF_CLK] = "lpddr_ref_clk", 101 [F_MIPI_CSI] = "mipi_csi", 102 [F_OSC] = "osc", 103 [F_PCIE] = "pcie", 104 [F_PWM] = "pwm", 105 [F_RGMII] = "rgmii", 106 [F_RESET] = "reset", 107 [F_SATA] = "sata", 108 [F_SDIO] = "sdio", 109 [F_SPI] = "spi", 110 [F_S_MODE] = "s_mode", 111 [F_UART] = "uart", 112 [F_USB] = "usb", 113}; 114 115#define EIC7700_PIN(_number, _name, ...) \ 116 { \ 117 .number = _number, \ 118 .name = _name, \ 119 .drv_data = (void *)&(struct eic7700_pin) { { __VA_ARGS__ } } \ 120 } 121 122static const struct pinctrl_pin_desc eic7700_pins[] = { 123 EIC7700_PIN(0, "chip_mode", [0] = F_CHIP_MODE), 124 EIC7700_PIN(1, "mode_set0", [0] = F_SDIO, [2] = F_GPIO), 125 EIC7700_PIN(2, "mode_set1", [0] = F_SDIO, [2] = F_GPIO), 126 EIC7700_PIN(3, "mode_set2", [0] = F_SDIO, [2] = F_GPIO), 127 EIC7700_PIN(4, "mode_set3", [0] = F_SDIO, [2] = F_GPIO), 128 EIC7700_PIN(5, "xin", [0] = F_OSC), 129 EIC7700_PIN(6, "rtc_xin", [0] = F_DISABLED), 130 EIC7700_PIN(7, "rst_out_n", [0] = F_RESET), 131 EIC7700_PIN(8, "key_reset_n", [0] = F_RESET), 132 EIC7700_PIN(9, "rst_in_n", [0] = F_DISABLED), 133 EIC7700_PIN(10, "por_in_n", [0] = F_DISABLED), 134 EIC7700_PIN(11, "por_out_n", [0] = F_DISABLED), 135 EIC7700_PIN(12, "gpio0", [0] = F_GPIO), 136 EIC7700_PIN(13, "por_sel", [0] = F_RESET), 137 EIC7700_PIN(14, "jtag0_tck", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO), 138 EIC7700_PIN(15, "jtag0_tms", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO), 139 EIC7700_PIN(16, "jtag0_tdi", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO), 140 EIC7700_PIN(17, "jtag0_tdo", [0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO), 141 EIC7700_PIN(18, "gpio5", [0] = F_GPIO, [1] = F_SPI), 142 EIC7700_PIN(19, "spi2_cs0_n", [0] = F_SPI, [2] = F_GPIO), 143 EIC7700_PIN(20, "jtag1_tck", [0] = F_JTAG, [2] = F_GPIO), 144 EIC7700_PIN(21, "jtag1_tms", [0] = F_JTAG, [2] = F_GPIO), 145 EIC7700_PIN(22, "jtag1_tdi", [0] = F_JTAG, [2] = F_GPIO), 146 EIC7700_PIN(23, "jtag1_tdo", [0] = F_JTAG, [2] = F_GPIO), 147 EIC7700_PIN(24, "gpio11", [0] = F_GPIO), 148 EIC7700_PIN(25, "spi2_cs1_n", [0] = F_SPI, [2] = F_GPIO), 149 EIC7700_PIN(26, "pcie_clkreq_n", [0] = F_PCIE), 150 EIC7700_PIN(27, "pcie_wake_n", [0] = F_PCIE), 151 EIC7700_PIN(28, "pcie_perst_n", [0] = F_PCIE), 152 EIC7700_PIN(29, "hdmi_scl", [0] = F_HDMI), 153 EIC7700_PIN(30, "hdmi_sda", [0] = F_HDMI), 154 EIC7700_PIN(31, "hdmi_cec", [0] = F_HDMI), 155 EIC7700_PIN(32, "jtag2_trst", [0] = F_JTAG, [2] = F_GPIO), 156 EIC7700_PIN(33, "rgmii0_clk_125", [0] = F_RGMII), 157 EIC7700_PIN(34, "rgmii0_txen", [0] = F_RGMII), 158 EIC7700_PIN(35, "rgmii0_txclk", [0] = F_RGMII), 159 EIC7700_PIN(36, "rgmii0_txd0", [0] = F_RGMII), 160 EIC7700_PIN(37, "rgmii0_txd1", [0] = F_RGMII), 161 EIC7700_PIN(38, "rgmii0_txd2", [0] = F_RGMII), 162 EIC7700_PIN(39, "rgmii0_txd3", [0] = F_RGMII), 163 EIC7700_PIN(40, "i2s0_bclk", [0] = F_I2S, [2] = F_GPIO), 164 EIC7700_PIN(41, "i2s0_wclk", [0] = F_I2S, [2] = F_GPIO), 165 EIC7700_PIN(42, "i2s0_sdi", [0] = F_I2S, [2] = F_GPIO), 166 EIC7700_PIN(43, "i2s0_sdo", [0] = F_I2S, [2] = F_GPIO), 167 EIC7700_PIN(44, "i2s_mclk", [0] = F_I2S, [2] = F_GPIO), 168 EIC7700_PIN(45, "rgmii0_rxclk", [0] = F_RGMII), 169 EIC7700_PIN(46, "rgmii0_rxdv", [0] = F_RGMII), 170 EIC7700_PIN(47, "rgmii0_rxd0", [0] = F_RGMII), 171 EIC7700_PIN(48, "rgmii0_rxd1", [0] = F_RGMII), 172 EIC7700_PIN(49, "rgmii0_rxd2", [0] = F_RGMII), 173 EIC7700_PIN(50, "rgmii0_rxd3", [0] = F_RGMII), 174 EIC7700_PIN(51, "i2s2_bclk", [0] = F_I2S, [2] = F_GPIO), 175 EIC7700_PIN(52, "i2s2_wclk", [0] = F_I2S, [2] = F_GPIO), 176 EIC7700_PIN(53, "i2s2_sdi", [0] = F_I2S, [2] = F_GPIO), 177 EIC7700_PIN(54, "i2s2_sdo", [0] = F_I2S, [2] = F_GPIO), 178 EIC7700_PIN(55, "gpio27", [0] = F_GPIO, [1] = F_SATA), 179 EIC7700_PIN(56, "gpio28", [0] = F_GPIO), 180 EIC7700_PIN(57, "gpio29", [0] = F_RESET, [1] = F_EMMC, [2] = F_GPIO), 181 EIC7700_PIN(58, "rgmii0_mdc", [0] = F_RGMII), 182 EIC7700_PIN(59, "rgmii0_mdio", [0] = F_RGMII), 183 EIC7700_PIN(60, "rgmii0_intb", [0] = F_RGMII), 184 EIC7700_PIN(61, "rgmii1_clk_125", [0] = F_RGMII), 185 EIC7700_PIN(62, "rgmii1_txen", [0] = F_RGMII), 186 EIC7700_PIN(63, "rgmii1_txclk", [0] = F_RGMII), 187 EIC7700_PIN(64, "rgmii1_txd0", [0] = F_RGMII), 188 EIC7700_PIN(65, "rgmii1_txd1", [0] = F_RGMII), 189 EIC7700_PIN(66, "rgmii1_txd2", [0] = F_RGMII), 190 EIC7700_PIN(67, "rgmii1_txd3", [0] = F_RGMII), 191 EIC7700_PIN(68, "i2s1_bclk", [0] = F_I2S, [2] = F_GPIO), 192 EIC7700_PIN(69, "i2s1_wclk", [0] = F_I2S, [2] = F_GPIO), 193 EIC7700_PIN(70, "i2s1_sdi", [0] = F_I2S, [2] = F_GPIO), 194 EIC7700_PIN(71, "i2s1_sdo", [0] = F_I2S, [2] = F_GPIO), 195 EIC7700_PIN(72, "gpio34", [0] = F_RESET, [1] = F_SDIO, [2] = F_GPIO), 196 EIC7700_PIN(73, "rgmii1_rxclk", [0] = F_RGMII), 197 EIC7700_PIN(74, "rgmii1_rxdv", [0] = F_RGMII), 198 EIC7700_PIN(75, "rgmii1_rxd0", [0] = F_RGMII), 199 EIC7700_PIN(76, "rgmii1_rxd1", [0] = F_RGMII), 200 EIC7700_PIN(77, "rgmii1_rxd2", [0] = F_RGMII), 201 EIC7700_PIN(78, "rgmii1_rxd3", [0] = F_RGMII), 202 EIC7700_PIN(79, "spi1_cs0_n", [0] = F_SPI, [2] = F_GPIO), 203 EIC7700_PIN(80, "spi1_clk", [0] = F_SPI, [2] = F_GPIO), 204 EIC7700_PIN(81, "spi1_d0", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART), 205 EIC7700_PIN(82, "spi1_d1", [0] = F_SPI, [1] = F_I2C, [2] = F_GPIO, [3] = F_UART), 206 EIC7700_PIN(83, "spi1_d2", [0] = F_SPI, [1] = F_SDIO, [2] = F_GPIO), 207 EIC7700_PIN(84, "spi1_d3", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO), 208 EIC7700_PIN(85, "spi1_cs1_n", [0] = F_SPI, [1] = F_PWM, [2] = F_GPIO), 209 EIC7700_PIN(86, "rgmii1_mdc", [0] = F_RGMII), 210 EIC7700_PIN(87, "rgmii1_mdio", [0] = F_RGMII), 211 EIC7700_PIN(88, "rgmii1_intb", [0] = F_RGMII), 212 EIC7700_PIN(89, "usb0_pwren", [0] = F_USB, [2] = F_GPIO), 213 EIC7700_PIN(90, "usb1_pwren", [0] = F_USB, [2] = F_GPIO), 214 EIC7700_PIN(91, "i2c0_scl", [0] = F_I2C, [2] = F_GPIO), 215 EIC7700_PIN(92, "i2c0_sda", [0] = F_I2C, [2] = F_GPIO), 216 EIC7700_PIN(93, "i2c1_scl", [0] = F_I2C, [2] = F_GPIO), 217 EIC7700_PIN(94, "i2c1_sda", [0] = F_I2C, [2] = F_GPIO), 218 EIC7700_PIN(95, "i2c2_scl", [0] = F_I2C, [2] = F_GPIO), 219 EIC7700_PIN(96, "i2c2_sda", [0] = F_I2C, [2] = F_GPIO), 220 EIC7700_PIN(97, "i2c3_scl", [0] = F_I2C, [2] = F_GPIO), 221 EIC7700_PIN(98, "i2c3_sda", [0] = F_I2C, [2] = F_GPIO), 222 EIC7700_PIN(99, "i2c4_scl", [0] = F_I2C, [2] = F_GPIO), 223 EIC7700_PIN(100, "i2c4_sda", [0] = F_I2C, [2] = F_GPIO), 224 EIC7700_PIN(101, "i2c5_scl", [0] = F_I2C, [2] = F_GPIO), 225 EIC7700_PIN(102, "i2c5_sda", [0] = F_I2C, [2] = F_GPIO), 226 EIC7700_PIN(103, "uart0_tx", [0] = F_UART, [2] = F_GPIO), 227 EIC7700_PIN(104, "uart0_rx", [0] = F_UART, [2] = F_GPIO), 228 EIC7700_PIN(105, "uart1_tx", [0] = F_UART, [2] = F_GPIO), 229 EIC7700_PIN(106, "uart1_rx", [0] = F_UART, [2] = F_GPIO), 230 EIC7700_PIN(107, "uart1_cts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO), 231 EIC7700_PIN(108, "uart1_rts", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO), 232 EIC7700_PIN(109, "uart2_tx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO), 233 EIC7700_PIN(110, "uart2_rx", [0] = F_UART, [1] = F_I2C, [2] = F_GPIO), 234 EIC7700_PIN(111, "jtag2_tck", [0] = F_JTAG, [2] = F_GPIO), 235 EIC7700_PIN(112, "jtag2_tms", [0] = F_JTAG, [2] = F_GPIO), 236 EIC7700_PIN(113, "jtag2_tdi", [0] = F_JTAG, [2] = F_GPIO), 237 EIC7700_PIN(114, "jtag2_tdo", [0] = F_JTAG, [2] = F_GPIO), 238 EIC7700_PIN(115, "fan_pwm", [0] = F_PWM, [2] = F_GPIO), 239 EIC7700_PIN(116, "fan_tach", [0] = F_FAN_TACH, [2] = F_GPIO), 240 EIC7700_PIN(117, "mipi_csi0_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 241 EIC7700_PIN(118, "mipi_csi0_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 242 EIC7700_PIN(119, "mipi_csi0_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 243 EIC7700_PIN(120, "mipi_csi1_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 244 EIC7700_PIN(121, "mipi_csi1_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 245 EIC7700_PIN(122, "mipi_csi1_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 246 EIC7700_PIN(123, "mipi_csi2_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 247 EIC7700_PIN(124, "mipi_csi2_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 248 EIC7700_PIN(125, "mipi_csi2_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 249 EIC7700_PIN(126, "mipi_csi3_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 250 EIC7700_PIN(127, "mipi_csi3_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 251 EIC7700_PIN(128, "mipi_csi3_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 252 EIC7700_PIN(129, "mipi_csi4_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 253 EIC7700_PIN(130, "mipi_csi4_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 254 EIC7700_PIN(131, "mipi_csi4_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 255 EIC7700_PIN(132, "mipi_csi5_xvs", [0] = F_MIPI_CSI, [2] = F_GPIO), 256 EIC7700_PIN(133, "mipi_csi5_xhs", [0] = F_MIPI_CSI, [2] = F_GPIO), 257 EIC7700_PIN(134, "mipi_csi5_mclk", [0] = F_MIPI_CSI, [2] = F_GPIO), 258 EIC7700_PIN(135, "spi3_cs_n", [0] = F_SPI, [2] = F_GPIO), 259 EIC7700_PIN(136, "spi3_clk", [0] = F_SPI, [2] = F_GPIO), 260 EIC7700_PIN(137, "spi3_di", [0] = F_SPI, [2] = F_GPIO), 261 EIC7700_PIN(138, "spi3_do", [0] = F_SPI, [2] = F_GPIO), 262 EIC7700_PIN(139, "gpio92", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART), 263 EIC7700_PIN(140, "gpio93", [0] = F_I2C, [1] = F_MIPI_CSI, [2] = F_GPIO, [3] = F_UART), 264 EIC7700_PIN(141, "s_mode", [0] = F_S_MODE, [2] = F_GPIO), 265 EIC7700_PIN(142, "gpio95", [0] = F_DDR_REF_CLK_SEL, [2] = F_GPIO), 266 EIC7700_PIN(143, "spi0_cs_n", [0] = F_SPI, [2] = F_GPIO), 267 EIC7700_PIN(144, "spi0_clk", [0] = F_SPI, [2] = F_GPIO), 268 EIC7700_PIN(145, "spi0_d0", [0] = F_SPI, [2] = F_GPIO), 269 EIC7700_PIN(146, "spi0_d1", [0] = F_SPI, [2] = F_GPIO), 270 EIC7700_PIN(147, "spi0_d2", [0] = F_SPI, [2] = F_GPIO), 271 EIC7700_PIN(148, "spi0_d3", [0] = F_SPI, [2] = F_GPIO), 272 EIC7700_PIN(149, "i2c10_scl", [0] = F_I2C, [2] = F_GPIO), 273 EIC7700_PIN(150, "i2c10_sda", [0] = F_I2C, [2] = F_GPIO), 274 EIC7700_PIN(151, "i2c11_scl", [0] = F_I2C, [2] = F_GPIO), 275 EIC7700_PIN(152, "i2c11_sda", [0] = F_I2C, [2] = F_GPIO), 276 EIC7700_PIN(153, "gpio106", [0] = F_GPIO), 277 EIC7700_PIN(154, "boot_sel0", [0] = F_BOOT_SEL, [2] = F_GPIO), 278 EIC7700_PIN(155, "boot_sel1", [0] = F_BOOT_SEL, [2] = F_GPIO), 279 EIC7700_PIN(156, "boot_sel2", [0] = F_BOOT_SEL, [2] = F_GPIO), 280 EIC7700_PIN(157, "boot_sel3", [0] = F_BOOT_SEL, [2] = F_GPIO), 281 EIC7700_PIN(158, "gpio111", [0] = F_GPIO), 282 EIC7700_PIN(159, "reserved0", [0] = F_DISABLED), 283 EIC7700_PIN(160, "reserved1", [0] = F_DISABLED), 284 EIC7700_PIN(161, "reserved2", [0] = F_DISABLED), 285 EIC7700_PIN(162, "reserved3", [0] = F_DISABLED), 286 EIC7700_PIN(163, "lpddr_ref_clk", [0] = F_LPDDR_REF_CLK), 287}; 288 289static int eic7700_get_groups_count(struct pinctrl_dev *pctldev) 290{ 291 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 292 293 return pc->desc.npins; 294} 295 296static const char *eic7700_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) 297{ 298 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 299 300 return pc->desc.pins[selector].name; 301} 302 303static int eic7700_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, 304 const unsigned int **pins, unsigned int *npins) 305{ 306 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 307 308 *pins = &pc->desc.pins[selector].number; 309 *npins = 1; 310 311 return 0; 312} 313 314static const struct pinctrl_ops eic7700_pinctrl_ops = { 315 .get_groups_count = eic7700_get_groups_count, 316 .get_group_name = eic7700_get_group_name, 317 .get_group_pins = eic7700_get_group_pins, 318#ifdef CONFIG_OF 319 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 320 .dt_free_map = pinconf_generic_dt_free_map, 321#endif 322}; 323 324static int eic7700_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 325 unsigned long *config) 326{ 327 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 328 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data; 329 u32 arg, value; 330 int param; 331 332 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED) 333 return -EOPNOTSUPP; 334 335 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin)); 336 337 param = pinconf_to_config_param(*config); 338 switch (param) { 339 case PIN_CONFIG_BIAS_DISABLE: 340 arg = (value & EIC7700_BIAS) == 0; 341 break; 342 case PIN_CONFIG_BIAS_PULL_DOWN: 343 arg = (value & EIC7700_BIAS) == EIC7700_PD; 344 break; 345 case PIN_CONFIG_BIAS_PULL_UP: 346 arg = (value & EIC7700_BIAS) == EIC7700_PU; 347 break; 348 case PIN_CONFIG_DRIVE_STRENGTH_UA: 349 if (pin_data->functions[0] == F_RGMII || 350 pin_data->functions[0] == F_LPDDR_REF_CLK) 351 arg = FIELD_GET(EIC7700_DS, value) * 3000 + 3000; 352 else 353 arg = FIELD_GET(EIC7700_DS, value) * 3000 + 6000; 354 break; 355 case PIN_CONFIG_INPUT_ENABLE: 356 arg = value & EIC7700_IE; 357 break; 358 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 359 arg = value & EIC7700_ST; 360 break; 361 default: 362 return -EOPNOTSUPP; 363 } 364 365 *config = pinconf_to_config_packed(param, arg); 366 return arg ? 0 : -EINVAL; 367} 368 369static int eic7700_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 370 unsigned long *configs, unsigned int num_configs) 371{ 372 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 373 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data; 374 u32 value; 375 376 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED) 377 return -EOPNOTSUPP; 378 379 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin)); 380 381 for (unsigned int i = 0; i < num_configs; i++) { 382 int param = pinconf_to_config_param(configs[i]); 383 u32 arg = pinconf_to_config_argument(configs[i]); 384 385 switch (param) { 386 case PIN_CONFIG_BIAS_DISABLE: 387 value &= ~EIC7700_BIAS; 388 break; 389 case PIN_CONFIG_BIAS_PULL_DOWN: 390 if (arg == 0) 391 return -EOPNOTSUPP; 392 value &= ~EIC7700_BIAS; 393 value |= EIC7700_PD; 394 break; 395 case PIN_CONFIG_BIAS_PULL_UP: 396 if (arg == 0) 397 return -EOPNOTSUPP; 398 value &= ~EIC7700_BIAS; 399 value |= EIC7700_PU; 400 break; 401 case PIN_CONFIG_DRIVE_STRENGTH_UA: 402 value &= ~EIC7700_DS; 403 if (pin_data->functions[0] == F_RGMII || 404 pin_data->functions[0] == F_LPDDR_REF_CLK) { 405 if (arg < 3000 || arg > 24000) 406 return -EOPNOTSUPP; 407 value |= FIELD_PREP(EIC7700_DS, (arg - 3000) / 3000); 408 } else { 409 if (arg < 6000 || arg > 27000) 410 return -EOPNOTSUPP; 411 value |= FIELD_PREP(EIC7700_DS, (arg - 6000) / 3000); 412 } 413 break; 414 case PIN_CONFIG_INPUT_ENABLE: 415 if (arg) 416 value |= EIC7700_IE; 417 else 418 value &= ~EIC7700_IE; 419 break; 420 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 421 if (arg) 422 value |= EIC7700_ST; 423 else 424 value &= ~EIC7700_ST; 425 break; 426 default: 427 return -EOPNOTSUPP; 428 } 429 } 430 431 writel_relaxed(value, pc->base + EIC7700_PIN_REG(pin)); 432 433 return 0; 434} 435 436#ifdef CONFIG_DEBUG_FS 437static void eic7700_pin_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 438 unsigned int pin) 439{ 440 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 441 u32 value = readl_relaxed(pc->base + EIC7700_PIN_REG(pin)) & EIC7700_PINCONF; 442 443 seq_printf(s, " [0x%02x]", value); 444} 445#else 446#define eic7700_pin_config_dbg_show NULL 447#endif 448 449static const struct pinconf_ops eic7700_pinconf_ops = { 450 .is_generic = true, 451 .pin_config_get = eic7700_pin_config_get, 452 .pin_config_set = eic7700_pin_config_set, 453 .pin_config_group_get = eic7700_pin_config_get, 454 .pin_config_group_set = eic7700_pin_config_set, 455 .pin_config_dbg_show = eic7700_pin_config_dbg_show, 456 .pin_config_group_dbg_show = eic7700_pin_config_dbg_show, 457}; 458 459static int eic7700_get_functions_count(struct pinctrl_dev *pctldev) 460{ 461 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 462 463 return pc->functions_count; 464} 465 466static const char *eic7700_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 467{ 468 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 469 470 return pc->functions[selector].name; 471} 472 473static int eic7700_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 474 const char *const **groups, unsigned int *num_groups) 475{ 476 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 477 478 *groups = pc->functions[selector].groups; 479 *num_groups = pc->functions[selector].ngroups; 480 481 return 0; 482} 483 484static int eic7700_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 485 unsigned int group_selector) 486{ 487 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 488 const struct eic7700_pin *pin_data = pc->desc.pins[group_selector].drv_data; 489 u32 fs, value; 490 491 if (pin_data->functions[0] == F_OSC || pin_data->functions[0] == F_DISABLED) 492 return -EOPNOTSUPP; 493 494 for (fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) 495 if (pin_data->functions[fs] == func_selector) 496 break; 497 498 if (fs == EIC7700_FUNCTIONS_PER_PIN) { 499 dev_err(pctldev->dev, "invalid mux %s for pin %s\n", 500 pc->functions[func_selector].name, 501 pc->desc.pins[group_selector].name); 502 return -EINVAL; 503 } 504 505 value = readl_relaxed(pc->base + EIC7700_PIN_REG(group_selector)); 506 value &= ~EIC7700_FUNC_SEL; 507 value |= FIELD_PREP(EIC7700_FUNC_SEL, fs); 508 writel_relaxed(value, pc->base + EIC7700_PIN_REG(group_selector)); 509 510 return 0; 511} 512 513static int eic7700_gpio_request_enable(struct pinctrl_dev *pctldev, 514 struct pinctrl_gpio_range *range, unsigned int offset) 515{ 516 return eic7700_set_mux(pctldev, F_GPIO, offset); 517} 518 519static void eic7700_gpio_disable_free(struct pinctrl_dev *pctldev, 520 struct pinctrl_gpio_range *range, unsigned int offset) 521{ 522 eic7700_set_mux(pctldev, F_DISABLED, offset); 523} 524 525static int eic7700_gpio_set_direction(struct pinctrl_dev *pctldev, 526 struct pinctrl_gpio_range *range, unsigned int offset, 527 bool input) 528{ 529 struct eic7700_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); 530 u32 value; 531 532 value = readl_relaxed(pc->base + EIC7700_PIN_REG(offset)); 533 if (input) 534 value |= EIC7700_IE; 535 else 536 value &= ~EIC7700_IE; 537 writel_relaxed(value, pc->base + EIC7700_PIN_REG(offset)); 538 539 return 0; 540} 541 542static const struct pinmux_ops eic7700_pinmux_ops = { 543 .get_functions_count = eic7700_get_functions_count, 544 .get_function_name = eic7700_get_function_name, 545 .get_function_groups = eic7700_get_function_groups, 546 .set_mux = eic7700_set_mux, 547 .gpio_request_enable = eic7700_gpio_request_enable, 548 .gpio_disable_free = eic7700_gpio_disable_free, 549 .gpio_set_direction = eic7700_gpio_set_direction, 550 .strict = true, 551}; 552 553static int eic7700_pinctrl_init_function_groups(struct device *dev, struct eic7700_pinctrl *pc, 554 const char *const *function_names) 555{ 556 unsigned int ngroups = 0; 557 const char **groups; 558 559 /* Count the number of groups for each function */ 560 for (unsigned int pin = 0; pin < pc->desc.npins; pin++) { 561 const struct eic7700_pin *pin_data = pc->desc.pins[pin].drv_data; 562 bool found_disabled = false; 563 564 for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) { 565 unsigned int selector = pin_data->functions[fs]; 566 struct pinfunction *function = &pc->functions[selector]; 567 568 /* Only count F_DISABLED once per pin */ 569 if (selector == F_DISABLED) { 570 if (found_disabled) 571 continue; 572 found_disabled = true; 573 } 574 575 function->ngroups++; 576 ngroups++; 577 } 578 } 579 580 groups = devm_kcalloc(dev, ngroups, sizeof(*groups), GFP_KERNEL); 581 if (!groups) 582 return -ENOMEM; 583 584 for (unsigned int selector = 0; selector < pc->functions_count; selector++) { 585 struct pinfunction *function = &pc->functions[selector]; 586 587 function->name = function_names[selector]; 588 function->groups = groups; 589 groups += function->ngroups; 590 591 /* Reset per-function ngroups for use as iterator below */ 592 function->ngroups = 0; 593 } 594 595 /* Fill in the group pointers for each function */ 596 for (unsigned int pin = 0; pin < pc->desc.npins; pin++) { 597 const struct pinctrl_pin_desc *desc = &pc->desc.pins[pin]; 598 const struct eic7700_pin *pin_data = desc->drv_data; 599 bool found_disabled = false; 600 601 for (unsigned int fs = 0; fs < EIC7700_FUNCTIONS_PER_PIN; fs++) { 602 unsigned int selector = pin_data->functions[fs]; 603 struct pinfunction *function = &pc->functions[selector]; 604 605 /* Only count F_DISABLED once per pin */ 606 if (selector == F_DISABLED) { 607 if (found_disabled) 608 continue; 609 found_disabled = true; 610 } 611 612 ((const char **)function->groups)[function->ngroups++] = desc->name; 613 } 614 } 615 616 return 0; 617} 618 619static int eic7700_pinctrl_probe(struct platform_device *pdev) 620{ 621 struct device *dev = &pdev->dev; 622 struct pinctrl_dev *pctldev; 623 struct eic7700_pinctrl *pc; 624 struct regulator *regulator; 625 u32 rgmii0_mode, rgmii1_mode; 626 int ret, voltage; 627 628 pc = devm_kzalloc(dev, struct_size(pc, functions, EIC7700_FUNCTIONS_COUNT), GFP_KERNEL); 629 if (!pc) 630 return -ENOMEM; 631 632 pc->base = devm_platform_ioremap_resource(pdev, 0); 633 if (IS_ERR(pc->base)) 634 return PTR_ERR(pc->base); 635 636 regulator = devm_regulator_get(dev, "vrgmii"); 637 if (IS_ERR(regulator)) { 638 return dev_err_probe(dev, PTR_ERR(regulator), 639 "failed to get vrgmii regulator\n"); 640 } 641 642 voltage = regulator_get_voltage(regulator); 643 if (voltage < 0) { 644 return dev_err_probe(&pdev->dev, voltage, 645 "Failed to get voltage from regulator\n"); 646 } 647 648 rgmii0_mode = readl_relaxed(pc->base + EIC7700_RGMII0_SEL_MODE); 649 rgmii1_mode = readl_relaxed(pc->base + EIC7700_RGMII1_SEL_MODE); 650 rgmii0_mode &= ~EIC7700_MS; 651 rgmii1_mode &= ~EIC7700_MS; 652 if (voltage == 1800000) { 653 rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8); 654 rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_1V8); 655 } else if (voltage == 3300000) { 656 rgmii0_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3); 657 rgmii1_mode |= FIELD_PREP(EIC7700_MS, EIC7700_MS_3V3); 658 } else { 659 return dev_err_probe(&pdev->dev, -EINVAL, 660 "Invalid voltage configuration, should be either 1.8V or 3.3V\n"); 661 } 662 663 writel_relaxed(rgmii0_mode, pc->base + EIC7700_RGMII0_SEL_MODE); 664 writel_relaxed(rgmii1_mode, pc->base + EIC7700_RGMII1_SEL_MODE); 665 666 pc->desc.name = dev_name(dev); 667 pc->desc.pins = eic7700_pins; 668 pc->desc.npins = ARRAY_SIZE(eic7700_pins); 669 pc->desc.pctlops = &eic7700_pinctrl_ops; 670 pc->desc.pmxops = &eic7700_pinmux_ops; 671 pc->desc.confops = &eic7700_pinconf_ops; 672 pc->desc.owner = THIS_MODULE; 673 674 pc->functions_count = EIC7700_FUNCTIONS_COUNT; 675 ret = eic7700_pinctrl_init_function_groups(dev, pc, eic7700_functions); 676 if (ret) 677 return ret; 678 679 ret = devm_pinctrl_register_and_init(dev, &pc->desc, pc, &pctldev); 680 if (ret) 681 return dev_err_probe(dev, ret, "could not register pinctrl driver\n"); 682 683 return pinctrl_enable(pctldev); 684} 685 686static const struct of_device_id eic7700_pinctrl_of_match[] = { 687 { .compatible = "eswin,eic7700-pinctrl" }, 688 { /* sentinel */ } 689}; 690MODULE_DEVICE_TABLE(of, eic7700_pinctrl_of_match); 691 692static struct platform_driver eic7700_pinctrl_driver = { 693 .probe = eic7700_pinctrl_probe, 694 .driver = { 695 .name = "pinctrl-eic7700", 696 .of_match_table = eic7700_pinctrl_of_match, 697 }, 698}; 699module_platform_driver(eic7700_pinctrl_driver); 700 701MODULE_DESCRIPTION("Pinctrl driver for the ESWIN EIC7700 SoC"); 702MODULE_AUTHOR("Samuel Holland <samuel.holland@sifive.com>"); 703MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>"); 704MODULE_LICENSE("GPL");
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