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pinctrl-cy8c95x0.c
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linux-6.19.14/drivers/pinctrl/pinctrl-cy8c95x0.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support 4 * 5 * Copyright (C) 2022 9elements GmbH 6 * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> 7 * Naresh Solanki <Naresh.Solanki@9elements.com> 8 */ 9 10#include <linux/acpi.h> 11#include <linux/bitmap.h> 12#include <linux/cleanup.h> 13#include <linux/dmi.h> 14#include <linux/gpio/driver.h> 15#include <linux/gpio/consumer.h> 16#include <linux/i2c.h> 17#include <linux/init.h> 18#include <linux/interrupt.h> 19#include <linux/mod_devicetable.h> 20#include <linux/module.h> 21#include <linux/property.h> 22#include <linux/regmap.h> 23#include <linux/regulator/consumer.h> 24#include <linux/seq_file.h> 25 26#include <linux/pinctrl/consumer.h> 27#include <linux/pinctrl/pinconf.h> 28#include <linux/pinctrl/pinconf-generic.h> 29#include <linux/pinctrl/pinctrl.h> 30#include <linux/pinctrl/pinmux.h> 31 32/* Fast access registers */ 33#define CY8C95X0_INPUT 0x00 34#define CY8C95X0_OUTPUT 0x08 35#define CY8C95X0_INTSTATUS 0x10 36 37#define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) 38#define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) 39#define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) 40 41/* Port Select configures the port */ 42#define CY8C95X0_PORTSEL 0x18 43 44/* Port settings, write PORTSEL first */ 45#define CY8C95X0_INTMASK 0x19 46#define CY8C95X0_SELPWM 0x1A 47#define CY8C95X0_INVERT 0x1B 48#define CY8C95X0_DIRECTION 0x1C 49/* Drive mode register change state on writing '1' */ 50#define CY8C95X0_DRV_PU 0x1D 51#define CY8C95X0_DRV_PD 0x1E 52#define CY8C95X0_DRV_ODH 0x1F 53#define CY8C95X0_DRV_ODL 0x20 54#define CY8C95X0_DRV_PP_FAST 0x21 55#define CY8C95X0_DRV_PP_SLOW 0x22 56#define CY8C95X0_DRV_HIZ 0x23 57 58/* Internal device configuration */ 59#define CY8C95X0_ENABLE_WDE 0x2D 60#define CY8C95X0_DEVID 0x2E 61#define CY8C95X0_WATCHDOG 0x2F 62#define CY8C95X0_COMMAND 0x30 63 64#define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) 65 66#define MAX_BANK 8 67#define BANK_SZ 8 68#define MAX_LINE (MAX_BANK * BANK_SZ) 69#define MUXED_STRIDE 16 70#define CY8C95X0_GPIO_MASK GENMASK(7, 0) 71#define CY8C95X0_VIRTUAL 0x40 72#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ 73 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE) 74 75static const struct i2c_device_id cy8c95x0_id[] = { 76 { "cy8c9520", 20, }, 77 { "cy8c9540", 40, }, 78 { "cy8c9560", 60, }, 79 { } 80}; 81MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); 82 83#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) 84 85static const struct of_device_id cy8c95x0_dt_ids[] = { 86 { .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), }, 87 { .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), }, 88 { .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), }, 89 { } 90}; 91MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); 92 93static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; 94 95static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { 96 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 97 { } 98}; 99 100static int cy8c95x0_acpi_get_irq(struct device *dev) 101{ 102 int ret; 103 104 ret = devm_acpi_dev_add_driver_gpios(dev, cy8c95x0_acpi_irq_gpios); 105 if (ret) 106 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 107 108 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 109 if (ret < 0) 110 return ret; 111 112 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 113 return ret; 114} 115 116static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { 117 { 118 /* 119 * On Intel Galileo Gen 1 board the IRQ pin is provided 120 * as an absolute number instead of being relative. 121 * Since first controller (gpio-sch.c) and second 122 * (gpio-dwapb.c) are at the fixed bases, we may safely 123 * refer to the number in the global space to get an IRQ 124 * out of it. 125 */ 126 .matches = { 127 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 128 }, 129 }, 130 {} 131}; 132 133/** 134 * struct cy8c95x0_pinctrl - driver data 135 * @regmap: Device's regmap. Only direct access registers. 136 * @irq_lock: IRQ bus lock 137 * @i2c_lock: Mutex to hold while using the regmap 138 * @irq_mask: I/O bits affected by interrupts 139 * @irq_trig_raise: I/O bits affected by raising voltage level 140 * @irq_trig_fall: I/O bits affected by falling voltage level 141 * @irq_trig_low: I/O bits affected by a low voltage level 142 * @irq_trig_high: I/O bits affected by a high voltage level 143 * @push_pull: I/O bits configured as push pull driver 144 * @map: Mask used to compensate for Gport2 width 145 * @nport: Number of Gports in this chip 146 * @gpio_chip: gpiolib chip 147 * @driver_data: private driver data 148 * @dev: struct device 149 * @pctldev: pin controller device 150 * @pinctrl_desc: pin controller description 151 * @name: Chip controller name 152 * @tpin: Total number of pins 153 * @gpio_reset: GPIO line handler that can reset the IC 154 */ 155struct cy8c95x0_pinctrl { 156 struct regmap *regmap; 157 struct mutex irq_lock; 158 struct mutex i2c_lock; 159 DECLARE_BITMAP(irq_mask, MAX_LINE); 160 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 161 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 162 DECLARE_BITMAP(irq_trig_low, MAX_LINE); 163 DECLARE_BITMAP(irq_trig_high, MAX_LINE); 164 DECLARE_BITMAP(push_pull, MAX_LINE); 165 DECLARE_BITMAP(map, MAX_LINE); 166 unsigned int nport; 167 struct gpio_chip gpio_chip; 168 unsigned long driver_data; 169 struct device *dev; 170 struct pinctrl_dev *pctldev; 171 struct pinctrl_desc pinctrl_desc; 172 char name[32]; 173 unsigned int tpin; 174 struct gpio_desc *gpio_reset; 175}; 176 177static const struct pinctrl_pin_desc cy8c9560_pins[] = { 178 PINCTRL_PIN(0, "gp00"), 179 PINCTRL_PIN(1, "gp01"), 180 PINCTRL_PIN(2, "gp02"), 181 PINCTRL_PIN(3, "gp03"), 182 PINCTRL_PIN(4, "gp04"), 183 PINCTRL_PIN(5, "gp05"), 184 PINCTRL_PIN(6, "gp06"), 185 PINCTRL_PIN(7, "gp07"), 186 187 PINCTRL_PIN(8, "gp10"), 188 PINCTRL_PIN(9, "gp11"), 189 PINCTRL_PIN(10, "gp12"), 190 PINCTRL_PIN(11, "gp13"), 191 PINCTRL_PIN(12, "gp14"), 192 PINCTRL_PIN(13, "gp15"), 193 PINCTRL_PIN(14, "gp16"), 194 PINCTRL_PIN(15, "gp17"), 195 196 PINCTRL_PIN(16, "gp20"), 197 PINCTRL_PIN(17, "gp21"), 198 PINCTRL_PIN(18, "gp22"), 199 PINCTRL_PIN(19, "gp23"), 200 201 PINCTRL_PIN(20, "gp30"), 202 PINCTRL_PIN(21, "gp31"), 203 PINCTRL_PIN(22, "gp32"), 204 PINCTRL_PIN(23, "gp33"), 205 PINCTRL_PIN(24, "gp34"), 206 PINCTRL_PIN(25, "gp35"), 207 PINCTRL_PIN(26, "gp36"), 208 PINCTRL_PIN(27, "gp37"), 209 210 PINCTRL_PIN(28, "gp40"), 211 PINCTRL_PIN(29, "gp41"), 212 PINCTRL_PIN(30, "gp42"), 213 PINCTRL_PIN(31, "gp43"), 214 PINCTRL_PIN(32, "gp44"), 215 PINCTRL_PIN(33, "gp45"), 216 PINCTRL_PIN(34, "gp46"), 217 PINCTRL_PIN(35, "gp47"), 218 219 PINCTRL_PIN(36, "gp50"), 220 PINCTRL_PIN(37, "gp51"), 221 PINCTRL_PIN(38, "gp52"), 222 PINCTRL_PIN(39, "gp53"), 223 PINCTRL_PIN(40, "gp54"), 224 PINCTRL_PIN(41, "gp55"), 225 PINCTRL_PIN(42, "gp56"), 226 PINCTRL_PIN(43, "gp57"), 227 228 PINCTRL_PIN(44, "gp60"), 229 PINCTRL_PIN(45, "gp61"), 230 PINCTRL_PIN(46, "gp62"), 231 PINCTRL_PIN(47, "gp63"), 232 PINCTRL_PIN(48, "gp64"), 233 PINCTRL_PIN(49, "gp65"), 234 PINCTRL_PIN(50, "gp66"), 235 PINCTRL_PIN(51, "gp67"), 236 237 PINCTRL_PIN(52, "gp70"), 238 PINCTRL_PIN(53, "gp71"), 239 PINCTRL_PIN(54, "gp72"), 240 PINCTRL_PIN(55, "gp73"), 241 PINCTRL_PIN(56, "gp74"), 242 PINCTRL_PIN(57, "gp75"), 243 PINCTRL_PIN(58, "gp76"), 244 PINCTRL_PIN(59, "gp77"), 245}; 246 247static const char * const cy8c95x0_groups[] = { 248 "gp00", 249 "gp01", 250 "gp02", 251 "gp03", 252 "gp04", 253 "gp05", 254 "gp06", 255 "gp07", 256 257 "gp10", 258 "gp11", 259 "gp12", 260 "gp13", 261 "gp14", 262 "gp15", 263 "gp16", 264 "gp17", 265 266 "gp20", 267 "gp21", 268 "gp22", 269 "gp23", 270 271 "gp30", 272 "gp31", 273 "gp32", 274 "gp33", 275 "gp34", 276 "gp35", 277 "gp36", 278 "gp37", 279 280 "gp40", 281 "gp41", 282 "gp42", 283 "gp43", 284 "gp44", 285 "gp45", 286 "gp46", 287 "gp47", 288 289 "gp50", 290 "gp51", 291 "gp52", 292 "gp53", 293 "gp54", 294 "gp55", 295 "gp56", 296 "gp57", 297 298 "gp60", 299 "gp61", 300 "gp62", 301 "gp63", 302 "gp64", 303 "gp65", 304 "gp66", 305 "gp67", 306 307 "gp70", 308 "gp71", 309 "gp72", 310 "gp73", 311 "gp74", 312 "gp75", 313 "gp76", 314 "gp77", 315}; 316 317static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) 318{ 319 /* Account for GPORT2 which only has 4 bits */ 320 return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; 321} 322 323static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) 324{ 325 /* Account for GPORT2 which only has 4 bits */ 326 return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); 327} 328 329static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) 330{ 331 /* 332 * Only 12 registers are present per port (see Table 6 in the datasheet). 333 */ 334 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 335 return false; 336 337 switch (reg) { 338 case 0x24 ... 0x27: 339 case 0x31 ... 0x3f: 340 return false; 341 default: 342 return true; 343 } 344} 345 346static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) 347{ 348 /* 349 * Only 12 registers are present per port (see Table 6 in the datasheet). 350 */ 351 if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) >= 12) 352 return false; 353 354 switch (reg) { 355 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 356 return false; 357 case CY8C95X0_DEVID: 358 return false; 359 case 0x24 ... 0x27: 360 case 0x31 ... 0x3f: 361 return false; 362 default: 363 return true; 364 } 365} 366 367static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) 368{ 369 switch (reg) { 370 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 371 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 372 case CY8C95X0_INTMASK: 373 case CY8C95X0_SELPWM: 374 case CY8C95X0_INVERT: 375 case CY8C95X0_DIRECTION: 376 case CY8C95X0_DRV_PU: 377 case CY8C95X0_DRV_PD: 378 case CY8C95X0_DRV_ODH: 379 case CY8C95X0_DRV_ODL: 380 case CY8C95X0_DRV_PP_FAST: 381 case CY8C95X0_DRV_PP_SLOW: 382 case CY8C95X0_DRV_HIZ: 383 return true; 384 default: 385 return false; 386 } 387} 388 389static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) 390{ 391 switch (reg) { 392 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 393 return true; 394 default: 395 return false; 396 } 397} 398 399static bool cy8c95x0_muxed_register(unsigned int reg) 400{ 401 switch (reg) { 402 case CY8C95X0_INTMASK: 403 case CY8C95X0_SELPWM: 404 case CY8C95X0_INVERT: 405 case CY8C95X0_DIRECTION: 406 case CY8C95X0_DRV_PU: 407 case CY8C95X0_DRV_PD: 408 case CY8C95X0_DRV_ODH: 409 case CY8C95X0_DRV_ODL: 410 case CY8C95X0_DRV_PP_FAST: 411 case CY8C95X0_DRV_PP_SLOW: 412 case CY8C95X0_DRV_HIZ: 413 return true; 414 default: 415 return false; 416 } 417} 418 419static bool cy8c95x0_wc_register(unsigned int reg) 420{ 421 switch (reg) { 422 case CY8C95X0_DRV_PU: 423 case CY8C95X0_DRV_PD: 424 case CY8C95X0_DRV_ODH: 425 case CY8C95X0_DRV_ODL: 426 case CY8C95X0_DRV_PP_FAST: 427 case CY8C95X0_DRV_PP_SLOW: 428 case CY8C95X0_DRV_HIZ: 429 return true; 430 default: 431 return false; 432 } 433} 434 435static bool cy8c95x0_quick_path_register(unsigned int reg) 436{ 437 switch (reg) { 438 case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): 439 case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): 440 case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7): 441 return true; 442 default: 443 return false; 444 } 445} 446 447static const struct regmap_range_cfg cy8c95x0_ranges[] = { 448 { 449 .range_min = CY8C95X0_VIRTUAL, 450 .range_max = 0, /* Updated at runtime */ 451 .selector_reg = CY8C95X0_PORTSEL, 452 .selector_mask = 0x07, 453 .selector_shift = 0x0, 454 .window_start = CY8C95X0_PORTSEL, 455 .window_len = MUXED_STRIDE, 456 } 457}; 458 459static const struct regmap_config cy8c9520_i2c_regmap = { 460 .reg_bits = 8, 461 .val_bits = 8, 462 463 .readable_reg = cy8c95x0_readable_register, 464 .writeable_reg = cy8c95x0_writeable_register, 465 .volatile_reg = cy8c95x0_volatile_register, 466 .precious_reg = cy8c95x0_precious_register, 467 468 .cache_type = REGCACHE_MAPLE, 469 .ranges = NULL, /* Updated at runtime */ 470 .num_ranges = 1, 471 .max_register = 0, /* Updated at runtime */ 472 .num_reg_defaults_raw = 0, /* Updated at runtime */ 473 .use_single_read = true, /* Workaround for regcache bug */ 474#if IS_ENABLED(CONFIG_DEBUG_PINCTRL) 475 .disable_locking = false, 476#else 477 .disable_locking = true, 478#endif 479}; 480 481/* Caller should never modify PORTSEL directly */ 482static int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, 483 unsigned int reg, unsigned int port, 484 unsigned int mask, unsigned int val, 485 bool *change, bool async, bool force) 486{ 487 int ret, off, i; 488 489 /* Registers behind the PORTSEL mux have their own range in regmap */ 490 if (cy8c95x0_muxed_register(reg)) { 491 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 492 } else { 493 /* Quick path direct access registers honor the port argument */ 494 if (cy8c95x0_quick_path_register(reg)) 495 off = reg + port; 496 else 497 off = reg; 498 } 499 guard(mutex)(&chip->i2c_lock); 500 501 ret = regmap_update_bits_base(chip->regmap, off, mask, val, change, async, force); 502 if (ret < 0) 503 return ret; 504 505 /* 506 * Mimic what hardware does and update the cache when a WC bit is written. 507 * Allows to mark the registers as non-volatile and reduces I/O cycles. 508 */ 509 if (cy8c95x0_wc_register(reg) && (mask & val)) { 510 /* Writing a 1 clears set bits in the other drive mode registers */ 511 regcache_cache_only(chip->regmap, true); 512 for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) { 513 if (i == reg) 514 continue; 515 516 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); 517 regmap_clear_bits(chip->regmap, off, mask & val); 518 } 519 regcache_cache_only(chip->regmap, false); 520 } 521 522 return 0; 523} 524 525/** 526 * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache 527 * @chip: The pinctrl to work on 528 * @reg: The register to write to. Can be direct access or muxed register. 529 * MUST NOT be the PORTSEL register. 530 * @port: The port to be used for muxed registers or quick path direct access 531 * registers. Otherwise unused. 532 * @mask: Bitmask to change 533 * @val: New value for bitmask 534 * 535 * This function handles the register writes to the direct access registers and 536 * the muxed registers while caching all register accesses, internally handling 537 * the correct state of the PORTSEL register and protecting the access to muxed 538 * registers. 539 * The caller must only use this function to change registers behind the PORTSEL mux. 540 * 541 * Return: 0 for successful request, else a corresponding error value 542 */ 543static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 544 unsigned int port, unsigned int mask, unsigned int val) 545{ 546 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, true); 547} 548 549/** 550 * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache 551 * @chip: The pinctrl to work on 552 * @reg: The register to write to. Can be direct access or muxed register. 553 * MUST NOT be the PORTSEL register. 554 * @port: The port to be used for muxed registers or quick path direct access 555 * registers. Otherwise unused. 556 * @mask: Bitmask to change 557 * @val: New value for bitmask 558 * 559 * This function handles the register updates to the direct access registers and 560 * the muxed registers while caching all register accesses, internally handling 561 * the correct state of the PORTSEL register and protecting the access to muxed 562 * registers. 563 * The caller must only use this function to change registers behind the PORTSEL mux. 564 * 565 * Return: 0 for successful request, else a corresponding error value 566 */ 567static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 568 unsigned int port, unsigned int mask, unsigned int val) 569{ 570 return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, false, false); 571} 572 573/** 574 * cy8c95x0_regmap_read_bits() - reads a register using the regmap cache 575 * @chip: The pinctrl to work on 576 * @reg: The register to read from. Can be direct access or muxed register. 577 * @port: The port to be used for muxed registers or quick path direct access 578 * registers. Otherwise unused. 579 * @mask: Bitmask to apply 580 * @val: Value read from hardware or cache 581 * 582 * This function handles the register reads from the direct access registers and 583 * the muxed registers while caching all register accesses, internally handling 584 * the correct state of the PORTSEL register and protecting the access to muxed 585 * registers. 586 * The caller must only use this function to read registers behind the PORTSEL mux. 587 * 588 * Return: 0 for successful request, else a corresponding error value 589 */ 590static int cy8c95x0_regmap_read_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, 591 unsigned int port, unsigned int mask, unsigned int *val) 592{ 593 unsigned int off; 594 unsigned int tmp; 595 int ret; 596 597 /* Registers behind the PORTSEL mux have their own range in regmap */ 598 if (cy8c95x0_muxed_register(reg)) { 599 off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); 600 } else { 601 /* Quick path direct access registers honor the port argument */ 602 if (cy8c95x0_quick_path_register(reg)) 603 off = reg + port; 604 else 605 off = reg; 606 } 607 608 scoped_guard(mutex, &chip->i2c_lock) 609 ret = regmap_read(chip->regmap, off, &tmp); 610 if (ret) 611 return ret; 612 613 *val = tmp & mask; 614 return 0; 615} 616 617static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 618 unsigned long *val, unsigned long *mask) 619{ 620 DECLARE_BITMAP(tmask, MAX_LINE); 621 DECLARE_BITMAP(tval, MAX_LINE); 622 unsigned long bits, offset; 623 int write_val; 624 int ret; 625 626 /* Add the 4 bit gap of Gport2 */ 627 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); 628 bitmap_scatter(tval, val, chip->map, MAX_LINE); 629 630 for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) { 631 unsigned int i = offset / 8; 632 633 write_val = bitmap_get_value8(tval, offset); 634 635 ret = cy8c95x0_regmap_update_bits(chip, reg, i, bits, write_val); 636 if (ret < 0) { 637 dev_err(chip->dev, "failed writing register %d, port %u: err %d\n", reg, i, ret); 638 return ret; 639 } 640 } 641 642 return 0; 643} 644 645static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, 646 unsigned long *val, unsigned long *mask) 647{ 648 DECLARE_BITMAP(tmask, MAX_LINE); 649 DECLARE_BITMAP(tval, MAX_LINE); 650 unsigned long bits, offset; 651 unsigned int read_val; 652 int ret; 653 654 /* Add the 4 bit gap of Gport2 */ 655 bitmap_scatter(tmask, mask, chip->map, MAX_LINE); 656 bitmap_scatter(tval, val, chip->map, MAX_LINE); 657 658 for_each_set_clump8(offset, bits, tmask, chip->nport * BANK_SZ) { 659 unsigned int i = offset / 8; 660 661 ret = cy8c95x0_regmap_read_bits(chip, reg, i, bits, &read_val); 662 if (ret < 0) { 663 dev_err(chip->dev, "failed reading register %d, port %u: err %d\n", reg, i, ret); 664 return ret; 665 } 666 667 read_val |= bitmap_get_value8(tval, offset) & ~bits; 668 bitmap_set_value8(tval, read_val, offset); 669 } 670 671 /* Fill the 4 bit gap of Gport2 */ 672 bitmap_gather(val, tval, chip->map, MAX_LINE); 673 674 return 0; 675} 676 677static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, unsigned int pin, bool input) 678{ 679 u8 port = cypress_get_port(chip, pin); 680 u8 bit = cypress_get_pin_mask(chip, pin); 681 int ret; 682 683 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, input ? bit : 0); 684 if (ret) 685 return ret; 686 687 /* 688 * Disable driving the pin by forcing it to HighZ. Only setting 689 * the direction register isn't sufficient in Push-Pull mode. 690 */ 691 if (input && test_bit(pin, chip->push_pull)) { 692 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, bit, bit); 693 if (ret) 694 return ret; 695 696 __clear_bit(pin, chip->push_pull); 697 } 698 699 return 0; 700} 701 702static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 703{ 704 return pinctrl_gpio_direction_input(gc, off); 705} 706 707static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, 708 unsigned int off, int val) 709{ 710 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 711 u8 port = cypress_get_port(chip, off); 712 u8 bit = cypress_get_pin_mask(chip, off); 713 int ret; 714 715 /* Set output level */ 716 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0); 717 if (ret) 718 return ret; 719 720 return pinctrl_gpio_direction_output(gc, off); 721} 722 723static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) 724{ 725 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 726 u8 port = cypress_get_port(chip, off); 727 u8 bit = cypress_get_pin_mask(chip, off); 728 unsigned int reg_val; 729 int ret; 730 731 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_INPUT, port, bit, ®_val); 732 if (ret < 0) { 733 /* 734 * NOTE: 735 * Diagnostic already emitted; that's all we should 736 * do unless gpio_*_value_cansleep() calls become different 737 * from their nonsleeping siblings (and report faults). 738 */ 739 return 0; 740 } 741 742 return reg_val ? 1 : 0; 743} 744 745static int cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, 746 int val) 747{ 748 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 749 u8 port = cypress_get_port(chip, off); 750 u8 bit = cypress_get_pin_mask(chip, off); 751 752 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, 753 val ? bit : 0); 754} 755 756static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) 757{ 758 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 759 u8 port = cypress_get_port(chip, off); 760 u8 bit = cypress_get_pin_mask(chip, off); 761 unsigned int reg_val; 762 int ret; 763 764 ret = cy8c95x0_regmap_read_bits(chip, CY8C95X0_DIRECTION, port, bit, ®_val); 765 if (ret < 0) 766 return ret; 767 768 if (reg_val) 769 return GPIO_LINE_DIRECTION_IN; 770 771 return GPIO_LINE_DIRECTION_OUT; 772} 773 774static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, 775 unsigned int off, 776 unsigned long *config) 777{ 778 enum pin_config_param param = pinconf_to_config_param(*config); 779 u8 port = cypress_get_port(chip, off); 780 u8 bit = cypress_get_pin_mask(chip, off); 781 unsigned int reg_val; 782 unsigned int reg; 783 u16 arg = 0; 784 int ret; 785 786 switch (param) { 787 case PIN_CONFIG_BIAS_PULL_UP: 788 reg = CY8C95X0_DRV_PU; 789 break; 790 case PIN_CONFIG_BIAS_PULL_DOWN: 791 reg = CY8C95X0_DRV_PD; 792 break; 793 case PIN_CONFIG_BIAS_DISABLE: 794 reg = CY8C95X0_DRV_HIZ; 795 break; 796 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 797 reg = CY8C95X0_DRV_ODL; 798 break; 799 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 800 reg = CY8C95X0_DRV_ODH; 801 break; 802 case PIN_CONFIG_DRIVE_PUSH_PULL: 803 reg = CY8C95X0_DRV_PP_FAST; 804 break; 805 case PIN_CONFIG_INPUT_ENABLE: 806 reg = CY8C95X0_DIRECTION; 807 break; 808 case PIN_CONFIG_MODE_PWM: 809 reg = CY8C95X0_SELPWM; 810 break; 811 case PIN_CONFIG_LEVEL: 812 reg = CY8C95X0_OUTPUT; 813 break; 814 case PIN_CONFIG_OUTPUT_ENABLE: 815 reg = CY8C95X0_DIRECTION; 816 break; 817 818 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 819 case PIN_CONFIG_BIAS_BUS_HOLD: 820 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 821 case PIN_CONFIG_DRIVE_STRENGTH: 822 case PIN_CONFIG_DRIVE_STRENGTH_UA: 823 case PIN_CONFIG_INPUT_DEBOUNCE: 824 case PIN_CONFIG_INPUT_SCHMITT: 825 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 826 case PIN_CONFIG_MODE_LOW_POWER: 827 case PIN_CONFIG_PERSIST_STATE: 828 case PIN_CONFIG_POWER_SOURCE: 829 case PIN_CONFIG_SKEW_DELAY: 830 case PIN_CONFIG_SLEEP_HARDWARE_STATE: 831 case PIN_CONFIG_SLEW_RATE: 832 default: 833 return -ENOTSUPP; 834 } 835 /* 836 * Writing 1 to one of the drive mode registers will automatically 837 * clear conflicting set bits in the other drive mode registers. 838 */ 839 ret = cy8c95x0_regmap_read_bits(chip, reg, port, bit, ®_val); 840 if (ret < 0) 841 return ret; 842 843 if (reg_val) 844 arg = 1; 845 if (param == PIN_CONFIG_OUTPUT_ENABLE) 846 arg = !arg; 847 848 *config = pinconf_to_config_packed(param, arg); 849 return 0; 850} 851 852static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, 853 unsigned int off, 854 unsigned long config) 855{ 856 u8 port = cypress_get_port(chip, off); 857 u8 bit = cypress_get_pin_mask(chip, off); 858 unsigned long param = pinconf_to_config_param(config); 859 unsigned long arg = pinconf_to_config_argument(config); 860 unsigned int reg; 861 862 switch (param) { 863 case PIN_CONFIG_BIAS_PULL_UP: 864 __clear_bit(off, chip->push_pull); 865 reg = CY8C95X0_DRV_PU; 866 break; 867 case PIN_CONFIG_BIAS_PULL_DOWN: 868 __clear_bit(off, chip->push_pull); 869 reg = CY8C95X0_DRV_PD; 870 break; 871 case PIN_CONFIG_BIAS_DISABLE: 872 __clear_bit(off, chip->push_pull); 873 reg = CY8C95X0_DRV_HIZ; 874 break; 875 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 876 __clear_bit(off, chip->push_pull); 877 reg = CY8C95X0_DRV_ODL; 878 break; 879 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 880 __clear_bit(off, chip->push_pull); 881 reg = CY8C95X0_DRV_ODH; 882 break; 883 case PIN_CONFIG_DRIVE_PUSH_PULL: 884 __set_bit(off, chip->push_pull); 885 reg = CY8C95X0_DRV_PP_FAST; 886 break; 887 case PIN_CONFIG_MODE_PWM: 888 reg = CY8C95X0_SELPWM; 889 break; 890 case PIN_CONFIG_OUTPUT_ENABLE: 891 return cy8c95x0_pinmux_direction(chip, off, !arg); 892 case PIN_CONFIG_INPUT_ENABLE: 893 return cy8c95x0_pinmux_direction(chip, off, arg); 894 default: 895 return -ENOTSUPP; 896 } 897 /* 898 * Writing 1 to one of the drive mode registers will automatically 899 * clear conflicting set bits in the other drive mode registers. 900 */ 901 return cy8c95x0_regmap_write_bits(chip, reg, port, bit, bit); 902} 903 904static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, 905 unsigned long *mask, unsigned long *bits) 906{ 907 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 908 909 return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask); 910} 911 912static int cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, 913 unsigned long *mask, unsigned long *bits) 914{ 915 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 916 917 return cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask); 918} 919 920static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) 921{ 922 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 923 struct device *dev = chip->dev; 924 int ret; 925 926 ret = gpiochip_add_pin_range(gc, dev_name(dev), 0, 0, chip->tpin); 927 if (ret) 928 dev_err(dev, "failed to add GPIO pin range\n"); 929 930 return ret; 931} 932 933static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) 934{ 935 struct gpio_chip *gc = &chip->gpio_chip; 936 937 gc->request = gpiochip_generic_request; 938 gc->free = gpiochip_generic_free; 939 gc->direction_input = cy8c95x0_gpio_direction_input; 940 gc->direction_output = cy8c95x0_gpio_direction_output; 941 gc->get = cy8c95x0_gpio_get_value; 942 gc->set = cy8c95x0_gpio_set_value; 943 gc->get_direction = cy8c95x0_gpio_get_direction; 944 gc->get_multiple = cy8c95x0_gpio_get_multiple; 945 gc->set_multiple = cy8c95x0_gpio_set_multiple; 946 gc->set_config = gpiochip_generic_config; 947 gc->can_sleep = true; 948 gc->add_pin_ranges = cy8c95x0_add_pin_ranges; 949 950 gc->base = -1; 951 gc->ngpio = chip->tpin; 952 953 gc->parent = chip->dev; 954 gc->owner = THIS_MODULE; 955 gc->names = NULL; 956 957 gc->label = dev_name(chip->dev); 958 959 return devm_gpiochip_add_data(chip->dev, gc, chip); 960} 961 962static void cy8c95x0_irq_mask(struct irq_data *d) 963{ 964 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 965 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 966 irq_hw_number_t hwirq = irqd_to_hwirq(d); 967 968 set_bit(hwirq, chip->irq_mask); 969 gpiochip_disable_irq(gc, hwirq); 970} 971 972static void cy8c95x0_irq_unmask(struct irq_data *d) 973{ 974 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 975 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 976 irq_hw_number_t hwirq = irqd_to_hwirq(d); 977 978 gpiochip_enable_irq(gc, hwirq); 979 clear_bit(hwirq, chip->irq_mask); 980} 981 982static void cy8c95x0_irq_bus_lock(struct irq_data *d) 983{ 984 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 985 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 986 987 mutex_lock(&chip->irq_lock); 988} 989 990static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) 991{ 992 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 993 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 994 DECLARE_BITMAP(ones, MAX_LINE); 995 DECLARE_BITMAP(irq_mask, MAX_LINE); 996 DECLARE_BITMAP(reg_direction, MAX_LINE); 997 998 bitmap_fill(ones, MAX_LINE); 999 1000 cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, chip->irq_mask, ones); 1001 1002 /* Switch direction to input if needed */ 1003 cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, reg_direction, chip->irq_mask); 1004 bitmap_or(irq_mask, chip->irq_mask, reg_direction, MAX_LINE); 1005 bitmap_complement(irq_mask, irq_mask, MAX_LINE); 1006 1007 /* Look for any newly setup interrupt */ 1008 cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, ones, irq_mask); 1009 1010 mutex_unlock(&chip->irq_lock); 1011} 1012 1013static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) 1014{ 1015 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1016 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1017 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1018 unsigned int trig_type; 1019 1020 switch (type) { 1021 case IRQ_TYPE_EDGE_RISING: 1022 case IRQ_TYPE_EDGE_FALLING: 1023 case IRQ_TYPE_EDGE_BOTH: 1024 trig_type = type; 1025 break; 1026 case IRQ_TYPE_LEVEL_HIGH: 1027 trig_type = IRQ_TYPE_EDGE_RISING; 1028 break; 1029 case IRQ_TYPE_LEVEL_LOW: 1030 trig_type = IRQ_TYPE_EDGE_FALLING; 1031 break; 1032 default: 1033 dev_err(chip->dev, "irq %d: unsupported type %d\n", d->irq, type); 1034 return -EINVAL; 1035 } 1036 1037 assign_bit(hwirq, chip->irq_trig_fall, trig_type & IRQ_TYPE_EDGE_FALLING); 1038 assign_bit(hwirq, chip->irq_trig_raise, trig_type & IRQ_TYPE_EDGE_RISING); 1039 assign_bit(hwirq, chip->irq_trig_low, type == IRQ_TYPE_LEVEL_LOW); 1040 assign_bit(hwirq, chip->irq_trig_high, type == IRQ_TYPE_LEVEL_HIGH); 1041 1042 return 0; 1043} 1044 1045static void cy8c95x0_irq_shutdown(struct irq_data *d) 1046{ 1047 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1048 struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); 1049 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1050 1051 clear_bit(hwirq, chip->irq_trig_raise); 1052 clear_bit(hwirq, chip->irq_trig_fall); 1053 clear_bit(hwirq, chip->irq_trig_low); 1054 clear_bit(hwirq, chip->irq_trig_high); 1055} 1056 1057static const struct irq_chip cy8c95x0_irqchip = { 1058 .name = "cy8c95x0-irq", 1059 .irq_mask = cy8c95x0_irq_mask, 1060 .irq_unmask = cy8c95x0_irq_unmask, 1061 .irq_bus_lock = cy8c95x0_irq_bus_lock, 1062 .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, 1063 .irq_set_type = cy8c95x0_irq_set_type, 1064 .irq_shutdown = cy8c95x0_irq_shutdown, 1065 .flags = IRQCHIP_IMMUTABLE, 1066 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1067}; 1068 1069static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) 1070{ 1071 DECLARE_BITMAP(ones, MAX_LINE); 1072 DECLARE_BITMAP(cur_stat, MAX_LINE); 1073 DECLARE_BITMAP(new_stat, MAX_LINE); 1074 DECLARE_BITMAP(trigger, MAX_LINE); 1075 1076 bitmap_fill(ones, MAX_LINE); 1077 1078 /* Read the current interrupt status from the device */ 1079 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, trigger, ones)) 1080 return false; 1081 1082 /* Check latched inputs */ 1083 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, cur_stat, trigger)) 1084 return false; 1085 1086 /* Apply filter for rising/falling edge selection */ 1087 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 1088 cur_stat, MAX_LINE); 1089 1090 bitmap_and(pending, new_stat, trigger, MAX_LINE); 1091 1092 return !bitmap_empty(pending, MAX_LINE); 1093} 1094 1095static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) 1096{ 1097 struct cy8c95x0_pinctrl *chip = devid; 1098 struct gpio_chip *gc = &chip->gpio_chip; 1099 DECLARE_BITMAP(pending, MAX_LINE); 1100 int nested_irq, level; 1101 bool ret; 1102 1103 ret = cy8c95x0_irq_pending(chip, pending); 1104 if (!ret) 1105 return IRQ_RETVAL(0); 1106 1107 ret = false; 1108 for_each_set_bit(level, pending, MAX_LINE) { 1109 /* Already accounted for 4bit gap in GPort2 */ 1110 nested_irq = irq_find_mapping(gc->irq.domain, level); 1111 1112 if (unlikely(nested_irq <= 0)) { 1113 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1114 continue; 1115 } 1116 1117 if (test_bit(level, chip->irq_trig_low)) 1118 while (!cy8c95x0_gpio_get_value(gc, level)) 1119 handle_nested_irq(nested_irq); 1120 else if (test_bit(level, chip->irq_trig_high)) 1121 while (cy8c95x0_gpio_get_value(gc, level)) 1122 handle_nested_irq(nested_irq); 1123 else 1124 handle_nested_irq(nested_irq); 1125 1126 ret = true; 1127 } 1128 1129 return IRQ_RETVAL(ret); 1130} 1131 1132static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1133{ 1134 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1135 1136 return chip->tpin; 1137} 1138 1139static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 1140 unsigned int group) 1141{ 1142 return cy8c95x0_groups[group]; 1143} 1144 1145static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 1146 unsigned int group, 1147 const unsigned int **pins, 1148 unsigned int *num_pins) 1149{ 1150 *pins = &cy8c9560_pins[group].number; 1151 *num_pins = 1; 1152 return 0; 1153} 1154 1155static const char *cy8c95x0_get_fname(unsigned int selector) 1156{ 1157 if (selector == 0) 1158 return "gpio"; 1159 else 1160 return "pwm"; 1161} 1162 1163static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1164 unsigned int pin) 1165{ 1166 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1167 DECLARE_BITMAP(mask, MAX_LINE); 1168 DECLARE_BITMAP(pwm, MAX_LINE); 1169 1170 bitmap_zero(mask, MAX_LINE); 1171 __set_bit(pin, mask); 1172 1173 if (cy8c95x0_read_regs_mask(chip, CY8C95X0_SELPWM, pwm, mask)) { 1174 seq_puts(s, "not available"); 1175 return; 1176 } 1177 1178 seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm))); 1179} 1180 1181static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { 1182 .get_groups_count = cy8c95x0_pinctrl_get_groups_count, 1183 .get_group_name = cy8c95x0_pinctrl_get_group_name, 1184 .get_group_pins = cy8c95x0_pinctrl_get_group_pins, 1185#ifdef CONFIG_OF 1186 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1187 .dt_free_map = pinconf_generic_dt_free_map, 1188#endif 1189 .pin_dbg_show = cy8c95x0_pin_dbg_show, 1190}; 1191 1192static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) 1193{ 1194 return cy8c95x0_get_fname(selector); 1195} 1196 1197static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) 1198{ 1199 return 2; 1200} 1201 1202static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, 1203 const char * const **groups, 1204 unsigned int * const num_groups) 1205{ 1206 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1207 1208 *groups = cy8c95x0_groups; 1209 *num_groups = chip->tpin; 1210 return 0; 1211} 1212 1213static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) 1214{ 1215 u8 port = cypress_get_port(chip, off); 1216 u8 bit = cypress_get_pin_mask(chip, off); 1217 1218 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_SELPWM, port, bit, mode ? bit : 0); 1219} 1220 1221static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, 1222 unsigned int selector, unsigned int group) 1223{ 1224 u8 port = cypress_get_port(chip, group); 1225 u8 bit = cypress_get_pin_mask(chip, group); 1226 int ret; 1227 1228 ret = cy8c95x0_set_mode(chip, group, selector); 1229 if (ret < 0) 1230 return ret; 1231 1232 if (selector == 0) 1233 return 0; 1234 1235 /* Set direction to output & set output to 1 so that PWM can work */ 1236 ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, bit, bit); 1237 if (ret < 0) 1238 return ret; 1239 1240 return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, bit); 1241} 1242 1243static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 1244 unsigned int group) 1245{ 1246 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1247 1248 return cy8c95x0_pinmux_mode(chip, selector, group); 1249} 1250 1251static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, 1252 struct pinctrl_gpio_range *range, 1253 unsigned int pin) 1254{ 1255 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1256 1257 return cy8c95x0_set_mode(chip, pin, false); 1258} 1259 1260static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, 1261 struct pinctrl_gpio_range *range, 1262 unsigned int pin, bool input) 1263{ 1264 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1265 1266 return cy8c95x0_pinmux_direction(chip, pin, input); 1267} 1268 1269static const struct pinmux_ops cy8c95x0_pmxops = { 1270 .get_functions_count = cy8c95x0_get_functions_count, 1271 .get_function_name = cy8c95x0_get_function_name, 1272 .get_function_groups = cy8c95x0_get_function_groups, 1273 .set_mux = cy8c95x0_set_mux, 1274 .gpio_request_enable = cy8c95x0_gpio_request_enable, 1275 .gpio_set_direction = cy8c95x0_gpio_set_direction, 1276 .strict = true, 1277}; 1278 1279static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 1280 unsigned long *config) 1281{ 1282 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1283 1284 return cy8c95x0_gpio_get_pincfg(chip, pin, config); 1285} 1286 1287static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 1288 unsigned long *configs, unsigned int num_configs) 1289{ 1290 struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); 1291 int ret; 1292 int i; 1293 1294 for (i = 0; i < num_configs; i++) { 1295 ret = cy8c95x0_gpio_set_pincfg(chip, pin, configs[i]); 1296 if (ret) 1297 return ret; 1298 } 1299 1300 return 0; 1301} 1302 1303static const struct pinconf_ops cy8c95x0_pinconf_ops = { 1304 .pin_config_get = cy8c95x0_pinconf_get, 1305 .pin_config_set = cy8c95x0_pinconf_set, 1306 .is_generic = true, 1307}; 1308 1309static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) 1310{ 1311 struct gpio_irq_chip *girq = &chip->gpio_chip.irq; 1312 DECLARE_BITMAP(pending_irqs, MAX_LINE); 1313 int ret; 1314 1315 mutex_init(&chip->irq_lock); 1316 1317 bitmap_zero(pending_irqs, MAX_LINE); 1318 1319 /* Read IRQ status register to clear all pending interrupts */ 1320 ret = cy8c95x0_irq_pending(chip, pending_irqs); 1321 if (ret) { 1322 dev_err(chip->dev, "failed to clear irq status register\n"); 1323 return ret; 1324 } 1325 1326 /* Mask all interrupts */ 1327 bitmap_fill(chip->irq_mask, MAX_LINE); 1328 1329 gpio_irq_chip_set_chip(girq, &cy8c95x0_irqchip); 1330 1331 /* This will let us handle the parent IRQ in the driver */ 1332 girq->parent_handler = NULL; 1333 girq->num_parents = 0; 1334 girq->parents = NULL; 1335 girq->default_type = IRQ_TYPE_NONE; 1336 girq->handler = handle_simple_irq; 1337 girq->threaded = true; 1338 1339 ret = devm_request_threaded_irq(chip->dev, irq, 1340 NULL, cy8c95x0_irq_handler, 1341 IRQF_ONESHOT | IRQF_SHARED, 1342 dev_name(chip->dev), chip); 1343 if (ret) { 1344 dev_err(chip->dev, "failed to request irq %d\n", irq); 1345 return ret; 1346 } 1347 dev_info(chip->dev, "Registered threaded IRQ\n"); 1348 1349 return 0; 1350} 1351 1352static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) 1353{ 1354 struct pinctrl_desc *pd = &chip->pinctrl_desc; 1355 1356 pd->pctlops = &cy8c95x0_pinctrl_ops; 1357 pd->confops = &cy8c95x0_pinconf_ops; 1358 pd->pmxops = &cy8c95x0_pmxops; 1359 pd->name = dev_name(chip->dev); 1360 pd->pins = cy8c9560_pins; 1361 pd->npins = chip->tpin; 1362 pd->owner = THIS_MODULE; 1363 1364 chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip); 1365 if (IS_ERR(chip->pctldev)) 1366 return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev), 1367 "can't register controller\n"); 1368 1369 return 0; 1370} 1371 1372static int cy8c95x0_detect(struct i2c_client *client, 1373 struct i2c_board_info *info) 1374{ 1375 struct i2c_adapter *adapter = client->adapter; 1376 int ret; 1377 const char *name; 1378 1379 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 1380 return -ENODEV; 1381 1382 ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); 1383 if (ret < 0) 1384 return ret; 1385 switch (ret & GENMASK(7, 4)) { 1386 case 0x20: 1387 name = cy8c95x0_id[0].name; 1388 break; 1389 case 0x40: 1390 name = cy8c95x0_id[1].name; 1391 break; 1392 case 0x60: 1393 name = cy8c95x0_id[2].name; 1394 break; 1395 default: 1396 return -ENODEV; 1397 } 1398 1399 dev_info(&client->dev, "Found a %s chip at 0x%02x.\n", name, client->addr); 1400 strscpy(info->type, name); 1401 1402 return 0; 1403} 1404 1405static int cy8c95x0_probe(struct i2c_client *client) 1406{ 1407 struct device *dev = &client->dev; 1408 struct cy8c95x0_pinctrl *chip; 1409 struct regmap_config regmap_conf; 1410 struct regmap_range_cfg regmap_range_conf; 1411 int ret; 1412 1413 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1414 if (!chip) 1415 return -ENOMEM; 1416 1417 chip->dev = dev; 1418 1419 /* Set the device type */ 1420 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1421 if (!chip->driver_data) 1422 return -ENODEV; 1423 1424 chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; 1425 chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); 1426 1427 memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf)); 1428 1429 switch (chip->tpin) { 1430 case 20: 1431 strscpy(chip->name, cy8c95x0_id[0].name); 1432 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1; 1433 break; 1434 case 40: 1435 strscpy(chip->name, cy8c95x0_id[1].name); 1436 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1; 1437 break; 1438 case 60: 1439 strscpy(chip->name, cy8c95x0_id[2].name); 1440 regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1; 1441 break; 1442 default: 1443 return -ENODEV; 1444 } 1445 1446 ret = devm_regulator_get_enable(dev, "vdd"); 1447 if (ret) 1448 return dev_err_probe(dev, ret, "failed to enable regulator vdd\n"); 1449 1450 /* bring the chip out of reset if reset pin is provided */ 1451 chip->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 1452 if (IS_ERR(chip->gpio_reset)) 1453 return dev_err_probe(dev, PTR_ERR(chip->gpio_reset), "Failed to get GPIO 'reset'\n"); 1454 gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); 1455 if (chip->gpio_reset) { 1456 fsleep(1000); 1457 gpiod_set_value_cansleep(chip->gpio_reset, 0); 1458 fsleep(250000); 1459 } 1460 1461 /* Regmap for direct and paged registers */ 1462 memcpy(®map_conf, &cy8c9520_i2c_regmap, sizeof(regmap_conf)); 1463 regmap_conf.ranges = ®map_range_conf; 1464 regmap_conf.max_register = regmap_range_conf.range_max; 1465 regmap_conf.num_reg_defaults_raw = regmap_range_conf.range_max; 1466 1467 chip->regmap = devm_regmap_init_i2c(client, ®map_conf); 1468 if (IS_ERR(chip->regmap)) 1469 return PTR_ERR(chip->regmap); 1470 1471 bitmap_zero(chip->push_pull, MAX_LINE); 1472 1473 /* Setup HW pins mapping */ 1474 bitmap_fill(chip->map, MAX_LINE); 1475 bitmap_clear(chip->map, 20, 4); 1476 1477 mutex_init(&chip->i2c_lock); 1478 1479 if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) { 1480 ret = cy8c95x0_acpi_get_irq(&client->dev); 1481 if (ret > 0) 1482 client->irq = ret; 1483 } 1484 1485 if (client->irq) { 1486 ret = cy8c95x0_irq_setup(chip, client->irq); 1487 if (ret) 1488 return ret; 1489 } 1490 1491 ret = cy8c95x0_setup_pinctrl(chip); 1492 if (ret) 1493 return ret; 1494 1495 return cy8c95x0_setup_gpiochip(chip); 1496} 1497 1498static const struct acpi_device_id cy8c95x0_acpi_ids[] = { 1499 { "INT3490", 40, }, 1500 { } 1501}; 1502MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); 1503 1504static struct i2c_driver cy8c95x0_driver = { 1505 .driver = { 1506 .name = "cy8c95x0-pinctrl", 1507 .of_match_table = cy8c95x0_dt_ids, 1508 .acpi_match_table = cy8c95x0_acpi_ids, 1509 }, 1510 .probe = cy8c95x0_probe, 1511 .id_table = cy8c95x0_id, 1512 .detect = cy8c95x0_detect, 1513}; 1514module_i2c_driver(cy8c95x0_driver); 1515 1516MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>"); 1517MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>"); 1518MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0"); 1519MODULE_LICENSE("GPL");
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