pinctrl-s32cc.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Core driver for the S32 CC (Common Chassis) pin controller
  4 *
  5 * Copyright 2017-2022,2024 NXP
  6 * Copyright (C) 2022 SUSE LLC
  7 * Copyright 2015-2016 Freescale Semiconductor, Inc.
  8 */
  9
 10#include <linux/bitops.h>
 11#include <linux/err.h>
 12#include <linux/gpio/driver.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/module.h>
 16#include <linux/of.h>
 17#include <linux/platform_device.h>
 18#include <linux/pinctrl/machine.h>
 19#include <linux/pinctrl/pinconf.h>
 20#include <linux/pinctrl/pinctrl.h>
 21#include <linux/pinctrl/pinmux.h>
 22#include <linux/regmap.h>
 23#include <linux/seq_file.h>
 24#include <linux/slab.h>
 25
 26#include "../core.h"
 27#include "../pinconf.h"
 28#include "../pinctrl-utils.h"
 29#include "pinctrl-s32.h"
 30
 31#define S32_PIN_ID_SHIFT	4
 32#define S32_PIN_ID_MASK		GENMASK(31, S32_PIN_ID_SHIFT)
 33
 34#define S32_MSCR_SSS_MASK	GENMASK(2, 0)
 35#define S32_MSCR_PUS		BIT(12)
 36#define S32_MSCR_PUE		BIT(13)
 37#define S32_MSCR_SRE(X)		(((X) & GENMASK(3, 0)) << 14)
 38#define S32_MSCR_IBE		BIT(19)
 39#define S32_MSCR_ODE		BIT(20)
 40#define S32_MSCR_OBE		BIT(21)
 41
 42enum s32_write_type {
 43	S32_PINCONF_UPDATE_ONLY,
 44	S32_PINCONF_OVERWRITE,
 45};
 46
 47static struct regmap_config s32_regmap_config = {
 48	.reg_bits = 32,
 49	.val_bits = 32,
 50	.reg_stride = 4,
 51};
 52
 53static u32 get_pin_no(u32 pinmux)
 54{
 55	return (pinmux & S32_PIN_ID_MASK) >> S32_PIN_ID_SHIFT;
 56}
 57
 58static u32 get_pin_func(u32 pinmux)
 59{
 60	return pinmux & GENMASK(3, 0);
 61}
 62
 63struct s32_pinctrl_mem_region {
 64	struct regmap *map;
 65	const struct s32_pin_range *pin_range;
 66	char name[8];
 67};
 68
 69/*
 70 * Holds pin configuration for GPIO's.
 71 * @pin_id: Pin ID for this GPIO
 72 * @config: Pin settings
 73 * @list: Linked list entry for each gpio pin
 74 */
 75struct gpio_pin_config {
 76	unsigned int pin_id;
 77	unsigned int config;
 78	struct list_head list;
 79};
 80
 81/*
 82 * Pad config save/restore for power suspend/resume.
 83 */
 84struct s32_pinctrl_context {
 85	unsigned int *pads;
 86};
 87
 88/*
 89 * @dev: a pointer back to containing device
 90 * @pctl: a pointer to the pinctrl device structure
 91 * @regions: reserved memory regions with start/end pin
 92 * @info: structure containing information about the pin
 93 * @gpio_configs: Saved configurations for GPIO pins
 94 * @gpiop_configs_lock: lock for the `gpio_configs` list
 95 * @s32_pinctrl_context: Configuration saved over system sleep
 96 */
 97struct s32_pinctrl {
 98	struct device *dev;
 99	struct pinctrl_dev *pctl;
100	struct s32_pinctrl_mem_region *regions;
101	struct s32_pinctrl_soc_info *info;
102	struct list_head gpio_configs;
103	spinlock_t gpio_configs_lock;
104#ifdef CONFIG_PM_SLEEP
105	struct s32_pinctrl_context saved_context;
106#endif
107};
108
109static struct s32_pinctrl_mem_region *
110s32_get_region(struct pinctrl_dev *pctldev, unsigned int pin)
111{
112	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
113	const struct s32_pin_range *pin_range;
114	unsigned int mem_regions = ipctl->info->soc_data->mem_regions;
115	unsigned int i;
116
117	for (i = 0; i < mem_regions; i++) {
118		pin_range = ipctl->regions[i].pin_range;
119		if (pin >= pin_range->start && pin <= pin_range->end)
120			return &ipctl->regions[i];
121	}
122
123	return NULL;
124}
125
126static inline int s32_check_pin(struct pinctrl_dev *pctldev,
127				unsigned int pin)
128{
129	return s32_get_region(pctldev, pin) ? 0 : -EINVAL;
130}
131
132static inline int s32_regmap_read(struct pinctrl_dev *pctldev,
133			   unsigned int pin, unsigned int *val)
134{
135	struct s32_pinctrl_mem_region *region;
136	unsigned int offset;
137
138	region = s32_get_region(pctldev, pin);
139	if (!region)
140		return -EINVAL;
141
142	offset = (pin - region->pin_range->start) *
143			regmap_get_reg_stride(region->map);
144
145	return regmap_read(region->map, offset, val);
146}
147
148static inline int s32_regmap_write(struct pinctrl_dev *pctldev,
149			    unsigned int pin,
150			    unsigned int val)
151{
152	struct s32_pinctrl_mem_region *region;
153	unsigned int offset;
154
155	region = s32_get_region(pctldev, pin);
156	if (!region)
157		return -EINVAL;
158
159	offset = (pin - region->pin_range->start) *
160			regmap_get_reg_stride(region->map);
161
162	return regmap_write(region->map, offset, val);
163
164}
165
166static inline int s32_regmap_update(struct pinctrl_dev *pctldev, unsigned int pin,
167			     unsigned int mask, unsigned int val)
168{
169	struct s32_pinctrl_mem_region *region;
170	unsigned int offset;
171
172	region = s32_get_region(pctldev, pin);
173	if (!region)
174		return -EINVAL;
175
176	offset = (pin - region->pin_range->start) *
177			regmap_get_reg_stride(region->map);
178
179	return regmap_update_bits(region->map, offset, mask, val);
180}
181
182static int s32_get_groups_count(struct pinctrl_dev *pctldev)
183{
184	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
185	const struct s32_pinctrl_soc_info *info = ipctl->info;
186
187	return info->ngroups;
188}
189
190static const char *s32_get_group_name(struct pinctrl_dev *pctldev,
191				      unsigned int selector)
192{
193	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
194	const struct s32_pinctrl_soc_info *info = ipctl->info;
195
196	return info->groups[selector].data.name;
197}
198
199static int s32_get_group_pins(struct pinctrl_dev *pctldev,
200			      unsigned int selector, const unsigned int **pins,
201			      unsigned int *npins)
202{
203	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
204	const struct s32_pinctrl_soc_info *info = ipctl->info;
205
206	*pins = info->groups[selector].data.pins;
207	*npins = info->groups[selector].data.npins;
208
209	return 0;
210}
211
212static void s32_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
213			     unsigned int offset)
214{
215	seq_printf(s, "%s", dev_name(pctldev->dev));
216}
217
218static int s32_dt_group_node_to_map(struct pinctrl_dev *pctldev,
219				    struct device_node *np,
220				    struct pinctrl_map **map,
221				    unsigned int *reserved_maps,
222				    unsigned int *num_maps,
223				    const char *func_name)
224{
225	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
226	struct device *dev = ipctl->dev;
227	unsigned long *cfgs = NULL;
228	unsigned int n_cfgs, reserve = 1;
229	int n_pins, ret;
230
231	n_pins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));
232	if (n_pins < 0) {
233		dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np);
234	} else if (!n_pins) {
235		return -EINVAL;
236	}
237
238	ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs);
239	if (ret) {
240		dev_err(dev, "%pOF: could not parse node property\n", np);
241		return ret;
242	}
243
244	if (n_cfgs)
245		reserve++;
246
247	ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
248					reserve);
249	if (ret < 0)
250		goto free_cfgs;
251
252	ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
253					np->name, func_name);
254	if (ret < 0)
255		goto free_cfgs;
256
257	if (n_cfgs) {
258		ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps,
259						    num_maps, np->name, cfgs, n_cfgs,
260						    PIN_MAP_TYPE_CONFIGS_GROUP);
261		if (ret < 0)
262			goto free_cfgs;
263	}
264
265free_cfgs:
266	kfree(cfgs);
267	return ret;
268}
269
270static int s32_dt_node_to_map(struct pinctrl_dev *pctldev,
271			      struct device_node *np_config,
272			      struct pinctrl_map **map,
273			      unsigned int *num_maps)
274{
275	unsigned int reserved_maps;
276	int ret;
277
278	reserved_maps = 0;
279	*map = NULL;
280	*num_maps = 0;
281
282	for_each_available_child_of_node_scoped(np_config, np) {
283		ret = s32_dt_group_node_to_map(pctldev, np, map,
284					       &reserved_maps, num_maps,
285					       np_config->name);
286		if (ret < 0) {
287			pinctrl_utils_free_map(pctldev, *map, *num_maps);
288			return ret;
289		}
290	}
291
292	return 0;
293}
294
295static const struct pinctrl_ops s32_pctrl_ops = {
296	.get_groups_count = s32_get_groups_count,
297	.get_group_name = s32_get_group_name,
298	.get_group_pins = s32_get_group_pins,
299	.pin_dbg_show = s32_pin_dbg_show,
300	.dt_node_to_map = s32_dt_node_to_map,
301	.dt_free_map = pinctrl_utils_free_map,
302};
303
304static int s32_pmx_set(struct pinctrl_dev *pctldev, unsigned int selector,
305		       unsigned int group)
306{
307	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
308	const struct s32_pinctrl_soc_info *info = ipctl->info;
309	int i, ret;
310	struct s32_pin_group *grp;
311
312	/*
313	 * Configure the mux mode for each pin in the group for a specific
314	 * function.
315	 */
316	grp = &info->groups[group];
317
318	dev_dbg(ipctl->dev, "set mux for function %s group %s\n",
319		info->functions[selector].name, grp->data.name);
320
321	/* Check beforehand so we don't have a partial config. */
322	for (i = 0; i < grp->data.npins; i++) {
323		if (s32_check_pin(pctldev, grp->data.pins[i]) != 0) {
324			dev_err(info->dev, "invalid pin: %u in group: %u\n",
325				grp->data.pins[i], group);
326			return -EINVAL;
327		}
328	}
329
330	for (i = 0, ret = 0; i < grp->data.npins && !ret; i++) {
331		ret = s32_regmap_update(pctldev, grp->data.pins[i],
332					S32_MSCR_SSS_MASK, grp->pin_sss[i]);
333		if (ret) {
334			dev_err(info->dev, "Failed to set pin %u\n",
335				grp->data.pins[i]);
336			return ret;
337		}
338	}
339
340	return 0;
341}
342
343static int s32_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
344{
345	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
346	const struct s32_pinctrl_soc_info *info = ipctl->info;
347
348	return info->nfunctions;
349}
350
351static const char *s32_pmx_get_func_name(struct pinctrl_dev *pctldev,
352					 unsigned int selector)
353{
354	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
355	const struct s32_pinctrl_soc_info *info = ipctl->info;
356
357	return info->functions[selector].name;
358}
359
360static int s32_pmx_get_groups(struct pinctrl_dev *pctldev,
361			      unsigned int selector,
362			      const char * const **groups,
363			      unsigned int * const num_groups)
364{
365	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
366	const struct s32_pinctrl_soc_info *info = ipctl->info;
367
368	*groups = info->functions[selector].groups;
369	*num_groups = info->functions[selector].ngroups;
370
371	return 0;
372}
373
374static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
375				       struct pinctrl_gpio_range *range,
376				       unsigned int offset)
377{
378	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
379	struct gpio_pin_config *gpio_pin;
380	unsigned int config;
381	unsigned long flags;
382	int ret;
383
384	ret = s32_regmap_read(pctldev, offset, &config);
385	if (ret)
386		return ret;
387
388	/* Save current configuration */
389	gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL);
390	if (!gpio_pin)
391		return -ENOMEM;
392
393	gpio_pin->pin_id = offset;
394	gpio_pin->config = config;
395	INIT_LIST_HEAD(&gpio_pin->list);
396
397	spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);
398	list_add(&gpio_pin->list, &ipctl->gpio_configs);
399	spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);
400
401	/* GPIO pin means SSS = 0 */
402	config &= ~S32_MSCR_SSS_MASK;
403
404	return s32_regmap_write(pctldev, offset, config);
405}
406
407static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
408				      struct pinctrl_gpio_range *range,
409				      unsigned int offset)
410{
411	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
412	struct gpio_pin_config *gpio_pin, *tmp;
413	unsigned long flags;
414	int ret;
415
416	spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);
417
418	list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) {
419		if (gpio_pin->pin_id == offset) {
420			ret = s32_regmap_write(pctldev, gpio_pin->pin_id,
421						 gpio_pin->config);
422			if (ret != 0)
423				goto unlock;
424
425			list_del(&gpio_pin->list);
426			kfree(gpio_pin);
427			break;
428		}
429	}
430
431unlock:
432	spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);
433}
434
435static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
436				      struct pinctrl_gpio_range *range,
437				      unsigned int offset,
438				      bool input)
439{
440	/* Always enable IBE for GPIOs. This allows us to read the
441	 * actual line value and compare it with the one set.
442	 */
443	unsigned int config = S32_MSCR_IBE;
444	unsigned int mask = S32_MSCR_IBE | S32_MSCR_OBE;
445
446	/* Enable output buffer */
447	if (!input)
448		config |= S32_MSCR_OBE;
449
450	return s32_regmap_update(pctldev, offset, mask, config);
451}
452
453static const struct pinmux_ops s32_pmx_ops = {
454	.get_functions_count = s32_pmx_get_funcs_count,
455	.get_function_name = s32_pmx_get_func_name,
456	.get_function_groups = s32_pmx_get_groups,
457	.set_mux = s32_pmx_set,
458	.gpio_request_enable = s32_pmx_gpio_request_enable,
459	.gpio_disable_free = s32_pmx_gpio_disable_free,
460	.gpio_set_direction = s32_pmx_gpio_set_direction,
461};
462
463/* Set the reserved elements as -1 */
464static const int support_slew[] = {208, -1, -1, -1, 166, 150, 133, 83};
465
466static int s32_get_slew_regval(int arg)
467{
468	unsigned int i;
469
470	/* Translate a real slew rate (MHz) to a register value */
471	for (i = 0; i < ARRAY_SIZE(support_slew); i++) {
472		if (arg == support_slew[i])
473			return i;
474	}
475
476	return -EINVAL;
477}
478
479static inline void s32_pin_set_pull(enum pin_config_param param,
480				   unsigned int *mask, unsigned int *config)
481{
482	switch (param) {
483	case PIN_CONFIG_BIAS_DISABLE:
484	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
485		*config &= ~(S32_MSCR_PUS | S32_MSCR_PUE);
486		break;
487	case PIN_CONFIG_BIAS_PULL_UP:
488		*config |= S32_MSCR_PUS | S32_MSCR_PUE;
489		break;
490	case PIN_CONFIG_BIAS_PULL_DOWN:
491		*config &= ~S32_MSCR_PUS;
492		*config |= S32_MSCR_PUE;
493		break;
494	default:
495		return;
496	}
497
498	*mask |= S32_MSCR_PUS | S32_MSCR_PUE;
499}
500
501static int s32_parse_pincfg(unsigned long pincfg, unsigned int *mask,
502			    unsigned int *config)
503{
504	enum pin_config_param param;
505	u32 arg;
506	int ret;
507
508	param = pinconf_to_config_param(pincfg);
509	arg = pinconf_to_config_argument(pincfg);
510
511	switch (param) {
512	/* All pins are persistent over suspend */
513	case PIN_CONFIG_PERSIST_STATE:
514		return 0;
515	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
516		*config |= S32_MSCR_ODE;
517		*mask |= S32_MSCR_ODE;
518		break;
519	case PIN_CONFIG_DRIVE_PUSH_PULL:
520		*config &= ~S32_MSCR_ODE;
521		*mask |= S32_MSCR_ODE;
522		break;
523	case PIN_CONFIG_OUTPUT_ENABLE:
524		if (arg)
525			*config |= S32_MSCR_OBE;
526		else
527			*config &= ~S32_MSCR_OBE;
528		*mask |= S32_MSCR_OBE;
529		break;
530	case PIN_CONFIG_INPUT_ENABLE:
531		if (arg)
532			*config |= S32_MSCR_IBE;
533		else
534			*config &= ~S32_MSCR_IBE;
535		*mask |= S32_MSCR_IBE;
536		break;
537	case PIN_CONFIG_SLEW_RATE:
538		ret = s32_get_slew_regval(arg);
539		if (ret < 0)
540			return ret;
541		*config |= S32_MSCR_SRE((u32)ret);
542		*mask |= S32_MSCR_SRE(~0);
543		break;
544	case PIN_CONFIG_BIAS_DISABLE:
545	case PIN_CONFIG_BIAS_PULL_UP:
546	case PIN_CONFIG_BIAS_PULL_DOWN:
547		s32_pin_set_pull(param, mask, config);
548		break;
549	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
550		*config &= ~(S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE);
551		*mask |= S32_MSCR_ODE | S32_MSCR_OBE | S32_MSCR_IBE;
552		s32_pin_set_pull(param, mask, config);
553		break;
554	default:
555		return -EOPNOTSUPP;
556	}
557
558	return 0;
559}
560
561static int s32_pinconf_mscr_write(struct pinctrl_dev *pctldev,
562				   unsigned int pin_id,
563				   unsigned long *configs,
564				   unsigned int num_configs,
565				   enum s32_write_type write_type)
566{
567	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
568	unsigned int config = 0, mask = 0;
569	int i, ret;
570
571	ret = s32_check_pin(pctldev, pin_id);
572	if (ret)
573		return ret;
574
575	dev_dbg(ipctl->dev, "pinconf set pin %s with %u configs\n",
576		pin_get_name(pctldev, pin_id), num_configs);
577
578	for (i = 0; i < num_configs; i++) {
579		ret = s32_parse_pincfg(configs[i], &mask, &config);
580		if (ret)
581			return ret;
582	}
583
584	/* If the MSCR configuration has to be written,
585	 * the SSS field should not be touched.
586	 */
587	if (write_type == S32_PINCONF_OVERWRITE)
588		mask = (unsigned int)~S32_MSCR_SSS_MASK;
589
590	if (!config && !mask)
591		return 0;
592
593	if (write_type == S32_PINCONF_OVERWRITE)
594		dev_dbg(ipctl->dev, "set: pin %u cfg 0x%x\n", pin_id, config);
595	else
596		dev_dbg(ipctl->dev, "update: pin %u cfg 0x%x\n", pin_id,
597			config);
598
599	return s32_regmap_update(pctldev, pin_id, mask, config);
600}
601
602static int s32_pinconf_get(struct pinctrl_dev *pctldev,
603			   unsigned int pin_id,
604			   unsigned long *config)
605{
606	return s32_regmap_read(pctldev, pin_id, (unsigned int *)config);
607}
608
609static int s32_pinconf_set(struct pinctrl_dev *pctldev,
610			   unsigned int pin_id, unsigned long *configs,
611			   unsigned int num_configs)
612{
613	return s32_pinconf_mscr_write(pctldev, pin_id, configs,
614				       num_configs, S32_PINCONF_UPDATE_ONLY);
615}
616
617static int s32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned int selector,
618			       unsigned long *configs, unsigned int num_configs)
619{
620	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
621	const struct s32_pinctrl_soc_info *info = ipctl->info;
622	struct s32_pin_group *grp;
623	int i, ret;
624
625	grp = &info->groups[selector];
626	for (i = 0; i < grp->data.npins; i++) {
627		ret = s32_pinconf_mscr_write(pctldev, grp->data.pins[i],
628					      configs, num_configs, S32_PINCONF_OVERWRITE);
629		if (ret)
630			return ret;
631	}
632
633	return 0;
634}
635
636static void s32_pinconf_dbg_show(struct pinctrl_dev *pctldev,
637				 struct seq_file *s, unsigned int pin_id)
638{
639	unsigned int config;
640	int ret;
641
642	ret = s32_regmap_read(pctldev, pin_id, &config);
643	if (ret)
644		return;
645
646	seq_printf(s, "0x%x", config);
647}
648
649static void s32_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
650				       struct seq_file *s, unsigned int selector)
651{
652	struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
653	const struct s32_pinctrl_soc_info *info = ipctl->info;
654	struct s32_pin_group *grp;
655	unsigned int config;
656	const char *name;
657	int i, ret;
658
659	seq_puts(s, "\n");
660	grp = &info->groups[selector];
661	for (i = 0; i < grp->data.npins; i++) {
662		name = pin_get_name(pctldev, grp->data.pins[i]);
663		ret = s32_regmap_read(pctldev, grp->data.pins[i], &config);
664		if (ret)
665			return;
666		seq_printf(s, "%s: 0x%x\n", name, config);
667	}
668}
669
670static const struct pinconf_ops s32_pinconf_ops = {
671	.pin_config_get = s32_pinconf_get,
672	.pin_config_set	= s32_pinconf_set,
673	.pin_config_group_set = s32_pconf_group_set,
674	.pin_config_dbg_show = s32_pinconf_dbg_show,
675	.pin_config_group_dbg_show = s32_pinconf_group_dbg_show,
676};
677
678#ifdef CONFIG_PM_SLEEP
679static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl,
680				    unsigned int pin)
681{
682	const struct pin_desc *pd = pin_desc_get(ipctl->pctl, pin);
683
684	if (!pd)
685		return false;
686
687	/*
688	 * Only restore the pin if it is actually in use by the kernel (or
689	 * by userspace).
690	 */
691	if (pd->mux_owner || pd->gpio_owner)
692		return true;
693
694	return false;
695}
696
697int s32_pinctrl_suspend(struct device *dev)
698{
699	struct platform_device *pdev = to_platform_device(dev);
700	struct s32_pinctrl *ipctl = platform_get_drvdata(pdev);
701	const struct pinctrl_pin_desc *pin;
702	const struct s32_pinctrl_soc_info *info = ipctl->info;
703	struct s32_pinctrl_context *saved_context = &ipctl->saved_context;
704	int i;
705	int ret;
706	unsigned int config;
707
708	for (i = 0; i < info->soc_data->npins; i++) {
709		pin = &info->soc_data->pins[i];
710
711		if (!s32_pinctrl_should_save(ipctl, pin->number))
712			continue;
713
714		ret = s32_regmap_read(ipctl->pctl, pin->number, &config);
715		if (ret)
716			return -EINVAL;
717
718		saved_context->pads[i] = config;
719	}
720
721	return 0;
722}
723
724int s32_pinctrl_resume(struct device *dev)
725{
726	struct platform_device *pdev = to_platform_device(dev);
727	struct s32_pinctrl *ipctl = platform_get_drvdata(pdev);
728	const struct s32_pinctrl_soc_info *info = ipctl->info;
729	const struct pinctrl_pin_desc *pin;
730	struct s32_pinctrl_context *saved_context = &ipctl->saved_context;
731	int ret, i;
732
733	for (i = 0; i < info->soc_data->npins; i++) {
734		pin = &info->soc_data->pins[i];
735
736		if (!s32_pinctrl_should_save(ipctl, pin->number))
737			continue;
738
739		ret = s32_regmap_write(ipctl->pctl, pin->number,
740					 saved_context->pads[i]);
741		if (ret)
742			return ret;
743	}
744
745	return 0;
746}
747#endif
748
749static int s32_pinctrl_parse_groups(struct device_node *np,
750				     struct s32_pin_group *grp,
751				     struct s32_pinctrl_soc_info *info)
752{
753	struct device *dev;
754	unsigned int *pins, *sss;
755	int i, npins;
756	u32 pinmux;
757
758	dev = info->dev;
759
760	dev_dbg(dev, "group: %pOFn\n", np);
761
762	/* Initialise group */
763	grp->data.name = np->name;
764
765	npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));
766	if (npins < 0) {
767		dev_err(dev, "Failed to read 'pinmux' property in node %s.\n",
768			grp->data.name);
769		return -EINVAL;
770	}
771	if (!npins) {
772		dev_err(dev, "The group %s has no pins.\n", grp->data.name);
773		return -EINVAL;
774	}
775
776	grp->data.npins = npins;
777
778	pins = devm_kcalloc(info->dev, npins, sizeof(*pins), GFP_KERNEL);
779	sss = devm_kcalloc(info->dev, npins, sizeof(*sss), GFP_KERNEL);
780	if (!pins || !sss)
781		return -ENOMEM;
782
783	i = 0;
784	of_property_for_each_u32(np, "pinmux", pinmux) {
785		pins[i] = get_pin_no(pinmux);
786		sss[i] = get_pin_func(pinmux);
787
788		dev_dbg(info->dev, "pin: 0x%x, sss: 0x%x", pins[i], sss[i]);
789		i++;
790	}
791
792	grp->data.pins = pins;
793	grp->pin_sss = sss;
794
795	return 0;
796}
797
798static int s32_pinctrl_parse_functions(struct device_node *np,
799					struct s32_pinctrl_soc_info *info,
800					u32 index)
801{
802	struct pinfunction *func;
803	struct s32_pin_group *grp;
804	const char **groups;
805	u32 i = 0;
806	int ret = 0;
807
808	dev_dbg(info->dev, "parse function(%u): %pOFn\n", index, np);
809
810	func = &info->functions[index];
811
812	/* Initialise function */
813	func->name = np->name;
814	func->ngroups = of_get_child_count(np);
815	if (func->ngroups == 0) {
816		dev_err(info->dev, "no groups defined in %pOF\n", np);
817		return -EINVAL;
818	}
819
820	groups = devm_kcalloc(info->dev, func->ngroups,
821				    sizeof(*func->groups), GFP_KERNEL);
822	if (!groups)
823		return -ENOMEM;
824
825	for_each_child_of_node_scoped(np, child) {
826		groups[i] = child->name;
827		grp = &info->groups[info->grp_index++];
828		ret = s32_pinctrl_parse_groups(child, grp, info);
829		if (ret)
830			return ret;
831		i++;
832	}
833
834	func->groups = groups;
835
836	return 0;
837}
838
839static int s32_pinctrl_probe_dt(struct platform_device *pdev,
840				struct s32_pinctrl *ipctl)
841{
842	struct s32_pinctrl_soc_info *info = ipctl->info;
843	struct device_node *np = pdev->dev.of_node;
844	struct resource *res;
845	struct regmap *map;
846	void __iomem *base;
847	unsigned int mem_regions = info->soc_data->mem_regions;
848	int ret;
849	u32 nfuncs = 0;
850	u32 i = 0;
851
852	if (!np)
853		return -ENODEV;
854
855	if (mem_regions == 0 || mem_regions >= 10000) {
856		dev_err(&pdev->dev, "mem_regions is invalid: %u\n", mem_regions);
857		return -EINVAL;
858	}
859
860	ipctl->regions = devm_kcalloc(&pdev->dev, mem_regions,
861				      sizeof(*ipctl->regions), GFP_KERNEL);
862	if (!ipctl->regions)
863		return -ENOMEM;
864
865	for (i = 0; i < mem_regions; i++) {
866		base = devm_platform_get_and_ioremap_resource(pdev, i, &res);
867		if (IS_ERR(base))
868			return PTR_ERR(base);
869
870		snprintf(ipctl->regions[i].name,
871			 sizeof(ipctl->regions[i].name), "map%u", i);
872
873		s32_regmap_config.name = ipctl->regions[i].name;
874		s32_regmap_config.max_register = resource_size(res) -
875						 s32_regmap_config.reg_stride;
876
877		map = devm_regmap_init_mmio(&pdev->dev, base,
878						&s32_regmap_config);
879		if (IS_ERR(map)) {
880			dev_err(&pdev->dev, "Failed to init regmap[%u]\n", i);
881			return PTR_ERR(map);
882		}
883
884		ipctl->regions[i].map = map;
885		ipctl->regions[i].pin_range = &info->soc_data->mem_pin_ranges[i];
886	}
887
888	nfuncs = of_get_child_count(np);
889	if (nfuncs <= 0) {
890		dev_err(&pdev->dev, "no functions defined\n");
891		return -EINVAL;
892	}
893
894	info->nfunctions = nfuncs;
895	info->functions = devm_kcalloc(&pdev->dev, nfuncs,
896				       sizeof(*info->functions), GFP_KERNEL);
897	if (!info->functions)
898		return -ENOMEM;
899
900	info->ngroups = 0;
901	for_each_child_of_node_scoped(np, child)
902		info->ngroups += of_get_child_count(child);
903
904	info->groups = devm_kcalloc(&pdev->dev, info->ngroups,
905				    sizeof(*info->groups), GFP_KERNEL);
906	if (!info->groups)
907		return -ENOMEM;
908
909	i = 0;
910	for_each_child_of_node_scoped(np, child) {
911		ret = s32_pinctrl_parse_functions(child, info, i++);
912		if (ret)
913			return ret;
914	}
915
916	return 0;
917}
918
919int s32_pinctrl_probe(struct platform_device *pdev,
920		      const struct s32_pinctrl_soc_data *soc_data)
921{
922	struct s32_pinctrl *ipctl;
923	int ret;
924	struct pinctrl_desc *s32_pinctrl_desc;
925	struct s32_pinctrl_soc_info *info;
926#ifdef CONFIG_PM_SLEEP
927	struct s32_pinctrl_context *saved_context;
928#endif
929
930	if (!soc_data || !soc_data->pins || !soc_data->npins) {
931		dev_err(&pdev->dev, "wrong pinctrl info\n");
932		return -EINVAL;
933	}
934
935	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
936	if (!info)
937		return -ENOMEM;
938
939	info->soc_data = soc_data;
940	info->dev = &pdev->dev;
941
942	/* Create state holders etc for this driver */
943	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
944	if (!ipctl)
945		return -ENOMEM;
946
947	ipctl->info = info;
948	ipctl->dev = info->dev;
949	platform_set_drvdata(pdev, ipctl);
950
951	INIT_LIST_HEAD(&ipctl->gpio_configs);
952	spin_lock_init(&ipctl->gpio_configs_lock);
953
954	s32_pinctrl_desc =
955		devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL);
956	if (!s32_pinctrl_desc)
957		return -ENOMEM;
958
959	s32_pinctrl_desc->name = dev_name(&pdev->dev);
960	s32_pinctrl_desc->pins = info->soc_data->pins;
961	s32_pinctrl_desc->npins = info->soc_data->npins;
962	s32_pinctrl_desc->pctlops = &s32_pctrl_ops;
963	s32_pinctrl_desc->pmxops = &s32_pmx_ops;
964	s32_pinctrl_desc->confops = &s32_pinconf_ops;
965	s32_pinctrl_desc->owner = THIS_MODULE;
966
967	ret = s32_pinctrl_probe_dt(pdev, ipctl);
968	if (ret) {
969		dev_err(&pdev->dev, "fail to probe dt properties\n");
970		return ret;
971	}
972
973	ipctl->pctl = devm_pinctrl_register(&pdev->dev, s32_pinctrl_desc,
974					    ipctl);
975	if (IS_ERR(ipctl->pctl))
976		return dev_err_probe(&pdev->dev, PTR_ERR(ipctl->pctl),
977				     "could not register s32 pinctrl driver\n");
978
979#ifdef CONFIG_PM_SLEEP
980	saved_context = &ipctl->saved_context;
981	saved_context->pads =
982		devm_kcalloc(&pdev->dev, info->soc_data->npins,
983			     sizeof(*saved_context->pads),
984			     GFP_KERNEL);
985	if (!saved_context->pads)
986		return -ENOMEM;
987#endif
988
989	dev_info(&pdev->dev, "initialized s32 pinctrl driver\n");
990
991	return 0;
992}