pinctrl-npcm8xx.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2020 Nuvoton Technology corporation.
   3
   4#include <linux/bits.h>
   5#include <linux/device.h>
   6#include <linux/gpio/driver.h>
   7#include <linux/gpio/generic.h>
   8#include <linux/interrupt.h>
   9#include <linux/irq.h>
  10#include <linux/mfd/syscon.h>
  11#include <linux/module.h>
  12#include <linux/debugfs.h>
  13#include <linux/seq_file.h>
  14#include <linux/mod_devicetable.h>
  15#include <linux/pinctrl/machine.h>
  16#include <linux/pinctrl/pinconf.h>
  17#include <linux/pinctrl/pinconf-generic.h>
  18#include <linux/pinctrl/pinctrl.h>
  19#include <linux/pinctrl/pinmux.h>
  20#include <linux/pinctrl/consumer.h>
  21#include <linux/platform_device.h>
  22#include <linux/property.h>
  23#include <linux/regmap.h>
  24
  25/* GCR registers */
  26#define NPCM8XX_GCR_SRCNT	0x068
  27#define NPCM8XX_GCR_FLOCKR1	0x074
  28#define NPCM8XX_GCR_DSCNT	0x078
  29#define NPCM8XX_GCR_I2CSEGSEL	0x0e0
  30#define NPCM8XX_GCR_MFSEL1	0x260
  31#define NPCM8XX_GCR_MFSEL2	0x264
  32#define NPCM8XX_GCR_MFSEL3	0x268
  33#define NPCM8XX_GCR_MFSEL4	0x26c
  34#define NPCM8XX_GCR_MFSEL5	0x270
  35#define NPCM8XX_GCR_MFSEL6	0x274
  36#define NPCM8XX_GCR_MFSEL7	0x278
  37
  38#define SRCNT_ESPI		BIT(3)
  39
  40/* GPIO registers */
  41#define NPCM8XX_GP_N_TLOCK1	0x00
  42#define NPCM8XX_GP_N_DIN	0x04
  43#define NPCM8XX_GP_N_POL	0x08
  44#define NPCM8XX_GP_N_DOUT	0x0c
  45#define NPCM8XX_GP_N_OE		0x10
  46#define NPCM8XX_GP_N_OTYP	0x14
  47#define NPCM8XX_GP_N_MP		0x18
  48#define NPCM8XX_GP_N_PU		0x1c
  49#define NPCM8XX_GP_N_PD		0x20
  50#define NPCM8XX_GP_N_DBNC	0x24
  51#define NPCM8XX_GP_N_EVTYP	0x28
  52#define NPCM8XX_GP_N_EVBE	0x2c
  53#define NPCM8XX_GP_N_OBL0	0x30
  54#define NPCM8XX_GP_N_OBL1	0x34
  55#define NPCM8XX_GP_N_OBL2	0x38
  56#define NPCM8XX_GP_N_OBL3	0x3c
  57#define NPCM8XX_GP_N_EVEN	0x40
  58#define NPCM8XX_GP_N_EVENS	0x44
  59#define NPCM8XX_GP_N_EVENC	0x48
  60#define NPCM8XX_GP_N_EVST	0x4c
  61#define NPCM8XX_GP_N_SPLCK	0x50
  62#define NPCM8XX_GP_N_MPLCK	0x54
  63#define NPCM8XX_GP_N_IEM	0x58
  64#define NPCM8XX_GP_N_OSRC	0x5c
  65#define NPCM8XX_GP_N_ODSC	0x60
  66#define NPCM8XX_GP_N_DOS	0x68
  67#define NPCM8XX_GP_N_DOC	0x6c
  68#define NPCM8XX_GP_N_OES	0x70
  69#define NPCM8XX_GP_N_OEC	0x74
  70#define NPCM8XX_GP_N_DBNCS0	0x80
  71#define NPCM8XX_GP_N_DBNCS1	0x84
  72#define NPCM8XX_GP_N_DBNCP0	0x88
  73#define NPCM8XX_GP_N_DBNCP1	0x8c
  74#define NPCM8XX_GP_N_DBNCP2	0x90
  75#define NPCM8XX_GP_N_DBNCP3	0x94
  76#define NPCM8XX_GP_N_TLOCK2	0xac
  77
  78#define NPCM8XX_GPIO_PER_BANK	32
  79#define NPCM8XX_GPIO_BANK_NUM	8
  80#define NPCM8XX_GCR_NONE	0
  81
  82#define NPCM8XX_DEBOUNCE_MAX		4
  83#define NPCM8XX_DEBOUNCE_NSEC		40
  84#define NPCM8XX_DEBOUNCE_VAL_MASK	GENMASK(23, 4)
  85#define NPCM8XX_DEBOUNCE_MAX_VAL	0xFFFFF7
  86
  87/* Structure for register banks */
  88struct debounce_time {
  89	bool	set_val[NPCM8XX_DEBOUNCE_MAX];
  90	u32	nanosec_val[NPCM8XX_DEBOUNCE_MAX];
  91};
  92
  93struct npcm8xx_gpio {
  94	struct gpio_generic_chip chip;
  95	void __iomem		*base;
  96	struct debounce_time	debounce;
  97	int			irqbase;
  98	int			irq;
  99	struct irq_chip		irq_chip;
 100	u32			pinctrl_id;
 101	int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
 102	int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
 103				int value);
 104	int (*request)(struct gpio_chip *chip, unsigned int offset);
 105	void (*free)(struct gpio_chip *chip, unsigned int offset);
 106};
 107
 108struct npcm8xx_pinctrl {
 109	struct pinctrl_dev	*pctldev;
 110	struct device		*dev;
 111	struct npcm8xx_gpio	gpio_bank[NPCM8XX_GPIO_BANK_NUM];
 112	struct irq_domain	*domain;
 113	struct regmap		*gcr_regmap;
 114	void __iomem		*regs;
 115	u32			bank_num;
 116};
 117
 118/* GPIO handling in the pinctrl driver */
 119static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg,
 120			  unsigned int pinmask)
 121{
 122	guard(gpio_generic_lock_irqsave)(chip);
 123
 124	iowrite32(ioread32(reg) | pinmask, reg);
 125}
 126
 127static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg,
 128			  unsigned int pinmask)
 129{
 130	guard(gpio_generic_lock_irqsave)(chip);
 131
 132	iowrite32(ioread32(reg) & ~pinmask, reg);
 133}
 134
 135static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 136{
 137	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
 138
 139	seq_printf(s, "DIN :%.8x DOUT:%.8x IE  :%.8x OE	 :%.8x\n",
 140		   ioread32(bank->base + NPCM8XX_GP_N_DIN),
 141		   ioread32(bank->base + NPCM8XX_GP_N_DOUT),
 142		   ioread32(bank->base + NPCM8XX_GP_N_IEM),
 143		   ioread32(bank->base + NPCM8XX_GP_N_OE));
 144	seq_printf(s, "PU  :%.8x PD  :%.8x DB  :%.8x POL :%.8x\n",
 145		   ioread32(bank->base + NPCM8XX_GP_N_PU),
 146		   ioread32(bank->base + NPCM8XX_GP_N_PD),
 147		   ioread32(bank->base + NPCM8XX_GP_N_DBNC),
 148		   ioread32(bank->base + NPCM8XX_GP_N_POL));
 149	seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
 150		   ioread32(bank->base + NPCM8XX_GP_N_EVTYP),
 151		   ioread32(bank->base + NPCM8XX_GP_N_EVBE),
 152		   ioread32(bank->base + NPCM8XX_GP_N_EVEN),
 153		   ioread32(bank->base + NPCM8XX_GP_N_EVST));
 154	seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
 155		   ioread32(bank->base + NPCM8XX_GP_N_OTYP),
 156		   ioread32(bank->base + NPCM8XX_GP_N_OSRC),
 157		   ioread32(bank->base + NPCM8XX_GP_N_ODSC));
 158	seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
 159		   ioread32(bank->base + NPCM8XX_GP_N_OBL0),
 160		   ioread32(bank->base + NPCM8XX_GP_N_OBL1),
 161		   ioread32(bank->base + NPCM8XX_GP_N_OBL2),
 162		   ioread32(bank->base + NPCM8XX_GP_N_OBL3));
 163	seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
 164		   ioread32(bank->base + NPCM8XX_GP_N_SPLCK),
 165		   ioread32(bank->base + NPCM8XX_GP_N_MPLCK));
 166}
 167
 168static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 169{
 170	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
 171	int ret;
 172
 173	ret = pinctrl_gpio_direction_input(chip, offset);
 174	if (ret)
 175		return ret;
 176
 177	return bank->direction_input(chip, offset);
 178}
 179
 180static int npcmgpio_direction_output(struct gpio_chip *chip,
 181				     unsigned int offset, int value)
 182{
 183	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
 184	int ret;
 185
 186	ret = pinctrl_gpio_direction_output(chip, offset);
 187	if (ret)
 188		return ret;
 189
 190	return bank->direction_output(chip, offset, value);
 191}
 192
 193static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
 194{
 195	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
 196	int ret;
 197
 198	ret = pinctrl_gpio_request(chip, offset);
 199	if (ret)
 200		return ret;
 201
 202	return bank->request(chip, offset);
 203}
 204
 205static void npcmgpio_irq_handler(struct irq_desc *desc)
 206{
 207	unsigned long sts, en, bit;
 208	struct npcm8xx_gpio *bank;
 209	struct irq_chip *chip;
 210	struct gpio_chip *gc;
 211
 212	gc = irq_desc_get_handler_data(desc);
 213	bank = gpiochip_get_data(gc);
 214	chip = irq_desc_get_chip(desc);
 215
 216	chained_irq_enter(chip, desc);
 217	sts = ioread32(bank->base + NPCM8XX_GP_N_EVST);
 218	en  = ioread32(bank->base + NPCM8XX_GP_N_EVEN);
 219	sts &= en;
 220	for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK)
 221		generic_handle_domain_irq(gc->irq.domain, bit);
 222	chained_irq_exit(chip, desc);
 223}
 224
 225static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
 226{
 227	struct npcm8xx_gpio *bank =
 228		gpiochip_get_data(irq_data_get_irq_chip_data(d));
 229	unsigned int gpio = BIT(irqd_to_hwirq(d));
 230
 231	switch (type) {
 232	case IRQ_TYPE_EDGE_RISING:
 233		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
 234		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
 235		break;
 236	case IRQ_TYPE_EDGE_FALLING:
 237		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
 238		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
 239		break;
 240	case IRQ_TYPE_EDGE_BOTH:
 241		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
 242		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
 243		break;
 244	case IRQ_TYPE_LEVEL_LOW:
 245		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
 246		break;
 247	case IRQ_TYPE_LEVEL_HIGH:
 248		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
 249		break;
 250	default:
 251		return -EINVAL;
 252	}
 253
 254	if (type & IRQ_TYPE_LEVEL_MASK) {
 255		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
 256		irq_set_handler_locked(d, handle_level_irq);
 257	} else if (type & IRQ_TYPE_EDGE_BOTH) {
 258		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
 259		irq_set_handler_locked(d, handle_edge_irq);
 260	}
 261
 262	return 0;
 263}
 264
 265static void npcmgpio_irq_ack(struct irq_data *d)
 266{
 267	struct npcm8xx_gpio *bank =
 268		gpiochip_get_data(irq_data_get_irq_chip_data(d));
 269	unsigned int gpio = irqd_to_hwirq(d);
 270
 271	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST);
 272}
 273
 274static void npcmgpio_irq_mask(struct irq_data *d)
 275{
 276	struct npcm8xx_gpio *bank =
 277		gpiochip_get_data(irq_data_get_irq_chip_data(d));
 278	unsigned int gpio = irqd_to_hwirq(d);
 279
 280	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC);
 281}
 282
 283static void npcmgpio_irq_unmask(struct irq_data *d)
 284{
 285	struct npcm8xx_gpio *bank =
 286		gpiochip_get_data(irq_data_get_irq_chip_data(d));
 287	unsigned int gpio = irqd_to_hwirq(d);
 288
 289	iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS);
 290}
 291
 292static unsigned int npcmgpio_irq_startup(struct irq_data *d)
 293{
 294	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 295	unsigned int gpio = irqd_to_hwirq(d);
 296
 297	/* active-high, input, clear interrupt, enable interrupt */
 298	npcmgpio_direction_input(gc, gpio);
 299	npcmgpio_irq_ack(d);
 300	npcmgpio_irq_unmask(d);
 301
 302	return 0;
 303}
 304
 305static struct irq_chip npcmgpio_irqchip = {
 306	.name = "NPCM8XX-GPIO-IRQ",
 307	.irq_ack = npcmgpio_irq_ack,
 308	.irq_unmask = npcmgpio_irq_unmask,
 309	.irq_mask = npcmgpio_irq_mask,
 310	.irq_set_type = npcmgpio_set_irq_type,
 311	.irq_startup = npcmgpio_irq_startup,
 312	.flags =  IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
 313	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 314};
 315
 316static const int gpi36_pins[] = { 36 };
 317static const int gpi35_pins[] = { 35 };
 318
 319static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
 320static const int tp_uart_pins[] = { 50, 51 };
 321
 322static const int tp_smb2_pins[] = { 24, 25 };
 323static const int tp_smb1_pins[] = { 142, 143 };
 324
 325static const int tp_gpio7_pins[] = { 96 };
 326static const int tp_gpio6_pins[] = { 97 };
 327static const int tp_gpio5_pins[] = { 98 };
 328static const int tp_gpio4_pins[] = { 99 };
 329static const int tp_gpio3_pins[] = { 100 };
 330static const int tp_gpio2_pins[] = { 16 };
 331static const int tp_gpio1_pins[] = { 9 };
 332static const int tp_gpio0_pins[] = { 8 };
 333
 334static const int tp_gpio2b_pins[] = { 101 };
 335static const int tp_gpio1b_pins[] = { 92 };
 336static const int tp_gpio0b_pins[] = { 91 };
 337
 338static const int vgadig_pins[] = { 102, 103, 104, 105 };
 339
 340static const int nbu1crts_pins[] = { 44, 62 };
 341
 342static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 };
 343static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 };
 344static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 };
 345
 346static const int gpio1836_pins[] = { 183, 184, 185, 186 };
 347static const int gpio1889_pins[] = { 188, 189 };
 348static const int gpo187_pins[] = { 187 };
 349
 350static const int cp1urxd_pins[] = { 41 };
 351static const int r3rxer_pins[] = { 212 };
 352
 353static const int cp1gpio2c_pins[] = { 101 };
 354static const int cp1gpio3c_pins[] = { 100 };
 355
 356static const int cp1gpio0b_pins[] = { 127 };
 357static const int cp1gpio1b_pins[] = { 126 };
 358static const int cp1gpio2b_pins[] = { 125 };
 359static const int cp1gpio3b_pins[] = { 124 };
 360static const int cp1gpio4b_pins[] = { 99 };
 361static const int cp1gpio5b_pins[] = { 98 };
 362static const int cp1gpio6b_pins[] = { 97 };
 363static const int cp1gpio7b_pins[] = { 96 };
 364
 365static const int cp1gpio0_pins[] = {  };
 366static const int cp1gpio1_pins[] = {  };
 367static const int cp1gpio2_pins[] = {  };
 368static const int cp1gpio3_pins[] = {  };
 369static const int cp1gpio4_pins[] = {  };
 370static const int cp1gpio5_pins[] = { 17 };
 371static const int cp1gpio6_pins[] = { 91 };
 372static const int cp1gpio7_pins[] = { 92 };
 373
 374static const int cp1utxd_pins[] = { 42 };
 375
 376static const int spi1cs3_pins[] = { 192 };
 377static const int spi1cs2_pins[] = { 191 };
 378static const int spi1cs1_pins[] = { 233 };
 379static const int spi1cs0_pins[] = { 203 };
 380
 381static const int spi1d23_pins[] = { 191, 192 };
 382
 383static const int j2j3_pins[] = { 44, 62, 45, 46 };
 384
 385static const int r3oen_pins[] = { 213 };
 386static const int r2oen_pins[] = { 90 };
 387static const int r1oen_pins[] = { 56 };
 388static const int bu4b_pins[] = { 98, 99 };
 389static const int bu4_pins[] = { 54, 55 };
 390static const int bu5b_pins[] = { 100, 101 };
 391static const int bu5_pins[] = { 52, 53 };
 392static const int bu6_pins[] = { 50, 51 };
 393static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 };
 394
 395static const int jm1_pins[] = { 136, 137, 138, 139, 140 };
 396static const int jm2_pins[] = { 251 };
 397
 398static const int tpgpio5b_pins[] = { 58 };
 399static const int tpgpio4b_pins[] = { 57 };
 400
 401static const int clkrun_pins[] = { 162 };
 402
 403static const int i3c5_pins[] = { 106, 107 };
 404static const int i3c4_pins[] = { 33, 34 };
 405static const int i3c3_pins[] = { 246, 247 };
 406static const int i3c2_pins[] = { 244, 245 };
 407static const int i3c1_pins[] = { 242, 243 };
 408static const int i3c0_pins[] = { 240, 241 };
 409
 410static const int hsi1a_pins[] = { 43, 63 };
 411static const int hsi2a_pins[] = { 48, 49 };
 412static const int hsi1b_pins[] = { 44, 62 };
 413static const int hsi2b_pins[] = { 50, 51 };
 414static const int hsi1c_pins[] = { 45, 46, 47, 61 };
 415static const int hsi2c_pins[] = { 45, 46, 47, 61 };
 416
 417static const int smb0_pins[]  = { 115, 114 };
 418static const int smb0b_pins[] = { 195, 194 };
 419static const int smb0c_pins[] = { 202, 196 };
 420static const int smb0d_pins[] = { 198, 199 };
 421static const int smb0den_pins[] = { 197 };
 422static const int smb1_pins[]  = { 117, 116 };
 423static const int smb1b_pins[] = { 126, 127 };
 424static const int smb1c_pins[] = { 124, 125 };
 425static const int smb1d_pins[] = { 4, 5 };
 426static const int smb2_pins[]  = { 119, 118 };
 427static const int smb2b_pins[] = { 122, 123 };
 428static const int smb2c_pins[] = { 120, 121 };
 429static const int smb2d_pins[] = { 6, 7 };
 430static const int smb3_pins[]  = { 30, 31 };
 431static const int smb3b_pins[] = { 39, 40 };
 432static const int smb3c_pins[] = { 37, 38 };
 433static const int smb3d_pins[] = { 59, 60 };
 434static const int smb4_pins[]  = { 28, 29 };
 435static const int smb4b_pins[] = { 18, 19 };
 436static const int smb4c_pins[] = { 20, 21 };
 437static const int smb4d_pins[] = { 22, 23 };
 438static const int smb5_pins[]  = { 26, 27 };
 439static const int smb5b_pins[] = { 13, 12 };
 440static const int smb5c_pins[] = { 15, 14 };
 441static const int smb5d_pins[] = { 94, 93 };
 442static const int ga20kbc_pins[] = { 94, 93 };
 443
 444static const int smb6_pins[]  = { 172, 171 };
 445static const int smb6b_pins[] = { 2, 3 };
 446static const int smb6c_pins[]  = { 0, 1 };
 447static const int smb6d_pins[]  = { 10, 11 };
 448static const int smb7_pins[]  = { 174, 173 };
 449static const int smb7b_pins[]  = { 16, 141 };
 450static const int smb7c_pins[]  = { 24, 25 };
 451static const int smb7d_pins[]  = { 142, 143 };
 452static const int smb8_pins[]  = { 129, 128 };
 453static const int smb9_pins[]  = { 131, 130 };
 454static const int smb10_pins[] = { 133, 132 };
 455static const int smb11_pins[] = { 135, 134 };
 456static const int smb12_pins[] = { 221, 220 };
 457static const int smb13_pins[] = { 223, 222 };
 458static const int smb14_pins[] = { 22, 23 };
 459static const int smb14b_pins[] = { 32, 187 };
 460static const int smb15_pins[] = { 20, 21 };
 461static const int smb15b_pins[] = { 192, 191 };
 462
 463static const int smb16_pins[] = { 10, 11 };
 464static const int smb16b_pins[] = { 218, 219 };
 465static const int smb17_pins[] = { 3, 2 };
 466static const int smb18_pins[] = { 0, 1 };
 467static const int smb19_pins[] = { 60, 59 };
 468static const int smb20_pins[] = { 234, 235 };
 469static const int smb21_pins[] = { 169, 170 };
 470static const int smb22_pins[] = { 40, 39 };
 471static const int smb23_pins[] = { 38, 37 };
 472static const int smb23b_pins[] = { 134, 135 };
 473
 474static const int fanin0_pins[] = { 64 };
 475static const int fanin1_pins[] = { 65 };
 476static const int fanin2_pins[] = { 66 };
 477static const int fanin3_pins[] = { 67 };
 478static const int fanin4_pins[] = { 68 };
 479static const int fanin5_pins[] = { 69 };
 480static const int fanin6_pins[] = { 70 };
 481static const int fanin7_pins[] = { 71 };
 482static const int fanin8_pins[] = { 72 };
 483static const int fanin9_pins[] = { 73 };
 484static const int fanin10_pins[] = { 74 };
 485static const int fanin11_pins[] = { 75 };
 486static const int fanin12_pins[] = { 76 };
 487static const int fanin13_pins[] = { 77 };
 488static const int fanin14_pins[] = { 78 };
 489static const int fanin15_pins[] = { 79 };
 490static const int faninx_pins[] = { 175, 176, 177, 203 };
 491
 492static const int pwm0_pins[] = { 80 };
 493static const int pwm1_pins[] = { 81 };
 494static const int pwm2_pins[] = { 82 };
 495static const int pwm3_pins[] = { 83 };
 496static const int pwm4_pins[] = { 144 };
 497static const int pwm5_pins[] = { 145 };
 498static const int pwm6_pins[] = { 146 };
 499static const int pwm7_pins[] = { 147 };
 500static const int pwm8_pins[] = { 220 };
 501static const int pwm9_pins[] = { 221 };
 502static const int pwm10_pins[] = { 234 };
 503static const int pwm11_pins[] = { 235 };
 504
 505static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 };
 506static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
 507
 508static const int sg1mdio_pins[] = { 108, 109 };
 509
 510static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
 511	213, 214, 215 };
 512static const int rg2mdio_pins[] = { 216, 217 };
 513
 514static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
 515	213, 214, 215, 216, 217, 250 };
 516
 517static const int iox1_pins[] = { 0, 1, 2, 3 };
 518static const int iox2_pins[] = { 4, 5, 6, 7 };
 519static const int ioxh_pins[] = { 10, 11, 24, 25 };
 520
 521static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
 522static const int mmcwp_pins[] = { 153 };
 523static const int mmccd_pins[] = { 155 };
 524static const int mmcrst_pins[] = { 155 };
 525static const int mmc8_pins[] = { 148, 149, 150, 151 };
 526
 527static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
 528static const int r1err_pins[] = { 56 };
 529static const int r1md_pins[] = { 57, 58 };
 530static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
 531static const int r2err_pins[] = { 90 };
 532static const int r2md_pins[] = { 91, 92 };
 533static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
 534static const int sd1pwr_pins[] = { 143 };
 535
 536static const int wdog1_pins[] = { 218 };
 537static const int wdog2_pins[] = { 219 };
 538
 539static const int bmcuart0a_pins[] = { 41, 42 };
 540static const int bmcuart0b_pins[] = { 48, 49 };
 541static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
 542
 543static const int scipme_pins[] = { 169 };
 544static const int smi_pins[] = { 170 };
 545static const int serirq_pins[] = { 168 };
 546
 547static const int clkout_pins[] = { 160 };
 548static const int clkreq_pins[] = { 231 };
 549
 550static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
 551static const int gspi_pins[] = { 12, 13, 14, 15 };
 552
 553static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
 554static const int spixcs1_pins[] = { 228 };
 555
 556static const int spi1_pins[] = { 175, 176, 177 };
 557static const int pspi_pins[] = { 17, 18, 19 };
 558
 559static const int spi0cs1_pins[] = { 32 };
 560
 561static const int spi3_pins[] = { 183, 184, 185, 186 };
 562static const int spi3cs1_pins[] = { 187 };
 563static const int spi3quad_pins[] = { 188, 189 };
 564static const int spi3cs2_pins[] = { 188 };
 565static const int spi3cs3_pins[] = { 189 };
 566
 567static const int ddc_pins[] = { 204, 205, 206, 207 };
 568
 569static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
 570static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
 571
 572static const int lkgpo0_pins[] = { 16 };
 573static const int lkgpo1_pins[] = { 8 };
 574static const int lkgpo2_pins[] = { 9 };
 575
 576static const int nprd_smi_pins[] = { 190 };
 577
 578static const int hgpio0_pins[] = { 20 };
 579static const int hgpio1_pins[] = { 21 };
 580static const int hgpio2_pins[] = { 22 };
 581static const int hgpio3_pins[] = { 23 };
 582static const int hgpio4_pins[] = { 24 };
 583static const int hgpio5_pins[] = { 25 };
 584static const int hgpio6_pins[] = { 59 };
 585static const int hgpio7_pins[] = { 60 };
 586
 587#define NPCM8XX_GRPS \
 588	NPCM8XX_GRP(gpi36), \
 589	NPCM8XX_GRP(gpi35), \
 590	NPCM8XX_GRP(tp_jtag3), \
 591	NPCM8XX_GRP(tp_uart), \
 592	NPCM8XX_GRP(tp_smb2), \
 593	NPCM8XX_GRP(tp_smb1), \
 594	NPCM8XX_GRP(tp_gpio7), \
 595	NPCM8XX_GRP(tp_gpio6), \
 596	NPCM8XX_GRP(tp_gpio5), \
 597	NPCM8XX_GRP(tp_gpio4), \
 598	NPCM8XX_GRP(tp_gpio3), \
 599	NPCM8XX_GRP(tp_gpio2), \
 600	NPCM8XX_GRP(tp_gpio1), \
 601	NPCM8XX_GRP(tp_gpio0), \
 602	NPCM8XX_GRP(tp_gpio2b), \
 603	NPCM8XX_GRP(tp_gpio1b), \
 604	NPCM8XX_GRP(tp_gpio0b), \
 605	NPCM8XX_GRP(vgadig), \
 606	NPCM8XX_GRP(nbu1crts), \
 607	NPCM8XX_GRP(fm2), \
 608	NPCM8XX_GRP(fm1), \
 609	NPCM8XX_GRP(fm0), \
 610	NPCM8XX_GRP(gpio1836), \
 611	NPCM8XX_GRP(gpio1889), \
 612	NPCM8XX_GRP(gpo187), \
 613	NPCM8XX_GRP(cp1urxd), \
 614	NPCM8XX_GRP(r3rxer), \
 615	NPCM8XX_GRP(cp1gpio2c), \
 616	NPCM8XX_GRP(cp1gpio3c), \
 617	NPCM8XX_GRP(cp1gpio0b), \
 618	NPCM8XX_GRP(cp1gpio1b), \
 619	NPCM8XX_GRP(cp1gpio2b), \
 620	NPCM8XX_GRP(cp1gpio3b), \
 621	NPCM8XX_GRP(cp1gpio4b), \
 622	NPCM8XX_GRP(cp1gpio5b), \
 623	NPCM8XX_GRP(cp1gpio6b), \
 624	NPCM8XX_GRP(cp1gpio7b), \
 625	NPCM8XX_GRP(cp1gpio0), \
 626	NPCM8XX_GRP(cp1gpio1), \
 627	NPCM8XX_GRP(cp1gpio2), \
 628	NPCM8XX_GRP(cp1gpio3), \
 629	NPCM8XX_GRP(cp1gpio4), \
 630	NPCM8XX_GRP(cp1gpio5), \
 631	NPCM8XX_GRP(cp1gpio6), \
 632	NPCM8XX_GRP(cp1gpio7), \
 633	NPCM8XX_GRP(cp1utxd), \
 634	NPCM8XX_GRP(spi1cs3), \
 635	NPCM8XX_GRP(spi1cs2), \
 636	NPCM8XX_GRP(spi1cs1), \
 637	NPCM8XX_GRP(spi1cs0), \
 638	NPCM8XX_GRP(spi1d23), \
 639	NPCM8XX_GRP(j2j3), \
 640	NPCM8XX_GRP(r3oen), \
 641	NPCM8XX_GRP(r2oen), \
 642	NPCM8XX_GRP(r1oen), \
 643	NPCM8XX_GRP(bu4b), \
 644	NPCM8XX_GRP(bu4), \
 645	NPCM8XX_GRP(bu5b), \
 646	NPCM8XX_GRP(bu5), \
 647	NPCM8XX_GRP(bu6), \
 648	NPCM8XX_GRP(rmii3), \
 649	NPCM8XX_GRP(jm1), \
 650	NPCM8XX_GRP(jm2), \
 651	NPCM8XX_GRP(tpgpio5b), \
 652	NPCM8XX_GRP(tpgpio4b), \
 653	NPCM8XX_GRP(clkrun), \
 654	NPCM8XX_GRP(i3c5), \
 655	NPCM8XX_GRP(i3c4), \
 656	NPCM8XX_GRP(i3c3), \
 657	NPCM8XX_GRP(i3c2), \
 658	NPCM8XX_GRP(i3c1), \
 659	NPCM8XX_GRP(i3c0), \
 660	NPCM8XX_GRP(hsi1a), \
 661	NPCM8XX_GRP(hsi2a), \
 662	NPCM8XX_GRP(hsi1b), \
 663	NPCM8XX_GRP(hsi2b), \
 664	NPCM8XX_GRP(hsi1c), \
 665	NPCM8XX_GRP(hsi2c), \
 666	NPCM8XX_GRP(smb0), \
 667	NPCM8XX_GRP(smb0b), \
 668	NPCM8XX_GRP(smb0c), \
 669	NPCM8XX_GRP(smb0d), \
 670	NPCM8XX_GRP(smb0den), \
 671	NPCM8XX_GRP(smb1), \
 672	NPCM8XX_GRP(smb1b), \
 673	NPCM8XX_GRP(smb1c), \
 674	NPCM8XX_GRP(smb1d), \
 675	NPCM8XX_GRP(smb2), \
 676	NPCM8XX_GRP(smb2b), \
 677	NPCM8XX_GRP(smb2c), \
 678	NPCM8XX_GRP(smb2d), \
 679	NPCM8XX_GRP(smb3), \
 680	NPCM8XX_GRP(smb3b), \
 681	NPCM8XX_GRP(smb3c), \
 682	NPCM8XX_GRP(smb3d), \
 683	NPCM8XX_GRP(smb4), \
 684	NPCM8XX_GRP(smb4b), \
 685	NPCM8XX_GRP(smb4c), \
 686	NPCM8XX_GRP(smb4d), \
 687	NPCM8XX_GRP(smb5), \
 688	NPCM8XX_GRP(smb5b), \
 689	NPCM8XX_GRP(smb5c), \
 690	NPCM8XX_GRP(smb5d), \
 691	NPCM8XX_GRP(ga20kbc), \
 692	NPCM8XX_GRP(smb6), \
 693	NPCM8XX_GRP(smb6b), \
 694	NPCM8XX_GRP(smb6c), \
 695	NPCM8XX_GRP(smb6d), \
 696	NPCM8XX_GRP(smb7), \
 697	NPCM8XX_GRP(smb7b), \
 698	NPCM8XX_GRP(smb7c), \
 699	NPCM8XX_GRP(smb7d), \
 700	NPCM8XX_GRP(smb8), \
 701	NPCM8XX_GRP(smb9), \
 702	NPCM8XX_GRP(smb10), \
 703	NPCM8XX_GRP(smb11), \
 704	NPCM8XX_GRP(smb12), \
 705	NPCM8XX_GRP(smb13), \
 706	NPCM8XX_GRP(smb14), \
 707	NPCM8XX_GRP(smb14b), \
 708	NPCM8XX_GRP(smb15), \
 709	NPCM8XX_GRP(smb15b), \
 710	NPCM8XX_GRP(smb16), \
 711	NPCM8XX_GRP(smb16b), \
 712	NPCM8XX_GRP(smb17), \
 713	NPCM8XX_GRP(smb18), \
 714	NPCM8XX_GRP(smb19), \
 715	NPCM8XX_GRP(smb20), \
 716	NPCM8XX_GRP(smb21), \
 717	NPCM8XX_GRP(smb22), \
 718	NPCM8XX_GRP(smb23), \
 719	NPCM8XX_GRP(smb23b), \
 720	NPCM8XX_GRP(fanin0), \
 721	NPCM8XX_GRP(fanin1), \
 722	NPCM8XX_GRP(fanin2), \
 723	NPCM8XX_GRP(fanin3), \
 724	NPCM8XX_GRP(fanin4), \
 725	NPCM8XX_GRP(fanin5), \
 726	NPCM8XX_GRP(fanin6), \
 727	NPCM8XX_GRP(fanin7), \
 728	NPCM8XX_GRP(fanin8), \
 729	NPCM8XX_GRP(fanin9), \
 730	NPCM8XX_GRP(fanin10), \
 731	NPCM8XX_GRP(fanin11), \
 732	NPCM8XX_GRP(fanin12), \
 733	NPCM8XX_GRP(fanin13), \
 734	NPCM8XX_GRP(fanin14), \
 735	NPCM8XX_GRP(fanin15), \
 736	NPCM8XX_GRP(faninx), \
 737	NPCM8XX_GRP(pwm0), \
 738	NPCM8XX_GRP(pwm1), \
 739	NPCM8XX_GRP(pwm2), \
 740	NPCM8XX_GRP(pwm3), \
 741	NPCM8XX_GRP(pwm4), \
 742	NPCM8XX_GRP(pwm5), \
 743	NPCM8XX_GRP(pwm6), \
 744	NPCM8XX_GRP(pwm7), \
 745	NPCM8XX_GRP(pwm8), \
 746	NPCM8XX_GRP(pwm9), \
 747	NPCM8XX_GRP(pwm10), \
 748	NPCM8XX_GRP(pwm11), \
 749	NPCM8XX_GRP(sg1mdio), \
 750	NPCM8XX_GRP(rg2), \
 751	NPCM8XX_GRP(rg2mdio), \
 752	NPCM8XX_GRP(ddr), \
 753	NPCM8XX_GRP(uart1), \
 754	NPCM8XX_GRP(uart2), \
 755	NPCM8XX_GRP(bmcuart0a), \
 756	NPCM8XX_GRP(bmcuart0b), \
 757	NPCM8XX_GRP(bmcuart1), \
 758	NPCM8XX_GRP(iox1), \
 759	NPCM8XX_GRP(iox2), \
 760	NPCM8XX_GRP(ioxh), \
 761	NPCM8XX_GRP(gspi), \
 762	NPCM8XX_GRP(mmc), \
 763	NPCM8XX_GRP(mmcwp), \
 764	NPCM8XX_GRP(mmccd), \
 765	NPCM8XX_GRP(mmcrst), \
 766	NPCM8XX_GRP(mmc8), \
 767	NPCM8XX_GRP(r1), \
 768	NPCM8XX_GRP(r1err), \
 769	NPCM8XX_GRP(r1md), \
 770	NPCM8XX_GRP(r2), \
 771	NPCM8XX_GRP(r2err), \
 772	NPCM8XX_GRP(r2md), \
 773	NPCM8XX_GRP(sd1), \
 774	NPCM8XX_GRP(sd1pwr), \
 775	NPCM8XX_GRP(wdog1), \
 776	NPCM8XX_GRP(wdog2), \
 777	NPCM8XX_GRP(scipme), \
 778	NPCM8XX_GRP(smi), \
 779	NPCM8XX_GRP(serirq), \
 780	NPCM8XX_GRP(jtag2), \
 781	NPCM8XX_GRP(spix), \
 782	NPCM8XX_GRP(spixcs1), \
 783	NPCM8XX_GRP(spi1), \
 784	NPCM8XX_GRP(pspi), \
 785	NPCM8XX_GRP(ddc), \
 786	NPCM8XX_GRP(clkreq), \
 787	NPCM8XX_GRP(clkout), \
 788	NPCM8XX_GRP(spi3), \
 789	NPCM8XX_GRP(spi3cs1), \
 790	NPCM8XX_GRP(spi3quad), \
 791	NPCM8XX_GRP(spi3cs2), \
 792	NPCM8XX_GRP(spi3cs3), \
 793	NPCM8XX_GRP(spi0cs1), \
 794	NPCM8XX_GRP(lpc), \
 795	NPCM8XX_GRP(espi), \
 796	NPCM8XX_GRP(lkgpo0), \
 797	NPCM8XX_GRP(lkgpo1), \
 798	NPCM8XX_GRP(lkgpo2), \
 799	NPCM8XX_GRP(nprd_smi), \
 800	NPCM8XX_GRP(hgpio0), \
 801	NPCM8XX_GRP(hgpio1), \
 802	NPCM8XX_GRP(hgpio2), \
 803	NPCM8XX_GRP(hgpio3), \
 804	NPCM8XX_GRP(hgpio4), \
 805	NPCM8XX_GRP(hgpio5), \
 806	NPCM8XX_GRP(hgpio6), \
 807	NPCM8XX_GRP(hgpio7), \
 808	\
 809
 810enum {
 811#define NPCM8XX_GRP(x) fn_ ## x
 812	NPCM8XX_GRPS
 813	NPCM8XX_GRP(none),
 814	NPCM8XX_GRP(gpio),
 815#undef NPCM8XX_GRP
 816};
 817
 818static struct pingroup npcm8xx_pingroups[] = {
 819#define NPCM8XX_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins))
 820	NPCM8XX_GRPS
 821#undef NPCM8XX_GRP
 822};
 823
 824#define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a)
 825#define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
 826
 827NPCM8XX_SFUNC(gpi36);
 828NPCM8XX_SFUNC(gpi35);
 829NPCM8XX_SFUNC(tp_jtag3);
 830NPCM8XX_SFUNC(tp_uart);
 831NPCM8XX_SFUNC(tp_smb2);
 832NPCM8XX_SFUNC(tp_smb1);
 833NPCM8XX_SFUNC(tp_gpio7);
 834NPCM8XX_SFUNC(tp_gpio6);
 835NPCM8XX_SFUNC(tp_gpio5);
 836NPCM8XX_SFUNC(tp_gpio4);
 837NPCM8XX_SFUNC(tp_gpio3);
 838NPCM8XX_SFUNC(tp_gpio2);
 839NPCM8XX_SFUNC(tp_gpio1);
 840NPCM8XX_SFUNC(tp_gpio0);
 841NPCM8XX_SFUNC(tp_gpio2b);
 842NPCM8XX_SFUNC(tp_gpio1b);
 843NPCM8XX_SFUNC(tp_gpio0b);
 844NPCM8XX_SFUNC(vgadig);
 845NPCM8XX_SFUNC(nbu1crts);
 846NPCM8XX_SFUNC(fm2);
 847NPCM8XX_SFUNC(fm1);
 848NPCM8XX_SFUNC(fm0);
 849NPCM8XX_SFUNC(gpio1836);
 850NPCM8XX_SFUNC(gpio1889);
 851NPCM8XX_SFUNC(gpo187);
 852NPCM8XX_SFUNC(cp1urxd);
 853NPCM8XX_SFUNC(r3rxer);
 854NPCM8XX_SFUNC(cp1gpio2c);
 855NPCM8XX_SFUNC(cp1gpio3c);
 856NPCM8XX_SFUNC(cp1gpio0b);
 857NPCM8XX_SFUNC(cp1gpio1b);
 858NPCM8XX_SFUNC(cp1gpio2b);
 859NPCM8XX_SFUNC(cp1gpio3b);
 860NPCM8XX_SFUNC(cp1gpio4b);
 861NPCM8XX_SFUNC(cp1gpio5b);
 862NPCM8XX_SFUNC(cp1gpio6b);
 863NPCM8XX_SFUNC(cp1gpio7b);
 864NPCM8XX_SFUNC(cp1gpio0);
 865NPCM8XX_SFUNC(cp1gpio1);
 866NPCM8XX_SFUNC(cp1gpio2);
 867NPCM8XX_SFUNC(cp1gpio3);
 868NPCM8XX_SFUNC(cp1gpio4);
 869NPCM8XX_SFUNC(cp1gpio5);
 870NPCM8XX_SFUNC(cp1gpio6);
 871NPCM8XX_SFUNC(cp1gpio7);
 872NPCM8XX_SFUNC(cp1utxd);
 873NPCM8XX_SFUNC(spi1cs3);
 874NPCM8XX_SFUNC(spi1cs2);
 875NPCM8XX_SFUNC(spi1cs1);
 876NPCM8XX_SFUNC(spi1cs0);
 877NPCM8XX_SFUNC(spi1d23);
 878NPCM8XX_SFUNC(j2j3);
 879NPCM8XX_SFUNC(r3oen);
 880NPCM8XX_SFUNC(r2oen);
 881NPCM8XX_SFUNC(r1oen);
 882NPCM8XX_SFUNC(bu4b);
 883NPCM8XX_SFUNC(bu4);
 884NPCM8XX_SFUNC(bu5b);
 885NPCM8XX_SFUNC(bu5);
 886NPCM8XX_SFUNC(bu6);
 887NPCM8XX_SFUNC(rmii3);
 888NPCM8XX_SFUNC(jm1);
 889NPCM8XX_SFUNC(jm2);
 890NPCM8XX_SFUNC(tpgpio5b);
 891NPCM8XX_SFUNC(tpgpio4b);
 892NPCM8XX_SFUNC(clkrun);
 893NPCM8XX_SFUNC(i3c5);
 894NPCM8XX_SFUNC(i3c4);
 895NPCM8XX_SFUNC(i3c3);
 896NPCM8XX_SFUNC(i3c2);
 897NPCM8XX_SFUNC(i3c1);
 898NPCM8XX_SFUNC(i3c0);
 899NPCM8XX_SFUNC(hsi1a);
 900NPCM8XX_SFUNC(hsi2a);
 901NPCM8XX_SFUNC(hsi1b);
 902NPCM8XX_SFUNC(hsi2b);
 903NPCM8XX_SFUNC(hsi1c);
 904NPCM8XX_SFUNC(hsi2c);
 905NPCM8XX_SFUNC(smb0);
 906NPCM8XX_SFUNC(smb0b);
 907NPCM8XX_SFUNC(smb0c);
 908NPCM8XX_SFUNC(smb0d);
 909NPCM8XX_SFUNC(smb0den);
 910NPCM8XX_SFUNC(smb1);
 911NPCM8XX_SFUNC(smb1b);
 912NPCM8XX_SFUNC(smb1c);
 913NPCM8XX_SFUNC(smb1d);
 914NPCM8XX_SFUNC(smb2);
 915NPCM8XX_SFUNC(smb2b);
 916NPCM8XX_SFUNC(smb2c);
 917NPCM8XX_SFUNC(smb2d);
 918NPCM8XX_SFUNC(smb3);
 919NPCM8XX_SFUNC(smb3b);
 920NPCM8XX_SFUNC(smb3c);
 921NPCM8XX_SFUNC(smb3d);
 922NPCM8XX_SFUNC(smb4);
 923NPCM8XX_SFUNC(smb4b);
 924NPCM8XX_SFUNC(smb4c);
 925NPCM8XX_SFUNC(smb4d);
 926NPCM8XX_SFUNC(smb5);
 927NPCM8XX_SFUNC(smb5b);
 928NPCM8XX_SFUNC(smb5c);
 929NPCM8XX_SFUNC(smb5d);
 930NPCM8XX_SFUNC(ga20kbc);
 931NPCM8XX_SFUNC(smb6);
 932NPCM8XX_SFUNC(smb6b);
 933NPCM8XX_SFUNC(smb6c);
 934NPCM8XX_SFUNC(smb6d);
 935NPCM8XX_SFUNC(smb7);
 936NPCM8XX_SFUNC(smb7b);
 937NPCM8XX_SFUNC(smb7c);
 938NPCM8XX_SFUNC(smb7d);
 939NPCM8XX_SFUNC(smb8);
 940NPCM8XX_SFUNC(smb9);
 941NPCM8XX_SFUNC(smb10);
 942NPCM8XX_SFUNC(smb11);
 943NPCM8XX_SFUNC(smb12);
 944NPCM8XX_SFUNC(smb13);
 945NPCM8XX_SFUNC(smb14);
 946NPCM8XX_SFUNC(smb14b);
 947NPCM8XX_SFUNC(smb15);
 948NPCM8XX_SFUNC(smb16);
 949NPCM8XX_SFUNC(smb16b);
 950NPCM8XX_SFUNC(smb17);
 951NPCM8XX_SFUNC(smb18);
 952NPCM8XX_SFUNC(smb19);
 953NPCM8XX_SFUNC(smb20);
 954NPCM8XX_SFUNC(smb21);
 955NPCM8XX_SFUNC(smb22);
 956NPCM8XX_SFUNC(smb23);
 957NPCM8XX_SFUNC(smb23b);
 958NPCM8XX_SFUNC(fanin0);
 959NPCM8XX_SFUNC(fanin1);
 960NPCM8XX_SFUNC(fanin2);
 961NPCM8XX_SFUNC(fanin3);
 962NPCM8XX_SFUNC(fanin4);
 963NPCM8XX_SFUNC(fanin5);
 964NPCM8XX_SFUNC(fanin6);
 965NPCM8XX_SFUNC(fanin7);
 966NPCM8XX_SFUNC(fanin8);
 967NPCM8XX_SFUNC(fanin9);
 968NPCM8XX_SFUNC(fanin10);
 969NPCM8XX_SFUNC(fanin11);
 970NPCM8XX_SFUNC(fanin12);
 971NPCM8XX_SFUNC(fanin13);
 972NPCM8XX_SFUNC(fanin14);
 973NPCM8XX_SFUNC(fanin15);
 974NPCM8XX_SFUNC(faninx);
 975NPCM8XX_SFUNC(pwm0);
 976NPCM8XX_SFUNC(pwm1);
 977NPCM8XX_SFUNC(pwm2);
 978NPCM8XX_SFUNC(pwm3);
 979NPCM8XX_SFUNC(pwm4);
 980NPCM8XX_SFUNC(pwm5);
 981NPCM8XX_SFUNC(pwm6);
 982NPCM8XX_SFUNC(pwm7);
 983NPCM8XX_SFUNC(pwm8);
 984NPCM8XX_SFUNC(pwm9);
 985NPCM8XX_SFUNC(pwm10);
 986NPCM8XX_SFUNC(pwm11);
 987NPCM8XX_SFUNC(sg1mdio);
 988NPCM8XX_SFUNC(rg2);
 989NPCM8XX_SFUNC(rg2mdio);
 990NPCM8XX_SFUNC(ddr);
 991NPCM8XX_SFUNC(uart1);
 992NPCM8XX_SFUNC(uart2);
 993NPCM8XX_SFUNC(bmcuart0a);
 994NPCM8XX_SFUNC(bmcuart0b);
 995NPCM8XX_SFUNC(bmcuart1);
 996NPCM8XX_SFUNC(iox1);
 997NPCM8XX_SFUNC(iox2);
 998NPCM8XX_SFUNC(ioxh);
 999NPCM8XX_SFUNC(gspi);
1000NPCM8XX_SFUNC(mmc);
1001NPCM8XX_SFUNC(mmcwp);
1002NPCM8XX_SFUNC(mmccd);
1003NPCM8XX_SFUNC(mmcrst);
1004NPCM8XX_SFUNC(mmc8);
1005NPCM8XX_SFUNC(r1);
1006NPCM8XX_SFUNC(r1err);
1007NPCM8XX_SFUNC(r1md);
1008NPCM8XX_SFUNC(r2);
1009NPCM8XX_SFUNC(r2err);
1010NPCM8XX_SFUNC(r2md);
1011NPCM8XX_SFUNC(sd1);
1012NPCM8XX_SFUNC(sd1pwr);
1013NPCM8XX_SFUNC(wdog1);
1014NPCM8XX_SFUNC(wdog2);
1015NPCM8XX_SFUNC(scipme);
1016NPCM8XX_SFUNC(smi);
1017NPCM8XX_SFUNC(serirq);
1018NPCM8XX_SFUNC(jtag2);
1019NPCM8XX_SFUNC(spix);
1020NPCM8XX_SFUNC(spixcs1);
1021NPCM8XX_SFUNC(spi1);
1022NPCM8XX_SFUNC(pspi);
1023NPCM8XX_SFUNC(ddc);
1024NPCM8XX_SFUNC(clkreq);
1025NPCM8XX_SFUNC(clkout);
1026NPCM8XX_SFUNC(spi3);
1027NPCM8XX_SFUNC(spi3cs1);
1028NPCM8XX_SFUNC(spi3quad);
1029NPCM8XX_SFUNC(spi3cs2);
1030NPCM8XX_SFUNC(spi3cs3);
1031NPCM8XX_SFUNC(spi0cs1);
1032NPCM8XX_SFUNC(lpc);
1033NPCM8XX_SFUNC(espi);
1034NPCM8XX_SFUNC(lkgpo0);
1035NPCM8XX_SFUNC(lkgpo1);
1036NPCM8XX_SFUNC(lkgpo2);
1037NPCM8XX_SFUNC(nprd_smi);
1038NPCM8XX_SFUNC(hgpio0);
1039NPCM8XX_SFUNC(hgpio1);
1040NPCM8XX_SFUNC(hgpio2);
1041NPCM8XX_SFUNC(hgpio3);
1042NPCM8XX_SFUNC(hgpio4);
1043NPCM8XX_SFUNC(hgpio5);
1044NPCM8XX_SFUNC(hgpio6);
1045NPCM8XX_SFUNC(hgpio7);
1046
1047/* Function names */
1048static struct pinfunction npcm8xx_funcs[] = {
1049#define NPCM8XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp))
1050	NPCM8XX_MKFUNC(gpi36),
1051	NPCM8XX_MKFUNC(gpi35),
1052	NPCM8XX_MKFUNC(tp_jtag3),
1053	NPCM8XX_MKFUNC(tp_uart),
1054	NPCM8XX_MKFUNC(tp_smb2),
1055	NPCM8XX_MKFUNC(tp_smb1),
1056	NPCM8XX_MKFUNC(tp_gpio7),
1057	NPCM8XX_MKFUNC(tp_gpio6),
1058	NPCM8XX_MKFUNC(tp_gpio5),
1059	NPCM8XX_MKFUNC(tp_gpio4),
1060	NPCM8XX_MKFUNC(tp_gpio3),
1061	NPCM8XX_MKFUNC(tp_gpio2),
1062	NPCM8XX_MKFUNC(tp_gpio1),
1063	NPCM8XX_MKFUNC(tp_gpio0),
1064	NPCM8XX_MKFUNC(tp_gpio2b),
1065	NPCM8XX_MKFUNC(tp_gpio1b),
1066	NPCM8XX_MKFUNC(tp_gpio0b),
1067	NPCM8XX_MKFUNC(vgadig),
1068	NPCM8XX_MKFUNC(nbu1crts),
1069	NPCM8XX_MKFUNC(fm2),
1070	NPCM8XX_MKFUNC(fm1),
1071	NPCM8XX_MKFUNC(fm0),
1072	NPCM8XX_MKFUNC(gpio1836),
1073	NPCM8XX_MKFUNC(gpio1889),
1074	NPCM8XX_MKFUNC(gpo187),
1075	NPCM8XX_MKFUNC(cp1urxd),
1076	NPCM8XX_MKFUNC(r3rxer),
1077	NPCM8XX_MKFUNC(cp1gpio2c),
1078	NPCM8XX_MKFUNC(cp1gpio3c),
1079	NPCM8XX_MKFUNC(cp1gpio0b),
1080	NPCM8XX_MKFUNC(cp1gpio1b),
1081	NPCM8XX_MKFUNC(cp1gpio2b),
1082	NPCM8XX_MKFUNC(cp1gpio3b),
1083	NPCM8XX_MKFUNC(cp1gpio4b),
1084	NPCM8XX_MKFUNC(cp1gpio5b),
1085	NPCM8XX_MKFUNC(cp1gpio6b),
1086	NPCM8XX_MKFUNC(cp1gpio7b),
1087	NPCM8XX_MKFUNC(cp1gpio0),
1088	NPCM8XX_MKFUNC(cp1gpio1),
1089	NPCM8XX_MKFUNC(cp1gpio2),
1090	NPCM8XX_MKFUNC(cp1gpio3),
1091	NPCM8XX_MKFUNC(cp1gpio4),
1092	NPCM8XX_MKFUNC(cp1gpio5),
1093	NPCM8XX_MKFUNC(cp1gpio6),
1094	NPCM8XX_MKFUNC(cp1gpio7),
1095	NPCM8XX_MKFUNC(cp1utxd),
1096	NPCM8XX_MKFUNC(spi1cs3),
1097	NPCM8XX_MKFUNC(spi1cs2),
1098	NPCM8XX_MKFUNC(spi1cs1),
1099	NPCM8XX_MKFUNC(spi1cs0),
1100	NPCM8XX_MKFUNC(spi1d23),
1101	NPCM8XX_MKFUNC(j2j3),
1102	NPCM8XX_MKFUNC(r3oen),
1103	NPCM8XX_MKFUNC(r2oen),
1104	NPCM8XX_MKFUNC(r1oen),
1105	NPCM8XX_MKFUNC(bu4b),
1106	NPCM8XX_MKFUNC(bu4),
1107	NPCM8XX_MKFUNC(bu5b),
1108	NPCM8XX_MKFUNC(bu5),
1109	NPCM8XX_MKFUNC(bu6),
1110	NPCM8XX_MKFUNC(rmii3),
1111	NPCM8XX_MKFUNC(jm1),
1112	NPCM8XX_MKFUNC(jm2),
1113	NPCM8XX_MKFUNC(tpgpio5b),
1114	NPCM8XX_MKFUNC(tpgpio4b),
1115	NPCM8XX_MKFUNC(clkrun),
1116	NPCM8XX_MKFUNC(i3c5),
1117	NPCM8XX_MKFUNC(i3c4),
1118	NPCM8XX_MKFUNC(i3c3),
1119	NPCM8XX_MKFUNC(i3c2),
1120	NPCM8XX_MKFUNC(i3c1),
1121	NPCM8XX_MKFUNC(i3c0),
1122	NPCM8XX_MKFUNC(hsi1a),
1123	NPCM8XX_MKFUNC(hsi2a),
1124	NPCM8XX_MKFUNC(hsi1b),
1125	NPCM8XX_MKFUNC(hsi2b),
1126	NPCM8XX_MKFUNC(hsi1c),
1127	NPCM8XX_MKFUNC(hsi2c),
1128	NPCM8XX_MKFUNC(smb0),
1129	NPCM8XX_MKFUNC(smb0b),
1130	NPCM8XX_MKFUNC(smb0c),
1131	NPCM8XX_MKFUNC(smb0d),
1132	NPCM8XX_MKFUNC(smb0den),
1133	NPCM8XX_MKFUNC(smb1),
1134	NPCM8XX_MKFUNC(smb1b),
1135	NPCM8XX_MKFUNC(smb1c),
1136	NPCM8XX_MKFUNC(smb1d),
1137	NPCM8XX_MKFUNC(smb2),
1138	NPCM8XX_MKFUNC(smb2b),
1139	NPCM8XX_MKFUNC(smb2c),
1140	NPCM8XX_MKFUNC(smb2d),
1141	NPCM8XX_MKFUNC(smb3),
1142	NPCM8XX_MKFUNC(smb3b),
1143	NPCM8XX_MKFUNC(smb3c),
1144	NPCM8XX_MKFUNC(smb3d),
1145	NPCM8XX_MKFUNC(smb4),
1146	NPCM8XX_MKFUNC(smb4b),
1147	NPCM8XX_MKFUNC(smb4c),
1148	NPCM8XX_MKFUNC(smb4d),
1149	NPCM8XX_MKFUNC(smb5),
1150	NPCM8XX_MKFUNC(smb5b),
1151	NPCM8XX_MKFUNC(smb5c),
1152	NPCM8XX_MKFUNC(smb5d),
1153	NPCM8XX_MKFUNC(ga20kbc),
1154	NPCM8XX_MKFUNC(smb6),
1155	NPCM8XX_MKFUNC(smb6b),
1156	NPCM8XX_MKFUNC(smb6c),
1157	NPCM8XX_MKFUNC(smb6d),
1158	NPCM8XX_MKFUNC(smb7),
1159	NPCM8XX_MKFUNC(smb7b),
1160	NPCM8XX_MKFUNC(smb7c),
1161	NPCM8XX_MKFUNC(smb7d),
1162	NPCM8XX_MKFUNC(smb8),
1163	NPCM8XX_MKFUNC(smb9),
1164	NPCM8XX_MKFUNC(smb10),
1165	NPCM8XX_MKFUNC(smb11),
1166	NPCM8XX_MKFUNC(smb12),
1167	NPCM8XX_MKFUNC(smb13),
1168	NPCM8XX_MKFUNC(smb14),
1169	NPCM8XX_MKFUNC(smb14b),
1170	NPCM8XX_MKFUNC(smb15),
1171	NPCM8XX_MKFUNC(smb16),
1172	NPCM8XX_MKFUNC(smb16b),
1173	NPCM8XX_MKFUNC(smb17),
1174	NPCM8XX_MKFUNC(smb18),
1175	NPCM8XX_MKFUNC(smb19),
1176	NPCM8XX_MKFUNC(smb20),
1177	NPCM8XX_MKFUNC(smb21),
1178	NPCM8XX_MKFUNC(smb22),
1179	NPCM8XX_MKFUNC(smb23),
1180	NPCM8XX_MKFUNC(smb23b),
1181	NPCM8XX_MKFUNC(fanin0),
1182	NPCM8XX_MKFUNC(fanin1),
1183	NPCM8XX_MKFUNC(fanin2),
1184	NPCM8XX_MKFUNC(fanin3),
1185	NPCM8XX_MKFUNC(fanin4),
1186	NPCM8XX_MKFUNC(fanin5),
1187	NPCM8XX_MKFUNC(fanin6),
1188	NPCM8XX_MKFUNC(fanin7),
1189	NPCM8XX_MKFUNC(fanin8),
1190	NPCM8XX_MKFUNC(fanin9),
1191	NPCM8XX_MKFUNC(fanin10),
1192	NPCM8XX_MKFUNC(fanin11),
1193	NPCM8XX_MKFUNC(fanin12),
1194	NPCM8XX_MKFUNC(fanin13),
1195	NPCM8XX_MKFUNC(fanin14),
1196	NPCM8XX_MKFUNC(fanin15),
1197	NPCM8XX_MKFUNC(faninx),
1198	NPCM8XX_MKFUNC(pwm0),
1199	NPCM8XX_MKFUNC(pwm1),
1200	NPCM8XX_MKFUNC(pwm2),
1201	NPCM8XX_MKFUNC(pwm3),
1202	NPCM8XX_MKFUNC(pwm4),
1203	NPCM8XX_MKFUNC(pwm5),
1204	NPCM8XX_MKFUNC(pwm6),
1205	NPCM8XX_MKFUNC(pwm7),
1206	NPCM8XX_MKFUNC(pwm8),
1207	NPCM8XX_MKFUNC(pwm9),
1208	NPCM8XX_MKFUNC(pwm10),
1209	NPCM8XX_MKFUNC(pwm11),
1210	NPCM8XX_MKFUNC(sg1mdio),
1211	NPCM8XX_MKFUNC(rg2),
1212	NPCM8XX_MKFUNC(rg2mdio),
1213	NPCM8XX_MKFUNC(ddr),
1214	NPCM8XX_MKFUNC(uart1),
1215	NPCM8XX_MKFUNC(uart2),
1216	NPCM8XX_MKFUNC(bmcuart0a),
1217	NPCM8XX_MKFUNC(bmcuart0b),
1218	NPCM8XX_MKFUNC(bmcuart1),
1219	NPCM8XX_MKFUNC(iox1),
1220	NPCM8XX_MKFUNC(iox2),
1221	NPCM8XX_MKFUNC(ioxh),
1222	NPCM8XX_MKFUNC(gspi),
1223	NPCM8XX_MKFUNC(mmc),
1224	NPCM8XX_MKFUNC(mmcwp),
1225	NPCM8XX_MKFUNC(mmccd),
1226	NPCM8XX_MKFUNC(mmcrst),
1227	NPCM8XX_MKFUNC(mmc8),
1228	NPCM8XX_MKFUNC(r1),
1229	NPCM8XX_MKFUNC(r1err),
1230	NPCM8XX_MKFUNC(r1md),
1231	NPCM8XX_MKFUNC(r2),
1232	NPCM8XX_MKFUNC(r2err),
1233	NPCM8XX_MKFUNC(r2md),
1234	NPCM8XX_MKFUNC(sd1),
1235	NPCM8XX_MKFUNC(sd1pwr),
1236	NPCM8XX_MKFUNC(wdog1),
1237	NPCM8XX_MKFUNC(wdog2),
1238	NPCM8XX_MKFUNC(scipme),
1239	NPCM8XX_MKFUNC(smi),
1240	NPCM8XX_MKFUNC(serirq),
1241	NPCM8XX_MKFUNC(jtag2),
1242	NPCM8XX_MKFUNC(spix),
1243	NPCM8XX_MKFUNC(spixcs1),
1244	NPCM8XX_MKFUNC(spi1),
1245	NPCM8XX_MKFUNC(pspi),
1246	NPCM8XX_MKFUNC(ddc),
1247	NPCM8XX_MKFUNC(clkreq),
1248	NPCM8XX_MKFUNC(clkout),
1249	NPCM8XX_MKFUNC(spi3),
1250	NPCM8XX_MKFUNC(spi3cs1),
1251	NPCM8XX_MKFUNC(spi3quad),
1252	NPCM8XX_MKFUNC(spi3cs2),
1253	NPCM8XX_MKFUNC(spi3cs3),
1254	NPCM8XX_MKFUNC(spi0cs1),
1255	NPCM8XX_MKFUNC(lpc),
1256	NPCM8XX_MKFUNC(espi),
1257	NPCM8XX_MKFUNC(lkgpo0),
1258	NPCM8XX_MKFUNC(lkgpo1),
1259	NPCM8XX_MKFUNC(lkgpo2),
1260	NPCM8XX_MKFUNC(nprd_smi),
1261	NPCM8XX_MKFUNC(hgpio0),
1262	NPCM8XX_MKFUNC(hgpio1),
1263	NPCM8XX_MKFUNC(hgpio2),
1264	NPCM8XX_MKFUNC(hgpio3),
1265	NPCM8XX_MKFUNC(hgpio4),
1266	NPCM8XX_MKFUNC(hgpio5),
1267	NPCM8XX_MKFUNC(hgpio6),
1268	NPCM8XX_MKFUNC(hgpio7),
1269#undef NPCM8XX_MKFUNC
1270};
1271
1272#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \
1273	[a] = {								  \
1274			.flag = q,					  \
1275			.fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \
1276			.fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \
1277			.fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \
1278			.fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \
1279			.fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \
1280	}
1281
1282/* Drive strength controlled by NPCM8XX_GP_N_ODSC */
1283#define DRIVE_STRENGTH_LO_SHIFT		8
1284#define DRIVE_STRENGTH_HI_SHIFT		12
1285#define DRIVE_STRENGTH_MASK		GENMASK(15, 8)
1286
1287#define DSTR(lo, hi)	(((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
1288			 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
1289#define DSLO(x)		(((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0))
1290#define DSHI(x)		(((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0))
1291
1292#define GPI		BIT(0) /* Not GPO */
1293#define GPO		BIT(1) /* Not GPI */
1294#define SLEW		BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */
1295#define SLEWLPC		BIT(3) /* Has Slew Control, SRCNT.3 */
1296
1297struct npcm8xx_pincfg {
1298	int flag;
1299	int fn0, reg0, bit0;
1300	int fn1, reg1, bit1;
1301	int fn2, reg2, bit2;
1302	int fn3, reg3, bit3;
1303	int fn4, reg4, bit4;
1304};
1305
1306static const struct npcm8xx_pincfg pincfg[] = {
1307	/*		PIN	  FUNCTION 1		   FUNCTION 2		  FUNCTION 3		FUNCTION 4		FUNCTION 5		FLAGS */
1308	NPCM8XX_PINCFG(0,	iox1, MFSEL1, 30,	smb6c, I2CSEGSEL, 25,	smb18, MFSEL5, 26,	none, NONE, 0,		none, NONE, 0,		SLEW),
1309	NPCM8XX_PINCFG(1,	iox1, MFSEL1, 30,	smb6c, I2CSEGSEL, 25,	smb18, MFSEL5, 26,	none, NONE, 0,		none, NONE, 0,		SLEW),
1310	NPCM8XX_PINCFG(2,	iox1, MFSEL1, 30,	smb6b, I2CSEGSEL, 24,	smb17, MFSEL5, 25,	none, NONE, 0,		none, NONE, 0,		SLEW),
1311	NPCM8XX_PINCFG(3,	iox1, MFSEL1, 30,	smb6b, I2CSEGSEL, 24,	smb17, MFSEL5, 25,	none, NONE, 0,		none, NONE, 0,		SLEW),
1312	NPCM8XX_PINCFG(4,	iox2, MFSEL3, 14,	smb1d, I2CSEGSEL, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1313	NPCM8XX_PINCFG(5,	iox2, MFSEL3, 14,	smb1d, I2CSEGSEL, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1314	NPCM8XX_PINCFG(6,	iox2, MFSEL3, 14,	smb2d, I2CSEGSEL, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1315	NPCM8XX_PINCFG(7,	iox2, MFSEL3, 14,	smb2d, I2CSEGSEL, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1316	NPCM8XX_PINCFG(8,	lkgpo1,	FLOCKR1, 4,	tp_gpio0b, MFSEL7, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1317	NPCM8XX_PINCFG(9,	lkgpo2,	FLOCKR1, 8,	tp_gpio1b, MFSEL7, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1318	NPCM8XX_PINCFG(10,	ioxh, MFSEL3, 18,	smb6d, I2CSEGSEL, 26,	smb16, MFSEL5, 24,	none, NONE, 0,		none, NONE, 0,		SLEW),
1319	NPCM8XX_PINCFG(11,	ioxh, MFSEL3, 18,	smb6d, I2CSEGSEL, 26,	smb16, MFSEL5, 24,	none, NONE, 0,		none, NONE, 0,		SLEW),
1320	NPCM8XX_PINCFG(12,	gspi, MFSEL1, 24,	smb5b, I2CSEGSEL, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1321	NPCM8XX_PINCFG(13,	gspi, MFSEL1, 24,	smb5b, I2CSEGSEL, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1322	NPCM8XX_PINCFG(14,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1323	NPCM8XX_PINCFG(15,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1324	NPCM8XX_PINCFG(16,	lkgpo0, FLOCKR1, 0,	smb7b, I2CSEGSEL, 27,	tp_gpio2b, MFSEL7, 10,	none, NONE, 0,		none, NONE, 0,		SLEW),
1325	NPCM8XX_PINCFG(17,	pspi, MFSEL3, 13,	cp1gpio5, MFSEL6, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1326	NPCM8XX_PINCFG(18,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1327	NPCM8XX_PINCFG(19,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1328	NPCM8XX_PINCFG(20,	hgpio0,	MFSEL2, 24,	smb15, MFSEL3, 8,	smb4c, I2CSEGSEL, 15,	none, NONE, 0,		none, NONE, 0,		SLEW),
1329	NPCM8XX_PINCFG(21,	hgpio1,	MFSEL2, 25,	smb15, MFSEL3, 8,	smb4c, I2CSEGSEL, 15,	none, NONE, 0,		none, NONE, 0,		SLEW),
1330	NPCM8XX_PINCFG(22,	hgpio2,	MFSEL2, 26,	smb14, MFSEL3, 7,	smb4d, I2CSEGSEL, 16,	none, NONE, 0,		none, NONE, 0,		SLEW),
1331	NPCM8XX_PINCFG(23,	hgpio3,	MFSEL2, 27,	smb14, MFSEL3, 7,	smb4d, I2CSEGSEL, 16,	none, NONE, 0,		none, NONE, 0,		SLEW),
1332	NPCM8XX_PINCFG(24,	hgpio4,	MFSEL2, 28,	ioxh, MFSEL3, 18,	smb7c, I2CSEGSEL, 28,	tp_smb2, MFSEL7, 28,	none, NONE, 0,		SLEW),
1333	NPCM8XX_PINCFG(25,	hgpio5,	MFSEL2, 29,	ioxh, MFSEL3, 18,	smb7c, I2CSEGSEL, 28,	tp_smb2, MFSEL7, 28,	none, NONE, 0,		SLEW),
1334	NPCM8XX_PINCFG(26,	smb5, MFSEL1, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1335	NPCM8XX_PINCFG(27,	smb5, MFSEL1, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1336	NPCM8XX_PINCFG(28,	smb4, MFSEL1, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1337	NPCM8XX_PINCFG(29,	smb4, MFSEL1, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1338	NPCM8XX_PINCFG(30,	smb3, MFSEL1, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1339	NPCM8XX_PINCFG(31,	smb3, MFSEL1, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1340	NPCM8XX_PINCFG(32,	spi0cs1, MFSEL1, 3,	smb14b, MFSEL7, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1341	NPCM8XX_PINCFG(33,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1342	NPCM8XX_PINCFG(34,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1343	NPCM8XX_PINCFG(35,	gpi35, MFSEL5, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1344	NPCM8XX_PINCFG(36,	gpi36, MFSEL5, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1345	NPCM8XX_PINCFG(37,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1346	NPCM8XX_PINCFG(38,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1347	NPCM8XX_PINCFG(39,	smb3b, I2CSEGSEL, 11,	smb22, MFSEL5, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1348	NPCM8XX_PINCFG(40,	smb3b, I2CSEGSEL, 11,	smb22, MFSEL5, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1349	NPCM8XX_PINCFG(41,	bmcuart0a, MFSEL1, 9,	cp1urxd, MFSEL6, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1350	NPCM8XX_PINCFG(42,	bmcuart0a, MFSEL1, 9,	cp1utxd, MFSEL6, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4) | GPO),
1351	NPCM8XX_PINCFG(43,	uart1, MFSEL1, 10,	bmcuart1, MFSEL3, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1352	NPCM8XX_PINCFG(44,	hsi1b, MFSEL1, 28,	nbu1crts, MFSEL6, 15,	jtag2, MFSEL4, 0,	tp_jtag3, MFSEL7, 13,	j2j3, MFSEL5, 2,	GPO),
1353	NPCM8XX_PINCFG(45,	hsi1c, MFSEL1, 4,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	tp_jtag3, MFSEL7, 13,	none, NONE, 0,		GPO),
1354	NPCM8XX_PINCFG(46,	hsi1c, MFSEL1, 4,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	tp_jtag3, MFSEL7, 13,	none, NONE, 0,		GPO),
1355	NPCM8XX_PINCFG(47,	hsi1c, MFSEL1, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 8)),
1356	NPCM8XX_PINCFG(48,	hsi2a, MFSEL1, 11,	bmcuart0b, MFSEL4, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1357	NPCM8XX_PINCFG(49,	hsi2a, MFSEL1, 11,	bmcuart0b, MFSEL4, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1358	NPCM8XX_PINCFG(50,	hsi2b, MFSEL1, 29,	bu6, MFSEL5, 6,		tp_uart, MFSEL7, 12,	none, NONE, 0,		none, NONE, 0,		GPO),
1359	NPCM8XX_PINCFG(51,	hsi2b, MFSEL1, 29,	bu6, MFSEL5, 6,		tp_uart, MFSEL7, 12,	none, NONE, 0,		none, NONE, 0,		GPO),
1360	NPCM8XX_PINCFG(52,	hsi2c, MFSEL1, 5,	bu5, MFSEL5, 7,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1361	NPCM8XX_PINCFG(53,	hsi2c, MFSEL1, 5,	bu5, MFSEL5, 7,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1362	NPCM8XX_PINCFG(54,	hsi2c, MFSEL1, 5,	bu4, MFSEL5, 8,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1363	NPCM8XX_PINCFG(55,	hsi2c, MFSEL1, 5,	bu4, MFSEL5, 8,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1364	NPCM8XX_PINCFG(56,	r1err, MFSEL1, 12,	r1oen, MFSEL5, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1365	NPCM8XX_PINCFG(57,	r1md, MFSEL1, 13,	tpgpio4b, MFSEL5, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1366	NPCM8XX_PINCFG(58,	r1md, MFSEL1, 13,	tpgpio5b, MFSEL5, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1367	NPCM8XX_PINCFG(59,	hgpio6, MFSEL2, 30,	smb3d, I2CSEGSEL, 13,	smb19, MFSEL5, 27,	none, NONE, 0,		none, NONE, 0,		0),
1368	NPCM8XX_PINCFG(60,	hgpio7, MFSEL2, 31,	smb3d, I2CSEGSEL, 13,	smb19, MFSEL5, 27,	none, NONE, 0,		none, NONE, 0,		0),
1369	NPCM8XX_PINCFG(61,	hsi1c, MFSEL1, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1370	NPCM8XX_PINCFG(62,	hsi1b, MFSEL1, 28,	jtag2, MFSEL4, 0,	j2j3, MFSEL5, 2,	nbu1crts, MFSEL6, 15,	tp_jtag3, MFSEL7, 13,	GPO),
1371	NPCM8XX_PINCFG(63,	hsi1a, MFSEL1, 10,	bmcuart1, MFSEL3, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1372	NPCM8XX_PINCFG(64,	fanin0, MFSEL2, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1373	NPCM8XX_PINCFG(65,	fanin1, MFSEL2, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1374	NPCM8XX_PINCFG(66,	fanin2, MFSEL2, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1375	NPCM8XX_PINCFG(67,	fanin3, MFSEL2, 3,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1376	NPCM8XX_PINCFG(68,	fanin4, MFSEL2, 4,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1377	NPCM8XX_PINCFG(69,	fanin5, MFSEL2, 5,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1378	NPCM8XX_PINCFG(70,	fanin6, MFSEL2, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1379	NPCM8XX_PINCFG(71,	fanin7, MFSEL2, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1380	NPCM8XX_PINCFG(72,	fanin8, MFSEL2, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1381	NPCM8XX_PINCFG(73,	fanin9, MFSEL2, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1382	NPCM8XX_PINCFG(74,	fanin10, MFSEL2, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1383	NPCM8XX_PINCFG(75,	fanin11, MFSEL2, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1384	NPCM8XX_PINCFG(76,	fanin12, MFSEL2, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1385	NPCM8XX_PINCFG(77,	fanin13, MFSEL2, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1386	NPCM8XX_PINCFG(78,	fanin14, MFSEL2, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1387	NPCM8XX_PINCFG(79,	fanin15, MFSEL2, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1388	NPCM8XX_PINCFG(80,	pwm0, MFSEL2, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1389	NPCM8XX_PINCFG(81,	pwm1, MFSEL2, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1390	NPCM8XX_PINCFG(82,	pwm2, MFSEL2, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1391	NPCM8XX_PINCFG(83,	pwm3, MFSEL2, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1392	NPCM8XX_PINCFG(84,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1393	NPCM8XX_PINCFG(85,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1394	NPCM8XX_PINCFG(86,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1395	NPCM8XX_PINCFG(87,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1396	NPCM8XX_PINCFG(88,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1397	NPCM8XX_PINCFG(89,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1398	NPCM8XX_PINCFG(90,	r2err, MFSEL1, 15,	r2oen, MFSEL5, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1399	NPCM8XX_PINCFG(91,	r2md, MFSEL1, 16,	cp1gpio6, MFSEL6, 8,	tp_gpio0, MFSEL7, 0,	none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1400	NPCM8XX_PINCFG(92,	r2md, MFSEL1, 16,	cp1gpio7, MFSEL6, 9,	tp_gpio1, MFSEL7, 1,	none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1401	NPCM8XX_PINCFG(93,	ga20kbc, MFSEL1, 17,	smb5d, I2CSEGSEL, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1402	NPCM8XX_PINCFG(94,	ga20kbc, MFSEL1, 17,	smb5d, I2CSEGSEL, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1403	NPCM8XX_PINCFG(95,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1404	NPCM8XX_PINCFG(96,	cp1gpio7b, MFSEL6, 24,	tp_gpio7, MFSEL7, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1405	NPCM8XX_PINCFG(97,	cp1gpio6b, MFSEL6, 25,	tp_gpio6, MFSEL7, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1406	NPCM8XX_PINCFG(98,	bu4b, MFSEL5, 13,	cp1gpio5b, MFSEL6, 26,	tp_gpio5, MFSEL7, 5,	none, NONE, 0,		none, NONE, 0,		SLEW),
1407	NPCM8XX_PINCFG(99,	bu4b, MFSEL5, 13,	cp1gpio4b, MFSEL6, 27,	tp_gpio4, MFSEL7, 4,	none, NONE, 0,		none, NONE, 0,		SLEW),
1408	NPCM8XX_PINCFG(100,	bu5b, MFSEL5, 12,	cp1gpio3c, MFSEL6, 28,	tp_gpio3, MFSEL7, 3,	none, NONE, 0,		none, NONE, 0,		SLEW),
1409	NPCM8XX_PINCFG(101,	bu5b, MFSEL5, 12,	cp1gpio2c, MFSEL6, 29,	tp_gpio2, MFSEL7, 2,	none, NONE, 0,		none, NONE, 0,		SLEW),
1410	NPCM8XX_PINCFG(102,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1411	NPCM8XX_PINCFG(103,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1412	NPCM8XX_PINCFG(104,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1413	NPCM8XX_PINCFG(105,	vgadig, MFSEL7, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1414	NPCM8XX_PINCFG(106,	i3c5, MFSEL3, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1415	NPCM8XX_PINCFG(107,	i3c5, MFSEL3, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1416	NPCM8XX_PINCFG(108,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1417	NPCM8XX_PINCFG(109,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1418	NPCM8XX_PINCFG(110,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW),
1419	NPCM8XX_PINCFG(111,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW),
1420	NPCM8XX_PINCFG(112,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1421	NPCM8XX_PINCFG(113,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1422	NPCM8XX_PINCFG(114,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1423	NPCM8XX_PINCFG(115,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1424	NPCM8XX_PINCFG(116,	smb1, MFSEL1, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1425	NPCM8XX_PINCFG(117,	smb1, MFSEL1, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1426	NPCM8XX_PINCFG(118,	smb2, MFSEL1, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1427	NPCM8XX_PINCFG(119,	smb2, MFSEL1, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1428	NPCM8XX_PINCFG(120,	smb2c, I2CSEGSEL, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1429	NPCM8XX_PINCFG(121,	smb2c, I2CSEGSEL, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1430	NPCM8XX_PINCFG(122,	smb2b, I2CSEGSEL, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1431	NPCM8XX_PINCFG(123,	smb2b, I2CSEGSEL, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1432	NPCM8XX_PINCFG(124,	smb1c, I2CSEGSEL, 6,	cp1gpio3b, MFSEL6, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1433	NPCM8XX_PINCFG(125,	smb1c, I2CSEGSEL, 6,	cp1gpio2b, MFSEL6, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1434	NPCM8XX_PINCFG(126,	smb1b, I2CSEGSEL, 5,	cp1gpio1b, MFSEL6, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1435	NPCM8XX_PINCFG(127,	smb1b, I2CSEGSEL, 5,	cp1gpio0b, MFSEL6, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1436	NPCM8XX_PINCFG(128,	smb8, MFSEL4, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1437	NPCM8XX_PINCFG(129,	smb8, MFSEL4, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1438	NPCM8XX_PINCFG(130,	smb9, MFSEL4, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1439	NPCM8XX_PINCFG(131,	smb9, MFSEL4, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1440	NPCM8XX_PINCFG(132,	smb10, MFSEL4, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1441	NPCM8XX_PINCFG(133,	smb10, MFSEL4, 13,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1442	NPCM8XX_PINCFG(134,	smb11, MFSEL4, 14,	smb23b, MFSEL6, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1443	NPCM8XX_PINCFG(135,	smb11, MFSEL4, 14,	smb23b, MFSEL6, 0,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1444	NPCM8XX_PINCFG(136,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1445	NPCM8XX_PINCFG(137,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1446	NPCM8XX_PINCFG(138,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1447	NPCM8XX_PINCFG(139,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1448	NPCM8XX_PINCFG(140,	jm1, MFSEL5, 15,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1449	NPCM8XX_PINCFG(141,	smb7b, I2CSEGSEL, 27,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1450	NPCM8XX_PINCFG(142,	smb7d, I2CSEGSEL, 29,	tp_smb1, MFSEL7, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1451	NPCM8XX_PINCFG(143,	smb7d, I2CSEGSEL, 29,	tp_smb1, MFSEL7, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1452	NPCM8XX_PINCFG(144,	pwm4, MFSEL2, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1453	NPCM8XX_PINCFG(145,	pwm5, MFSEL2, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1454	NPCM8XX_PINCFG(146,	pwm6, MFSEL2, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1455	NPCM8XX_PINCFG(147,	pwm7, MFSEL2, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 8)),
1456	NPCM8XX_PINCFG(148,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1457	NPCM8XX_PINCFG(149,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1458	NPCM8XX_PINCFG(150,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1459	NPCM8XX_PINCFG(151,	mmc8, MFSEL3, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1460	NPCM8XX_PINCFG(152,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1461	NPCM8XX_PINCFG(153,	mmcwp, FLOCKR1, 24,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1462	NPCM8XX_PINCFG(154,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1463	NPCM8XX_PINCFG(155,	mmccd, MFSEL3, 25,	mmcrst, MFSEL4, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1464	NPCM8XX_PINCFG(156,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1465	NPCM8XX_PINCFG(157,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1466	NPCM8XX_PINCFG(158,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1467	NPCM8XX_PINCFG(159,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1468	NPCM8XX_PINCFG(160,	clkout, MFSEL1, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1469	NPCM8XX_PINCFG(161,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1470	NPCM8XX_PINCFG(162,	clkrun, MFSEL3, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1471	NPCM8XX_PINCFG(163,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1472	NPCM8XX_PINCFG(164,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1473	NPCM8XX_PINCFG(165,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1474	NPCM8XX_PINCFG(166,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1475	NPCM8XX_PINCFG(167,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1476	NPCM8XX_PINCFG(168,	serirq, MFSEL1, 31,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1477	NPCM8XX_PINCFG(169,	scipme, MFSEL3, 0,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1478	NPCM8XX_PINCFG(170,	smi, MFSEL1, 22,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1479	NPCM8XX_PINCFG(171,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1480	NPCM8XX_PINCFG(172,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1481	NPCM8XX_PINCFG(173,	smb7, MFSEL3, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1482	NPCM8XX_PINCFG(174,	smb7, MFSEL3, 2,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1483	NPCM8XX_PINCFG(175,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1484	NPCM8XX_PINCFG(176,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1485	NPCM8XX_PINCFG(177,	spi1, MFSEL3, 4,	faninx, MFSEL3, 3,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1486	NPCM8XX_PINCFG(178,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1487	NPCM8XX_PINCFG(179,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1488	NPCM8XX_PINCFG(180,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1489	NPCM8XX_PINCFG(181,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1490	NPCM8XX_PINCFG(182,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1491	NPCM8XX_PINCFG(183,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1492	NPCM8XX_PINCFG(184,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1493	NPCM8XX_PINCFG(185,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1494	NPCM8XX_PINCFG(186,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1495	NPCM8XX_PINCFG(187,	gpo187, MFSEL7, 24,	smb14b, MFSEL7, 26,	spi3cs1, MFSEL4, 17,	none, NONE, 0,		none, NONE, 0,		SLEW),
1496	NPCM8XX_PINCFG(188,	gpio1889, MFSEL7, 25,	spi3cs2, MFSEL4, 18,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1497	NPCM8XX_PINCFG(189,	gpio1889, MFSEL7, 25,	spi3cs3, MFSEL4, 19,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1498	NPCM8XX_PINCFG(190,	nprd_smi, FLOCKR1, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
1499	NPCM8XX_PINCFG(191,	spi1d23, MFSEL5, 3,	spi1cs2, MFSEL5, 4,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		SLEW),  /* XX */
1500	NPCM8XX_PINCFG(192,	spi1d23, MFSEL5, 3,	spi1cs3, MFSEL5, 5,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		SLEW),  /* XX */
1501	NPCM8XX_PINCFG(193,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1502	NPCM8XX_PINCFG(194,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1503	NPCM8XX_PINCFG(195,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1504	NPCM8XX_PINCFG(196,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1505	NPCM8XX_PINCFG(197,	smb0den, I2CSEGSEL, 22,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1506	NPCM8XX_PINCFG(198,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1507	NPCM8XX_PINCFG(199,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1508	NPCM8XX_PINCFG(200,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1509	NPCM8XX_PINCFG(201,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
1510	NPCM8XX_PINCFG(202,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1511	NPCM8XX_PINCFG(203,	faninx, MFSEL3, 3,	spi1cs0, MFSEL3, 4,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
1512	NPCM8XX_PINCFG(208,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */
1513	NPCM8XX_PINCFG(209,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */
1514	NPCM8XX_PINCFG(210,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1515	NPCM8XX_PINCFG(211,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1516	NPCM8XX_PINCFG(212,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	r3rxer, MFSEL6, 30,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1517	NPCM8XX_PINCFG(213,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	r3oen, MFSEL5, 14,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1518	NPCM8XX_PINCFG(214,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1519	NPCM8XX_PINCFG(215,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1520	NPCM8XX_PINCFG(216,	rg2mdio, MFSEL4, 23,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1521	NPCM8XX_PINCFG(217,	rg2mdio, MFSEL4, 23,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1522	NPCM8XX_PINCFG(218,	wdog1, MFSEL3, 19,	smb16b, MFSEL7, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1523	NPCM8XX_PINCFG(219,	wdog2, MFSEL3, 20,	smb16b, MFSEL7, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1524	NPCM8XX_PINCFG(220,	smb12, MFSEL3, 5,	pwm8, MFSEL6, 11,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1525	NPCM8XX_PINCFG(221,	smb12, MFSEL3, 5,	pwm9, MFSEL6, 12,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1526	NPCM8XX_PINCFG(222,	smb13, MFSEL3, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1527	NPCM8XX_PINCFG(223,	smb13, MFSEL3, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1528	NPCM8XX_PINCFG(224,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1529	NPCM8XX_PINCFG(225,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1530	NPCM8XX_PINCFG(226,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
1531	NPCM8XX_PINCFG(227,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1532	NPCM8XX_PINCFG(228,	spixcs1, MFSEL4, 28,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1533	NPCM8XX_PINCFG(229,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
1534	NPCM8XX_PINCFG(230,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
1535	NPCM8XX_PINCFG(231,	clkreq, MFSEL4, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 12) | SLEW),
1536	NPCM8XX_PINCFG(233,	spi1cs1, MFSEL5, 0,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0), /* slewlpc ? */
1537	NPCM8XX_PINCFG(234,	pwm10, MFSEL6, 13,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1538	NPCM8XX_PINCFG(235,	pwm11, MFSEL6, 14,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1539	NPCM8XX_PINCFG(240,	i3c0, MFSEL5, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1540	NPCM8XX_PINCFG(241,	i3c0, MFSEL5, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1541	NPCM8XX_PINCFG(242,	i3c1, MFSEL5, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1542	NPCM8XX_PINCFG(243,	i3c1, MFSEL5, 19,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1543	NPCM8XX_PINCFG(244,	i3c2, MFSEL5, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1544	NPCM8XX_PINCFG(245,	i3c2, MFSEL5, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1545	NPCM8XX_PINCFG(246,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1546	NPCM8XX_PINCFG(247,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
1547	NPCM8XX_PINCFG(250,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
1548	NPCM8XX_PINCFG(251,	jm2, MFSEL5, 1,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
1549	NPCM8XX_PINCFG(253,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC1 power */
1550	NPCM8XX_PINCFG(254,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC2 power */
1551	NPCM8XX_PINCFG(255,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* DACOSEL */
1552};
1553
1554/* number, name, drv_data */
1555static const struct pinctrl_pin_desc npcm8xx_pins[] = {
1556	PINCTRL_PIN(0,	"GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"),
1557	PINCTRL_PIN(1,	"GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"),
1558	PINCTRL_PIN(2,	"GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"),
1559	PINCTRL_PIN(3,	"GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"),
1560	PINCTRL_PIN(4,	"GPIO4/IOX2_DI/SMB1D_SDA"),
1561	PINCTRL_PIN(5,	"GPIO5/IOX2_LD/SMB1D_SCL"),
1562	PINCTRL_PIN(6,	"GPIO6/IOX2_CK/SMB2D_SDA"),
1563	PINCTRL_PIN(7,	"GPIO7/IOX2_D0/SMB2D_SCL"),
1564	PINCTRL_PIN(8,	"GPIO8/LKGPO1/TP_GPIO0"),
1565	PINCTRL_PIN(9,	"GPIO9/LKGPO2/TP_GPIO1"),
1566	PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"),
1567	PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"),
1568	PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"),
1569	PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"),
1570	PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"),
1571	PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"),
1572	PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"),
1573	PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"),
1574	PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"),
1575	PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"),
1576	PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"),
1577	PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"),
1578	PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"),
1579	PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"),
1580	PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"),
1581	PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"),
1582	PINCTRL_PIN(26, "GPIO26/SMB5_SDA"),
1583	PINCTRL_PIN(27, "GPIO27/SMB5_SCL"),
1584	PINCTRL_PIN(28, "GPIO28/SMB4_SDA"),
1585	PINCTRL_PIN(29, "GPIO29/SMB4_SCL"),
1586	PINCTRL_PIN(30, "GPIO30/SMB3_SDA"),
1587	PINCTRL_PIN(31, "GPIO31/SMB3_SCL"),
1588	PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
1589	PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
1590	PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
1591	PINCTRL_PIN(35, "MCBPCK/GPI35_AHB2PCI_DIS"),
1592	PINCTRL_PIN(36, "SYSBPCK/GPI36"),
1593	PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
1594	PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
1595	PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),
1596	PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"),
1597	PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"),
1598	PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"),
1599	PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"),
1600	PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"),
1601	PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"),
1602	PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"),
1603	PINCTRL_PIN(47, "GPIO47/SI1n_RI1"),
1604	PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"),
1605	PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"),
1606	PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"),
1607	PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"),
1608	PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"),
1609	PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"),
1610	PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"),
1611	PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"),
1612	PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"),
1613	PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"),
1614	PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"),
1615	PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"),
1616	PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"),
1617	PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"),
1618	PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"),
1619	PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"),
1620	PINCTRL_PIN(64, "GPIO64/FANIN0"),
1621	PINCTRL_PIN(65, "GPIO65/FANIN1"),
1622	PINCTRL_PIN(66, "GPIO66/FANIN2"),
1623	PINCTRL_PIN(67, "GPIO67/FANIN3"),
1624	PINCTRL_PIN(68, "GPIO68/FANIN4"),
1625	PINCTRL_PIN(69, "GPIO69/FANIN5"),
1626	PINCTRL_PIN(70, "GPIO70/FANIN6"),
1627	PINCTRL_PIN(71, "GPIO71/FANIN7"),
1628	PINCTRL_PIN(72, "GPIO72/FANIN8"),
1629	PINCTRL_PIN(73, "GPIO73/FANIN9"),
1630	PINCTRL_PIN(74, "GPIO74/FANIN10"),
1631	PINCTRL_PIN(75, "GPIO75/FANIN11"),
1632	PINCTRL_PIN(76, "GPIO76/FANIN12"),
1633	PINCTRL_PIN(77, "GPIO77/FANIN13"),
1634	PINCTRL_PIN(78, "GPIO78/FANIN14"),
1635	PINCTRL_PIN(79, "GPIO79/FANIN15"),
1636	PINCTRL_PIN(80, "GPIO80/PWM0"),
1637	PINCTRL_PIN(81, "GPIO81/PWM1"),
1638	PINCTRL_PIN(82, "GPIO82/PWM2"),
1639	PINCTRL_PIN(83, "GPIO83/PWM3"),
1640	PINCTRL_PIN(84, "GPIO84/R2_TXD0"),
1641	PINCTRL_PIN(85, "GPIO85/R2_TXD1"),
1642	PINCTRL_PIN(86, "GPIO86/R2_TXEN"),
1643	PINCTRL_PIN(87, "GPIO87/R2_RXD0"),
1644	PINCTRL_PIN(88, "GPIO88/R2_RXD1"),
1645	PINCTRL_PIN(89, "GPIO89/R2_CRSDV"),
1646	PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"),
1647	PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"),
1648	PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"),
1649	PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"),
1650	PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"),
1651	PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"),
1652	PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"),
1653	PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"),
1654	PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"),
1655	PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"),
1656	PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"),
1657	PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"),
1658	PINCTRL_PIN(102, "GPIO102/HSYNC"),
1659	PINCTRL_PIN(103, "GPIO103/VSYNC"),
1660	PINCTRL_PIN(104, "GPIO104/DDC_SCL"),
1661	PINCTRL_PIN(105, "GPIO105/DDC_SDA"),
1662	PINCTRL_PIN(106, "GPIO106/I3C5_SCL"),
1663	PINCTRL_PIN(107, "GPIO107/I3C5_SDA"),
1664	PINCTRL_PIN(108, "GPIO108/SG1_MDC"),
1665	PINCTRL_PIN(109, "GPIO109/SG1_MDIO"),
1666	PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"),
1667	PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"),
1668	PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"),
1669	PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"),
1670	PINCTRL_PIN(114, "GPIO114/SMB0_SCL"),
1671	PINCTRL_PIN(115, "GPIO115/SMB0_SDA"),
1672	PINCTRL_PIN(116, "GPIO116/SMB1_SCL"),
1673	PINCTRL_PIN(117, "GPIO117/SMB1_SDA"),
1674	PINCTRL_PIN(118, "GPIO118/SMB2_SCL"),
1675	PINCTRL_PIN(119, "GPIO119/SMB2_SDA"),
1676	PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"),
1677	PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"),
1678	PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"),
1679	PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"),
1680	PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"),
1681	PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"),
1682	PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"),
1683	PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"),
1684	PINCTRL_PIN(128, "GPIO128/SMB824_SCL"),
1685	PINCTRL_PIN(129, "GPIO129/SMB824_SDA"),
1686	PINCTRL_PIN(130, "GPIO130/SMB925_SCL"),
1687	PINCTRL_PIN(131, "GPIO131/SMB925_SDA"),
1688	PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"),
1689	PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"),
1690	PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"),
1691	PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"),
1692	PINCTRL_PIN(136, "GPIO136/JM1_TCK"),
1693	PINCTRL_PIN(137, "GPIO137/JM1_TDO"),
1694	PINCTRL_PIN(138, "GPIO138/JM1_TMS"),
1695	PINCTRL_PIN(139, "GPIO139/JM1_TDI"),
1696	PINCTRL_PIN(140, "GPIO140/JM1_nTRST"),
1697	PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"),
1698	PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"),
1699	PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"),
1700	PINCTRL_PIN(144, "GPIO144/PWM4"),
1701	PINCTRL_PIN(145, "GPIO145/PWM5"),
1702	PINCTRL_PIN(146, "GPIO146/PWM6"),
1703	PINCTRL_PIN(147, "GPIO147/PWM7"),
1704	PINCTRL_PIN(148, "GPIO148/MMC_DT4"),
1705	PINCTRL_PIN(149, "GPIO149/MMC_DT5"),
1706	PINCTRL_PIN(150, "GPIO150/MMC_DT6"),
1707	PINCTRL_PIN(151, "GPIO151/MMC_DT7"),
1708	PINCTRL_PIN(152, "GPIO152/MMC_CLK"),
1709	PINCTRL_PIN(153, "GPIO153/MMC_WP"),
1710	PINCTRL_PIN(154, "GPIO154/MMC_CMD"),
1711	PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"),
1712	PINCTRL_PIN(156, "GPIO156/MMC_DT0"),
1713	PINCTRL_PIN(157, "GPIO157/MMC_DT1"),
1714	PINCTRL_PIN(158, "GPIO158/MMC_DT2"),
1715	PINCTRL_PIN(159, "GPIO159/MMC_DT3"),
1716	PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"),
1717	PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"),
1718	PINCTRL_PIN(162, "GPIO162/SERIRQ"),
1719	PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"),
1720	PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"),
1721	PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"),
1722	PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"),
1723	PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"),
1724	PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"),
1725	PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"),
1726	PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"),
1727	PINCTRL_PIN(171, "GPIO171/SMB6_SCL"),
1728	PINCTRL_PIN(172, "GPIO172/SMB6_SDA"),
1729	PINCTRL_PIN(173, "GPIO173/SMB7_SCL"),
1730	PINCTRL_PIN(174, "GPIO174/SMB7_SDA"),
1731	PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"),
1732	PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"),
1733	PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"),
1734	PINCTRL_PIN(178, "GPIO178/R1_TXD0"),
1735	PINCTRL_PIN(179, "GPIO179/R1_TXD1"),
1736	PINCTRL_PIN(180, "GPIO180/R1_TXEN"),
1737	PINCTRL_PIN(181, "GPIO181/R1_RXD0"),
1738	PINCTRL_PIN(182, "GPIO182/R1_RXD1"),
1739	PINCTRL_PIN(183, "GPIO183/SPI3_SEL"),
1740	PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"),
1741	PINCTRL_PIN(185, "GPIO185/SPI3_D1"),
1742	PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"),
1743	PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"),
1744	PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"),
1745	PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"),
1746	PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
1747	PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"),
1748	PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"),
1749	PINCTRL_PIN(193, "GPIO193/R1_CRSDV"),
1750	PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"),
1751	PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"),
1752	PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"),
1753	PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"),
1754	PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"),
1755	PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"),
1756	PINCTRL_PIN(200, "GPIO200/R2_CK"),
1757	PINCTRL_PIN(201, "GPIO201/R1_CK"),
1758	PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"),
1759	PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"),
1760	PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"),
1761	PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"),
1762	PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"),
1763	PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"),
1764	PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"),
1765	PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"),
1766	PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"),
1767	PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"),
1768	PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"),
1769	PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"),
1770	PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"),
1771	PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"),
1772	PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"),
1773	PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"),
1774	PINCTRL_PIN(222, "GPIO222/SMB13_SCL"),
1775	PINCTRL_PIN(223, "GPIO223/SMB13_SDA"),
1776	PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"),
1777	PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"),
1778	PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"),
1779	PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"),
1780	PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"),
1781	PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"),
1782	PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"),
1783	PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"),
1784	PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"),
1785	PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"),
1786	PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"),
1787	PINCTRL_PIN(240, "GPIO240/I3C0_SCL"),
1788	PINCTRL_PIN(241, "GPIO241/I3C0_SDA"),
1789	PINCTRL_PIN(242, "GPIO242/I3C1_SCL"),
1790	PINCTRL_PIN(243, "GPIO243/I3C1_SDA"),
1791	PINCTRL_PIN(244, "GPIO244/I3C2_SCL"),
1792	PINCTRL_PIN(245, "GPIO245/I3C2_SDA"),
1793	PINCTRL_PIN(246, "GPIO246/I3C3_SCL"),
1794	PINCTRL_PIN(247, "GPIO247/I3C3_SDA"),
1795	PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"),
1796	PINCTRL_PIN(251, "JM2/CP1_GPIO"),
1797	};
1798
1799/* Enable mode in pin group */
1800static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
1801			    int pin_number, int mode)
1802{
1803	const struct npcm8xx_pincfg *cfg;
1804	int i;
1805
1806	for (i = 0 ; i < pin_number ; i++) {
1807		cfg = &pincfg[pin[i]];
1808		if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode ||
1809		    cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) {
1810			if (cfg->reg0)
1811				regmap_update_bits(gcr_regmap, cfg->reg0,
1812						   BIT(cfg->bit0),
1813						   (cfg->fn0 == mode) ?
1814						   BIT(cfg->bit0) : 0);
1815			if (cfg->reg1)
1816				regmap_update_bits(gcr_regmap, cfg->reg1,
1817						   BIT(cfg->bit1),
1818						   (cfg->fn1 == mode) ?
1819						   BIT(cfg->bit1) : 0);
1820			if (cfg->reg2)
1821				regmap_update_bits(gcr_regmap, cfg->reg2,
1822						   BIT(cfg->bit2),
1823						   (cfg->fn2 == mode) ?
1824						   BIT(cfg->bit2) : 0);
1825			if (cfg->reg3)
1826				regmap_update_bits(gcr_regmap, cfg->reg3,
1827						   BIT(cfg->bit3),
1828						   (cfg->fn3 == mode) ?
1829						   BIT(cfg->bit3) : 0);
1830			if (cfg->reg4)
1831				regmap_update_bits(gcr_regmap, cfg->reg4,
1832						   BIT(cfg->bit4),
1833						   (cfg->fn4 == mode) ?
1834						   BIT(cfg->bit4) : 0);
1835		}
1836	}
1837}
1838
1839static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
1840				 struct regmap *gcr_regmap, unsigned int pin)
1841{
1842	int gpio = pin % bank->chip.gc.ngpio;
1843	unsigned long pinmask = BIT(gpio);
1844	u32 val;
1845
1846	if (pincfg[pin].flag & SLEW)
1847		return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask;
1848	/* LPC Slew rate in SRCNT register */
1849	if (pincfg[pin].flag & SLEWLPC) {
1850		regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val);
1851		return !!(val & SRCNT_ESPI);
1852	}
1853
1854	return -EINVAL;
1855}
1856
1857static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
1858				 struct regmap *gcr_regmap, unsigned int pin,
1859				 int arg)
1860{
1861	void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
1862	int gpio = BIT(pin % bank->chip.gc.ngpio);
1863
1864	if (pincfg[pin].flag & SLEW) {
1865		switch (arg) {
1866		case 0:
1867			npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio);
1868			return 0;
1869		case 1:
1870			npcm_gpio_set(&bank->chip, OSRC_Offset, gpio);
1871			return 0;
1872		default:
1873			return -EINVAL;
1874		}
1875	}
1876
1877	if (!(pincfg[pin].flag & SLEWLPC))
1878		return -EINVAL;
1879
1880	switch (arg) {
1881	case 0:
1882		regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1883				   SRCNT_ESPI, 0);
1884		break;
1885	case 1:
1886		regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT,
1887				   SRCNT_ESPI, SRCNT_ESPI);
1888		break;
1889	default:
1890		return -EINVAL;
1891		}
1892
1893	return 0;
1894}
1895
1896static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
1897				      unsigned int pin)
1898{
1899	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1900	struct npcm8xx_gpio *bank =
1901		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
1902	int gpio = pin % bank->chip.gc.ngpio;
1903	unsigned long pinmask = BIT(gpio);
1904	int flg, val;
1905	u32 ds = 0;
1906
1907	flg = pincfg[pin].flag;
1908	if (!(flg & DRIVE_STRENGTH_MASK))
1909		return -EINVAL;
1910
1911	val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
1912	ds = val ? DSHI(flg) : DSLO(flg);
1913	dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
1914
1915	return ds;
1916}
1917
1918static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
1919				      unsigned int pin, int nval)
1920{
1921	struct npcm8xx_gpio *bank =
1922		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
1923	int gpio = BIT(pin % bank->chip.gc.ngpio);
1924	int v;
1925
1926	v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
1927
1928	if (DSLO(v) == nval)
1929		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
1930	else if (DSHI(v) == nval)
1931		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
1932	else
1933		return -ENOTSUPP;
1934
1935	return 0;
1936}
1937
1938/* pinctrl_ops */
1939static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev)
1940{
1941	return ARRAY_SIZE(npcm8xx_pingroups);
1942}
1943
1944static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev,
1945					  unsigned int selector)
1946{
1947	return npcm8xx_pingroups[selector].name;
1948}
1949
1950static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev,
1951				  unsigned int selector,
1952				  const unsigned int **pins,
1953				  unsigned int *npins)
1954{
1955	*npins = npcm8xx_pingroups[selector].npins;
1956	*pins  = npcm8xx_pingroups[selector].pins;
1957
1958	return 0;
1959}
1960
1961static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev,
1962				  struct device_node *np_config,
1963				  struct pinctrl_map **map,
1964				  u32 *num_maps)
1965{
1966	return pinconf_generic_dt_node_to_map(pctldev, np_config,
1967					      map, num_maps,
1968					      PIN_MAP_TYPE_INVALID);
1969}
1970
1971static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev,
1972				struct pinctrl_map *map, u32 num_maps)
1973{
1974	kfree(map);
1975}
1976
1977static const struct pinctrl_ops npcm8xx_pinctrl_ops = {
1978	.get_groups_count = npcm8xx_get_groups_count,
1979	.get_group_name = npcm8xx_get_group_name,
1980	.get_group_pins = npcm8xx_get_group_pins,
1981	.dt_node_to_map = npcm8xx_dt_node_to_map,
1982	.dt_free_map = npcm8xx_dt_free_map,
1983};
1984
1985static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev)
1986{
1987	return ARRAY_SIZE(npcm8xx_funcs);
1988}
1989
1990static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev,
1991					     unsigned int function)
1992{
1993	return npcm8xx_funcs[function].name;
1994}
1995
1996static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev,
1997				       unsigned int function,
1998				       const char * const **groups,
1999				       unsigned int * const ngroups)
2000{
2001	*ngroups = npcm8xx_funcs[function].ngroups;
2002	*groups	 = npcm8xx_funcs[function].groups;
2003
2004	return 0;
2005}
2006
2007static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
2008				  unsigned int function,
2009				  unsigned int group)
2010{
2011	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2012
2013	npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins,
2014			npcm8xx_pingroups[group].npins, group);
2015
2016	return 0;
2017}
2018
2019static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
2020				       struct pinctrl_gpio_range *range,
2021				       unsigned int offset)
2022{
2023	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2024	const unsigned int *pin = &offset;
2025	int mode = fn_gpio;
2026
2027	if ((pin[0] >= 183 && pin[0] <= 189) || pin[0] == 35 || pin[0] == 36)
2028		mode = pincfg[pin[0]].fn0;
2029
2030	npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
2031
2032	return 0;
2033}
2034
2035static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev,
2036				      struct pinctrl_gpio_range *range,
2037				      unsigned int offset)
2038{
2039	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2040	int virq;
2041
2042	virq = irq_find_mapping(npcm->domain, offset);
2043	if (virq)
2044		irq_dispose_mapping(virq);
2045}
2046
2047static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
2048				   struct pinctrl_gpio_range *range,
2049				   unsigned int offset, bool input)
2050{
2051	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2052	struct npcm8xx_gpio *bank =
2053		&npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
2054	int gpio = BIT(offset % bank->chip.gc.ngpio);
2055
2056	if (input)
2057		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2058	else
2059		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2060
2061	return 0;
2062}
2063
2064static const struct pinmux_ops npcm8xx_pinmux_ops = {
2065	.get_functions_count = npcm8xx_get_functions_count,
2066	.get_function_name = npcm8xx_get_function_name,
2067	.get_function_groups = npcm8xx_get_function_groups,
2068	.set_mux = npcm8xx_pinmux_set_mux,
2069	.gpio_request_enable = npcm8xx_gpio_request_enable,
2070	.gpio_disable_free = npcm8xx_gpio_request_free,
2071	.gpio_set_direction = npcm_gpio_set_direction,
2072};
2073
2074static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
2075				   u32 nanosecs)
2076{
2077	void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4);
2078	int gpio_debounce = (gpio % 16) * 2, debounce_select, i;
2079	u32 dbncp_val, dbncp_val_mod;
2080
2081	for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) {
2082		if (bank->debounce.set_val[i]) {
2083			if (bank->debounce.nanosec_val[i] == nanosecs) {
2084				debounce_select = i << gpio_debounce;
2085				npcm_gpio_set(&bank->chip, DBNCS_offset,
2086					      debounce_select);
2087				break;
2088			}
2089		} else {
2090			bank->debounce.set_val[i] = true;
2091			bank->debounce.nanosec_val[i] = nanosecs;
2092			debounce_select = i << gpio_debounce;
2093			npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select);
2094			switch (nanosecs) {
2095			case 1 ... 1040:
2096				iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2097				break;
2098			case 1041 ... 1640:
2099				iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2100				break;
2101			case 1641 ... 2280:
2102				iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2103				break;
2104			case 2281 ... 2700:
2105				iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2106				break;
2107			case 2701 ... 2856:
2108				iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2109				break;
2110			case 2857 ... 3496:
2111				iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2112				break;
2113			case 3497 ... 4136:
2114				iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2115				break;
2116			case 4137 ... 5025:
2117				iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2118				break;
2119			default:
2120				dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC);
2121				if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL)
2122					return -ENOTSUPP;
2123				dbncp_val_mod = dbncp_val & GENMASK(3, 0);
2124				if (dbncp_val_mod > GENMASK(2, 0))
2125					dbncp_val += 0x10;
2126				iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK,
2127					  bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
2128				break;
2129			}
2130			break;
2131		}
2132	}
2133
2134	if (i == 4)
2135		return -ENOTSUPP;
2136
2137	return 0;
2138}
2139
2140static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
2141			     u32 nanosecs)
2142{
2143	struct npcm8xx_gpio *bank =
2144		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2145	int gpio = BIT(pin % bank->chip.gc.ngpio);
2146	int ret;
2147
2148	if (nanosecs) {
2149		ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio,
2150					      nanosecs);
2151		if (ret)
2152			dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin);
2153		else
2154			npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC,
2155				      gpio);
2156		return ret;
2157	}
2158
2159	npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio);
2160
2161	return 0;
2162}
2163
2164/* pinconf_ops */
2165static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
2166			      unsigned long *config)
2167{
2168	enum pin_config_param param = pinconf_to_config_param(*config);
2169	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2170	struct npcm8xx_gpio *bank =
2171		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2172	int gpio = pin % bank->chip.gc.ngpio;
2173	unsigned long pinmask = BIT(gpio);
2174	u32 ie, oe, pu, pd;
2175	int rc = 0;
2176
2177	switch (param) {
2178	case PIN_CONFIG_BIAS_DISABLE:
2179	case PIN_CONFIG_BIAS_PULL_UP:
2180	case PIN_CONFIG_BIAS_PULL_DOWN:
2181		pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask;
2182		pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask;
2183		if (param == PIN_CONFIG_BIAS_DISABLE)
2184			rc = !pu && !pd;
2185		else if (param == PIN_CONFIG_BIAS_PULL_UP)
2186			rc = pu && !pd;
2187		else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
2188			rc = !pu && pd;
2189		break;
2190	case PIN_CONFIG_LEVEL:
2191	case PIN_CONFIG_INPUT_ENABLE:
2192		ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask;
2193		oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask;
2194		if (param == PIN_CONFIG_INPUT_ENABLE)
2195			rc = (ie && !oe);
2196		else if (param == PIN_CONFIG_LEVEL)
2197			rc = (!ie && oe);
2198		break;
2199	case PIN_CONFIG_DRIVE_PUSH_PULL:
2200		rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask);
2201		break;
2202	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2203		rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask;
2204		break;
2205	case PIN_CONFIG_INPUT_DEBOUNCE:
2206		rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask;
2207		break;
2208	case PIN_CONFIG_DRIVE_STRENGTH:
2209		rc = npcm8xx_get_drive_strength(pctldev, pin);
2210		if (rc)
2211			*config = pinconf_to_config_packed(param, rc);
2212		break;
2213	case PIN_CONFIG_SLEW_RATE:
2214		rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
2215		if (rc >= 0)
2216			*config = pinconf_to_config_packed(param, rc);
2217		break;
2218	default:
2219		return -ENOTSUPP;
2220	}
2221
2222	if (!rc)
2223		return -EINVAL;
2224
2225	return 0;
2226}
2227
2228static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
2229				  unsigned int pin, unsigned long config)
2230{
2231	enum pin_config_param param = pinconf_to_config_param(config);
2232	struct npcm8xx_gpio *bank =
2233		&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
2234	u32 arg = pinconf_to_config_argument(config);
2235	int gpio = BIT(pin % bank->chip.gc.ngpio);
2236
2237	switch (param) {
2238	case PIN_CONFIG_BIAS_DISABLE:
2239		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2240		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2241		break;
2242	case PIN_CONFIG_BIAS_PULL_DOWN:
2243		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2244		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2245		break;
2246	case PIN_CONFIG_BIAS_PULL_UP:
2247		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
2248		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
2249		break;
2250	case PIN_CONFIG_INPUT_ENABLE:
2251		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
2252		bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
2253		break;
2254	case PIN_CONFIG_LEVEL:
2255		bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
2256		iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
2257		break;
2258	case PIN_CONFIG_DRIVE_PUSH_PULL:
2259		npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2260		break;
2261	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
2262		npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
2263		break;
2264	case PIN_CONFIG_INPUT_DEBOUNCE:
2265		return npcm_set_debounce(npcm, pin, arg * 1000);
2266	case PIN_CONFIG_SLEW_RATE:
2267		return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
2268	case PIN_CONFIG_DRIVE_STRENGTH:
2269		return npcm8xx_set_drive_strength(npcm, pin, arg);
2270	default:
2271		return -ENOTSUPP;
2272	}
2273
2274	return 0;
2275}
2276
2277static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
2278			      unsigned long *configs, unsigned int num_configs)
2279{
2280	struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
2281	int rc;
2282
2283	while (num_configs--) {
2284		rc = npcm8xx_config_set_one(npcm, pin, *configs++);
2285		if (rc)
2286			return rc;
2287	}
2288
2289	return 0;
2290}
2291
2292static const struct pinconf_ops npcm8xx_pinconf_ops = {
2293	.is_generic = true,
2294	.pin_config_get = npcm8xx_config_get,
2295	.pin_config_set = npcm8xx_config_set,
2296};
2297
2298/* pinctrl_desc */
2299static const struct pinctrl_desc npcm8xx_pinctrl_desc = {
2300	.name = "npcm8xx-pinctrl",
2301	.pins = npcm8xx_pins,
2302	.npins = ARRAY_SIZE(npcm8xx_pins),
2303	.pctlops = &npcm8xx_pinctrl_ops,
2304	.pmxops = &npcm8xx_pinmux_ops,
2305	.confops = &npcm8xx_pinconf_ops,
2306	.owner = THIS_MODULE,
2307};
2308
2309static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
2310{
2311	struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
2312
2313	return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent),
2314				      bank->pinctrl_id, bank->chip.gc.base,
2315				      bank->chip.gc.ngpio);
2316}
2317
2318static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
2319{
2320	struct gpio_generic_chip_config config;
2321	struct fwnode_reference_args args;
2322	struct device *dev = pctrl->dev;
2323	struct fwnode_handle *child;
2324	int ret = -ENXIO;
2325	int id = 0, i;
2326
2327	for_each_gpiochip_node(dev, child) {
2328		pctrl->gpio_bank[id].base = fwnode_iomap(child, 0);
2329		if (!pctrl->gpio_bank[id].base)
2330			return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
2331
2332		config = (struct gpio_generic_chip_config) {
2333			.dev = dev,
2334			.sz = 4,
2335			.dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
2336			.set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
2337			.dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
2338			.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
2339		};
2340
2341		ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);
2342		if (ret)
2343			return dev_err_probe(dev, ret,
2344					     "failed to initialize the generic GPIO chip\n");
2345
2346		ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
2347		if (ret < 0)
2348			return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id);
2349
2350		ret = fwnode_irq_get(child, 0);
2351		if (ret < 0)
2352			return dev_err_probe(dev, ret, "Failed to retrieve IRQ for bank %u\n", id);
2353
2354		pctrl->gpio_bank[id].irq = ret;
2355		pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
2356		pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
2357		pctrl->gpio_bank[id].pinctrl_id = args.args[0];
2358		pctrl->gpio_bank[id].chip.gc.base = -1;
2359		pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2];
2360		pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE;
2361		pctrl->gpio_bank[id].chip.gc.parent = dev;
2362		pctrl->gpio_bank[id].chip.gc.fwnode = child;
2363		pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
2364		if (pctrl->gpio_bank[id].chip.gc.label == NULL)
2365			return -ENOMEM;
2366
2367		pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show;
2368		pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input;
2369		pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input;
2370		pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output;
2371		pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output;
2372		pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request;
2373		pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request;
2374		pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free;
2375		for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
2376			pctrl->gpio_bank[id].debounce.set_val[i] = false;
2377		pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges;
2378		id++;
2379	}
2380
2381	pctrl->bank_num = id;
2382	return ret;
2383}
2384
2385static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
2386{
2387	int ret, id;
2388
2389	for (id = 0 ; id < pctrl->bank_num ; id++) {
2390		struct gpio_irq_chip *girq;
2391
2392		girq = &pctrl->gpio_bank[id].chip.gc.irq;
2393		girq->chip = &pctrl->gpio_bank[id].irq_chip;
2394		girq->parent_handler = npcmgpio_irq_handler;
2395		girq->num_parents = 1;
2396		girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents,
2397					     sizeof(*girq->parents),
2398					     GFP_KERNEL);
2399		if (!girq->parents)
2400			return -ENOMEM;
2401
2402		girq->parents[0] = pctrl->gpio_bank[id].irq;
2403		girq->default_type = IRQ_TYPE_NONE;
2404		girq->handler = handle_level_irq;
2405		ret = devm_gpiochip_add_data(pctrl->dev,
2406					     &pctrl->gpio_bank[id].chip.gc,
2407					     &pctrl->gpio_bank[id]);
2408		if (ret)
2409			return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);
2410	}
2411
2412	return 0;
2413}
2414
2415static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
2416{
2417	struct device *dev = &pdev->dev;
2418	struct npcm8xx_pinctrl *pctrl;
2419	int ret;
2420
2421	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
2422	if (!pctrl)
2423		return -ENOMEM;
2424
2425	pctrl->dev = dev;
2426	platform_set_drvdata(pdev, pctrl);
2427
2428	pctrl->gcr_regmap =
2429		syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sysgcr");
2430	if (IS_ERR(pctrl->gcr_regmap))
2431		return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
2432				      "Failed to find nuvoton,sysgcr property\n");
2433
2434	ret = npcm8xx_gpio_fw(pctrl);
2435	if (ret < 0)
2436		return dev_err_probe(dev, ret,
2437				      "Failed to gpio dt-binding\n");
2438
2439	pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl);
2440	if (IS_ERR(pctrl->pctldev))
2441		return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
2442				     "Failed to register pinctrl device\n");
2443
2444	ret = npcm8xx_gpio_register(pctrl);
2445	if (ret < 0)
2446		dev_err_probe(dev, ret, "Failed to register gpio\n");
2447
2448	return 0;
2449}
2450
2451static const struct of_device_id npcm8xx_pinctrl_match[] = {
2452	{ .compatible = "nuvoton,npcm845-pinctrl" },
2453	{ }
2454};
2455MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match);
2456
2457static struct platform_driver npcm8xx_pinctrl_driver = {
2458	.probe = npcm8xx_pinctrl_probe,
2459	.driver = {
2460		.name = "npcm8xx-pinctrl",
2461		.of_match_table = npcm8xx_pinctrl_match,
2462		.suppress_bind_attrs = true,
2463	},
2464};
2465
2466static int __init npcm8xx_pinctrl_register(void)
2467{
2468	return platform_driver_register(&npcm8xx_pinctrl_driver);
2469}
2470arch_initcall(npcm8xx_pinctrl_register);
2471
2472MODULE_LICENSE("GPL v2");
2473MODULE_AUTHOR("tomer.maimon@nuvoton.com");
2474MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver");